GAA hetero stack structure with gradient transition and stress buffer and method of fabrication

Abstract

The application discloses a GAA heterogeneous stacking structure with gradient transition and stress buffering and a preparation method. X Ga 1‑X N component gradient layer and a 2nm GAA circuit structure, the aluminum component in the gradient layer changes linearly and continuously from the diamond side to the outside, and the thermal expansion coefficient is smoothly transitioned; a plurality of GAA stacking wafers are stacked through micro-bumps and are plastic sealed, and a heat-conducting micro-channel is arranged in the packaging layer; the preparation method comprises the steps of surface cleaning, gradient layer deposition, stress testing, low-temperature hybrid bonding, symmetric stacking and multi-layer integration and the like. The application effectively eliminates the thermal mismatch stress between the diamond and the silicon through the component gradient transition, protects the electrical performance of the GAA microstructure, reduces the interface thermal resistance by more than 40%, the bonding strength is greater than 55MPa, no debonding and no cracks are found after 1000 thermal cycle tests, and the chip heat dissipation capacity and long-term reliability are significantly improved.

Description

Technical Field

[0001] This invention belongs to the field of advanced semiconductor packaging and heterogeneous integration technology, specifically relating to a 2nm GAA heterogeneous stacked structure with heterogeneous stress buffer interface and gradient transition structure and its preparation method. It is particularly suitable for solving the problems of interface failure, stress damage and electrical performance drift caused by the mismatch of thermal expansion coefficients between high thermal conductivity diamond and silicon-based 2nm advanced chips. Background Technology

[0002] As semiconductor processes have entered the advanced 2nm node, GAA (gate-all-around) transistors have replaced FinFETs as the mainstream structure. GAA microstructures are highly sensitive to mechanical stress, and high-performance computing and AI chips generally use high thermal conductivity single-crystal diamond as the heat dissipation core layer to overcome heat dissipation bottlenecks. Its thermal conductivity can reach over 1800W / (m・K).

[0003] There is a significant difference in the coefficient of thermal expansion (CTE) between diamond and silicon, as well as the encapsulation metal. Under repeated thermal cycling and high-power heating conditions, destructive stress can rapidly accumulate at the interface, leading to the following problems: 1. Thermal stress accumulation and interface failure problems caused by CTE mismatch at the diamond / silicon heterostructure interface, such as debonding and crack propagation, lead to failure of the heat conduction path; 2. Stress concentration in the 2nm GAA microstructure causes threshold voltage drift, increased leakage current, and decreased operating frequency. 3. Traditional thermal interface materials (TIMs) have low thermal conductivity, which severely offsets the high thermal conductivity advantage of diamond, creating a new thermal bottleneck.

[0004] Existing technologies typically employ thick thermal interface materials or flexible solders for buffering, but the thermal conductivity of such materials is generally below 20 W / (m·K), which cannot meet the requirements of both high heat dissipation and low stress. At the same time, existing interface structures do not achieve a continuous gradient transition of the coefficient of thermal expansion, which cannot fundamentally solve the problem of abrupt stress change at heterogeneous interfaces and makes it difficult to meet the long-term reliability requirements of 2nm GAA chips under ultra-high speed and high power at 3.2T. Summary of the Invention

[0005] The purpose of this invention is to provide a gradient transition and stress buffering GAA heterogeneous stacked structure and its preparation method, so as to achieve a continuous gradient transition of the coefficient of thermal expansion and solve the problem of abrupt stress change at the heterogeneous interface.

[0006] The objective of this invention is achieved through the following technical solution: A gradient transition and stress buffering GAA heterostructure includes: Multiple GAA stacked wafers stacked together, each GAA stacked wafer containing: Diamond interlayer serves as a heat dissipation substrate; A gradient layer symmetrically arranged on both sides of the diamond interlayer, wherein the gradient layer is Al X Ga 1-X The N-material composition gradient layer, in which the aluminum composition x changes linearly and continuously from the diamond interlayer side outwards, achieves a linear and smooth transition of the coefficient of thermal expansion; A 2nm GAA circuit structure disposed outside the gradient layer, and a dielectric layer located between the 2nm GAA circuit structure and the gradient layer. Electrical connections between two adjacent GAA stacked wafers are achieved through microbumps; The encapsulation layer is formed by integral plastic sealing, and the encapsulation layer is provided with thermally conductive microchannels for connection with an external cooling system.

[0007] As a further improvement of the present invention, the aluminum component x varies in the range of 0.7→0.2, and the linearity of the component is controlled within 3%; the thickness of the gradient layer is 100-500nm, and the thermal conductivity is ≥150W / (m·K).

[0008] As a further improvement of the present invention, the diamond interlayer is any one of single crystal diamond, polycrystalline diamond or boron-doped diamond, with a thickness of 50-200 μm, thermal conductivity ≥1800 W / (m·K), and surface roughness Ra≤0.5 nm.

[0009] As a further improvement of the present invention, the dielectric layer is a SiO2 coating with a thickness of ≤5nm, which is deposited by ALD or PECVD and activated by O2 plasma, and its surface contact angle is <5°.

[0010] As a further improvement of the present invention, the encapsulation layer is made of high thermal conductivity epoxy resin or ceramic-based encapsulation material; the thermally conductive microchannel is a micron-scale mesh structure, which is made by photolithography etching or laser engraving process.

[0011] A method for fabricating a gradient transition and stress buffering GAA heterostructure includes the following steps: Step 1: Polish and microwave plasma clean the surface of the diamond interlayer; Step 2: Deposit Al on one side of the diamond interlayer using chemical vapor deposition. X Ga 1-X The gradient layer of material N is named the first gradient layer, in which the aluminum component x changes linearly and continuously from one side of the diamond interlayer outwards. Step 3: Perform residual stress testing on the first gradient layer to ensure that the residual stress is <200MPa; then prepare a SiO2 coating on the surface of the first gradient layer as a dielectric layer, named the first dielectric layer, and perform O2 plasma activation. Step 4: Provide a first wafer, which is composed of a 2nm GAA circuit structure A and a silicon substrate A bonded together. Thin one side of the silicon substrate A to 30-50μm, and prepare a SiO2 coating on the thinned back side as a second dielectric layer and activate it. Step 5: Align the thinned back side of the first wafer with the first gradient layer, and connect them using a low-temperature hybrid bonding process. The bonding temperature is 180℃, the pressure is 5kN, and the holding pressure is 10min, followed by annealing. Step 6: Symmetrically deposit Al on the other side of the diamond interlayer. X Ga 1-X The gradient layer of material N is named the second gradient layer, and the second wafer is bonded to the second gradient layer using the same process to form a symmetrical stacked structure. Step 7: Peel off the glass substrate, remove residual adhesive, clean and dry to obtain GAA stacked wafers; Step 8: Stack multiple GAA stacked wafers in multiple layers using pre-fabricated microbumps and copper-copper bonding, then encapsulate them to form an encapsulation layer, and fabricate thermally conductive microchannels within the encapsulation layer for connection to an external cooling system.

[0012] As a further improvement of the present invention, the first gradient layer and the second gradient layer are the same, with a thickness of 100-500 nm, the aluminum component x varies from 0.7 to 0.2, and the linearity of the composition is controlled within 3%.

[0013] As a further improvement of the present invention, the low-temperature hybrid bonding process in step 5 includes: a heating rate of 5°C / min, a post-bonding annealing temperature of 150°C, and a multi-stage slow backpressure method for depressurization; the post-bonding testing standards are: bond strength > 55 MPa, and airtightness leakage rate < 1 × 10⁻⁶. -9 Pa·m³ / s, shear strength > 60MPa.

[0014] As a further improvement of the present invention, the laser ablation parameters in step 7 are: wavelength 355nm, power 8W, energy 200mJ / cm²; cleaning is performed by immersion in organic solvent combined with ultrasonic cleaning at 50°C for 5 minutes; and transfer is performed by non-contact transfer using a Bernoulli arm.

[0015] As a further improvement of the present invention, in step 8, before stacking, microbumps made of high thermal conductivity copper alloy are prefabricated on the surface of the 2nm GAA circuit structure of each GAA stacking wafer, with a stacking alignment accuracy of ≤±0.5µm and copper-copper bonding is used; the thermally conductive microchannel is a micron-level mesh structure and is connected to the external cooling system.

[0016] The above technical solution has the following beneficial effects: 1. Eliminate thermal expansion coefficient mismatch stress: By placing Al between the diamond and silicon-based GAA circuitsX Ga 1-X A graded gradient N-component layer (aluminum component linearly decreasing from 0.7 to 0.2) was used to achieve a coefficient of thermal expansion (CTE) of (1-2)×10⁻⁶ for diamond. -6 / K to silicon (2.6-3.3)×10 -6 The continuous and smooth transition of / K fundamentally avoids stress concentration caused by CTE abrupt changes at heterogeneous interfaces, effectively solving interface failure problems such as debonding and crack propagation in traditional structures.

[0017] 2. Protect the electrical performance of the 2nm GAA microstructure: The gradient layer, as an "atomic-level spring", can decompose the stress abrupt change between heterogeneous layers, keeping the residual stress at the interface below 200MPa, avoiding stress transmission to the 2nm GAA circuit structure, thereby preventing threshold voltage drift, leakage current increase and operating frequency decay, and ensuring electrical stability under ultra-high speed (3.2T) high power.

[0018] 3. Significantly reduced interfacial thermal resistance: The gradient layer has a thermal conductivity of ≥150W / (m·K). Combined with an ultra-thin (≤5nm) SiO2 dielectric layer and a low-temperature hybrid bonding process, the total thermal resistance of the heterogeneous interface is reduced by more than 40%, giving full play to the high thermal conductivity advantage of diamond (≥1800W / (m·K)) and breaking through the thermal bottleneck caused by traditional thermal interface materials (<20W / (m·K)).

[0019] 4. Symmetrical stacking structure improves heat dissipation and integration: With the diamond sandwich layer as the center, gradient layers and 2nm GAA circuits are symmetrically arranged on both sides to form a double-sided integrated structure. This forms a stacked structure with repeating units, improving process flexibility and making it easy to add or remove layers. This achieves double the computing power within the same package volume. At the same time, the multi-layer stacking achieves three-dimensional heat dissipation through copper-copper bonding and built-in thermally conductive microchannels, which greatly improves heat exchange efficiency.

[0020] 5. High reliability bonding and long-term stability: Utilizing a 180℃ low-temperature hybrid bonding process, the bond strength is >55MPa, shear strength >60MPa, and airtightness leakage rate <1×10⁻⁶. -9 Pa·m³ / s, combined with multi-stage slow back pressure and annealing treatment, avoids thermal stress damage. After 1000 thermal cycle tests at -40℃ to 125℃, there is no debonding or cracking at the interface, and the electrical properties do not drift, meeting the long-term reliability requirements.

[0021] 6. Process compatibility and yield assurance: Through precise control such as microwave plasma cleaning (contact angle < 5°), R-corner edge grinding, real-time Raman stress monitoring, and Bernoulli non-contact transfer, thin wafer breakage, residual adhesive contamination and electrostatic breakdown are effectively prevented, ensuring the integrity and process yield of the 2nm GAA structure in the heterogeneous integration process. Attached Figure Description

[0022] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0023] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0024] Figure 1 This is a schematic diagram of the process provided by the present invention.

[0025] Figure 2 This is a schematic diagram of the product structure provided in step 2 of the present invention.

[0026] Figure 3 This is a schematic diagram of the product structure provided in step 4 of the present invention.

[0027] Figure 4 This is a schematic diagram of the product structure provided in step 5 of the present invention.

[0028] Figure 5 This is a schematic diagram of the product structure provided in step 6 of the present invention.

[0029] Figure 6 This is a schematic diagram of the product structure provided in step 7 of the present invention.

[0030] Figure 7 This is a schematic diagram of the product structure provided in step 8 of the present invention.

[0031] In the picture: 1. Diamond interlayer; 21. First gradient layer; 22. Second gradient layer; 31. First dielectric layer; 32. Second dielectric layer; 41. First wafer; 411. 2nm GAA circuit structure A; 412. Silicon substrate A; 42. Second wafer; 421. 2nm GAA circuit structure B; 422. Silicon substrate B; 51. First TBA adhesive; 52. First glass substrate; 53. Second TBA adhesive; 54. Second glass substrate; 6. Microbump; 7. Encapsulation layer; 8. Thermally conductive microchannel; 100. GAA stacked wafer (repeating unit). Detailed Implementation

[0032] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0033] like Figure 1 As shown, a method for fabricating a gradient transition and stress buffering heterogeneous stacked structure of GAA effectively solves the problems of abrupt stress changes between heterogeneous layers, excessively high interface thermal resistance, and insufficient chip heat dissipation in GAA devices, and is adapted to the protection requirements of 2nm GAA circuit structures. The specific steps are as follows: Step 1, Surface Plasma Cleaning: Diamond interlayer 1 is selected as the heat dissipation substrate. First, the surface of diamond interlayer 1 is precision polished to ensure surface flatness meets standards. Then, a microwave plasma cleaning machine is used to clean the polished diamond interlayer 1 to remove adsorbed oil, impurities, and oxide layers, improving the adhesion between the subsequent gradient layer and the diamond interlayer. The cleaning process parameters are controlled as follows: microwave power 300W, cleaning time 60-120s, and continuous introduction of Ar / O2 mixed gas during the cleaning process, with an Ar to O2 volume ratio of 3:1. After cleaning, the contact angle of the diamond interlayer 1 surface is less than 5°.

[0034] The prepared diamond interlayer 1 has a thickness controlled within the range of 50-200 μm, a thermal conductivity of 1800-2200 W / (m・K), and a surface roughness Ra≤0.5 nm. This allows for rapid heat dissipation from hot spots generated during chip operation, preventing heat accumulation from affecting device performance. The diamond interlayer 1 can be made of any of the following: single-crystal diamond, polycrystalline diamond, or boron-doped diamond. Single-crystal diamond is suitable for high precision and high thermal conductivity requirements, polycrystalline diamond is suitable for low-cost, large-scale production requirements, and boron-doped diamond is suitable for requirements that balance high electrical and thermal conductivity. All of these are equivalent implementation methods in this step. To avoid secondary surface contamination after cleaning, the next process must be initiated within 10 minutes of cleaning completion.

[0035] Step 2, Gradient Layer Deposition: Al is deposited on the cleaned side surface of diamond interlayer 1 using vapor deposition. X Ga 1-X The N (aluminum gallium nitride) material composition gradient layer is named the first gradient layer 21. The thickness of the first gradient layer 21 is controlled between 100-500nm, preferably 300nm, and the thickness tolerance is strictly controlled within ±2nm to ensure layer thickness uniformity.

[0036] The above Al X Ga 1-XThe aluminum composition x in N exhibits a linear and continuous variation from the diamond interlayer 1 side outwards, typically ranging from 0.7 to 0.2. The linearity of the composition is controlled within 3%. During deposition, the reactive gas flow rate is strictly controlled to avoid abrupt changes in the aluminum composition, thus achieving a coefficient of thermal expansion (CTE) that decreases from (1–2) × 10⁻⁶ in the diamond interlayer. -6 / K to GAA device requires (2.6–3.3)×10 -6 The linear and smooth transition of / K. The thermal conductivity of the first gradient layer 21 is ≥150W / (m・K), which can reduce the total thermal resistance of the heterostructure interface by more than 40%. As an "atomic-level spring", it can effectively decompose the stress abrupt change between heterostructure layers, establish a stable stress buffer interface, and avoid stress concentration damage to the 2nm GAA circuit structure. The product structure prepared by it is as follows. Figure 2 As shown.

[0037] Step 3, Stress Testing and Activation Bonding: To ensure that the stress state of the first gradient layer 21 meets the requirements of subsequent bonding and device operation, a Raman spectrometer is used to test the residual stress of the first gradient layer 21. During the test, the scanning step is set to 1µm, the number of test points is no less than 9, and the test points are evenly distributed on the surface of the layer to ensure that the test results are representative. The residual stress value must be strictly controlled to be less than 200MPa. If the stress exceeds the standard, the process must be repeated in step 2 until the stress meets the standard.

[0038] After the quality of the first gradient layer 21 is verified to be qualified, a SiO2 coating is prepared on its surface as the first dielectric layer 31. The preparation process can be ALD (atomic layer deposition) or PECVD (plasma-enhanced chemical vapor deposition). Both processes are equivalent implementation methods and can be selected according to actual production conditions. The thickness of the first dielectric layer 31 is controlled within 5nm to ensure that it does not affect the overall performance of the heterostructure.

[0039] After deposition, the surface of the first dielectric layer 31 is activated using O2 plasma with a plasma power of 200W. After activation, the contact angle of the surface of the first dielectric layer 31 must be less than 5° to effectively remove inert groups on the surface, improve the surface activity of the coating, lay the foundation for the subsequent bonding process of heterostructures, and ensure the bonding strength and interfacial stability.

[0040] Step 4: Select the first wafer 41. This first wafer 41 is composed of a 2nm GAA circuit structure A411 and a silicon substrate A412, which are fixed together by a bonding process. The bonding process can be direct bonding, anodic bonding, or other similar implementation methods, both of which can achieve a stable connection between the two and adapt to different production requirements. Subsequently, a back-side thinning machine (Grinder) is used to thin the back side of the first wafer 41 (i.e., the side of the silicon substrate A412). After thinning, the overall thickness of the first wafer 41 is controlled within the range of 30~50µm. The specific value can be flexibly adjusted within this thickness range according to the actual heterogeneous stacking structural requirements.

[0041] During the thinning process, the thinning rate must be strictly controlled to avoid scratches, chipping, and other defects on the surface of the silicon substrate A412 due to excessive speed. The core purpose of the thinning process is to effectively reduce the overall thermal resistance of the heterogeneous stacked structure, ensuring efficient heat conduction from the GAA circuit structure to the diamond interlayer and ensuring device stability. After thinning, the absence of surface defects is confirmed by visual inspection and is considered acceptable. Subsequently, the first TBA adhesive 51 is spin-coated onto the front side of the 2nm GAA circuit structure A411. After the pre-baking process, it is vacuum-bonded onto the first glass substrate 52 to fix the first wafer 41 and provide stable support for subsequent processes.

[0042] It is important to note that applied stress tends to concentrate at the sharp edges of the wafer, leading to corner chipping defects and affecting the integrity of the wafer structure. Therefore, before performing DRIE etching on the first wafer 41, its edges must be micro-grinded with rounded corners. After grinding, the edges must achieve a smooth transition, which can buffer the mechanical impact during handling, reduce crack formation, ensure the integrity of the wafer structure, and provide a guarantee for the smooth progress of subsequent process steps.

[0043] Finally, a SiO2 coating was prepared as the second dielectric layer 32 on the surface of the silicon substrate A412 using either ALD (atomic layer deposition) or PECVD (plasma-enhanced chemical vapor deposition). These two deposition processes are equivalent implementation methods and can be flexibly selected according to production conditions. The thickness of the second dielectric layer 32 was controlled to be within 5 nm. After deposition, the surface was activated using O2 plasma with a power of 200 W. After activation, the surface contact angle needed to be <5° to effectively improve surface bonding activity and prepare for subsequent heterostructure bonding. The resulting product structure is shown below. Figure 3 As shown.

[0044] Step 5: Using a wafer bonding machine, precisely align the thinned back side of the first wafer 41 (i.e., the side of the silicon substrate A412) with the first gradient layer 21. The alignment accuracy is strictly controlled within ≤±0.5µm to ensure accurate bonding of the heterostructure and guarantee subsequent thermal conductivity and electrical performance. At this time, the first dielectric layer 31 and the second dielectric layer 32 are in a plasma-activated state. A low-temperature hybrid bonding process is used to complete the connection between the two. The bonding process parameters must be strictly controlled: the bonding temperature is set to 180℃, the bonding pressure is 5kN, the holding time is 10min, and the heating rate is controlled at 5℃ / min. A programmed temperature rise method can be used to ensure a stable rate.

[0045] After bonding, a low-temperature annealing treatment at 150℃ is performed, followed by gradual cooling and pressure release. A slow, controlled approach is used to ensure a uniform decrease in temperature and pressure, preventing residual stress from rapid temperature and pressure changes that could damage the bonding interface and the thin wafer structure. Because rapid airflow impacts can easily cause severe vibrations in the thin wafer, a multi-stage, slow pressure recovery method is employed during depressurization, gradually restoring atmospheric pressure in stages. This ensures that pressure differences do not cause bursting during the initial bonding process, preserving the product's structural integrity. After bonding, the wafer must be properly stored to avoid severe vibrations and prevent delamination or damage to the bonding interface.

[0046] After bonding is completed, the product undergoes comprehensive testing for bond strength and airtightness. Testing can be performed using tensile testing, airtightness testing equipment, or similar methods. The testing standards are clearly defined: bond strength > 55 MPa, no bubbles or delamination at the bond interface, and airtightness leakage rate < 1 × 10⁻⁶. -9 Only after all test items meet the standards (Pa·m³ / s, shear strength > 60MPa) can the subsequent process steps begin. The structure of the prepared product is as follows: Figure 4 As shown.

[0047] Step 6: First, on the other side of the diamond interlayer 1 where the first gradient layer 21 has not been deposited, deposit Al using the same deposition process as the first gradient layer 21. X Ga 1-X The N (aluminum gallium nitride) material composition gradient layer is named the second gradient layer 22. The second gradient layer 22 has the same structure as the first gradient layer 21. Its aluminum composition x changes linearly and continuously from the diamond interlayer 1 side outward, with a typical range of 0.7→0.2. The linearity of the composition is strictly controlled within 3%. During the deposition process, the flow rate of the reactive gas is strictly controlled to avoid abrupt changes in the aluminum composition, thereby achieving a linear and smooth transition of the coefficient of thermal expansion (CTE). Together with the first gradient layer 21, it forms a symmetrical stress buffer structure, further improving the stress dispersion capability of the overall structure.

[0048] A second wafer 42 is selected. The structure of the second wafer 42 is exactly the same as that of the first wafer 41. Both are composed of a 2nm GAA circuit structure B421 and a silicon substrate B422, which are fixed together by bonding. Subsequently, the silicon substrate B422 is thinned according to the thinning standard of silicon substrate A412 in step 4. After thinning, the overall thickness of the second wafer 42 is kept consistent with that of the first wafer 41 to meet the requirements of symmetrical stacking.

[0049] After thinning to the acceptable level, a second TBA adhesive 53 is spin-coated onto the front side of the 2nm GAA circuit structure B421. After pre-baking, it is vacuum-bonded onto the second glass substrate 54 to achieve stable fixation of the second wafer 42, providing support for subsequent bonding processes. Then, SiO2 coatings are prepared as dielectric layers on the surfaces of the second gradient layer 22 and the silicon substrate B422 respectively using ALD (atomic layer deposition) or PECVD (plasma-enhanced chemical vapor deposition). These two deposition processes are equivalent implementations and can be flexibly selected according to production conditions. After deposition, the surfaces of the two SiO2 coatings are activated using O2 plasma. After activation, the surface contact angle is ensured to be <5°. Then, the second gradient layer 22 is precisely bonded to the silicon substrate B422 using the same low-temperature hybrid bonding process as in step 5, ultimately forming a heterogeneous stacked structure symmetrically distributed on both sides with the diamond interlayer 1 as the center. The resulting product structure is shown in the figure. Figure 5 As shown.

[0050] Step 7, Glass Carrier Stripping and Wafer Cleaning: After the wafers on both sides are bonded, a laser stripper (DB) is used to perform laser stripping on the first glass carrier 52 and the second glass carrier 54 on both sides of the product. During the stripping process, the process parameters must be strictly controlled. The laser wavelength is set to 355nm, the laser power is 8W, and the operating energy is 200mJ / cm². At the same time, the laser path must accurately avoid the core area of ​​the circuit to prevent the laser from damaging the circuit structure.

[0051] After separation from the carrier plate, the product is immersed in an organic solvent, such as acetone or NMP (N-methylpyrrolidone), both of which can effectively dissolve residual first TBA adhesive 51 and second TBA adhesive 53. After immersion, the product is ultrasonically cleaned at a temperature strictly controlled at 50°C for 5 minutes. The ultrasonic vibration completely removes the residual adhesive, preventing it from affecting subsequent processes.

[0052] After ultrasonic cleaning, the product is rinsed multiple times with pure water to thoroughly remove any residual organic solvents and impurities adhering to the surface. It is then dried with nitrogen to ensure no moisture remains on the surface, ultimately yielding GAA stacked wafer 100. The fabricated product structure is as follows... Figure 6As shown. This GAA stacked wafer 100 serves as a repeating unit for subsequent heterogeneous stacking. It adopts a stack structure and can be stacked multiple times according to actual stacking requirements, improving process flexibility and facilitating the addition or removal of layers.

[0053] A Bernoulli arm is used to transfer GAA stacked wafers 100 onto a FOUP (Wafer Transfer Unit). This utilizes the Bernoulli effect to achieve contactless wafer transfer, avoiding direct contact that could cause wafer breakage or damage. After transfer, the following testing requirements must be met: no physical damage to the front-side circuitry, residual adhesive content controlled to within 10 particles, insulation resistance meeting device operating standards, and no electrostatic breakdown. Only after meeting these requirements can the wafer proceed to subsequent stacking or packaging processes.

[0054] Step 8: Multi-wafer stacking to form a heterogeneous structure: Using the multiple GAA stacked wafers 100 prepared in Step 7 as repeated stacking units, a low-temperature bonding process is used to achieve double-sided layer-by-layer stacking, ultimately forming a complete GAA heterogeneous stacked structure. Before stacking, microbumps 6 need to be prefabricated on the 2nm GAA circuit structure surface of each GAA stacked wafer 100 to be stacked. The specifications of the microbumps 6 (including size and spacing) can be flexibly adjusted according to the actual circuit conduction requirements. The material used is a high thermal conductivity copper alloy, which not only ensures circuit conduction efficiency but also lays the foundation for subsequent heat conduction.

[0055] After the microbumps 6 are prefabricated, multiple GAA stacked wafers 100 are precisely aligned and stacked using copper-copper bonding. The alignment accuracy is controlled to ≤±0.5µm according to the standard in step 5 to ensure corresponding circuit conduction. Copper-copper bonding technology enables tight bonding between wafers, ensuring good circuit conduction and stable connection after stacking. At the same time, the high thermal conductivity of copper accelerates heat transfer between adjacent wafers, reduces local heat accumulation, and avoids damage to the circuit structure caused by high temperature. There is no fixed limit to the number of stacked wafers, which can be flexibly set according to the performance requirements of the actual application scenario to adapt to the requirements of devices with different power and integration levels.

[0056] After the multi-wafer stacking is completed, the above products undergo molding to form a dense encapsulation layer 7. Encapsulation layer 7 uses a high thermal conductivity encapsulation material, which combines excellent insulation and thermal conductivity, and can quickly dissipate heat from the wafer surface, further improving the overall heat dissipation capacity. The key to this step is that the encapsulation layer 7 is specially designed with thermally conductive microchannels 8. These microchannels are manufactured using micron-level precision processing technology, and are uniformly distributed in a mesh pattern inside the encapsulation layer, closely adhering to the surface of each wafer, ensuring that the heat generated during wafer operation can be quickly conducted to the microchannels.

[0057] The aforementioned thermally conductive microchannel 8 is seamlessly connected to the external cooling system. The cooling medium circulates within the microchannel, rapidly removing the large amount of heat generated by the wafer through heat exchange. This effectively controls the chip's operating temperature within a safe threshold, preventing issues such as circuit performance degradation, stability reduction, and shortened lifespan caused by high temperatures. This ensures the long-term stable operation of the GAA heterostructure stacked structure, and the resulting product structure is as follows: Figure 7 As shown.

[0058] like Figure 7 As shown, a gradient transition and stress buffering GAA heterogeneous stacked structure is fabricated using the above-described method. Its core structure includes multiple stacked GAA wafers 100. Adjacent GAA wafers 100 are connected electrically by pre-fabricated microbumps 3. The microbumps 3 can be made of high thermal conductivity copper alloy, copper-silver alloy, or other similar materials to ensure smooth signal transmission and reliable contact after stacking, without signal attenuation or poor contact, thus ensuring the stable operation of the overall circuit.

[0059] After multiple GAA stacked wafers 100 are stacked, they undergo molding to form a packaging layer 4. Packaging layer 4 uses a high thermal conductivity and high insulation packaging material, such as high thermal conductivity epoxy resin or ceramic-based packaging materials. This protects the internal stacked structure from damage caused by external impurities and mechanical impacts, while also aiding in heat dissipation from the wafer surface. Simultaneously, thermally conductive microchannels 5 are specifically designed within packaging layer 4. These microchannels are fabricated using micron-level precision processing techniques, such as photolithography or laser engraving. They are uniformly distributed in a mesh pattern within packaging layer 4, tightly adhering to the surface of each GAA stacked wafer 100, for seamless connection with an external cooling system, enabling rapid heat dissipation.

[0060] Each GAA stacked wafer 100 is a double-sided 2nm GAA integrated structure, that is, it has a 2nm GAA circuit structure A411 and a 2nm GAA circuit structure B421 on its two sides respectively. Compared with the traditional single-sided integrated structure, this double-sided integrated design can achieve double the computing power within the same package volume, effectively improving chip integration and computing efficiency, and adapting to the application requirements of high integration and high computing speed.

[0061] Each GAA stacked wafer 100 has a diamond interlayer 1 in the middle, serving as the core heat dissipation substrate. The diamond interlayer 1 uses high thermal conductivity single-crystal diamond, with its thickness controlled within the range of 50-200μm, thermal conductivity ≥1800W / (m・K), and surface roughness Ra≤0.5nm. This allows for rapid heat dissipation from hot spots generated during chip operation, preventing heat accumulation from affecting circuit performance. A first gradient layer 21 and a second gradient layer 22 are symmetrically disposed on both sides of the diamond interlayer 1. Both the first gradient layer 21 and the second gradient layer 22 are deposited Al. X Ga 1-X The N (aluminum gallium nitride) material is a composition gradient layer, in which the aluminum composition x changes linearly and continuously from the diamond interlayer 1 side outwards, with a typical range of 0.7→0.2. The composition linearity is strictly controlled within 3%, achieving a linear and smooth transition of the coefficient of thermal expansion (CTE). This gradient layer acts as an "atomic-level spring," which can effectively decompose stress abrupt changes between heterogeneous layers, avoid stress concentration, and thus protect the corresponding 2nm GAA circuit structure from damage.

[0062] In this design, the first wafer 41 and the second wafer have completely identical structures, and their core components are also identical. Specifically, the 2nm GAA circuit structure A on the first wafer 41 and the 2nm GAA circuit structure B on the second wafer have no difference in structure, performance, or fabrication process, and can be collectively referred to as 2nm GAA circuit structures. The different names are used only to distinguish the corresponding structures on different wafers. Similarly, silicon substrate A and silicon substrate B have completely identical materials and specifications, and can be collectively referred to as silicon substrates; the first gradient layer and the second gradient layer have the same structure, composition, and function, and can be collectively referred to as gradient layers. This unified naming does not change the actual structure and function of each component.

[0063] Long-term reliability verification was conducted on the GAA heterogeneous stacked structure product prepared above to ensure its stable operation in actual working environment. During verification, the product was placed in a temperature cycling chamber with a temperature cycling range of -40℃ to 125℃, and 1000 thermal cycle tests were completed. Each cycle lasted 30 minutes. The heating and cooling rates needed to be controlled steadily to avoid excessively rapid temperature changes that could generate additional stress.

[0064] Upon completion of testing, the product must meet the following standards: no debonding at the bonding interface, no cracks in any structural layer, no drift in the electrical performance of the 2nm GAA circuit structure, all parameters must meet the preset standards, possess excellent long-term reliability, and be suitable for long-term operation.

[0065] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0066] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A gradient transition and stress buffering GAA heterogeneous stacked structure, characterized in that, include: Multiple GAA stacked wafers (100) stacked together, each GAA stacked wafer (100) containing: Diamond interlayer (1) serves as a heat dissipation substrate; A gradient layer symmetrically arranged on both sides of the diamond interlayer (1), wherein the gradient layer is Al X Ga 1-X The N material composition gradient layer, in which the aluminum composition x changes linearly and continuously from the diamond interlayer (1) side outwards, to achieve a linear and smooth transition of the thermal expansion coefficient; A 2nm GAA circuit structure disposed outside the gradient layer, and a dielectric layer located between the 2nm GAA circuit structure and the gradient layer. Electrical connections are achieved between two adjacent GAA stacked wafers (100) through microbumps (6); The encapsulation layer (7) is formed by overall plastic encapsulation, and the encapsulation layer (7) is provided with heat-conducting microchannels (8) for connecting with an external cooling system.

2. The GAA heterogeneous stacking structure according to claim 1, characterized in that, The aluminum component x varies from 0.7 to 0.2, and the linearity of the component is controlled within 3%; the thickness of the gradient layer is 100-500 nm, and the thermal conductivity is ≥150 W / (m·K).

3. The GAA heterogeneous stacking structure according to claim 1, characterized in that, The diamond interlayer (1) is any one of single crystal diamond, polycrystalline diamond or boron-doped diamond, with a thickness of 50-200μm, thermal conductivity ≥1800W / (m·K) and surface roughness Ra≤0.5nm.

4. The GAA heterogeneous stacking structure according to claim 1, characterized in that, The dielectric layer is a SiO2 coating with a thickness of ≤5nm, deposited by ALD or PECVD and activated by O2 plasma, with a surface contact angle of <5°.

5. The GAA heterogeneous stacking structure according to claim 1, characterized in that, The encapsulation layer (7) is made of high thermal conductivity epoxy resin or ceramic-based encapsulation material; the thermally conductive microchannel (8) is a micron-level mesh structure, which is made by photolithography or laser engraving.

6. A method for preparing a GAA heterostructure stacked according to any one of claims 1 to 5, characterized in that, Includes the following steps: Step 1: Polish and microwave plasma clean the surface of the diamond interlayer (1); Step 2: A gradient layer of AlxGa1₋xN material is deposited on one side of the diamond interlayer (1) using vapor deposition method, named the first gradient layer (21), wherein the aluminum composition x changes linearly and continuously from one side of the diamond interlayer (1) outward; Step 3: Perform residual stress test on the first gradient layer (21) to ensure that the residual stress is <200MPa; then prepare a SiO2 coating on the surface of the first gradient layer (21) as a dielectric layer, named the first dielectric layer (31), and perform O2 plasma activation. Step 4: Provide a first wafer (41), which is composed of a 2nm GAA circuit structure A (411) and a silicon substrate A (412) bonded together. Thin one side of the silicon substrate A (412) to 30-50μm, and prepare a SiO2 coating on the thinned back side as a second dielectric layer (32) and activate it. Step 5: Align the thinned back side of the first wafer (41) with the first gradient layer (21), and connect them using a low-temperature hybrid bonding process. The bonding temperature is 180°C, the pressure is 5kN, the holding pressure is 10min, and then the wafer is annealed. Step 6: Symmetrically deposit Al on the other side of the diamond interlayer (1) X Ga 1-X The gradient layer of material N is named the second gradient layer (22), and the second wafer (42) is bonded to the second gradient layer (22) using the same process to form a symmetrical stacked structure; Step 7: Peel off the glass substrate, remove residual adhesive, clean and dry to obtain GAA stacked wafer (100). Step 8: Multiple GAA stacked wafers (100) are stacked in multiple layers through prefabricated microbumps (6) and copper-copper bonding, and then encapsulated to form an encapsulation layer (7). Thermally conductive microchannels (8) are fabricated in the encapsulation layer for connection with an external cooling system.

7. The preparation method according to claim 6, characterized in that, The first gradient layer (21) and the second gradient layer (22) are the same, with a thickness of 100-500nm, and the aluminum composition x varies from 0.7 to 0.2, with the linearity of the composition controlled within 3%.

8. The preparation method according to claim 6, characterized in that, The low-temperature hybrid bonding process described in step 5 includes: a heating rate of 5℃ / min, a post-bonding annealing temperature of 150℃, and a multi-stage slow backpressure method for depressurization; post-bonding testing standards: bond strength > 55MPa, and airtightness leakage rate < 1×10⁻⁶. -9 Pa·m³ / s, shear strength > 60MPa.

9. The preparation method according to claim 6, characterized in that, In step 7, the laser ablation parameters are: wavelength 355nm, power 8W, energy 200mJ / cm²; cleaning is performed by immersion in organic solvent combined with ultrasonic cleaning at 50℃ for 5 minutes; and transfer is performed by non-contact transfer using a Bernoulli arm.

10. The preparation method according to claim 6, characterized in that, In step 8, before stacking, microbumps (6) of high thermal conductivity copper alloy are prefabricated on the surface of the 2nm GAA circuit structure of each GAA stacking wafer (100). The stacking alignment accuracy is ≤ ±0.5µm, and copper-copper bonding is used. The thermally conductive microchannel (8) is a micron-level mesh structure and is connected to the external cooling system.

Images