Semiconductor device and method of manufacturing semiconductor device

Abstract

This invention provides a semiconductor device and a method for fabricating the semiconductor device, comprising: a substrate, a source region, a gate trench, a gate electrode, a dielectric region, and an implantation region; the substrate includes a substrate and an epitaxial layer located on the substrate; the source region is located on the epitaxial layer; the gate trench extends from the top surface of the source region into the epitaxial layer; the gate electrode is located at the bottom of the gate trench; the dielectric region is embedded in the substrate at the bottom of the gate trench, and the top of the dielectric region contacts the bottom of the gate electrode; the implantation region is located in the epitaxial layer on the periphery of the bottom of the gate trench, wherein the bottom surface of the implantation region is lower than the bottom surface of the gate trench, and the upper surface of the implantation region is higher than the upper surface of the gate electrode. This application reduces the gate-drain capacitance between the gate and drain by forming a dielectric region in the substrate between the gate electrode and the drain electrode, i.e., reduces the reverse transfer capacitance and the output capacitance, thereby accelerating the switching speed and reducing switching losses.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for fabricating the semiconductor device. Background Technology

[0002] A junction field-effect transistor (JFET) is a classic voltage-controlled unipolar semiconductor device. Its core structure consists of a reverse-biased PN junction gate formed on both sides of an N-type or P-type semiconductor channel. The width of the depletion region is controlled by adjusting the gate voltage, thereby modulating the channel current between the source and drain. JFETs possess characteristics such as high input impedance, low noise, and high temperature resistance, making them valuable in power conversion, analog circuits, and extreme environment applications.

[0003] However, compared to silicon carbide MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), silicon carbide JFETs have inherent shortcomings in switching performance. Due to differences in device structure, silicon carbide JFETs have larger reverse transfer capacitance (Crss) and output capacitance (Coss), resulting in higher switching losses.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the present invention provides a semiconductor device and a method for fabricating the semiconductor device, which solves the problem that the reverse transfer capacitance (Crss) and output capacitance (Coss) of the JFET device in the prior art are large, resulting in large switching losses.

[0006] To achieve the above and other related objectives, the present invention provides a semiconductor device comprising:

[0007] The substrate includes a substrate and an epitaxial layer located on the substrate;

[0008] The source region is located on the epitaxial layer;

[0009] A gate trench extends from the top surface of the source region into the epitaxial layer;

[0010] The gate electrode is located at the bottom of the gate trench;

[0011] A dielectric region, embedded in the substrate at the bottom of the gate trench, wherein the top of the dielectric region contacts the bottom of the gate electrode; and

[0012] An injection region is located within the epitaxial layer on the bottom periphery of the gate trench; wherein the bottom surface of the injection region is lower than the bottom surface of the gate trench, and the upper surface of the injection region is higher than the upper surface of the gate electrode.

[0013] In one embodiment, the width of the dielectric region is less than or equal to the width of the gate trench.

[0014] In one embodiment, the dielectric constant of the dielectric region is greater than the dielectric constant of the epitaxial layer and the substrate.

[0015] In one embodiment, the dielectric region is made of silicon oxide.

[0016] In one embodiment, the bottom of the dielectric region is located within the epitaxial layer.

[0017] In one embodiment, the dielectric region penetrates the epitaxial layer and extends into a portion of the substrate.

[0018] In one embodiment, the semiconductor device further includes:

[0019] An insulating layer is located on the gate electrode;

[0020] The source electrode is located on the source region;

[0021] The drain electrode is located on the side of the substrate opposite to the source electrode.

[0022] Secondly, this application also provides a method for fabricating a semiconductor device, comprising:

[0023] A substrate is provided, the substrate comprising a substrate and an epitaxial layer located on the substrate;

[0024] A source region is formed on the epitaxial layer;

[0025] The source region and the epitaxial layer are etched to form a gate trench, wherein the gate trench extends from the top surface of the source region into the epitaxial layer;

[0026] An injection region is formed on the periphery of the bottom of the gate trench;

[0027] The substrate located at the bottom of the gate trench is etched to form a dielectric trench, wherein the dielectric trench is located within the substrate at the bottom of the gate trench and is connected to the corresponding gate trench.

[0028] An insulating dielectric material is filled into the dielectric trench to form a dielectric region, wherein the top surface of the insulating dielectric material is flush with the bottom surface of the gate trench;

[0029] A gate electrode is formed on the bottom surface of the gate trench, wherein the bottom surface of the injection region is lower than the bottom surface of the gate trench, and the upper surface of the injection region is higher than the upper surface of the gate electrode.

[0030] In one embodiment, the etching of the substrate at the bottom of the gate trench to form a dielectric trench includes:

[0031] A barrier layer is formed on the inner surface of the gate trench;

[0032] Remove the barrier layer located at the bottom surface of the gate trench, and retain the barrier layer located on the sidewall of the gate trench;

[0033] Based on the retained barrier layer, the substrate is etched to form the dielectric trench at the bottom of the gate trench; and

[0034] Remove the remaining blocking layer.

[0035] In one embodiment, the width of the dielectric region is less than or equal to the width of the gate trench. Attached Figure Description

[0036] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0037] Figure 1 This is a schematic diagram of a semiconductor device 100 provided in one embodiment of this application;

[0038] Figure 2 This is a schematic flowchart of a semiconductor device fabrication method 200 provided in one embodiment of this application;

[0039] Figure 3 This is a schematic diagram of the structure obtained in step S202 of the method for fabricating a semiconductor device provided in one embodiment of this application;

[0040] Figure 4 This is a schematic diagram of the structure obtained in step S204 of the method for fabricating a semiconductor device provided in one embodiment of this application;

[0041] Figure 5 This is a schematic diagram of the structure obtained in step S206 of the method for fabricating a semiconductor device provided in one embodiment of this application;

[0042] Figure 6 This is a schematic diagram of the structure obtained in step S208 of the method for fabricating a semiconductor device provided in one embodiment of this application;

[0043] Figures 7-9 This is a schematic diagram of the structure obtained in step S210 of the method for fabricating a semiconductor device provided in one embodiment of this application;

[0044] Figure 10 This is a schematic diagram of the structure obtained in step S212 of the method for fabricating a semiconductor device provided in one embodiment of this application;

[0045] Figure 11 This is a schematic diagram of the structure obtained in step S214 of the method for fabricating a semiconductor device provided in one embodiment of this application;

[0046] Figure 12 This is a schematic diagram of a semiconductor device 300 provided in another embodiment of this application;

[0047] Figure 13 This is a schematic diagram of a semiconductor device 400 provided in yet another embodiment of this application;

[0048] Figure 14 This is a schematic diagram of a semiconductor device 500 provided in another embodiment of this application.

[0049] Explanation of reference numerals in the attached figures: 110, substrate; 120, epitaxial layer; 130, source region; 140, patterned mask; 151, first gate trench; 153, second gate trench; 160, implantation region; 170, barrier layer; 180, dielectric trench; 190, dielectric region; 210, gate electrode; 220, insulating layer; 230, drain electrode; 240, source electrode. Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0052] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0053] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0054] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0055] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0056] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] As mentioned in the background section, compared to silicon carbide MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), silicon carbide JFETs have inherent limitations in switching performance. Due to differences in device structure, silicon carbide JFETs have larger reverse transfer capacitance (Crss) and output capacitance (Coss), resulting in higher switching losses. The reverse transfer capacitance is equal to the gate-drain capacitance. Since the output capacitance equals the gate-drain capacitance and the drain-source capacitance, but the drain-source capacitance is small and negligible in JFET devices, the output capacitance can be approximated as equal to the gate-drain capacitance.

[0058] Based on the above, please refer to Figure 1One embodiment of this application provides a semiconductor device 100, including: a substrate, a source region 130, a gate trench, a gate electrode 210, a dielectric region 190, and an implantation region 160; wherein, the substrate includes a substrate 110 and an epitaxial layer 120 located on the substrate 110; the source region 130 is located on the epitaxial layer 120; the gate trench extends from the top surface of the source region 130 into the epitaxial layer 120; the gate electrode 210 is located at the bottom of the gate trench; the dielectric region 190 is embedded in the substrate at the bottom of the gate trench, and the top of the dielectric region 190 contacts the bottom of the gate electrode 210; the implantation region 160 is located in the epitaxial layer 120 on the periphery of the bottom of the gate trench, wherein the bottom surface of the implantation region 160 is lower than the bottom surface of the gate trench, and the upper surface of the implantation region 160 is higher than the upper surface of the gate electrode 210.

[0059] In the above embodiments, the semiconductor device includes: a substrate, a source region, a gate trench, a gate electrode, a dielectric region, and an implantation region; the substrate includes a substrate and an epitaxial layer located on the substrate; the source region is located on the epitaxial layer; the gate trench extends from the top surface of the source region into the epitaxial layer; the gate electrode is located at the bottom of the gate trench; the dielectric region is embedded in the substrate at the bottom of the gate trench, and the top of the dielectric region contacts the bottom of the gate electrode; the implantation region is located in the epitaxial layer on the periphery of the bottom of the gate trench, wherein the bottom surface of the implantation region is lower than the bottom surface of the gate trench, and the upper surface of the implantation region is higher than the upper surface of the gate electrode. This application reduces the gate-drain capacitance between the gate and drain by forming a dielectric region in the substrate between the gate electrode and the drain electrode, i.e., reduces the reverse transfer capacitance and the output capacitance, thereby accelerating the switching speed and reducing switching losses.

[0060] As an example, the source region 130, the epitaxial layer 120, and the substrate 110 are doped with a first conductivity type; the implantation region 160 is doped with a second conductivity type.

[0061] As an example, the semiconductor device further includes: an insulating layer 220, a source electrode 240, and a drain electrode 230; wherein the insulating layer 220 is located on the gate electrode 210, and the top surface of the insulating layer 220 is flush with the top surface of the source region 130; the source electrode 240 is located on the source region 130; and the drain electrode 230 is located on the side of the substrate opposite to the source electrode 240.

[0062] As an example, the width of dielectric region 190 is less than or equal to the width of the gate trench. The width of dielectric region 190 affects the facing area between gate electrode 210 and drain electrode 230. The wider dielectric region 190 is, the smaller the facing area between gate electrode 210 and drain electrode 230 is, and the smaller the gate-drain capacitance is. By making the width of dielectric region 190 less than or equal to the width of the gate trench, the gate-drain capacitance can be reduced, thereby reducing the switching losses of the device.

[0063] As an example, the dielectric constant of dielectric region 190 is greater than that of epitaxial layer 120 and substrate 110. By making the dielectric constant of dielectric region 190 greater than that of epitaxial layer 120 and substrate 110, the dielectric constant of the medium between gate electrode 210 and drain electrode 230 is increased, thereby reducing gate-drain capacitance.

[0064] As an example, the dielectric region 190 may be made of silicon oxide. The epitaxial layer 120 and the substrate 110 may be made of silicon carbide.

[0065] As an example, the bottom of dielectric region 190 is located within epitaxial layer 120.

[0066] As an example, the dielectric region 190 penetrates the epitaxial layer 120 and extends into a portion of the substrate 110.

[0067] Please refer to Figure 2 The diagram shows a process flow chart of a semiconductor device fabrication method 200 according to an embodiment of the present invention, which includes at least the following steps:

[0068] Step S202: Provide a substrate, the substrate including a substrate and an epitaxial layer located on the substrate;

[0069] Step S204: Form a source region on the epitaxial layer;

[0070] Step S206: Etch the source region and the epitaxial layer to form a gate trench, wherein the gate trench extends from the top surface of the source region into the epitaxial layer;

[0071] Step S208: Form an implantation region on the periphery of the bottom of the gate trench;

[0072] Step S210: Etch the substrate located at the bottom of the gate trench to form a dielectric trench, wherein the dielectric trench is located in the substrate at the bottom of the gate trench and is connected to the corresponding gate trench.

[0073] Step S212: Fill the dielectric trench with insulating dielectric material to form a dielectric region; the top surface of the insulating dielectric material is flush with the bottom surface of the gate trench;

[0074] Step S214: Form a gate electrode on the bottom surface of the gate trench; wherein the bottom surface of the implantation region is lower than the bottom surface of the gate trench, and the upper surface of the implantation region is higher than the upper surface of the gate electrode.

[0075] The following section, using a structural diagram, details the specific implementation methods for each of the above steps.

[0076] Please refer to the following first. Figure 3 Step S202: Provide a substrate, which includes a substrate 110 and an epitaxial layer 120 located on the substrate 110.

[0077] As an example, substrate 110 may be constructed of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. For example, substrate 110 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, substrate 110 may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0078] As an example, the material of the epitaxial layer 120 may include silicon, silicon carbide, gallium arsenide, gallium nitride, indium phosphide, etc.

[0079] Please refer to Figure 4 Step S204 is executed: a source region 130 is formed on the epitaxial layer 120; wherein the source region 130, the epitaxial layer 120, and the substrate 110 are doped with the first conductivity type.

[0080] As an example, the first conductivity type may include N-type or P-type. A source region 130 can be formed on the upper surface of the epitaxial layer 120 by ion implantation. The implanted ion type may include N-type dopant ions or P-type dopant ions. For example, P-type dopant ions may include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, or indium (In) ions. Similarly, N-type dopant ions may include, but are not limited to, one or more of phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions.

[0081] Please refer to Figure 5 Step S206 is executed: the source region 130 and the epitaxial layer 120 are etched to form a gate trench; wherein the gate trench extends from the top surface of the source region 130 into the epitaxial layer 120.

[0082] As an example, the gate trench may include a plurality of gate trenches spaced apart from each other, for example, the gate trenches include a first gate trench 151 and a second gate trench 153 spaced apart from each other.

[0083] As an example, the source implantation layer 130 and the epitaxial layer 120 can be etched using photolithography or dry etching processes to form a gate trench. The width and depth of the gate trench are not specifically limited in this application and can be set according to the requirements of the fabricated device.

[0084] As an example, etching the source region 130 and the epitaxial layer 120 to form a gate trench includes the steps of: forming a patterned mask 140 on the source region 130; and etching the source region 130 and the epitaxial layer 120 based on the patterned mask 140 to form a gate trench.

[0085] Specifically, the patterned mask 140 includes a window that exposes the gate trench. The source region 130 and the epitaxial layer 120 can be etched using a dry etching process based on the patterned mask 140 to form the gate trench.

[0086] Please refer to Figure 6 Step S208 is executed: an implantation region 160 is formed on the periphery of the gate trench; the implantation region 160 is doped with a second conductivity type.

[0087] As an example, the implantation region 160 can be formed on the periphery of the gate trench based on the patterned mask 140, or the implantation region 160 can be formed by directional implantation on the periphery of the gate trench using a focused ion implantation machine.

[0088] As an example, the second conductivity type is the opposite of the first conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type, and vice versa.

[0089] Please refer to Figures 7-9 Step S210: Etch the substrate located at the bottom of the gate trench to form a dielectric trench 180; wherein the dielectric trench 180 is located in the substrate at the bottom of the gate trench and is connected to the corresponding gate trench.

[0090] As an example, etching the substrate at the bottom of the gate trench to form a dielectric trench 180 includes: forming a barrier layer 170 on the inner surface of the gate trench and on a patterned mask 140; removing the barrier layer 170 on the bottom surface of the gate trench and on the patterned mask 140, retaining the barrier layer 170 on the sidewalls of the gate trench; and etching the substrate based on the retained barrier layer 170 and the patterned mask 140 to form the dielectric trench 180 at the bottom of the gate trench. The barrier layer 170 is used to protect the sidewalls of the gate trench, preventing damage to the sidewalls during the etching of the dielectric trench 180. The material of the barrier layer 170 may include silicon dioxide.

[0091] Specifically, the substrate located at the bottom of the gate trench can be etched using photolithography and dry etching to form a dielectric trench 180. The first gate trench 151 and the second gate trench 153 each correspond to a dielectric trench 180.

[0092] As an example, the width of the dielectric trench 180 is less than or equal to the width of the gate trench.

[0093] In the example above, the width of the dielectric trench 180 is equal to the width of the insulating dielectric material filling the dielectric trench 180. The width of the dielectric trench 180 affects the facing area between the gate electrode and the drain electrode. The wider the dielectric trench 180, the smaller the facing area between the gate electrode and the drain electrode, and the smaller the gate-drain capacitance. By making the width of the dielectric trench 180 less than or equal to the width of the gate trench, the gate-drain capacitance can be reduced, thereby reducing the switching losses of the device.

[0094] As an example, after etching the substrate at the bottom of the gate trench to form the dielectric trench 180, the process further includes removing the remaining barrier layer 170 and the patterned mask 140. Specifically, a wet etching process can be used to remove the remaining barrier layer 170 and the patterned mask 140.

[0095] In the above steps, during the formation of the gate trench, etching can be performed based on the patterned mask 140. After etching to form the gate trench, the patterned mask 140 on the surface of the source region 130 is retained, and ion implantation is performed on the periphery of the gate trench based on the patterned mask 140, saving the mask when forming the implantation region. Secondly, during the formation of the dielectric trench, the patterned mask 140 on the surface of the source region 130 is retained, and the dielectric trench is formed using a self-aligned process. Due to the presence of the patterned mask 140, during the removal of the barrier layer located on the bottom surface of the gate trench and on the patterned mask, the patterned mask 140 can avoid damaging the device film layer, thereby greatly simplifying the process steps and improving the fabrication efficiency.

[0096] Please refer to Figure 10 Step S212: Fill the dielectric trench 180 with insulating dielectric material to form dielectric region 190. Preferably, the top surface of the insulating dielectric material is flush with the bottom surface of the gate trench.

[0097] As an example, insulating dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc.

[0098] Please refer to Figure 11 Step S214 is executed: a gate electrode 210 is formed on the bottom surface of the gate trench; wherein the bottom surface of the injection region 160 is lower than the bottom surface of the gate trench, and the upper surface of the injection region 160 is higher than the upper surface of the gate electrode 210.

[0099] As an example, the material of the gate electrode 210 may include polysilicon, aluminum, tungsten, titanium, gold, silver, titanium nitride, tungsten nitride, and other materials. The gate electrode 210 is in contact with the implantation region 160.

[0100] Please refer to Figure 12The image shows a semiconductor device 300 provided in one embodiment of this application. The method for fabricating the semiconductor device further includes: forming an insulating layer 220 on the gate electrode 210; the insulating layer 220 filling the remaining space of the gate trench.

[0101] As an example, insulating layer 220 is used to isolate the gate electrode 210 from the source region 130. The materials of insulating layer 220 include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, aluminum oxide, hafnium oxide, etc.

[0102] Please refer to Figure 1 After forming an insulating layer 220 on the gate electrode 210, the method further includes: forming a source electrode 240 on at least the source region 130; and forming a drain electrode 230 on the side of the substrate 110 opposite to the source electrode 240.

[0103] As an example, the source electrode 240 may be located on the source region 130, or the source electrode 240 may be located on the source region 130 and the insulating layer 220.

[0104] As an example, the materials of the source electrode 240 and the drain electrode 230 may include aluminum, tungsten, titanium, gold, silver, titanium nitride, tungsten nitride, and other materials.

[0105] Please refer to Figure 13 The semiconductor device 400 provided in one embodiment of this application is shown, wherein the dielectric region 190 penetrates the epitaxial layer 120 and extends into a portion of the substrate 110.

[0106] As an example, the width of dielectric region 190 may be less than or equal to the width of the gate trench.

[0107] Please refer to Figure 14 The image shows a semiconductor device 500 provided in one embodiment of this application, where the bottom of the dielectric region 190 is located within the epitaxial layer 120.

[0108] In summary, the semiconductor device and its fabrication method of the present invention include: a substrate, a source region, a gate trench, a gate electrode, a dielectric region, and an implantation region; the substrate includes a substrate and an epitaxial layer located on the substrate; the source region is located on the epitaxial layer; the gate trench extends from the top surface of the source region into the epitaxial layer; the gate electrode is located at the bottom of the gate trench; the dielectric region is embedded in the substrate at the bottom of the gate trench, and the top of the dielectric region contacts the bottom of the gate electrode; the implantation region is located in the epitaxial layer on the periphery of the bottom of the gate trench, wherein the bottom surface of the implantation region is lower than the bottom surface of the gate trench, and the upper surface of the implantation region is higher than the upper surface of the gate electrode. This application reduces the gate-drain capacitance between the gate and drain by forming a dielectric region in the substrate between the gate electrode and the drain electrode, i.e., reduces the reverse transfer capacitance and the output capacitance, thereby accelerating the switching speed and reducing switching losses. The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention shall still be covered by the claims of this invention.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a substrate and an epitaxial layer located on the substrate; The source region is located on the epitaxial layer; A gate trench extends from the top surface of the source region into the epitaxial layer; The gate electrode is located at the bottom of the gate trench; A dielectric region is embedded in the substrate at the bottom of the gate trench, and the top of the dielectric region is in contact with the bottom of the gate electrode; as well as An injection region is located within the epitaxial layer on the bottom periphery of the gate trench; wherein the bottom surface of the injection region is lower than the bottom surface of the gate trench, and the upper surface of the injection region is higher than the upper surface of the gate electrode.

2. The semiconductor device according to claim 1, characterized in that, The width of the dielectric region is less than or equal to the width of the gate trench.

3. The semiconductor device according to claim 1, characterized in that, The dielectric constant of the dielectric region is greater than the dielectric constant of the epitaxial layer and the substrate.

4. The semiconductor device according to claim 1, characterized in that, The dielectric region is made of silicon oxide.

5. The semiconductor device according to claim 1, characterized in that, The bottom of the dielectric region is located within the epitaxial layer.

6. The semiconductor device according to claim 1, characterized in that, The dielectric region penetrates the epitaxial layer and extends into a portion of the substrate.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: An insulating layer is located on the gate electrode; The source electrode is located on the source region; The drain electrode is located on the side of the substrate opposite to the source electrode.

8. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a substrate and an epitaxial layer located on the substrate; A source region is formed on the epitaxial layer; The source region and the epitaxial layer are etched to form a gate trench, wherein the gate trench extends from the top surface of the source region into the epitaxial layer; An injection region is formed on the periphery of the bottom of the gate trench; The substrate located at the bottom of the gate trench is etched to form a dielectric trench, wherein the dielectric trench is located within the substrate at the bottom of the gate trench and is connected to the corresponding gate trench. An insulating dielectric material is filled into the dielectric trench to form a dielectric region, wherein the top surface of the insulating dielectric material is flush with the bottom surface of the gate trench; A gate electrode is formed on the bottom surface of the gate trench, wherein the bottom surface of the injection region is lower than the bottom surface of the gate trench, and the upper surface of the injection region is higher than the upper surface of the gate electrode.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The etching of the substrate at the bottom of the gate trench forms a dielectric trench, including: A barrier layer is formed on the inner surface of the gate trench; Remove the barrier layer located at the bottom surface of the gate trench, and retain the barrier layer located on the sidewall of the gate trench; Based on the retained barrier layer, the substrate is etched to form the dielectric trench at the bottom of the gate trench; and Remove the remaining blocking layer.

10. The method for fabricating a semiconductor device according to claim 8, characterized in that, The width of the dielectric region is less than or equal to the width of the gate trench.

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