Insulated gate bipolar transistor (IGBT) cutoff layer preparation method, IGBT, chip, and electronic device

Abstract

The application provides an IGBT cutoff layer preparation method, an IGBT, a chip and an electronic device. The IGBT cutoff layer is prepared by a layered epitaxial growth and multi-stage ion implantation mode. A substrate is provided first, then a plurality of epitaxial layers are sequentially grown on the substrate, the thickness and the doping concentration of each epitaxial layer are independently controllable, ion implantation is performed on each epitaxial layer to form an ion implantation layer, and the implantation dose of the ion implantation presents a layer-by-layer decreasing change value on each epitaxial layer, thereby forming a multi-peak doping distribution, and a high-dose implantation region can be formed on each epitaxial layer, the doping concentration is significantly improved, the minority carrier lifetime is shortened, and the turn-off loss, thermal resistance and junction temperature are significantly reduced, thereby effectively improving the performance of the IGBT.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for preparing the cutoff layer of an IGBT, the IGBT, the chip, and electronic equipment. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite power device with advantages such as high input impedance, fast switching speed, and low output impedance.

[0003] In the prior art, some IGBT devices can be implemented using a trench gate and field stop layer (FS) structure, mainly using a single-layer or double-layer epitaxial structure. The fabrication process includes: growing one or more epitaxial layers with different doping concentrations on a substrate as field stop layers, and then forming a gate-controlled MOSFET structure and termination region through front-side processes such as photolithography, ion implantation, and annealing.

[0004] However, existing IGBT devices have significant shortcomings in terms of switching losses, thermal management, and structural integration, making it difficult to meet the stringent requirements of high-frequency, high-power-density applications. Therefore, improving IGBT performance is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] This application provides a method for fabricating the cutoff layer of an IGBT, the IGBT itself, a chip, and an electronic device. The cutoff layer of the IGBT is fabricated by combining multilayer epitaxy with decreasing dose ion implantation, which enables precise control of the field cutoff layer doping concentration, thickness reduction, optimization of electric field distribution, and improved process compatibility. This significantly reduces turn-off loss, thermal resistance, and junction temperature, thereby improving the overall performance of the IGBT.

[0006] The first aspect of this application provides a method for preparing a cutoff layer of an IGBT, comprising: providing a substrate; sequentially growing multiple epitaxial layers on the substrate, and performing ion implantation on each grown epitaxial layer to form an ion implantation layer, thereby forming the cutoff layer of the IGBT; wherein the implantation dose of the ion implantation shows a decreasing trend in each epitaxial layer.

[0007] A second aspect of this application provides an IGBT including a cutoff layer, said cutoff layer being formed by the method described in the first aspect.

[0008] A third aspect of this application provides a chip including the IGBT as described in the second aspect.

[0009] A fourth aspect of this application provides an electronic device including the chip described in the third aspect.

[0010] In summary, the IGBT cutoff layer fabrication method, IGBT, chip, and electronic device provided in this application, and the IGBT cutoff layer fabrication method provided in the embodiments of this application, and the IGBT obtained by this fabrication method, can fabricate the IGBT cutoff layer through layered epitaxial growth and multi-stage ion implantation. First, a substrate is provided, and then multiple epitaxial layers are sequentially grown on the substrate. The thickness and doping concentration of each epitaxial layer are independently controllable. Ion implantation is performed on each epitaxial layer to form an ion implantation layer, and the implantation dose is varied in each epitaxial layer. The progressively decreasing doping values ​​create a multi-peak doping distribution, forming high-dose implantation regions on each epitaxial layer. This significantly increases the doping concentration and shortens the minority carrier lifetime. Consequently, during IGBT turn-off, holes implanted from the back-side P-type emitter recombine rapidly in the highly doped regions, drastically reducing tail current. This allows the electric field to decrease slowly during IGBT turn-off, preventing device failure caused by excessively high dV / dt and voltage peaks due to rapid electric field rise. This significantly reduces turn-off losses and overcomes the high turn-off loss problem caused by low doping in the cutoff layer in existing technologies. Furthermore, the multi-peak doping distribution, through the synergistic effect of layered implantation and epitaxial growth, suppresses the redistribution effect of doped atoms during thermal processing, ensuring doping concentration stability. This guarantees a high repair rate for implanted defects and a high activation rate for implanted ions during subsequent front-side thermal processes, avoiding the low lattice damage repair rate and low ion implantation activation efficiency problems associated with high-energy ion implantation on the back side. This achieves energy efficiency optimization for IGBTs in high-frequency switching scenarios, effectively improving IGBT performance. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic flowchart of an embodiment of a method for preparing a cutoff layer of an IGBT provided in this application;

[0013] Figure 2 A schematic diagram of the first process of the IGBT cutoff layer fabrication method provided in this application;

[0014] Figure 3 A schematic diagram of the second process of the IGBT cutoff layer preparation method provided in this application;

[0015] Figure 4A schematic diagram of the third process of the IGBT cutoff layer preparation method provided in this application;

[0016] Figure 5 A schematic diagram of the fourth process of the IGBT cutoff layer preparation method provided in this application;

[0017] Figure 6 A schematic diagram of the fifth step in the method for preparing the stop layer of the IGBT provided in this application;

[0018] Figure 7 A schematic diagram of the sixth process in the IGBT cutoff layer fabrication method provided in this application;

[0019] Figure 8 This is a schematic diagram of the doping concentration distribution of the stop layer of the IGBT provided in this application.

[0020] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] An Insulated Gate Bipolar Transistor (IGBT) is a composite power device developed based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and the Bipolar Junction Transistor (BJT). It combines the advantages of high input impedance and fast switching speed of MOSFET with the low output impedance of BJT.

[0025] Specifically, IGBTs, as high-voltage, high-current power switching devices, are widely used in industrial motor drives, rail transit traction systems, new energy vehicle electric drive systems, and renewable energy grid-connected inverters. For example, in industrial motor drives, IGBTs need to frequently switch high voltage and high current to control motor speed and torque, and their switching performance directly affects system energy efficiency and reliability. In new energy vehicles, IGBT modules are core components of motor controllers and on-board chargers, requiring them to withstand high power density and fast switching frequencies while maintaining stable operation in high-temperature and high-vibration environments. In photovoltaic inverters and wind power grid-connected systems, IGBTs need to efficiently convert DC to AC, and their conduction and turn-off losses directly affect the overall system conversion efficiency. Furthermore, with the increasing demand for high-power-density power electronic equipment in data centers and smart grids, the application of IGBTs in high-voltage DC transmission and energy storage systems is becoming increasingly widespread. In these scenarios, the performance of IGBT devices directly determines the system's energy efficiency, reliability, thermal management capabilities, and lifespan.

[0026] In existing technologies, some IGBT devices can be implemented using a trench gate and field stop layer (FS) structure, mainly employing single-layer or multi-layer epitaxial structures, typically consisting of a substrate of the first conductivity type (such as N-type) and an epitaxial layer. The stop layer, also known as the field stop layer, can control the electric field distribution through a doping concentration gradient, thereby reducing turn-off losses.

[0027] The existing IGBT cutoff layer fabrication process includes: growing one or more epitaxial layers with different doping concentrations on a substrate as field cutoff layers, and then forming a gate-controlled MOSFET structure and termination region through front-side processes such as photolithography, ion implantation, and annealing.

[0028] However, to prevent self-doping effects and the large-scale diffusion of doped atoms during subsequent heat treatment, the doping concentration of the cutoff layer of existing IGBTs is usually low, resulting in a longer minority carrier lifetime.

[0029] Furthermore, during IGBT turn-off, the holes injected from the P-type emitter on the back recombine slowly in the FS layer, resulting in a large tail current and significantly increasing the turn-off loss E. off .

[0030] To ensure a uniform electric field distribution in the off state, the off layer needs to have a certain thickness, usually exceeding 50μm. This limits the overall thinning of the wafer where the IGBT is located, resulting in a thicker chip, higher thermal resistance after packaging, and increased junction temperature, which in turn affects the reliability, lifespan, and stability of the device under high-temperature conditions.

[0031] Furthermore, in the conventional processes used to prepare the cutoff layer of existing IGBTs, the lattice damage repair rate after high-energy ion implantation on the back side is low, which further limits the improvement of the cutoff layer performance of field IGBTs.

[0032] It can be seen that the cutoff layer and its fabrication method provided by the existing technology for IGBTs have significant shortcomings in terms of switching losses, thermal management and structural integration, making it difficult to meet the stringent requirements of IGBT applications requiring high frequency and high power density.

[0033] Based on this, this application provides a method for preparing the cutoff layer of an IGBT, an IGBT, a chip, and an electronic device. The cutoff layer of the IGBT is prepared by combining multilayer epitaxy with decreasing dose ion implantation, which achieves precise control of the field cutoff layer doping concentration, thickness reduction, electric field distribution optimization, and improved process compatibility, thereby significantly reducing turn-off loss, thermal resistance, and junction temperature, and improving the overall performance of the IGBT.

[0034] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0035] Figure 1 This is a schematic flowchart of an embodiment of a method for fabricating a cutoff layer of an IGBT provided in this application, as shown below. Figure 1 The method for preparing the IGBT cutoff layer shown can be performed by an apparatus for preparing the cutoff layer of an IGBT, specifically, as follows: Figure 1 The method for fabricating the cutoff layer of the IGBT shown includes:

[0036] S101: Provides a substrate.

[0037] In one embodiment, the provided substrate may specifically be a silicon substrate of a first conductivity type, wherein the first conductivity type may be N-type.

[0038] S102: Multiple epitaxial layers are grown sequentially on the substrate, and ion implantation is performed on each grown epitaxial layer to form an implantation layer.

[0039] Figure 2 This is a schematic diagram of the first process of the IGBT cutoff layer fabrication method provided in this application, as shown in the figure. Figure 2 As shown, in S102, a first epitaxial layer 2 of the first conductivity type can first be grown on the substrate 1.

[0040] In one embodiment, the thickness of the first epitaxial layer 2 of the first conductivity type grown on the substrate 1 ranges from 3 μm to 8 μm, and the resistivity is greater than 30 Ω•cm. -2 .

[0041] Figure 3 This is a schematic diagram of the second process of the IGBT cutoff layer fabrication method provided in this application, as shown below. Figure 3 As shown, in S102, ion implantation can then be performed on the first epitaxial layer 2 of the first conductivity type to form the first ion implantation layer 3.

[0042] Understandably, in S102, the process of growing an epitaxial layer and performing ion implantation on the grown epitaxial layer to form an implanted layer will be repeated.

[0043] In this embodiment, a multilayer epitaxial layer comprising three epitaxial layers is used as an example, wherein the three epitaxial layers have the same conductivity type, and their thickness and doping concentration can be independently controlled. For example, the thickness of the first epitaxial layer of the first conductivity type can be 3 μm to 8 μm, and the thickness of the second epitaxial layer of the first conductivity type can be 3 μm to 10 μm, etc. In one embodiment, the first epitaxial layer of the first conductivity type can also be thickened.

[0044] Figure 4This is a schematic diagram of the third process of the IGBT cutoff layer preparation method provided in this application. A second epitaxial layer 4 of the first conductivity type is grown above the first ion implantation layer 3, and ion implantation is performed on the second epitaxial layer 4 of the first conductivity type to form a second ion implantation layer 5.

[0045] Specifically, in this embodiment, the ion implantation dose decreases with each epitaxial layer. Therefore, the ion implantation dose when ion implantation is performed on the second epitaxial layer 4 (first conductivity type) to form the second ion implantation layer 5 is less than the ion implantation dose when ion implantation is performed on the first epitaxial layer 2 (first conductivity type) to form the first ion implantation layer 3.

[0046] Figure 5 This is a schematic diagram of the fourth process of the IGBT cutoff layer preparation method provided in this application. A third epitaxial layer 6 of the first conductivity type is grown above the second ion implantation layer 5, and ion implantation is performed on the third epitaxial layer 6 of the first conductivity type to form a third ion implantation layer 7.

[0047] Accordingly, since the ion implantation dose decreases with each epitaxial layer, for example, the implantation dose of the first layer is 1 × 10⁻⁶. -11 -5×10 -12 cm -2 The dosage is gradually reduced in subsequent stages. This application does not limit the specific value of the implantation dose for each layer. Therefore, the ion implantation dose for forming the third ion implantation layer 7 by ion implantation on the third epitaxial layer 6 of the first conductivity type is less than the ion implantation dose for forming the second ion implantation layer 5 by ion implantation on the second epitaxial layer 4 of the first conductivity type. This design of decreasing implantation dose further optimizes the doping concentration gradient of the cutoff layer, enabling a smooth electric field transition during turn-off of the gradient doped structure. This reduces dV / dt overshoot and abnormal voltage peaks, improving the stability and safety of the device under high voltage and high current conditions. Simultaneously, it increases the minority carrier recombination rate and significantly reduces turn-off losses.

[0048] Furthermore, the uniformity and stability of the multi-peak doping distribution can be further optimized by increasing the number of epitaxial layers and the number of implantation stages. The synergistic effect of multi-layer epitaxy and multi-stage implantation ensures precise control of the doping concentration in the depth direction, improves the electric field modulation capability and minority carrier lifetime control effect of the cutoff layer, thereby further reducing turn-off loss.

[0049] Figure 6 This is a schematic diagram of the fifth step in the IGBT cutoff layer fabrication method provided in this application, as shown below. Figure 6As shown, in one embodiment, after forming three epitaxial layers of multiple epitaxial layers and performing ion implantation to form ion implantation layers, a fourth epitaxial layer of the first conductivity type 8 can be formed above the last formed third ion implantation layer 7.

[0050] In one embodiment, the thickness of the fourth epitaxial layer 8 of the first conductivity type ranges from 3 μm to 10 μm, and its doping concentration ranges from 1 × 10⁻⁶. 14 ㎝ -3 Up to 5×10 14 ㎝ -3 .

[0051] Finally, through the above steps, the IGBT's cutoff layer is formed. Figure 7 This is a schematic diagram of the sixth process in the IGBT cutoff layer fabrication method provided in this application, as shown below. Figure 7 The location of the cutoff layer in the IGBT is shown, specifically including: substrate 1, first epitaxial layer of first conductivity type 2, first ion implantation layer 3, second epitaxial layer of first conductivity type 4, second ion implantation layer 5, third epitaxial layer of first conductivity type 6, third ion implantation layer 7, and fourth epitaxial layer of first conductivity type 8.

[0052] In one embodiment, a fifth epitaxial layer 9 of the first conductivity type can also be deposited on the fourth epitaxial layer 8. The fifth epitaxial layer 9 of the first conductivity type has the lowest epitaxial layer concentration, the highest resistivity, and the thickest thickness.

[0053] In one embodiment, the fifth epitaxial layer 9 of the first conductivity type may be lightly doped, wherein the light doping concentration is less than 1 × 10⁻⁶. 14 ㎝ -3 .

[0054] In one embodiment, after the fifth first conductivity type epitaxial layer 9 is formed and the front-side process is completed, the first conductivity type substrate 1 can be completely removed, and second conductivity type ions can be implanted onto the first first conductivity type epitaxial layer 1 to improve the uniformity and consistency of the IGBT cutoff layer.

[0055] In one embodiment, the first conductivity type ion implantation for forming the first ion implantation layer 3, the second ion implantation layer 5, and the third ion implantation layer 7 provided in this application can all employ arsenic ion implantation, with an implantation dose of 1×10⁻⁶. -11 -5×10 -12 cm -2Arsenic atoms have a lower diffusion coefficient than phosphorus atoms, which can effectively reduce the diffusion of implanted atoms during the subsequent front-side thermal process, thereby reducing the thickness requirements of the first first conductivity type epitaxial layer 2, the second first conductivity type epitaxial layer 4, and the third first conductivity type epitaxial layer 6, and thus reducing the thickness of the IGBT cutoff layer.

[0056] Specifically, before removing all or part of the substrate, the front-side termination region and active region of the IGBT can be formed above the fifth epitaxial layer 9 of the first conductivity type through front-side processes such as photolithography, etching, ion implantation, and annealing. During the front-side annealing process, the implanted arsenic atoms are activated and diffuse to form a stop layer with a multi-peak doped distribution.

[0057] More specifically, during the front annealing process, the atoms implanted in the first ion implantation layer 3, the second ion implantation layer 5, and the third ion implantation layer 7 are activated and redistributed at high temperature to form the field cutoff (FS) layer of the IGBT.

[0058] like Figure 7 As shown, the terminal region and active region forming the IGBT specifically include: a first conductivity type ion implantation doped region 10, a first conductivity type gate electrode region 11, a second conductivity type ion implantation doped region 12, a first conductivity type ion implantation doped region 13, an interlayer isolation layer 14, a second conductivity type ion implantation doped region 15, and an emitter metal 16.

[0059] Furthermore, the wafer with the front-side process completed is thinned to remove all or part of the substrate of the first conductivity type, leaving a substrate thickness of 5-30 μm. After thinning, ion implantation is performed on the remaining epitaxial layer or the back side of the substrate. Specifically, P-type ions can be implanted and laser annealing can be performed to form a heavily doped region of the second conductivity type, namely the collector region 17. Subsequently, metal is deposited on the back side of the collector region 17 to form the collector metal 18.

[0060] In one embodiment, during the thinning process, phosphorus ion implantation can be performed on the back side of the IGBT to adjust the implantation efficiency of the back collector. The implantation energy range during phosphorus ion implantation is 100 keV to 200 keV.

[0061] In summary, the IGBT cutoff layer preparation method provided in this application, and the IGBT obtained by this preparation method, can prepare the IGBT cutoff layer by layered epitaxial growth and multi-stage ion implantation. First, a substrate is provided, and then multiple epitaxial layers are grown sequentially on the substrate. The thickness and doping concentration of each epitaxial layer are independently controllable. Ion implantation is performed on each epitaxial layer to form an ion implantation layer, and the implantation dose of the ion implantation shows a decreasing value layer by layer on each epitaxial layer, thereby forming a multi-peak doping distribution.

[0062] For example, Figure 8 A schematic diagram of the doping concentration distribution of the IGBT cutoff layer provided in this application is shown below. Figure 8 As shown, the doping concentration of the IGBT cutoff layer formed by the preparation method provided in this application has multiple peaks from bottom to top, and these peaks gradually decrease. The cutoff layer with a higher doping concentration has a lower minority carrier lifetime, which allows the holes injected from the back side to recombine more quickly after turn-off, reducing the tail current of the device and lowering the turn-off loss. The thinner field cutoff layer can meet the requirements for thinner chip thickness reduction, thereby reducing the thermal resistance of the chip package and improving the reliability of the device.

[0063] Therefore, this embodiment prepares the IGBT cutoff layer through multilayer epitaxial growth and multi-stage ion implantation, which can form a high-dose implantation region on each epitaxial layer, significantly increasing the doping concentration and shortening the minority carrier lifetime. As a result, when the IGBT is turned off, the holes implanted by the P-type emitter on the back side recombine rapidly in the highly doped region, greatly reducing the tail current. This allows the electric field to decrease slowly when the IGBT is turned off, avoiding device failure caused by factors such as excessive dV / dt and excessive voltage peak caused by rapid rise of the electric field. This significantly reduces turn-off loss and overcomes the problem of high turn-off loss caused by low doping of the cutoff layer in the prior art.

[0064] Furthermore, in the IGBT cutoff layer preparation method provided in this embodiment, the multi-peak doping distribution, through the synergistic effect of layered implantation and epitaxial growth, and the ion implantation method in the epitaxial layer, suppresses the redistribution effect of doped atoms during the heat treatment process, ensuring the stability of the doping concentration. In addition, the subsequent front-side thermal process can guarantee a high repair rate of implanted defects and a high activation rate of implanted ions, avoiding problems such as low lattice damage repair rate and low ion implantation activation efficiency after high-energy ion implantation on the back side. Thus, the energy efficiency optimization of IGBT in high-frequency switching scenarios can be achieved.

[0065] Furthermore, combined Figure 8 As shown in the thickness distribution of the IGBT, the total thickness of the epitaxial layer of the IGBT prepared by the method provided in this application is 20-30 μm, which is lower than the thickness of the field stop layer formed by single-layer thick epitaxy in the prior art, where the thickness of the stop layer is greater than 50 μm. Therefore, this application can also replace the traditional single-layer thick epitaxial structure with layered epitaxial growth, allowing the thickness of each epitaxial layer to be independently controlled, significantly reducing the total thickness. By thinning the field stop layer, the overall chip thickness and packaging thermal resistance are further reduced, enabling thin-chip designs to shorten the heat transfer path, reduce the junction temperature rise, and improve the reliability and lifespan of the device under high-temperature conditions.

[0066] It should be noted that, as Figure 7The IGBT shown here has a cutoff layer consisting of multiple epitaxial layers, specifically three epitaxial layers as an example. In actual implementation, the number of epitaxial layers in the IGBT's cutoff layer can be adjusted according to the switching frequency requirements of different IGBT application scenarios. For example, the number of epitaxial layers can be four or five, thereby adjusting the IGBT's conduction loss E by adjusting the number of peaks in the cutoff layer. on and shutdown loss E off The proportion, etc.

[0067] This application also provides an IGBT, the structure of which can be referred to. Figure 7 As shown, the IGBT includes a cutoff layer, which is formed by the preparation method in any of the foregoing embodiments of this application.

[0068] This application also provides a chip, including the IGBT provided in the above embodiments of this application.

[0069] This application also provides an electronic device, including the chip provided in the above embodiments of this application.

[0070] In the foregoing embodiments of this application, a method for fabricating the cutoff layer of an IGBT provided in this application has been described. To achieve the functions of the methods provided in the embodiments of this application, the fabrication apparatus, as the executing entity, can implement these functions through hardware structures and / or software modules. Whether a particular function is executed through hardware structures, software modules, or a combination of hardware structures and software modules depends on the specific application and design constraints of the technical solution.

[0071] It should be understood that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, a module can be a separately established processing element, or it can be integrated into a chip within the above device. Alternatively, it can be stored as program code in the memory of the above device, and its functions can be called and executed by a processing element of the device. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0072] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to implement a system-on-a-chip (SOC).

[0073] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0074] For example, this application also provides a fabrication apparatus for performing a method for fabricating a cutoff layer of an IGBT. The fabrication apparatus includes one or more processors and a memory. The memory stores computer-executable instructions, and the processors can execute the computer-executable instructions stored in the memory. When the computer-executable instructions are executed by the processor, the processor implements the cutoff layer fabrication method of any of the IGBTs described in the foregoing embodiments of this application.

[0075] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0076] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0077] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0078] This application also provides a chip for executing instructions, which is used to execute the cutoff layer fabrication method of any of the IGBTs described above.

[0079] This application also provides a computer program product, including a computer program that, when executed, implements the cutoff layer preparation method of any of the IGBTs described above.

[0080] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed, can be used to implement the cutoff layer preparation method of any of the IGBTs described above in this application.

[0081] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0082] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0083] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0084] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0086] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for preparing a cutoff layer of an IGBT, characterized in that, include: Provide substrate; Multiple epitaxial layers are sequentially grown on the substrate, and ion implantation is performed on each epitaxial layer to form an ion implantation layer, thereby forming the cutoff layer of the IGBT; wherein the implantation dose of the ion implantation decreases in each epitaxial layer.

2. The method according to claim 1, characterized in that, The multilayer epitaxial layer includes at least three epitaxial layers, each with a thickness ranging from 3 μm to 10 μm, and each epitaxial layer has an independent doping concentration.

3. The method according to claim 2, characterized in that, The ion implantation uses arsenic ions, and the ion implantation dose on each epitaxial layer decreases progressively from the first layer to the last layer. Specifically, the implantation dose in the first layer ranges from 1 × 10⁻⁶. -11 cm -2 Up to 5×10 -12 cm -2 The injection dose in each subsequent layer is reduced compared to the previous layer.

4. The method according to claim 3, characterized in that, After forming the last ion implantation layer, the process further includes: growing a lightly doped epitaxial layer above the last ion implantation layer, wherein the doping concentration of the lightly doped epitaxial layer is less than 1×10⁻⁶. 14 cm -3 The thickness ranges from 3μm to 10μm.

5. The method according to claim 4, characterized in that, After forming the lightly doped epitaxial layer, the method further includes: removing all or part of the substrate, performing ion implantation and laser annealing on the remaining epitaxial layer or the back side of the substrate to form a collector region, and depositing a metal layer on the back side of the collector region as a collector metal.

6. The method according to claim 5, characterized in that, Before removing all or part of the substrate, the process further includes forming the front-side terminal region and the active region of the IGBT by photolithography, etching, ion implantation, and annealing.

7. An IGBT, characterized in that, Includes a stop layer, which is formed by the method described in any one of claims 1-6.

8. The IGBT according to claim 7, characterized in that, The thickness of the stop layer is less than 50 μm.

9. A chip, characterized in that, Including the IGBT as described in claim 8.

10. An electronic device, characterized in that, Includes the chip as described in claim 9.

Images