Three-dimensional structure deep trench super junction and method of manufacturing the same

Abstract

The application provides a three-dimensional structure deep trench super junction and a manufacturing method thereof. The application discloses a three-dimensional structure deep trench super junction and a manufacturing method thereof. The super junction comprises an epitaxial layer with a first conductive type, a first conductive column and at least one group of second conductive columns arranged in the epitaxial layer. The first conductive column is composed of a second conductive type material, and the second conductive column is composed of a first conductive type material and extends along a cross direction. The second conductive column is arranged in cross with the first conductive column, and the first conductive column presents a structure of wide at the top and narrow at the bottom in a cross section along the extending direction of the first conductive column, and presents a structure of narrow at the top and wide at the bottom in a cross section along the cross direction. The application realizes three-dimensional morphology complementation through multiple etching and backfilling in the cross direction, greatly reduces the charge mismatch, improves the breakdown voltage, avoids the filling difficulty of the hole-shaped trench, and reduces the on-resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a three-dimensional deep trench superjunction and its manufacturing method. Background Technology

[0002] In the Deep Trench Super Junction (DT-SJ) process, to ensure the filling capability of the trench, the deep trench must have a certain angle, typically forming a structure that is wider at the top and narrower at the bottom, also known as a "trapezoidal" structure. After the semiconductor material is filled, the resulting pillar structure has the same shape as the deep trench, also exhibiting a trapezoidal shape.

[0003] like Figure 1 The traditional deep trench superjunction structure shown typically consists of alternating N-type pillars and P-type pillars formed on an N-type heavily doped substrate (N+ Sub). When viewed from the front, the etched deep trenches exhibit a trapezoidal shape that is wider at the top and narrower at the bottom to meet the filling requirements of the process, and the P-type pillars formed after backfilling also exhibit a corresponding trapezoidal shape.

[0004] However, this trapezoidal pillar structure introduces unbalanced charges, causing a decrease in the device's breakdown voltage (BV), thus severely hindering further improvements in superjunction performance. Simply put, in traditional deep trench superjunction technology, the trapezoidal deep trenches inevitably lead to a trapezoidal pillar structure, which in turn causes charge mismatch problems. Furthermore, traditional direct-filling of via shapes (such as square, cross-shaped, hexagonal, and triangular) easily leads to filling difficulties and defects such as voids.

[0005] Therefore, how to reduce the charge mismatch of deep trench superjunctions, improve trench filling capacity, and further enhance the overall performance of superjunctions has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The present invention aims to solve the technical problems in the traditional deep trench superjunction process, where the trapezoidal deep trenches inevitably lead to trapezoidal pillar structures, which in turn cause charge mismatch problems and reduce the breakdown voltage of the device, and the traditional direct filling of hole-shaped trenches easily leads to filling difficulties and defects such as voids.

[0007] To address the aforementioned technical problems, this invention provides a three-dimensional deep trench superjunction, comprising:

[0008] An epitaxial layer having a first conductivity type;

[0009] A first conductive pillar is disposed in the epitaxial layer, and the first conductive pillar is made of a semiconductor material having a second conductivity type;

[0010] At least one set of second conductive pillars is disposed in the epitaxial layer, the second conductive pillars being made of a semiconductor material having a first conductivity type, and the at least one set of second conductive pillars extending along at least one intersecting direction;

[0011] Wherein, the at least one intersecting direction has an intersecting angle with the extending direction of the first conductive post, the second conductive post is intersecting with the first conductive post, the first conductive post has a structure that is wider at the top and narrower at the bottom in the cross section along its extending direction, and a structure that is narrower at the top and wider at the bottom in the cross section along the intersecting direction.

[0012] Preferably, the first conductive post has a trapezoidal cross-sectional shape along its extension direction and an inverted trapezoidal cross-sectional shape along the intersecting direction.

[0013] Preferably, the at least one set of second conductive pillars includes multiple sets of second conductive pillars extending along different intersecting directions, and the multiple sets of second conductive pillars are intersecting with the first conductive pillar to form a cell structure with a polygonal surface window, wherein the polygon includes hexagons or triangles.

[0014] Preferably, the epitaxial layer, the semiconductor material having a first conductivity type, and the semiconductor material having a second conductivity type include silicon, germanium, silicon carbide, gallium nitride, or gallium oxide.

[0015] Preferably, the first conductivity type is N-type and the second conductivity type is P-type.

[0016] Preferably, the intersection angle is 30°, 45°, 60° or 90°.

[0017] Preferably, the depth of the second conductive post is greater than the depth of the first conductive post.

[0018] Preferably, the depth of the second conductive post is 0.5 μm to 2 μm deeper than the depth of the first conductive post.

[0019] Preferably, the doping concentration of the semiconductor material having the second conductivity type is 2 to 4 times that of the doping concentration of the epitaxial layer.

[0020] Preferably, the doping concentration of the semiconductor material having the first conductivity type is the same as or higher than the doping concentration of the epitaxial layer.

[0021] This invention also provides a method for manufacturing a three-dimensional deep trench superjunction, comprising:

[0022] Step 1: Form a first hard mask pattern on an epitaxial layer having a first conductivity type;

[0023] Step 2: Perform the first deep trench etching according to the first hard mask pattern to form the first deep trench;

[0024] Step 3: Backfill the first deep trench with a semiconductor material of the second conductivity type and perform planarization treatment;

[0025] Step 4: Form a second hard mask pattern on the epitaxial layer after planarization.

[0026] Step 5: Perform a second deep trench etching according to the second hard mask pattern to form a second deep trench. The extension direction of the second deep trench has an intersection angle with the extension direction of the first deep trench.

[0027] Step 6: Backfill the second deep trench with semiconductor material of the first conductivity type and perform the planarization process.

[0028] Preferably, in step two, the cross-section of the first deep trench has a structure that is wider at the top and narrower at the bottom.

[0029] Preferably, in step three, before backfilling the semiconductor material with the second conductivity type into the first deep trench, the method further includes: growing a sacrificial oxide layer to remove surface damage within the first deep trench, and cleaning the first deep trench.

[0030] Preferably, in step three, the planarization process is performed using a chemical mechanical polishing process.

[0031] Preferably, in step five, the cross-section of the second deep trench has a structure that is wider at the top and narrower at the bottom, so that the semiconductor material with the second conductivity type retained after the second deep trench etching has a structure that is wider at the top and narrower at the bottom in the cross-section along its extension direction, and a structure that is narrower at the top and wider at the bottom in the cross-section along the intersection direction.

[0032] Preferably, in step six, before backfilling the semiconductor material having the first conductivity type into the second deep trench, the method further includes: growing a sacrificial oxide layer to remove surface damage within the second deep trench, and cleaning the second deep trench.

[0033] Preferably, the process parameters for the first deep trench etching and the second deep trench etching are the same or different, and the process parameters include etching angle, etching depth and window size.

[0034] Preferably, both the first deep groove and the second deep groove are open striped deep grooves.

[0035] Preferably, the method further includes: after step six, performing a third or more deep trench etching and backfilling the semiconductor material having the first conductivity type to form a cell structure with polygonal surface windows, the polygons including hexagons or triangles.

[0036] As described above, the three-dimensional deep trench superjunction and its manufacturing method of the present invention have the following beneficial effects:

[0037] This invention utilizes two or more intersecting etching directions at angles to break down the traditional single-stage etching and filling process into multiple open-type striped deep trench etching and filling, effectively avoiding the filling difficulties caused by directly filling viad trenches. Simultaneously, through lateral deep trench etching, the originally single trapezoidal pillar is cut into an inverted trapezoid in the lateral direction, resulting in complementary three-dimensional morphologies of the remaining conductive pillars in the forward and lateral directions. This significantly reduces the unbalanced charge introduced by the single trapezoidal trench, improves the charge mismatch problem, and thus significantly improves the breakdown voltage of the superjunction. Furthermore, the method of this invention enables the fabrication of a closed deep trench cell structure, effectively reducing the pitch size of the superjunction, increasing the effective conduction area, and thereby significantly reducing the on-resistance of the device and improving the overall performance of the superjunction. Attached Figure Description

[0038] Figure 1 The diagram shown is a schematic representation of a deep trench superjunction structure in the prior art.

[0039] Figure 2 The diagram shows a process flow chart of the manufacturing method of the three-dimensional deep trench superjunction of the present invention.

[0040] Figure 3 The diagram shown is a structural schematic of the first deep trench backfilling according to the present invention.

[0041] Figure 4 The diagram shows the structure during the second deep trench etching of the present invention.

[0042] Figure 5 The diagram shown is a structural schematic of the second deep trench backfilling according to the present invention. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] A three-dimensional deep trench superjunction includes an epitaxial layer 102 having a first conductivity type.

[0045] In some embodiments, the epitaxial layer 102 includes silicon, germanium, silicon carbide, gallium nitride, or gallium oxide. The epitaxial layer 102 can be formed on the underlying semiconductor substrate 101 using semiconductor manufacturing processes such as chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, or liquid phase epitaxy. The underlying semiconductor substrate 101 is, for example, a heavily doped N-type silicon substrate, which can be a single-crystal silicon wafer. During the formation of the epitaxial layer 102, in-situ doping processes can be used to introduce impurities of a first conductivity type. Using these semiconductor materials allows for applications with different power levels, switching frequencies, and thermal management requirements. For example, silicon carbide and gallium nitride are suitable for high-frequency, high-voltage, wide-bandgap semiconductor devices, thereby expanding the applicability of the devices in automotive electronics, industrial control, and other fields.

[0046] In other alternative embodiments, the underlying semiconductor substrate 101 is not limited to a heavily doped N-type single-crystal silicon wafer. The underlying semiconductor substrate 101 may include polycrystalline silicon, amorphous silicon, silicon-on-insulator (SOI) substrate, germanium substrate, or silicon-germanium (SiGe) substrate. Furthermore, the underlying semiconductor substrate 101 may also include other compound semiconductor materials, such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb). In certain applications, the underlying semiconductor substrate 101 may also employ non-semiconductor materials as the support substrate, such as sapphire, glass, or quartz substrates. The crystal orientation of the underlying semiconductor substrate 101 can be selected according to the carrier mobility or etching morphology requirements of the device, for example, wafers with (100), (110), or (111) crystal orientations may be used.

[0047] Accordingly, in addition to silicon, germanium, silicon carbide, gallium nitride, or gallium oxide, the epitaxial layer 102 can also include other alloy semiconductors or compound semiconductors. For example, the epitaxial layer 102 may include silicon-germanium alloy (SiGe), silicon-germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or combinations thereof. For wide-bandgap semiconductor applications, the epitaxial layer 102 may also include multilayer heterojunction structures such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). This wide range of material choices allows for flexible customization of devices to meet different breakdown voltage, on-resistance, and switching speed requirements.

[0048] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. N-type dopant may include group 5 elements such as phosphorus, arsenic, or antimony, and P-type dopant may include group 3 elements such as boron, gallium, indium, or boron difluoride. In other alternative embodiments, the first conductivity type may also be P-type and the second conductivity type may be N-type, depending on the design requirements of the specific device, such as an N-channel or P-channel metal-oxide-semiconductor field-effect transistor. A first conductive post 103 is disposed in the epitaxial layer 102 and is made of a semiconductor material having the second conductivity type.

[0049] In some embodiments, the doping concentration of the semiconductor material having the second conductivity type is 2 to 4 times that of the doping concentration of the epitaxial layer 102. For example, the doping concentration of the first conductive pillar 103 can be 3 times that of the epitaxial layer 102. By reasonably configuring the doping concentration ratio, it is helpful to achieve a better charge balance in the three-dimensional space of the superjunction structure. Specifically, when the device is in a reverse bias state, the first conductive pillar 103 and the surrounding epitaxial layer 102 and second conductive pillar 105 deplete each other. Precise concentration matching can ensure that the positive and negative space charges in the depletion layer cancel each other out, avoid the premature appearance of local electric field peaks, and thus improve the overall breakdown voltage of the device. At least one set of second conductive pillars 105 is disposed in the epitaxial layer 102. The second conductive pillars 105 are made of semiconductor material having the first conductivity type, and the at least one set of second conductive pillars 105 extends along at least one intersecting direction.

[0050] In some embodiments, the doping concentration of the semiconductor material having a first conductivity type is the same as or higher than the doping concentration of the epitaxial layer 102. This doping concentration setting helps to provide a low-impedance conduction path for majority carriers, thereby reducing the on-resistance of the device and improving current conduction capability. In actual manufacturing, this concentration can be precisely controlled by adjusting the dopant gas flow rate during the epitaxial growth process.

[0051] In some embodiments, the depth of the second conductive post 105 is greater than the depth of the first conductive post 103. In some embodiments, the depth of the second conductive post 105 is 0.5 μm to 2 μm deeper than the depth of the first conductive post 103, for example, 1 μm deeper. By making the second conductive post 105 slightly deeper than the first conductive post 103, good electrical connection and physical isolation can be ensured at the bottom of the intersection area. This depth difference design can effectively avoid the electric field concentration effect at the bottom corner, prevent the device from prematurely breaking down at the bottom, and thus improve the reliability of the device.

[0052] In some embodiments, at least one set of second conductive pillars 105 includes multiple sets of second conductive pillars 105 extending along different intersecting directions. These multiple sets of second conductive pillars 105 intersect with the first conductive pillar 103 to form a cell structure with a polygonal surface window. The polygon includes hexagons or triangles. This polygonal cell structure can further optimize the surface electric field distribution and eliminate electric field congestion at the corners of traditional square cells. Simultaneously, the polygonal layout can improve the cell packaging density and effective conductive area, thereby achieving lower on-resistance within the same chip size. At least one intersecting direction has an intersecting angle with the extending direction of the first conductive pillar 103. The second conductive pillars 105 intersect with the first conductive pillar 103. The first conductive pillar 103 has a top-wide, bottom-narrow structure in its cross-section along its extending direction and a top-narrow, bottom-wide structure in its cross-section along the intersecting direction.

[0053] In some embodiments, the cross angle is 30°, 45°, 60°, or 90°. Different cross angles can be selected according to specific cell design requirements. For example, a 90° cross can form a regular grid structure, which facilitates the design and alignment of the mask; while a 60° cross is conducive to forming a high-density hexagonal honeycomb structure to achieve specific device performance optimization and more uniform current distribution.

[0054] Furthermore, the cross angle is not limited to the specific values ​​listed above. In other alternative embodiments, the cross angle can also be any other angle greater than 0° and less than 180°. This flexible angle selection provides greater freedom for chip layout design. For example, to avoid specific crystal orientations of semiconductor wafers to optimize the etch sidewall flatness of deep trenches, or to obtain higher carrier mobility in specific crystallographic directions, designers can fine-tune the cross angle to non-standard values. Simultaneously, in designs with asymmetric cell layouts or special edge termination structures, using cross etching at other arbitrary angles can better match the boundary shape of peripheral circuits, achieving a smoother electric field transition, thereby further improving the overall reliability and design flexibility of the device.

[0055] In some embodiments, the first conductive pillar 103 has a trapezoidal cross-sectional shape along its extension direction and an inverted trapezoidal cross-sectional shape along the intersection direction. This combination of trapezoidal and inverted trapezoidal three-dimensional morphology allows for complementary space charges in both the forward and lateral directions. Conventional single trapezoidal trenches suffer from insufficient doping in the bottom region due to reduced width, leading to charge mismatch. This embodiment compensates for the charge deficiency at the bottom by using inverted trapezoidal cuts in the lateral direction, significantly reducing the unbalanced charge introduced by a single trapezoidal trench. According to TCAD simulation data, under conditions of a 1 Ω·cm N-type substrate, a trench depth of 45 μm, a critical dimension of 4 μm, and an angle of 89°, the superjunction structure of this embodiment exhibits a breakdown voltage exceeding 700 V, which is more than 100 V higher than that of conventional deep trench superjunctions. Simultaneously, at the same breakdown voltage, the doping concentration of this embodiment is 2.5 times greater than that of the conventional structure, the conduction area is approximately 3 / 4, and the on-resistance is reduced by approximately 70% compared to the conventional structure.

[0056] A method for manufacturing a three-dimensional deep trench superjunction, the process flow of which is as follows: Figure 2 As shown, it includes:

[0057] Step 1: Form a first hard mask pattern on the epitaxial layer 102 having a first conductivity type.

[0058] In some embodiments, the material of the first hard mask pattern may include silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, spin-coated glass, or a composite stack thereof. The process for forming the first hard mask pattern may include deposition processes such as low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. Subsequently, photoresist is coated on the hard mask layer, and exposed and developed using a deep ultraviolet lithography or extreme ultraviolet lithography machine to form a photoresist pattern. Next, using dry etching equipment such as reactive ion etching or inductively coupled plasma etching, a fluorine-containing gas such as carbon tetrafluoride, trifluoromethane, or sulfur hexafluoride is used as the etching gas to transfer the photoresist pattern onto the hard mask layer. Finally, the remaining photoresist is removed by an ashing process or wet stripping.

[0059] Step 2: Perform the first deep trench etching based on the first hard mask pattern to form the first deep trench.

[0060] In some embodiments, in step two, the cross-section of the first deep trench has a structure that is wider at the top and narrower at the bottom.

[0061] In some embodiments, both the first and second deep trenches are open-type striped deep trenches. Breaking down the traditional single-stage etching and filling process into multiple etching and filling operations using open-type striped deep trenches effectively avoids the filling difficulties such as voids, gaps, or microtubes that easily occur when directly filling hole-shaped trenches, such as square, cross-shaped, or hexagonal holes. Open-type striped trenches have a larger opening area and better gas flow, making it easier for reactive gases to enter the bottom of the trench, thereby improving the quality of epitaxial filling and process yield. The first deep trench etching can employ deep reactive ion etching (DRIE), such as the Bosch process, to achieve high aspect ratio trench etching by alternating etching and passivation steps. During the etching process, the tilt angle of the trench sidewalls can be precisely controlled by adjusting parameters such as the ratio of etching gas to passivation gas, RF bias power, and chamber pressure to form the desired top-wide, bottom-narrow structure.

[0062] Step 3: Backfill the first deep trench with semiconductor material of the second conductivity type and perform planarization treatment.

[0063] like Figure 3 As shown, the first conductive pillar 103 fills the first deep trench and is formed in the epitaxial layer 102 on the substrate 101.

[0064] In some embodiments, step three, before backfilling the first deep trench with a semiconductor material of a second conductivity type, further includes: growing a sacrificial oxide layer to remove surface damage within the first deep trench and cleaning the first deep trench. High-energy plasma etching processes typically introduce lattice damage, dangling bonds, and polymer residues into the trench sidewalls. Damaged silicon layers can be consumed by growing a sacrificial oxide layer on the inner surface of the trench through a thermal oxidation process in an oxygen-containing atmosphere, such as dry or wet oxidation. Subsequently, these damages can be effectively eliminated by removing the sacrificial oxide layer using a wet etching process such as dilute hydrofluoric acid or a buffered oxide etchant. After removing the sacrificial oxide layer, standard cleaning processes such as RCA cleaning, sulfuric acid-hydrogen peroxide mixture cleaning, or ammonia-hydrogen peroxide mixture cleaning can be used to further remove surface particles, organic matter, and metal ion contamination, thereby providing an atomically smooth and clean interface for subsequent high-quality epitaxial growth.

[0065] In some embodiments, step three, the planarization process employs chemical mechanical polishing (CMP). The backfill process can utilize high-temperature epitaxial growth techniques, such as atmospheric pressure chemical vapor deposition (CVD) or reduced pressure CVD, introducing a silicon source gas, such as silane or dichlorosilane, and a dopant gas, such as diborane, to form a defect-free P-type semiconductor material. Since epitaxial growth typically extends beyond the top of the trench and forms a capping layer on the epitaxial layer surface, planarization is necessary. CMP utilizes a polishing slurry containing abrasive particles, such as silicon dioxide or cerium oxide, combined with the mechanical friction and chemical etching of the polishing pad, to remove excess semiconductor material and stops polishing when a hard mask layer or epitaxial layer surface is detected. This process provides a globally planarized surface, eliminating surface morphology undulations and providing a good morphological basis for subsequent photolithography and etching processes. After polishing, brushing and megasonic cleaning are typically performed to remove residual polishing slurry particles from the surface.

[0066] Step 4: Form a second hard mask pattern 104 on the planarized epitaxial layer 102.

[0067] In some embodiments, the formation process of the second hard mask pattern 104 is similar to that of the first hard mask pattern, also including steps such as thin film deposition, photolithography, and etching. The material of the second hard mask 104 can be the same as or different from that of the first hard mask to provide sufficient etching selectivity. In the photolithography step, the same mask can be used for exposure by rotating it at a certain angle, or different masks can be used for photolithographic pattern transfer. A high-precision alignment system ensures that the second hard mask pattern 104 forms a predetermined intersection angle with the filled first conductive pillars 103.

[0068] Step 5: Perform a second deep trench etching according to the second hard mask pattern 104 to form a second deep trench. The extension direction of the second deep trench has an intersection angle with the extension direction of the first deep trench.

[0069] like Figure 4 As shown, the second deep trench etching is performed perpendicular to the direction of the first conductive pillar 103, and the etching depth is deeper than that of the first time, forming an over-etched region that enters the epitaxial layer 102.

[0070] In some embodiments, in step five, the cross-section of the second deep trench has a structure that is wider at the top and narrower at the bottom. This results in the semiconductor material with the second conductivity type retained after the second deep trench etching having a structure that is wider at the top and narrower at the bottom in the cross-section along its extension direction, and narrower at the top and wider at the bottom in the cross-section along the intersection direction. By adding a first lateral deep trench etching, the originally single trapezoidal pillar is cut into an inverted trapezoid in the lateral direction. This three-dimensional morphology reshaping makes the retained first conductive pillar 103 exhibit complementary geometries in different cross-sections, and the two complement each other to achieve charge balance. The second deep trench etching can also adopt a deep reactive ion etching process. Since it is necessary to etch through the previously filled semiconductor material and part of the epitaxial layer, the selection of etching gas and the adjustment of process parameters need to take into account the consistency of etching rate in different regions to ensure the flatness of the trench bottom.

[0071] In some embodiments, the process parameters for the first and second deep trench etching may be the same or different, including etching angle, etching depth, and window size. For example, the pitch ratio of the first to the second deep trench etching can be 3:2, with both etching angles at 89°. Alternatively, the pitch ratio of the first deep trench etching can be 4:5, the etching angle 89.1°, and the etching depth 55µm; the pitch ratio of the second deep trench etching can be 3:4, the etching angle 88.6°, and the etching depth 56µm. By flexibly adjusting the parameters of the two etching processes, the upper and lower window areas of the deep trench can be made nearly equal, further optimizing the electric field distribution and carrier transport characteristics within the device.

[0072] Step 6: Backfill the second deep trench with semiconductor material of the first conductivity type and perform planarization treatment.

[0073] like Figure 5 As shown, the second conductive post 105 fills the second deep trench, ultimately forming a three-dimensional superjunction structure composed of the intersection of the first conductive post 103 and the second conductive post 105.

[0074] In some embodiments, step six, before backfilling the second deep trench with a semiconductor material of the first conductivity type, further includes: growing a sacrificial oxide layer to remove surface damage within the second deep trench, and cleaning the second deep trench. The damage removal and cleaning processes here are similar to those in step three, aiming to ensure the quality of the second backfill interface. The second backfill process can also employ high-temperature epitaxial growth technology, introducing a doping gas of the same conductivity type as the epitaxial layer 102, such as phosphine or arsine, to form an N-type semiconductor material. The subsequent planarization process again utilizes a chemical mechanical polishing process to remove excess material, completing the basic fabrication of the three-dimensional cross-junction structure.

[0075] In some embodiments, the method further includes: after step six, performing a third and subsequent deep trench etching and backfilling with a semiconductor material of a first conductivity type to form a cell structure with polygonal surface windows, the polygons including hexagons or triangles. Through multiple cycles of cross-etching and backfilling, a closed deep trench cell structure can be fabricated. This multi-cross process effectively reduces the pitch size of the superjunction, allowing for the fabrication of smaller pillar-structured superjunctions within the same chip area. Since the pillar regions of a superjunction are generally considered non-conductive depletion regions, reducing the pillar size and optimizing their arrangement can significantly increase the effective conduction area of ​​the device, thereby further reducing the on-resistance while maintaining a high breakdown voltage, and improving the overall power density and switching efficiency of the device.

[0076] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A three-dimensional deep trench superjunction, characterized in that, include: An epitaxial layer having a first conductivity type; A first conductive pillar is disposed in the epitaxial layer, and the first conductive pillar is made of a semiconductor material having a second conductivity type; At least one set of second conductive pillars is disposed in the epitaxial layer, the second conductive pillars being made of a semiconductor material having a first conductivity type, and the at least one set of second conductive pillars extending along at least one intersecting direction; Wherein, the at least one intersecting direction has an intersecting angle with the extending direction of the first conductive post, the second conductive post is intersecting with the first conductive post, the first conductive post has a structure that is wider at the top and narrower at the bottom in the cross section along its extending direction, and a structure that is narrower at the top and wider at the bottom in the cross section along the intersecting direction.

2. The three-dimensional deep trench superjunction according to claim 1, characterized in that: The first conductive post has a trapezoidal cross-sectional shape along its extension direction and an inverted trapezoidal cross-sectional shape along the intersecting direction.

3. The three-dimensional deep trench superjunction according to claim 1, characterized in that: The at least one set of second conductive pillars includes multiple sets of second conductive pillars extending along different intersecting directions. The multiple sets of second conductive pillars are intersected with the first conductive pillar to form a cell structure with a polygonal surface window, wherein the polygon includes hexagons or triangles.

4. The three-dimensional deep trench superjunction according to claim 1, characterized in that: The epitaxial layer, the semiconductor material having a first conductivity type, and the semiconductor material having a second conductivity type include silicon, germanium, silicon carbide, gallium nitride, or gallium oxide.

5. The three-dimensional deep trench superjunction according to claim 1, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type.

6. The three-dimensional deep trench superjunction according to claim 1, characterized in that: The intersection angle is 30°, 45°, 60° or 90°.

7. The three-dimensional deep trench superjunction according to claim 1, characterized in that: The depth of the second conductive post is greater than the depth of the first conductive post.

8. The three-dimensional deep trench superjunction according to claim 7, characterized in that: The depth of the second conductive post is 0.5 μm to 2 μm deeper than the depth of the first conductive post.

9. The three-dimensional deep trench superjunction according to claim 1, characterized in that: The doping concentration of the semiconductor material having the second conductivity type is 2 to 4 times that of the doping concentration of the epitaxial layer.

10. The three-dimensional deep trench superjunction according to claim 1, characterized in that: The doping concentration of the semiconductor material having the first conductivity type is the same as or higher than the doping concentration of the epitaxial layer.

11. A method for manufacturing a three-dimensional deep trench superjunction as described in any one of claims 1 to 10, characterized in that, include: Step 1: Form a first hard mask pattern on an epitaxial layer having a first conductivity type; Step 2: Perform the first deep trench etching according to the first hard mask pattern to form the first deep trench; Step 3: Backfill the first deep trench with a semiconductor material of the second conductivity type and perform planarization treatment; Step 4: Form a second hard mask pattern on the epitaxial layer after planarization. Step 5: Perform a second deep trench etching according to the second hard mask pattern to form a second deep trench. The extension direction of the second deep trench has an intersection angle with the extension direction of the first deep trench. Step 6: Backfill the second deep trench with semiconductor material of the first conductivity type and perform the planarization process.

12. The method for manufacturing a three-dimensional deep trench superjunction according to claim 11, characterized in that: In step two, the cross-section of the first deep trench has a structure that is wider at the top and narrower at the bottom.

13. The method for manufacturing a three-dimensional deep trench superjunction according to claim 11, characterized in that: In step three, before backfilling the semiconductor material with the second conductivity type into the first deep trench, the method further includes: growing a sacrificial oxide layer to remove surface damage within the first deep trench, and cleaning the first deep trench.

14. The method for manufacturing a three-dimensional deep trench superjunction according to claim 11, characterized in that: In step three, the planarization process is performed using a chemical mechanical polishing process.

15. The method for manufacturing a three-dimensional deep trench superjunction according to claim 11, characterized in that: In step five, the cross-section of the second deep trench is wider at the top and narrower at the bottom, so that the semiconductor material with the second conductivity type retained after the second deep trench etching has a wider-at-the-top and narrower-at-the-bottom cross-section along its extension direction and a narrower-at-the-top and wider-at-the-bottom cross-section along the intersection direction.

16. The method for manufacturing a three-dimensional deep trench superjunction according to claim 11, characterized in that: In step six, before backfilling the semiconductor material having the first conductivity type into the second deep trench, the method further includes: growing a sacrificial oxide layer to remove surface damage within the second deep trench, and cleaning the second deep trench.

17. The method for manufacturing a three-dimensional deep trench superjunction according to claim 11, characterized in that: The process parameters for the first deep trench etching and the second deep trench etching may be the same or different, and the process parameters include etching angle, etching depth and window size.

18. The method for manufacturing a three-dimensional deep trench superjunction according to claim 11, characterized in that: Both the first deep groove and the second deep groove are open striped deep grooves.

19. The method for manufacturing a three-dimensional deep trench superjunction according to claim 11, characterized in that: Also includes: After step six, a third and subsequent deep trench etching is performed, and the semiconductor material having the first conductivity type is backfilled to form a cellular structure with polygonal surface windows, the polygons including hexagons or triangles.

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