Methods of forming recessed gate terminals and wafers including recessed gate terminals and having reduced warpage

Abstract

Embodiments of the present disclosure relate to a method of forming recessed gate terminals and wafers including recessed gate terminals and having reduced warpage. The proposed solution is designed for IGBTs and discrete devices with vertical gates; the proposed method includes: trench formation in the wafer, including lithography and etching; oxidation to grow a gate dielectric; thin layer filling with polysilicon to form a first gate conductive layer; second dielectric deposition and etch back to fill half of the trench from the bottom up to a fixed depth; trench filling with polysilicon to form a second gate conductive layer. The second dielectric can be selected with a specific stress and a specific etch back amount to balance the polysilicon stress and reduce wafer warpage.

Description

Technical Field

[0001] This disclosure relates to a method for forming trench-gate terminals of an electronic device and a wafer or die including trench-gate terminals. Background Technology

[0002] IGBTs (Insulated Gate Bipolar Transistors) and other discrete devices with vertical conductive channels typically use trench-based designs for the gate region or terminals. The bottom and sidewalls of the trench are typically covered with a substantially uniform oxide layer, and then the trench is filled with polysilicon, which is then isolated from the substrate by the oxide layer. The oxide acts as the gate dielectric, and the polysilicon acts as the gate conductive plate.

[0003] The trenches typically cover most of the die area, providing a high mask transmittance (approximately 30%) for the corresponding mask level. The mask transmittance factor is the percentage of the mask that has removed the photoresist, corresponding to the area of ​​the etched trenches.

[0004] Given a relatively high coverage area of ​​the die region, the gate oxide (more specifically, polysilicon) generates stress, causing wafer deformation during manufacturing; moreover, the deformation is often asymmetrical (in a top view, wafer deformation along the orthogonal XY directions is asymmetrical). Manufacturing tools used to handle and process wafers have limited ability to manage deformed wafers.

[0005] Furthermore, for wafers with a diameter of approximately 300 mm (or even 200 mm or less), bending is exacerbated by geometric factors, while the bending tolerance of manufacturing tools remains almost unchanged; the risk of disposal problems and scrapped wafers and / or damaged tools is higher.

[0006] In the applicant's known field, warpage or bending can be managed by dividing polysilicon deposition into multiple deposition steps, followed by a heat treatment (typically RTP) after each deposition step. Warpage or bending compensation may also include depositing a dedicated layer on the back side of the wafer to balance stress.

[0007] However, these solutions have some drawbacks, such as requiring multiple polysilicon depositions and thermal processes, which increases manufacturing costs and slows down the manufacturing process. Furthermore, the deposition of the back layer requires specialized tooling, and the deposited back layer is often affected during periods of high thermal budget. Moreover, the latter solution does not address the problem of asymmetric warping or bending along the X and Y directions.

[0008] For the reasons mentioned above, there is a need to provide alternative methods for trench fabrication to minimize the stress generated. Summary of the Invention

[0009] According to this disclosure, a method for forming a gate terminal of an electronic device and a wafer or die including a gate are provided.

[0010] The method includes, in part,: trench formation in a wafer, including photolithography and etching; oxidation to grow a gate dielectric; polysilicon filling using a thin layer to form a first gate conductive layer; second dielectric deposition and recession to fill half of the trench from the bottom up to a fixed depth; and trench filling using polysilicon to form a second gate conductive layer. A second dielectric with specific stress and a specific recession amount can be selected to balance polysilicon stress and reduce wafer warpage. Attached Figure Description

[0011] To better understand this disclosure, some embodiments thereof are now described by way of non-limiting example only with reference to the accompanying drawings, wherein: Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F The side view illustrates the process steps for manufacturing a trench according to one aspect of this disclosure; and Figure 2 The flowchart illustrates the process. Figures 1A to 1F The process steps. Detailed Implementation

[0012] Figures 1A to 1F A portion 1A of the wafer or die 1 is shown in a side view, limited to features that aid in understanding this disclosure. Figures 1A to 1F The view is located in a three-axis coordinate system with mutually orthogonal axes X, Y, and Z. In one example, the wafer diameter is 300 mm. Depending on the manufacturing technology, the wafer can also have a diameter of 200 mm, or even smaller.

[0013] Figure 2 yes Figures 1A to 1F The flowchart of the process steps.

[0014] refer to Figure 1A The die 1 includes a solid body 2 of semiconductor material; for example, solid body 2 is a semiconductor substrate; alternatively, solid body 2 includes a semiconductor substrate on which one or more epitaxial layers are grown. The semiconductor material is or includes, for example, silicon or silicon carbide.

[0015] Entity 2 includes a first surface 2a and a second surface 2b. The first surface 2a and the second surface 2b are, for example, parallel to the XY plane and define opposing surfaces of entity 2 (opposite to each other along the Z axis).

[0016] In entity 2, a groove 4 is formed at the first surface 2a toward the second surface 2b (along the direction of axis Z). Figure 2 In step S1), the trench 4 terminates within the solid 2 (without reaching the second surface 2b). The trench 4 can be formed using photolithography and etching techniques.

[0017] The front opening 4a of the trench 4 is coplanar with the first surface 2a. The trench 4 has sidewalls or surfaces 4b and a bottom wall or surface 4c. In a top view (on a plane XY), the front opening 4a has a shape designed according to, for example, requirements (i.e., depending on functional requirements). For example, in a top view, the front opening 4a has a generally rectangular, elongated shape, with its main dimensions along the Y direction. The depth of the trench 4 along the Z-axis is in the range of 3 µm to 6 µm, for example, between 4 µm and 5 µm. The dimension of the trench 4 along the X-axis is in the range of 0.3 µm to 1.5 µm. The trench 4 has a dimension along the Y-axis, for example, between 1 mm and 10 mm, particularly between 2 mm and 6 mm.

[0018] Reference Figure 1B and Figure 2 In step S2, a gate dielectric layer 6 is formed within the trench 4, covering the sidewalls 4b and the bottom wall 4c. Specifically, the gate dielectric layer 6 uniformly covers the sidewalls 4b and the bottom wall 4c with structural continuity. The gate dielectric layer 6 also extends laterally to the trench opening 4a on the first surface 2a of the entity 2. The gate dielectric layer 6 can be any dielectric or electrically insulating material, such as silicon oxide (SiO2). The thickness of the gate dielectric layer 6 is in the range of 50 nm to 300 nm (e.g., measured along the X direction at the sidewall 4b, or along the Z direction at the bottom wall 4c). The gate dielectric layer 6 is thermally grown, for example, by CVD deposition or by a corresponding thermal process.

[0019] Then, refer to Figure 1B and Figure 2 In step S3, a first gate conductive layer 8 is formed on the gate dielectric layer 6 within the trench 4. The first gate conductive layer 8 extends at the sidewalls 4b and bottom wall 4c of the trench 4 and is electrically insulated and physically separated from the sidewalls 4b and bottom wall 4c of the trench 4 by the gate dielectric layer 6. The first gate conductive layer 8 extends on the gate dielectric layer 6 with physical and structural continuity and has a thickness ranging from 50 nm to 400 nm (e.g., measured along the X direction at the sidewall 4b, or along the Z direction at the bottom wall 4c). The first gate conductive layer 8 is, for example, a polycrystalline silicon material, and the concentration of dopant species includes 1 x 10⁻⁶. 19 at / cm 3 and 1x10 21 at / cm 3 between.

[0020] Optionally, the first gate conductive layer 8 extends further transversely to the trench opening 4a on the first surface 2a and extends on the gate dielectric layer 4.

[0021] It should be noted that the first gate conductive layer 8 does not completely fill the trench 4, but leaves blank spaces in the trench 4.

[0022] Reference Figure 1C and Figure 2 In step S4, the trench 4 is filled with a dielectric or insulating material (e.g., silicon oxide SiO2, silicon nitride SiN, Si3N4, or a combination of silicon oxide and silicon nitride) to form a filling layer 10. The filling layer 10 is formed on the first gate conductive layer 8 and completely fills the trench 4. Optionally, the filling layer 10 extends further laterally to the trench 4 above the first surface 2a of the solid. The filling layer 10 is formed by depositing the dielectric or insulating material using sputtering or CVD techniques or other techniques available in the art.

[0023] Then, refer to Figure 1D and Figure 2 Step S4 involves partially etching the filler layer 10, thereby removing the filler layer 10 from a portion of the trench 4 and above the first surface 2a (if present). The etching step is performed, for example, by a wet etching solution (wet etching, including HF in the case of SiO2, or H3PO4 in the case of SiN / Si3N4), or alternatively by a dry etching technique. For example, the etching is isotropic. The filler layer 10 is removed from the trench 4 starting from the front opening 4a and proceeding towards the Z-axis until a certain depth is reached, for example, the filler layer 10 is removed up to or less than half the trench depth. In other words, after etching is complete, the filler layer 10 remains in the trench 4 at the bottom wall 4c and uniformly fills a portion of the trench 4 above the bottom wall 4c. Generally, in Figure 2 In the process steps (i.e., after the formation of the first gate conductive layer 8), the filling layer 10 fills 40% to 80% (more specifically 50% to 70%) of the empty space of the trench 4.

[0024] In one embodiment, the filling layer 10 uniformly fills at least half (50%), preferably 70% to 80%, of the groove 4, starting from the bottom wall 4c.

[0025] In particular, for all disclosed embodiments, the filler layer 10 is uniform within the trench 4, which means that there are no holes, cavities or burial cavities within the filler layer 10.

[0026] In an alternative embodiment, the formation of the fill layer 10 includes depositing a dielectric or insulating material until the desired thickness of the fill layer 10 is reached within the trench, without performing an etching step that would recess the fill layer 10.

[0027] Then, refer to Figure 1E and Figure 2 In step S5, a second gate conductive layer 12 is deposited within the trench 4 to completely fill the trench 4 above the fill layer 10. Optionally, the second gate conductive layer 12 extends further transversely to the trench opening 4a above the first surface 2a of the entity 2. The second gate conductive layer 12 is, for example, polysilicon with an N-type doping concentration of 1x10⁻⁶. 19 at / cm 3 and 1x10 21 at / cm 3 The types of dopants used in the process.

[0028] Then, refer to Figure 1F and Figure 2 In step S6, a polishing step (e.g., by CMP chemical mechanical polishing) is performed to completely remove portions (if present) of the first gate conductive layer 8 and the second gate conductive layer 12 extending on the first surface 2a of the entity 2. Therefore, the second gate conductive layer 12 fills the trench 4 above the fill layer 10 and is coplanar at the hole 4a with the gate dielectric layer extending laterally to the trench opening 4a on the first surface 2a and the first gate conductive layer 8 at the hole 4a.

[0029] In one embodiment, the filling layer 10 has a dimension of groove 4 along the Z-axis. Figure 2 The blank space in the process steps is 1 / 5. In another embodiment, the filling layer 10 is dimensional along the Z-axis as groove 4 in Figure 2 The blank space in the process steps is 1 / 2. In another embodiment, the filling layer 10 is dimensional along the Z-axis as groove 4 in Figure 2 The blank space in the process steps is 1 / 1.25.

[0030] As an example, for a trench 4 with a Z-axis dimension of approximately 4.7 µm (in the process step of Figure 1), the filling layer 10 has a Z-axis dimension ranging from 0.95 µm to 3.8 µm.

[0031] Various embodiments of this disclosure can be used to fabricate recessed gate terminals for electronic devices with vertical conduction, i.e., conductive channels primarily along the Z-axis direction. As known in the art, such electronic devices have source terminals at a first surface 2a and drain terminals at a second surface 2b (and vice versa). Depending on the device design, the doping of entity 2 can be N-type or P-type. Therefore, based on the conductivity type (N or P) of the conductive channel, the doping type of the first polysilicon layer 8 and the second polysilicon layer 12 can also be the opposite of those previously described.

[0032] Electronic devices include, for example, one of the following: MOS transistor IC, BCD, IGBT, HV and LV discrete devices, and VI power supply.

[0033] From the above, the advantages of the various embodiments of this disclosure become clear.

[0034] In particular, wafer warping or bending is customizable by designing the fill layer 10 according to the material and the depth of the recess; moreover, it reduces costs compared to known process steps.

[0035] A method for forming a trench-gate terminal of an electronic device is summarized as comprising the following steps: forming (S1) a trench (4) on a first side (2a) of a solid (2), the trench extending from the first side (2a) toward a direction (Z); forming (S2) a gate dielectric layer (4) within the trench (4), the gate dielectric layer (4) covering the sidewalls and bottom walls (4b, 4c) of the trench (4) in structural continuity; forming (S3) a first gate conductive layer (8) on the gate dielectric layer (4) within the trench (4), the first gate conductive layer (8) extending along the sidewall (4b) to a first surface in structural continuity; forming (S4) a fill layer (10) on the first gate conductive layer (8) within the trench (4), the fill layer (10) partially filling the trench (4) from the bottom wall (4c) toward the first side (2a); and forming (S5, S6) a second gate conductive layer (12) on the fill layer (10) within the trench (4).

[0036] The second gate conductive layer (12) is formed to be in direct electrical contact with the first gate conductive layer (8) above the fill layer (10).

[0037] The filling layer (10) is separated from the bottom wall (4c) of the trench only through the first gate conductive layer (8) and the gate dielectric layer (4).

[0038] After the step of forming the first gate conductive layer (8), the fill layer (10) fills 20% to 80%, particularly 50% to 80%, of the empty space left in the trench.

[0039] Within the trench (4), the number of filling layers (10) is one of the following: five times the number of the second gate conductive layer (12); twice the number of the second gate conductive layer (12); or 1.25 times the number of the second gate conductive layer (12).

[0040] The filler layer (10) is made of silicon oxide or silicon nitride or a combination of silicon oxide and silicon nitride.

[0041] The first gate conductive layer and the second gate conductive layer (8, 12) are made of doped polycrystalline silicon.

[0042] The wafer or die is generally defined as including: a body (2) having a first side (2a) and a second side (2b) opposite each other along a direction (Z); a trench (4) extending in the body (2) from the first side (2a) toward the second side (2b) and terminating within the body (2); a gate dielectric layer (4) in the trench (4) covering the sidewalls and bottom wall (4b, 4c) of the trench (4) in structural continuity; a first gate conductive layer (8) in the trench (4) on the gate dielectric layer (4) extending in structural continuity along the sidewall (4b) to the first surface (2a); a filling layer (10) in the trench (4) on the first gate conductive layer (8) partially filling the trench (4) from the bottom wall (4c) toward the first side (2a); and a second gate conductive layer (12) in the trench (4) on the filling layer (10).

[0043] The second gate conductive layer (12) is in direct electrical contact with the first gate conductive layer (8) above the fill layer (10).

[0044] The filling layer (10) is separated from the bottom wall (4c) of the trench only through the first gate conductive layer (8) and the gate dielectric layer (4).

[0045] The second gate conductive layer (12) fills the trench (4) up to the first side (2a).

[0046] The filling layer (10) is separated from the bottom wall (4c) of the trench only through the first gate conductive layer (8) and the gate dielectric layer (4).

[0047] In the trench (4), the amount of the filling layer (10) relative to the second gate conductive layer (12) is in the range of 20% to 80%, and more particularly in the range of 50% to 80%.

[0048] Within the trench (4), the number of filling layers (10) is one of the following: five times the number of the second gate conductive layer (12); twice the number of the second gate conductive layer (12); or 1.25 times the number of the second gate conductive layer (12).

[0049] The filling layer (10) is made of silicon nitride, silicon oxide, or a combination of silicon oxide and silicon nitride; and the first gate conductive layer and the second gate conductive layer (8, 12) are made of doped polysilicon.

[0050] The various embodiments described above can be combined to provide other embodiments. Given the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents given to these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A method for forming a trench-gate terminal of an electronic device, the method comprising: A groove is formed on the first side of the entity, the groove extending from the first side toward a certain direction; A gate dielectric layer is formed within the trench, the gate dielectric layer covering the sidewalls and bottom wall of the trench with structural continuity; A first gate conductive layer is formed within the trench and on the gate dielectric layer, the first gate conductive layer extending along the sidewall to the first side with structural continuity; A filling layer is formed within the trench and on the first gate conductive layer, the filling layer partially filling the trench from the bottom wall toward the first side; as well as A second gate conductive layer is formed within the trench and on the filling layer.

2. The method of claim 1, wherein the second gate conductive layer is formed to be in direct electrical contact with the first gate conductive layer above the fill layer.

3. The method of claim 1, wherein the filling layer is separated from the bottom wall of the trench only through the first gate conductive layer and the gate dielectric layer.

4. The method of claim 1, wherein after forming the first gate conductive layer, the fill layer fills 20% to 80% of the empty space left in the trench.

5. The method of claim 4, wherein after forming the first gate conductive layer, the fill layer fills 50% to 80% of the empty space left in the trench.

6. The method according to claim 1, wherein, Within the trench, the number of the filling layer is five times the number of the second gate conductive layer, twice the number of the second gate conductive layer, or 1.25 times the number of the second gate conductive layer.

7. The method of claim 1, wherein the filling layer comprises silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

8. The method of claim 1, wherein the first gate conductive layer and the second gate conductive layer comprise doped polysilicon.

9. A wafer or bare die, comprising: An entity having a first side and a second side that are opposite to each other along a certain direction; A groove that extends from the first side toward the second side in the entity and terminates within the entity; A gate dielectric layer is provided in the trench and covers the sidewalls and bottom wall of the trench in structural continuity. A first gate conductive layer is located in the trench, on the gate dielectric layer, and extends along the sidewall to the first side with structural continuity. A filling layer, in the trench and on the first gate conductive layer, partially fills the trench from the bottom wall toward the first side; as well as A second gate conductive layer is located in the trench and on the fill layer.

10. The wafer or die of claim 9, wherein the second gate conductive layer is in direct electrical contact with the first gate conductive layer above the fill layer.

11. The wafer or die of claim 9, wherein the fill layer is separated from the bottom wall of the trench only through the first gate conductive layer and the gate dielectric layer.

12. The wafer or die of claim 9, wherein the second gate conductive layer fills the trench up to the first side.

13. The wafer or die of claim 9, wherein the fill layer is separated from the bottom wall of the trench only through the first gate conductive layer and the gate dielectric layer.

14. The wafer or die of claim 9, wherein in the trench, the amount of the filling layer relative to the second gate conductive layer is in the range of 20% to 80%.

15. The wafer or die of claim 14, wherein in the trench, the amount of the filling layer relative to the second gate conductive layer is in the range of 50% to 80%.

16. The wafer or die of claim 9, wherein the number of the filling layers in the trench is five times the number of the second gate conductive layers, twice the number of the second gate conductive layers, or 1.25 times the number of the second gate conductive layers.

17. The wafer or die according to claim 9, wherein: The filling layer comprises silicon nitride, silicon oxide, or a combination of silicon oxide and silicon nitride; and The first gate conductive layer and the second gate conductive layer comprise doped polysilicon.

18. A method comprising: A groove is formed in the first surface of the solid, the groove having a side surface and a bottom surface; A gate dielectric layer is formed on the first surface, the side surface, and the bottom surface; A first gate conductive layer is formed on the gate dielectric layer, and the first gate conductive layer is spaced apart from the first surface, the side surface and the bottom surface through the gate dielectric layer; A filling layer is formed on the first gate conductive layer, the filling layer being spaced apart from the side surface and the bottom surface through the first gate conductive layer and the gate dielectric layer, the filling layer filling a first portion of the trench; as well as A second gate conductive layer is formed on the fill layer. The second gate conductive layer is spaced apart from the side surface through the first gate conductive layer and the gate dielectric layer. The second gate conductive layer is spaced apart from the bottom surface through the first gate conductive layer, the gate dielectric layer and the fill layer. The second gate conductive layer fills a second portion of the trench.

19. The method of claim 18, wherein forming the filler layer comprises: The filling layer is formed on the first surface, and the filling layer is spaced apart from the first surface by the first gate conductive layer and the gate dielectric layer; as well as Remove the first portion of the filler layer on the first surface and the second portion of the filler layer in the trench.

20. The method of claim 19, wherein forming the second gate conductive layer comprises: A second gate conductive layer is formed on the first surface, and the second gate conductive layer is spaced apart from the first surface by the first gate conductive layer and the gate dielectric layer; as well as Remove the first portion of the second gate conductive layer on the first surface and the second portion of the second gate conductive layer that directly covers the trench.

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