A novel SiC MOSFET device with high reliability and long short-circuit withstand time

Abstract

The application relates to a novel SiC MOSFET device with high reliability long short-circuit tolerance time, and belongs to the technical field of semiconductor power devices. The device integrates a PiN diode composed of P+, N- and N+ type gates. The device has the following advantages: (1) during short-circuit, heat diffusion to the polysilicon area is caused by temperature rise, the leakage current of the PiN diode is increased, the voltage on the PiN resistance is increased, thereby reducing the gate voltage, compared with 5.5 mu s of a traditional planar gate SiC MOSFET, the short-circuit tolerance time of the device is prolonged to almost infinite. (2) during short-circuit, compared with the continuous rise of the internal junction temperature of a traditional planar gate SiC MOSFET to 2000K, through the gate voltage modulation effect of the PiN diode, the internal junction temperature of the device is kept stable at 550K. The device structure is prolonged to infinite in theory compared with the short-circuit time of a traditional planar gate, and the threshold voltage is reduced by 0.3V.

Description

[0001] This invention belongs to the field of semiconductor technology and relates to a novel SiCMOSFET device with high reliability and long short-circuit withstand time. Background Technology

[0002] With the continuous development of power electronics technology, especially in fields such as electric vehicles, power electronics, rail transportation, and high-efficiency power supplies, the demand for high-efficiency, high-frequency, and high-temperature power semiconductor devices is increasing. Silicon (Si) has long dominated the traditional power semiconductor field, but due to the limitations of its physical properties (such as lower breakdown voltage, higher on-resistance, and poorer high-temperature performance), its performance cannot meet the requirements of modern power electronic systems under high-voltage, high-temperature, and high-frequency operating environments. Therefore, wide-bandgap semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN), are gradually becoming emerging alternatives to traditional silicon materials due to their wider bandgap, higher breakdown voltage, and lower on-resistance.

[0003] SiC, as a semiconductor material with excellent high-temperature and high-pressure characteristics, has received widespread attention in the field of power electronics in recent years. SiC MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have become ideal devices for achieving high-efficiency, high-frequency switching power supplies and high-power conversion due to their high breakdown voltage, low on-resistance, excellent thermal conductivity, and high-frequency characteristics. While SiC MOSFETs have performed well in many areas, they still face some technical bottlenecks, particularly the short-circuit time under high-voltage short-circuit conditions, which affects the long-term reliability of the devices in applications.

[0004] To address this technical challenge, this paper proposes a SiC MOSFET device structure with high reliability and long short-circuit withstand time. By optimizing the device's structural design and doping process, the short-circuit time is significantly extended and the threshold voltage is reduced, thereby improving the device's performance in high-frequency, high-efficiency applications. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a highly reliable SiC MOSFET device with a long short-circuit time. This device embeds a PiN diode into the structure of a traditional planar gate MOSFET. Under high-voltage short-circuit conditions, the high voltage causes the current to rise rapidly, resulting in a rapid increase in power. Consequently, the internal temperature of the device rises, and the heat cannot be dissipated in time, leading to heat accumulation. The heat accumulation location is near the channel and is transferred to the PiN diode. Since the PiN diode is a temperature-sensitive device, a large leakage current is generated after the temperature rises. The leakage current loop is connected in series with Rg and the gate. With a total voltage of 15V, the voltage across Rg increases, causing the voltage across the gate to decrease. Therefore, the voltage gradually decreases, the current decreases, resulting in a decrease in power and a decrease in junction temperature, so that the temperature never reaches the thermal breakdown temperature, theoretically delaying the short-circuit time to indefinitely.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A novel SiC-MOSFET device with high reliability and long short-circuit time is disclosed. The device can be divided into two parts based on its structural characteristics: a traditional planar gate MOSFET structure and an embedded PiN structure. The device comprises a drain (1), an N+ SUB (2), an N-Drift (3), a P-base (4), a right-side source P+ region (5), a planar gate (6), a heavily N-doped planar gate oxide layer (7), a low-concentration N-doped intrinsic region (8), heavily P+-doped polysilicon (9), and a left-side N+ source (10).

[0008] A traditional MOSFET structure consists of a drain 1, an N+SUB 2, an N-Drift 3, a P-base 4, a right-side source P+ region 5, a planar gate 6, a planar gate oxide layer 7, and a left-side N+ source 10.

[0009] The drain (1) is located on the lower surface of N+SUB (2); The N+SUB (2) is located on the lower surface of the N-Drift (3) and the upper surface of the drain (1);

[0010] The N-Drift (3) is located on the upper surface of N+SUB (2) and the lower surface of the N-type heavily doped polysilicon planar gate oxide layer (7);

[0011] The P-base (4) is divided into two symmetrical sides. The P-base (4) is located on the lower surface of the N-type heavily doped polysilicon planar gate oxide layer (7) and the source (11).

[0012] The gate plane gate (6) is wrapped in an N-type heavily doped polysilicon oxide layer (7), and its lower side is in contact with the P-base (4) to form a channel;

[0013] The heavily doped N-type polysilicon oxide layer (7) wraps the gate plane gate (6), and the upper side is in contact with the low-concentration doped N-type region (8) and together with the highly doped P-type polysilicon (9) of the upper source electrode to form a PiN diode.

[0014] The right source P+ region (5) is located on the upper surface of P-base (4), and its left side is in contact with the right source N+ region;

[0015] Furthermore, the gate plane 6, the low-concentration doped N-type region 8, and the high-concentration doped P-type polysilicon 9 form an embedded PiN diode. Under short-circuit high voltage, the current increases and the temperature rises. The junction temperature rises the fastest in the JFET region. Since the PiN diode is a temperature-sensitive device, the leakage current rises rapidly. The external circuit Rg voltage divider causes the gate voltage to drop, thereby reducing the saturation current, power, and heat.

[0016] The beneficial effects of this invention are as follows: The device of this invention embeds a PiN diode into the structure of a traditional asymmetric trench MOSFET. During a short circuit, the PiN leakage current, in conjunction with Rg, reduces the gate voltage, thereby significantly reducing the current and junction temperature, and delaying the short-circuit time with almost no loss of other performance indicators. In summary, by designing a SiC MOSFET device with high reliability and a long short-circuit withstand time, the short-circuit withstand time of the device is greatly extended, and the long-term reliability of the device is improved. Attached Figure Description

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0018] Figure 1 A schematic diagram of the overall structure of the SiC MOSFET device of this invention;

[0019] Figure 2 A comparison of the output characteristic curves of the device of the present invention and a conventional planar gate SiC MOSFET when the gate voltage is 15V and the current path diagram of the SiC MOSFET of the present invention when it is operating in the first quadrant.

[0020] Figure 3 The graph shows a comparison of the breakdown characteristic curves of the device of the present invention and the conventional planar gate SiC MOSFET. The breakdown characteristic curves of the device of the present invention are slightly lower than those of the conventional device.

[0021] Figure 4 The reverse conduction characteristic diagram is a comparison of the third quadrant curves of the device of the present invention and the conventional planar gate SiC MOSFET when the gate voltage is -5V. Since both the device of the present invention and the conventional device rely on the body diode for freewheeling, the two images are superimposed.

[0022] Figure 5 A comparison of the short-circuit characteristic curves of the device of the present invention and that of a conventional planar gate SiC MOSFET under a short-circuit condition with a leakage voltage of 800V, and a comparison with the maximum junction temperature;

[0023] Figure 6 A comparison of the gate charge characteristics of the device of this invention and a conventional planar gate SiC MOSFET;

[0024] Figure reference numerals: Drain 1, N+SUB 2, N-Drift 3, P-base 4, Source P+ region 5, Gate plane 6, N-type heavily doped polysilicon plane gate oxide layer 7, Low-concentration doped N-type region 8, Source highly doped P-type polysilicon 9, -Source N+ region 10, Source 11. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0027] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0028] Example 1:

[0029] like Figure 1As shown, this embodiment provides a SiC MOSFET device with an embedded PiN diode, which is an improvement on the traditional planar gate device. It includes a drain 1, an N+SUB 2, an N-Drift 3, a P-base 4, a source P+ region 5, a gate planar gate 6, an N-type heavily doped polysilicon planar gate oxide layer 7, a low-concentration doped N-type region 8, a source highly doped P-type polysilicon 9, a source N+ region 10, and a source 11.

[0030] Figure 2 The diagram shows the IdVd characteristic curve. During forward conduction, the total current density increases because the PiN diode also participates in conduction, thus optimizing the forward characteristics.

[0031] Figure 3 The diagram shows the BV reverse breakdown voltage characteristics of the device. The breakdown voltage of the newly invented device is slightly lower than that of the conventional device. The introduction of the PiN diode causes the breakdown point to be concentrated at the PiN and amplified, but the breakdown voltage level is much greater than 1200V.

[0032] Figure 4 This is a comparison diagram of their reverse characteristics. The reverse characteristics of the two are identical because they both rely on the body diode for freewheeling, with a body diode turn-on voltage drop of 2.7V.

[0033] Figure 5 The diagram shows a comparison of short-circuit characteristics at 800V drain. It is evident that conventional planar gates experience uncontrolled thermal runaway current rises uncontrollably at 7.3µs, with the maximum junction temperature exceeding 2000K. However, due to the embedded PiN diode, the junction temperature of the device in this invention does not exceed 900K, theoretically delaying the short-circuit time to infinity.

[0034] Figure 6 Regarding gate charge characteristics, since the gate capacitance was not optimized, the gate charges of the two are almost identical.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A novel SiC-MOSFET device with high reliability and long short-circuit time. The device can be divided into two parts according to its structural characteristics: a traditional MOSFET structure and an embedded PiN diode structure. The device includes a drain (1), an N+SUB (2), an N-Drift (3), a P-base (4), a source P+ region (5), a planar gate (6), an N-type heavily doped polysilicon planar gate oxide layer (7), a low-concentration doped N-type region (8), a source highly doped P-type polysilicon (9), a source N+ region (10), and a source (11). The traditional planar MOSFET structure consists of a source (11). The structure consists of a source P+ region (5), a source N+ region (10), a P-base (4), an N-type heavily doped polysilicon planar gate oxide layer (7), a gate planar gate (6), a drain (1), an N+SUB (2), and an N-Drift (3); the drain (1) is located on the lower surface of the N+SUB (2); the N+SUB (2) is located on the lower surface of the N-Drift (3) and the upper surface of the drain (1); the N-Drift (3) is located on the upper surface of the N+SUB (2) and the lower surface of the N-type heavily doped polysilicon planar gate oxide layer (7); the P-base (4) is divided into two symmetrical sides. The P-base (4) is located on the lower surface of the N-type heavily doped polysilicon planar gate oxide layer (7) and the source (11); the gate planar gate (6) is wrapped in the N-type heavily doped polysilicon oxide layer (7), and its lower side is in contact with the P-base (4) to form a channel; the N-type heavily doped polysilicon oxide layer (7) wraps the gate planar gate (6), and its upper side is in contact with the low-concentration doped N-type region (8) and the high-concentration doped P-type polysilicon (9) of the upper source to form a PiN diode; the right source P+ region (5) is located on the upper surface of the P-base (4), and its left side is in contact with the right source N+ region.

2. The novel SiC MOSFET device with high reliability and long short-circuit time according to claim 1, characterized in that: An embedded PiN diode is formed by a plane gate (6), a low-concentration doped N-type region (8), and a high-concentration doped P-type polysilicon (9). Under short-circuit high voltage, the current increases and the temperature rises. The junction temperature rises the fastest in the JFET region. Since the PiN diode is a temperature-sensitive device, the leakage current rises rapidly. The external circuit Rg divides the voltage, causing the gate voltage to drop, which in turn reduces the saturation current, power, and heat.

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