Shielded gate trench type semiconductor device and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, and discloses a shielded gate trench type semiconductor device and a preparation method thereof. The shielded gate trench type semiconductor device comprises a first shielded gate trench type transistor and a second shielded gate trench type transistor. The second shielded gate trench type transistor comprises an epitaxial layer and a groove arranged on one side of a substrate base plate; a body region and a first source region arranged on a side of the epitaxial layer away from the substrate base plate; a first oxide layer arranged on a side wall of the groove and a side of the first source region away from the substrate base plate, wherein the thickness of the first oxide layer is less than that of an oxide layer of the first shielded gate trench type transistor; a gate electrode arranged opposite to the first oxide layer and filling and covering part of the groove; and a first metal layer arranged on a side of the source region away from the substrate base plate, wherein the first metal layer is connected with the gate electrode, the first source region, the body region and a source region of the first shielded gate trench type transistor respectively. The shielded gate trench type semiconductor device provided by the application has low forward voltage drop and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a shielded gate trench semiconductor device. Specifically, it can be applied to logic elements, mixed-signal elements, embedded memories, BCD (bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor), trench transistors (trench MOSFETs), and high-voltage components (such as power management integrated circuits) and related products and processes. Background Technology

[0002] Shielded gate trench MOSFETs are advanced power semiconductor devices that are widely used in many fields, such as new energy vehicles, photovoltaic new energy, industrial electronics, consumer electronics, smart manufacturing, 5G communication and the Internet of Things, due to their excellent performance and reliability.

[0003] The disadvantages of existing shielded gate trench semiconductor devices are high forward conduction voltage and high power consumption, which make it difficult to meet the application requirements. Summary of the Invention

[0004] In view of this, the present invention proposes a shielded gate trench semiconductor device and its fabrication method, which solves the problems of high forward conduction voltage and high power consumption of existing shielded gate trench semiconductor devices.

[0005] On one hand, embodiments of the present invention provide a shielded gate trench semiconductor device, the shielded gate trench semiconductor device comprising: A substrate and a first shielded gate trench transistor and a second shielded gate trench transistor formed thereon, wherein, The second shielded gate trench transistor includes: An epitaxial layer disposed on one side of a substrate; A body region disposed on the side of the epitaxial layer away from the substrate; A first source region is disposed on the side of the body region facing away from the substrate. The groove penetrates the first source region and the body region, and extends into the interior of the epitaxial layer; A first oxide layer is disposed on the sidewall of the trench and on the side of the first source region away from the substrate, and the thickness of the first oxide layer is less than the thickness of the oxide layer of the first shielded gate trench transistor. A gate electrode is disposed opposite to the first oxide layer and fills and covers a portion of the groove; A first metal layer is disposed on the side of the source region away from the substrate, and the first metal layer is connected to the gate, the first source region, the body region, and the source region of the first shielded gate trench transistor.

[0006] In some implementations, the concentration of the first source region is greater than the concentration of the source region of the first shielded gate trench transistor.

[0007] In some embodiments, the thickness of the first oxide layer is 50 angstroms ± 10 angstroms.

[0008] In some implementations, the doping type of the first source region is a first doping type, the doping type of the body region is a second doping type, and the doping concentration of the body region is less than the doping concentration of the first source region.

[0009] In some embodiments, the first metal layer is used to apply a first voltage to the gate, the first source region, the body region, and the source region of the second shielded gate trench transistor.

[0010] In some embodiments, the first shielded gate trench transistor includes: A second metal layer connected to the gate of the first shielded gate trench transistor; the second metal layer is used to apply a second voltage to the gate of the first shielded gate trench transistor. A third metal layer is connected to the source region and body region of the first shielded gate trench transistor; the third metal layer is used to apply a third voltage to the source region and body region of the first shielded gate trench transistor.

[0011] On the other hand, embodiments of the present invention also provide a method for fabricating a shielded gate trench semiconductor device, the method comprising: A first shielded gate trench transistor and a second shielded gate trench transistor are formed on a substrate; wherein forming the second shielded gate trench transistor includes: An epitaxial layer is formed on one side of the substrate. A groove is formed in the epitaxial layer, and the groove extends from the side of the epitaxial layer away from the substrate towards the substrate. A first oxide layer is formed on the sidewall of the trench and on the side of the epitaxial layer away from the substrate. The thickness of the first oxide layer is less than the thickness of the oxide layer of the first shielded gate trench transistor. A gate is formed inside the trench, at a position opposite to the first oxide layer, to fill and cover part of the trench; A body region is formed on the side of the first oxide layer closest to the substrate. A first source region is formed on the side of the bulk region closest to the first oxide layer; A first metal layer is formed on the side of the first oxide layer away from the substrate, wherein the first metal layer is connected to the gate, the first source region, the body region, and the source region of the first shielded gate trench transistor.

[0012] In some embodiments, a first source region is formed on the side of the body region closest to the first oxide layer, including: A second source region is formed on the side of the body region near the first oxide layer, and a first source region is formed based on the second source region. The concentration of the first source region is greater than the concentration of the source region of the first shielded gate trench transistor.

[0013] In some embodiments, a second source region is formed on the side of the body region closest to the first oxide layer, and a first source region is formed based on the second source region, including: A second source region is formed on the side of the bulk region near the first oxide layer using photolithography and ion implantation processes. The first source region is formed based on the second source region through photolithography, ion implantation and tempering processes.

[0014] In some embodiments, forming a first oxide layer on the sidewall of the groove and on the side of the epitaxial layer facing away from the substrate includes: A second oxide layer is formed in the groove and on the side of the epitaxial layer away from the substrate. The second oxide layer on the side of the epitaxial layer away from the substrate and the second oxide layer on the sidewall of the groove away from the substrate are removed by photolithography and etching processes. At the locations where the second oxide layer has been removed from the epitaxial layer and the sidewalls of the groove, a first oxide layer is formed by a deposition process, wherein the thickness of the first oxide layer is 50 angstroms ± 10 angstroms.

[0015] The present invention has at least the following beneficial effects: This invention provides a shielded gate trench semiconductor device and its fabrication method. The shielded gate trench semiconductor device provided by this invention includes: a substrate and a first shielded gate trench transistor and a second shielded gate trench transistor formed thereon. The second shielded gate trench transistor includes: an epitaxial layer disposed on one side of the substrate; a body region disposed on the side of the epitaxial layer opposite to the substrate; a first source region disposed on the side of the body region opposite to the substrate; a groove penetrating the first source region and the body region and extending into the epitaxial layer; a first oxide layer disposed on the sidewall of the groove and on the side of the first source region opposite to the substrate, the thickness of the first oxide layer being less than the thickness of the oxide layer of the first shielded gate trench transistor; a gate disposed opposite to the first oxide layer and filling and covering part of the groove; and a first metal layer disposed on the side of the source region opposite to the substrate, the first metal layer being connected to the gate, the first source region, the body region, and the source region of the first shielded gate trench transistor. The shielded gate trench semiconductor device provided by this invention has a low forward voltage drop and low power consumption.

[0016] Specifically, this invention is applicable to logic elements, mixed-signal elements, embedded memories, BCD (bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor), trench MOSFETs, and high-voltage components (such as power management integrated circuits) and related products and processes. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0018] Figure 1a This is a schematic diagram of an exemplary shielded gate trench semiconductor device; Figure 1b for Figure 1a The diagram shows the fabrication process of a shielded gate trench semiconductor device. Figure 2 This is a schematic diagram of the structure of a shielded gate trench semiconductor device provided in an embodiment of the present invention; Figure 3a This is a schematic diagram of the fabrication process of the second shielded gate trench transistor provided in an embodiment of the present invention; Figure 3b This is a schematic diagram of the fabrication process of the first oxide layer of the second shielded gate trench transistor provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the fabrication process of the first source region of the second shielded gate trench transistor provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0020] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0021] like Figure 1a As shown, an exemplary shielded gate trench semiconductor device includes: a substrate 10, an epitaxial layer 11 disposed on the substrate, a trench 12 disposed in the epitaxial layer, an oxide layer 13 disposed in the trench and on the side of the epitaxial layer opposite to the substrate, a gate 14 disposed in the trench, a source region 15 and a body region 16 disposed between the oxide layer 13 and the epitaxial layer 11, a source metal layer 17 connected to the source region 15 and the body region 16, and a gate metal layer 18 connected to the gate 14.

[0022] like Figure 1bAs shown, the exemplary method for fabricating a shielded gate trench semiconductor device is as follows: forming a substrate 10, an epitaxial layer 11, and a trench 12; forming a gate oxide (GOX) 13 on the epitaxial layer (EPI) 11 → forming a gate polysilicon layer → forming a body region (also called a body region) 16 by ion implantation and tempering → forming a source region (also called a source region) 15 by photolithography, ion implantation, and tempering → forming an inter-layer dielectric (ILD) 19 → forming a source metal layer 17 and a gate metal layer 18, wherein the source metal layer 17 is connected to the body region 16, and the gate metal layer is connected to the source region 15, thereby obtaining the following... Figure 1a The shielded gate trench type semiconductor device shown.

[0023] The forward voltage drop of the shielded gate trench semiconductor device obtained by the above preparation method is 0.5V. This forward voltage drop is relatively large, resulting in high power consumption of the shielded gate trench semiconductor device, which cannot meet the application requirements.

[0024] In view of the above, in order to solve at least one of the above technical problems, embodiments of the present invention provide a shielded gate trench semiconductor device and a method for fabricating the same, which can reduce the forward voltage drop of the shielded gate trench semiconductor device and reduce the power consumption of the shielded gate trench semiconductor device under the same input current. The present invention will now be described in detail with reference to embodiments and accompanying drawings.

[0025] The first aspect of this invention provides a shielded gate trench semiconductor device, such as... Figure 2 As shown, the shielded gate trench semiconductor device includes: a substrate 20 and a first shielded gate trench transistor 21 and a second shielded gate trench transistor 22 formed thereon. The second shielded gate trench transistor 22 includes: an epitaxial layer 221 disposed on one side of the substrate 20; a body region 222 disposed on the side of the epitaxial layer 221 away from the substrate 20; a first source region 223 disposed on the side of the body region 222 away from the substrate; a groove 224 penetrating the first source region 223 and the body region 222 and extending into the interior of the epitaxial layer 221; a first oxide layer 225 disposed on the sidewall of the groove and on the side of the first source region 223 away from the substrate 20, the thickness of the first oxide layer 225 being less than the thickness of the oxide layer of the first shielded gate trench transistor 21; a gate 226 disposed opposite to the first oxide layer 225 and filling and covering part of the groove; and a first metal layer 227 disposed on the side of the first source region 223 away from the substrate 20, the first metal layer 227 being connected to the gate 226, the first source region 223, the body region 222, and the source region of the first shielded gate trench transistor 21.

[0026] In this embodiment of the invention, the structure of the first shielded gate trench transistor 21 is similar to... Figure 1a The structures of the shielded gate trench semiconductor devices shown are basically the same, and will not be described in detail here.

[0027] The shielded gate trench semiconductor device of this invention can be applied in multiple fields, such as new energy vehicles, photovoltaic new energy, industrial electronics, consumer electronics, intelligent manufacturing, 5G communication and the Internet of Things.

[0028] The substrate 20 can be made of silicon as the base material; for example, it can be a single-crystal silicon substrate or a doped silicon substrate. The epitaxial layer 221 can be made of polycrystalline silicon. The body region 222 and the first source region 223 can be made of doped n-type or p-type semiconductor materials. For example, boron-doped SiGe (p-type) or phosphorus-doped SiC (n-type), but not limited thereto. The first oxide layer 225 can be made of oxides, such as silicon oxide, but not limited thereto. The gate 226 can be made of polycrystalline silicon. The first metal layer 227 can be made of metals such as silver, copper, or aluminum.

[0029] The operation process of the shielded gate trench semiconductor device provided in this embodiment of the invention is as follows: a positive voltage is simultaneously applied to the first source region 223 and gate 226 of the second shielded gate trench transistor 22 and the source region of the first shielded gate trench transistor 21. The drain region (i.e., epitaxial layer) of the second shielded gate trench transistor 22 and the drain region (i.e., epitaxial layer) of the first shielded gate trench transistor 21 are grounded. Since the thickness of the first oxide layer 225 of the second shielded gate trench transistor 22 is less than the thickness of the oxide layer of the first shielded gate trench transistor 21, and the voltage applied to the first source region 223 and gate 226 of the second shielded gate trench transistor 22 is the same as that applied to the source region of the first shielded gate trench transistor 21, the on-resistance of the second shielded gate trench transistor 22 is reduced. The second shielded gate trench transistor 22 turns on earlier than the first shielded gate trench transistor 21. Therefore, the forward voltage drop of the shielded gate trench semiconductor device is reduced, and the power consumption is also reduced accordingly.

[0030] In some embodiments of the present invention, such as Figure 2 The thickness h of the first oxide layer of the second shielded gate trench transistor 22 shown is 50 angstroms ± 10 angstroms. By controlling the thickness of the first oxide layer of the second shielded gate trench transistor 22 within the range of 50 angstroms ± 10 angstroms, the forward voltage drop of the shielded gate trench semiconductor device can be reduced by about 50%, which greatly reduces the forward voltage drop and power consumption of the shielded gate trench semiconductor device.

[0031] In some embodiments of the present invention, such as Figure 2The concentration of the first source region 223 of the second shielded gate trench transistor 22 shown is greater than the concentration of the source region of the first shielded gate trench transistor 21, thereby further reducing the forward voltage drop and power consumption of the shielded gate trench semiconductor device.

[0032] In some embodiments of the present invention, such as Figure 2 The first source region 223 of the second shielded gate trench transistor 22 shown is doped with a first doping type, and the body region 222 is doped with a second doping type.

[0033] The doping concentration of the body region 222 is less than that of the first source region 223.

[0034] In some examples, the first doping type can be N-type and the second doping type can be P-type. For example, an N-type semiconductor can be formed by arsenic (As) doping and a P-type semiconductor can be formed by boron (B) doping.

[0035] In some embodiments of the present invention, such as Figure 2 The first metal layer 227 of the second shielded gate trench transistor 22 shown is used to apply a first voltage to the gate 226, the first source region 223 and the body region 222 of the second shielded gate trench transistor 22 and the source region of the first shielded gate trench transistor 21.

[0036] In some embodiments of the present invention, such as Figure 2 The first shielded gate trench transistor 21 shown may include: a second metal layer 211 connected to the gate of the first shielded gate trench transistor, and a third metal layer 212 connected to the source region and body region of the first shielded gate trench transistor.

[0037] The second metal layer 211 is used to apply a second voltage to the gate of the first shielded gate trench transistor; the third metal layer 212 is used to apply a third voltage to the source region and body region of the first shielded gate trench transistor.

[0038] In some examples, the range of the first voltage can be (5 ± 10%) V, the range of the second voltage can be 0 V (i.e., ground), and the range of the third voltage can be (5 ± 10%) V.

[0039] In some embodiments of the present invention, such as Figure 2 The second shielded gate trench transistor 22 shown also includes an interlayer dielectric layer 228 disposed on the side of the first metal layer 227 near the substrate.

[0040] In some embodiments of the present invention, such as Figure 2 The second shielded gate trench transistor 22 shown also includes a field plate 229 disposed within the trench. The field plate 229 may be made of polysilicon.

[0041] Based on the same inventive concept, according to another aspect of the present invention, in order to form as Figure 2 The shielded gate trench semiconductor device shown in the present invention also provides a method for fabricating a shielded gate trench semiconductor device, the method comprising: forming a first shielded gate trench transistor and a second shielded gate trench transistor on a substrate.

[0042] like Figure 3a As shown, the method for forming the second shielded gate trench transistor includes S30 to S33.

[0043] S30. An epitaxial layer 22 is formed on one side of the substrate 20, and a groove 224 is formed in the epitaxial layer 22. A first oxide layer 225 is formed on the sidewall of the groove and on the side of the epitaxial layer 22 away from the substrate 20.

[0044] The groove 224 extends from the side of the epitaxial layer 22 away from the substrate 20 toward the substrate 20. The thickness of the first oxide layer 225 is less than the thickness of the oxide layer of the first shielded gate trench transistor.

[0045] S31. A gate is formed inside the groove 224 at a position opposite to the first oxide layer 225, filling and covering part of the groove.

[0046] S32, a body region 222 is formed on the side of the first oxide layer 225 near the substrate 20, and a first source region 223 is formed on the side of the body region 222 near the first oxide layer 225.

[0047] S33. An interlayer dielectric layer 228 and a first metal layer 227 are sequentially formed on the side of the first oxide layer 225 away from the substrate 20.

[0048] The first metal layer 227 is connected to the gate 226, the first source region 223, the body region 222, and the source region of the first shielded gate trench transistor.

[0049] The fabrication process of the first shielded gate trench transistor is basically the same as that of the exemplary shielded gate trench semiconductor device. Therefore, the fabrication process of the first shielded gate trench transistor will not be described in detail in this example.

[0050] In some embodiments of the present invention, the epitaxial layer of the first shielded gate trench transistor 21 and the epitaxial layer 221 of the second shielded gate trench transistor 22 can be formed simultaneously or separately, without specific limitations.

[0051] In some embodiments of the present invention, the second metal layer 211 and the third metal layer 212 of the first shielded gate trench transistor 21 and the first metal layer 227 of the second shielded gate trench transistor 22 can be formed simultaneously or separately, without specific limitation.

[0052] In some embodiments of the present invention, such as Figure 3b As shown, forming the first oxide layer through step S30 may include steps S301 to S307.

[0053] S301. An epitaxial layer 221 is formed on one side of the substrate 20.

[0054] S302, A groove 224 extending in a direction close to the substrate 20 is formed in the epitaxial layer 22.

[0055] S303, A third oxide layer is formed in the portion of the groove 224 near the substrate 20.

[0056] S304. A first groove is formed on the side of the third oxide layer away from the substrate 20, and polysilicon is deposited in the first groove to form a field plate 229.

[0057] S305. A second oxide layer 225a is formed in the groove 224 and on the side of the epitaxial layer 22 away from the substrate 20, covering the groove sidewall, the third oxide layer and the field plate.

[0058] S306, The second oxide layer on the side of the epitaxial layer away from the substrate and the second oxide layer 225a on the portion of the groove away from the substrate are removed by photolithography and etching processes.

[0059] S307. At the locations where the second oxide layer 225a has been removed from the epitaxial layer and the sidewall of the groove, the first oxide layer 225 is formed by a deposition process.

[0060] The thickness of the first oxide layer is 50 angstroms ± 10 angstroms.

[0061] To simplify the fabrication process of shielded gate trench semiconductor devices, some fabrication processes of the first shielded gate trench transistor 21 and the second shielded gate trench transistor 22 can be performed simultaneously. In this embodiment of the invention, steps S301 to S305 are performed simultaneously with the process of fabricating the oxide layer of the first shielded gate trench transistor 21. The thickness of the second oxide layer 225a is the same as the thickness of the oxide layer of the first shielded gate trench transistor 21. For example, the thickness of the second oxide layer 225a can be 650 Å, 660 Å, 670 Å, 680 Å, 690 Å, 700 Å, 710 Å, 720 Å, 730 Å, or 740 Å, etc.

[0062] The thickness of the first oxide layer 225 is less than that of the second oxide layer 225a. The thickness of the first oxide layer 225 can be 45A, 46A, 47A, 48A, 49A, 50A, 51A, 52A, 53A or 54A, etc.

[0063] In some embodiments of the present invention, such as Figure 3a In step S32 shown, forming a first source region on the side of the body region near the first oxide layer may include forming a second source region on the side of the body region near the first oxide layer, and forming the first source region based on the second source region. The concentration of the first source region is greater than the concentration of the source region of the first shielded gate trench transistor.

[0064] The first source region formed by secondary ion implantation can reduce the turn-on voltage of the second shielded gate trench transistor 22, thereby reducing the turn-on voltage of the entire shielded gate trench semiconductor device in advance and reducing power consumption.

[0065] In some embodiments of the present invention, such as Figure 4 As shown, forming a second source region on the side of the body region near the first oxide layer, and forming a first source region based on the second source region, may include: S40. A second source region 223a is formed on the side of the bulk region 222 near the first oxide layer 225 by photolithography and ion implantation.

[0066] In some examples, the thickness of the photoresist in the photolithography process can be controlled within the range of (0.6±0.06) μm, and As can be selected. A second source region with a depth range of (300~500) Å, a doping concentration range of 8E15±5%, and an N-type doping type can be obtained through ion implantation.

[0067] S41. The first source region 223 is formed based on the second source region 223a through photolithography, ion implantation and tempering processes.

[0068] In some examples, the thickness of the photoresist in the photolithography process can be controlled within the range of (0.6±0.06) μm, and As can be selected. The first source region with a depth range of (400~600) Å, a doping concentration range of 8E15±5%, and an N-type doping type can be obtained by ion implantation.

[0069] In some embodiments of the present invention, forming a body region on the side of the epitaxial layer away from the substrate may include: forming a body region on the side of the epitaxial layer away from the substrate by means of ion implantation and tempering processes.

[0070] Specifically, option B is selected. Through ion implantation, a body region with a depth in the range of (2700±800)A, a doping concentration of 9E12±5%, and a doping type of P is formed. The formed body region is then tempered at a temperature controlled at (950±50)℃.

[0071] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. The sequence numbers of the disclosed embodiments of this invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0072] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0073] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A shielded gate trench semiconductor device, characterized in that, include: A substrate and a first shielded gate trench transistor and a second shielded gate trench transistor formed thereon, wherein, The second shielded gate trench transistor includes: An epitaxial layer disposed on one side of the substrate; A body region disposed on the side of the epitaxial layer opposite to the substrate; A first source region is disposed on the side of the body region opposite to the substrate. A groove, the groove penetrating the first source region and the body region, and extending into the interior of the epitaxial layer; A first oxide layer is disposed on the sidewall of the groove and on the side of the first source region opposite to the substrate, wherein the thickness of the first oxide layer is less than the thickness of the oxide layer of the first shielded gate trench transistor. A gate is disposed opposite to the first oxide layer and fills and covers a portion of the groove; A first metal layer is disposed on the side of the source region away from the substrate, and the first metal layer is connected to the gate, the first source region, the body region, and the source region of the first shielded gate trench transistor.

2. The shielded gate trench semiconductor device according to claim 1, characterized in that, The concentration of the first source region is greater than the concentration of the source region of the first shielded gate trench transistor.

3. The shielded gate trench semiconductor device according to claim 1, characterized in that, The thickness of the first oxide layer is 50 angstroms ± 10 angstroms.

4. The shielded gate trench semiconductor device according to claim 1, characterized in that, The first source region is doped with a first doping type, the body region is doped with a second doping type, and the doping concentration of the body region is less than that of the first source region.

5. The shielded gate trench semiconductor device according to claim 1, characterized in that, The first metal layer is used to apply a first voltage to the gate, the first source region, the body region, and the source region of the second shielded gate trench transistor.

6. The shielded gate trench semiconductor device according to claim 5, characterized in that, The first shielded gate trench transistor includes: A second metal layer connected to the gate of the first shielded gate trench transistor; the second metal layer is used to apply a second voltage to the gate of the first shielded gate trench transistor; A third metal layer connected to the source and body regions of the first shielded gate trench transistor; the third metal layer is used to apply a third voltage to the source and body regions of the first shielded gate trench transistor.

7. A method for fabricating a shielded gate trench semiconductor device, characterized in that, include: A first shielded gate trench transistor and a second shielded gate trench transistor are formed on a substrate; wherein, forming the second shielded gate trench transistor includes: An epitaxial layer is formed on one side of the substrate. A groove is formed in the epitaxial layer, the groove extending from the side of the epitaxial layer away from the substrate towards the substrate; A first oxide layer is formed on the sidewall of the groove and on the side of the epitaxial layer opposite to the substrate, and the thickness of the first oxide layer is less than the thickness of the oxide layer of the first shielded gate trench transistor. A gate is formed inside the groove at a position opposite to the first oxide layer, filling and covering a portion of the groove; A body region is formed on the side of the first oxide layer near the substrate. A first source region is formed on the side of the body region closest to the first oxide layer; A first metal layer is formed on the side of the first oxide layer away from the substrate, wherein the first metal layer is connected to the gate, the first source region, the body region, and the source region of the first shielded gate trench transistor.

8. The preparation method according to claim 7, characterized in that, The formation of a first source region on the side of the body region near the first oxide layer includes: A second source region is formed on the side of the body region near the first oxide layer, and a first source region is formed based on the second source region, wherein the concentration of the first source region is greater than the concentration of the source region of the first shielded gate trench transistor.

9. The preparation method according to claim 8, characterized in that, A second source region is formed on the side of the body region near the first oxide layer, and a first source region is formed based on the second source region, including: A second source region is formed on the side of the bulk region near the first oxide layer using photolithography and ion implantation processes; The first source region is formed based on the second source region through photolithography, ion implantation, and tempering processes.

10. The preparation method according to claim 7, characterized in that, The formation of a first oxide layer on the sidewall of the groove and on the side of the epitaxial layer opposite to the substrate includes: A second oxide layer is formed in the groove and on the side of the epitaxial layer opposite to the substrate. The second oxide layer on the side of the epitaxial layer away from the substrate and the second oxide layer on the sidewall of the groove away from the substrate are removed by photolithography and etching processes. At the locations where the second oxide layer has been removed from the epitaxial layer and the sidewalls of the groove, a first oxide layer is formed by a deposition process, wherein the thickness of the first oxide layer is 50 angstroms ± 10 angstroms.

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