Array substrate, preparation method thereof and display panel

Abstract

The application discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, a first conductive layer and a second conductive layer. The first signal line is further divided into a first subsegment and a second subsegment in the first segment in the display area. The first subsegment extends along the first direction and overlaps with the orthographic projection of a row of pixel electrode rows. The second subsegment extends along the second direction and connects adjacent first subsegments. Different first subsegments overlap with different rows of pixel electrode rows. The structure helps to improve the parasitic capacitance coupling problem caused by the first segment of the first signal line continuously crossing multiple pixel electrodes in the first direction, reduces the interference risk of the first signal line in the single row initialization or data writing process, and improves the adverse problems such as bright lines caused by the interference of the first signal line in the display area. At the same time, part of the first signal line is included in the display area, which is conducive to realizing a narrower frame design.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, its fabrication method, and a display panel. Background Technology

[0002] As users increasingly demand higher screen-to-body ratios and greater aesthetic appeal, the bezel width, especially the bottom bezel, has become a key design consideration. In conventional display panels, the driver chip is typically located in the bottom bezel area, requiring fan-out lines to route the data signals output by the driver chip to the various data lines within the display area. However, these fan-out lines need to be distributed in a fan shape in the bottom bezel area, occupying a significant portion of the non-display area. This makes it difficult to further narrow the bottom bezel, becoming one of the main bottlenecks in achieving narrow bezel designs.

[0003] Existing technology proposes a scheme to lay out fan-out traces inside the display area, known as Fanout in AA (FIAA). This scheme moves some of the fan-out signal lines, which were originally all located in the non-display area of ​​the lower bezel, into the display area, connecting them to the corresponding data lines through internal traces within the display area. By adopting the FIAA scheme, the required trace width or number of lines in the non-display area of ​​the lower bezel is significantly reduced, thus enabling a narrower bezel design.

[0004] However, when the fan-out signal lines are moved into the display area, these traces will generate large capacitance with other components, resulting in defects such as bright lines. Summary of the Invention

[0005] This application provides an array substrate, its fabrication method, and a display panel, aiming to improve the problems of traces generating large capacitance with other devices, resulting in bright lines and other defects.

[0006] A first aspect of this application provides an array substrate having a display area and a non-display area, the non-display area surrounding at least a portion of the display area. The array substrate includes: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer including first signal lines located in the display area and the non-display area; and a second conductive layer located on the side of the first conductive layer facing away from the substrate, the second conductive layer including a plurality of pixel electrodes, the plurality of pixel electrodes being arranged along a first direction to form a pixel electrode row, the plurality of pixel electrode rows being arranged along a second direction, the first direction and the second direction intersecting, wherein the first signal line includes a first segment located in the display area, the first segment including a first sub-segment extending along the first direction and a second sub-segment extending along the second direction, at least a portion of the second sub-segment being connected between two adjacent first sub-segments, the orthographic projection of a first sub-segment on the substrate overlapping the orthographic projection of a row of pixel electrodes on the substrate, and the orthographic projections of different first sub-segments on the substrate overlapping the orthographic projections of different rows of pixel electrodes on the substrate.

[0007] According to the implementation of the first aspect of this application, the total scanning time of the multi-row pixel electrode rows corresponding to the first segment is the total row time, the initialization period of the pixel electrodes is the working period, and the total row time is less than the working period.

[0008] According to any of the foregoing embodiments of the first aspect of this application, within one frame time, the initialization control circuit of a row of pixel electrodes performs an initialization operation more than twice.

[0009] According to any of the foregoing embodiments of the first aspect of this application, the dimensions of a plurality of first segments are the same or different in a first direction.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the non-display area includes a binding area, which is located on one side of the display area in the second direction. In the direction from the display area to the binding area, the size of the first sub-segment gradually increases in the first direction.

[0011] According to any of the foregoing embodiments of the first aspect of this application, two adjacent first segments are spaced apart in a first direction to form a preset interval.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the preset intervals corresponding to each pair of adjacent first sub-segments are equal or unequal.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the non-display area includes a binding area, which is located on one side of the display area in the second direction. In the direction from the display area to the binding area, the preset interval between each pair of adjacent first sub-segments gradually increases.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the angle between the second sub-segment and the first direction is less than 90 degrees.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the array substrate further includes: a third conductive layer located between the substrate and the first conductive layer, the third conductive layer further including a second signal line, at least a portion of the second signal line being located within the display area and extending along a first direction.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the second signal line is a scan signal line.

[0017] According to any of the foregoing embodiments of the first aspect of this application, the array substrate further includes: a fourth conductive layer located between the third conductive layer and the first conductive layer, the fourth conductive layer including a first shielding portion, the orthographic projection of the first sub-segment on the substrate at least partially overlapping the orthographic projection of the first shielding portion on the substrate, and the first shielding portion being connected to a fixed potential.

[0018] According to any of the foregoing embodiments of the first aspect of this application, the array substrate further includes: a fifth conductive layer located between the first conductive layer and the second conductive layer, the fifth conductive layer including a second shielding portion, the orthographic projection of the first sub-segment on the substrate at least partially overlapping the orthographic projection of the second shielding portion on the substrate, and the second shielding portion being connected to a fixed potential.

[0019] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projections of two adjacent first sub-segments on the substrate overlap with the orthographic projections of two adjacent pixel electrode rows on the substrate, or one or more rows of pixel electrode rows are provided between two adjacent first sub-segments.

[0020] According to any of the foregoing embodiments of the first aspect of this application, the number of pixel electrode rows between two adjacent first sub-segments may be equal or unequal.

[0021] According to any of the foregoing embodiments of the first aspect of this application, there are multiple first signal lines, which are spaced apart.

[0022] According to any of the foregoing embodiments of the first aspect of this application, a plurality of first signal lines are disposed on both sides of the array substrate in a first direction.

[0023] According to any of the foregoing embodiments of the first aspect of this application, a plurality of first signal lines are symmetrical about a first reference line, and the first reference line extends along a second direction.

[0024] According to any of the foregoing embodiments of the first aspect of this application, the first signal line further includes a second segment and a third segment located in the non-display area, the second segment being located on one side of the display area in the first direction, and the third segment being located on one side of the display area in the second direction.

[0025] According to any of the foregoing embodiments of the first aspect of this application, the first signal line is a fan-out signal line.

[0026] An embodiment of the second aspect of this application provides a display panel that includes an array substrate of any of the above embodiments.

[0027] An array substrate according to an embodiment of this application. The array substrate includes a substrate, a first conductive layer, and a second conductive layer. A first segment of a first signal line located within a display area is further divided into a first sub-segment and a second sub-segment, wherein the first sub-segment extends along a first direction and overlaps with the orthographic projection of a row of pixel electrodes, and the second sub-segment extends along a second direction and connects to adjacent first sub-segments, and different first sub-segments overlap with different rows of pixel electrodes respectively. Without this segmentation structure, when one row of pixel electrodes is initialized, the first segment will simultaneously overlap with multiple pixel electrodes within that row of pixel electrodes and generate parasitic capacitance. With this segmentation structure, when one row of pixel electrodes is initialized, a certain first sub-segment of the first segment will overlap with the pixel electrodes within that row of pixel electrodes and generate parasitic capacitance, but the length of the split first sub-segment is smaller than that of the continuous first segment in the first direction, the overlap area between the first sub-segment and the pixel electrode is smaller, the generated parasitic capacitance is less, and the pixel electrodes corresponding to other first sub-segments have not yet been initialized, thus reducing the parasitic capacitance between other first sub-segments and pixel electrodes. Therefore, this structure helps to improve the parasitic capacitive coupling problem caused by the first segment of the first signal line continuously crossing multiple pixel electrodes in the first direction, reduces the risk of interference to the first signal line during single-line initialization or data writing, and improves defects such as bright lines caused by interference to the first signal line in the display area. At the same time, since part of the first signal line's trace is incorporated into the display area, the line width or number of lines required in the non-display area can be reduced, thereby facilitating a narrower bezel design. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0029] Figure 1 This is a top view schematic diagram of an array substrate provided in an embodiment of this application; Figure 2 This is a partial top view of an array substrate provided in an embodiment of this application; Figure 3 This is an initialization timing diagram of a pixel electrode provided in an embodiment of this application; Figure 4 This is a top view of the array substrate in another embodiment; Figure 5 This is a top view of the array substrate in yet another embodiment; Figure 6 This is a partial top view of the array substrate in another embodiment; Figure 7This is a partial cross-sectional view of an array substrate provided in an embodiment of this application; Figure 8 This is a partial cross-sectional view of the array substrate in another embodiment; Figure 9 This is a top view of the array substrate in another embodiment; Figure 10 This is a top view of the array substrate in another embodiment.

[0030] Explanation of reference numerals in the attached figures: 10. Array substrate; AA, display area; NA, non-display area; NA1, bonding area; 100. Substrate; 200, First conductive layer; 210, First signal line; 211, First segment; 211a, First sub-segment; 211b, Second sub-segment; 212, Second segment; 213, Third segment; 300, Second conductive layer; 310, Pixel electrode; 320, Pixel electrode row; 400, Third conductive layer; 410, Second signal line; 500, Fourth conductive layer; 510, First shielding part; 600. Fifth conductive layer; 610. Second shielding section; m, total number of rows in time; T, work cycle; D0, preset interval; L1, first reference line; X, the first direction; Y, the second direction. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0033] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0034] For certain elements, terms like "above" or "over" are sometimes used when describing their location, while "below" or "under" is used when describing the location of an element in the opposite direction. Furthermore, when using terms like "above," "over," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only situations where the two elements are directly adjacent but also situations where they are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for descriptive distinction and should not be interpreted as indicating or implying relative importance.

[0035] As users increasingly demand higher screen-to-body ratios and greater aesthetic appeal, the bezel width, especially the bottom bezel, has become a key design consideration. In conventional display panels, the driver chip is typically located in the bottom bezel area, requiring fan-out lines to route the data signals output by the driver chip to the various data lines within the display area. However, these fan-out lines need to be distributed in a fan shape in the bottom bezel area, occupying a significant portion of the non-display area. This makes it difficult to further narrow the bottom bezel, becoming one of the main bottlenecks in achieving narrow bezel designs.

[0036] In a display panel, the non-display area (usually called the bezel area) needs to accommodate fanout lines to route the data signals output by the driver chip to the data lines in each column of the display area. With increasing user demand for narrow bezels, the traditional method of concentrating all fanout lines on the bottom bezel is limited by space constraints. One improvement is to route some of the fanout lines (i.e., the first signal line of this application) inside the display area (Fanout in AA, FIAA). However, this results in large-area parasitic capacitive coupling between the first signal line and the pixel electrode, as well as coupling capacitance between the first signal line and the scan signal line, which can easily produce diagonal bright lines or striped bright lines on the displayed image.

[0037] To address the aforementioned technical problems, this application provides an array substrate, its fabrication method, and a display panel. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the array substrate, its fabrication method, and the display panel.

[0038] Please see Figure 1 and Figure 2 , Figure 1This is a top view schematic diagram of an array substrate provided in an embodiment of this application; Figure 2 This is a partial top view of an array substrate provided in an embodiment of this application.

[0039] like Figure 1 and Figure 2 As shown, a first aspect embodiment of this application provides an array substrate 10, which has a display area AA and a non-display area NA. The non-display area NA is disposed around at least a portion of the display area AA. The array substrate 10 includes: a substrate 100; a first conductive layer 200 located on one side of the substrate 100, the first conductive layer 200 including first signal lines 210 located in the display area AA and the non-display area NA; and a second conductive layer 300 located on the side of the first conductive layer 200 away from the substrate 100, the second conductive layer 300 including a plurality of pixel electrodes 310. The plurality of pixel electrodes 310 are arranged along a first direction X to form a pixel electrode row 320. The pixel electrode row 320 is arranged along the second direction Y, and the first direction X and the second direction Y intersect. The first signal line 210 includes a first segment 211 located in the display area AA. The first segment 211 includes a first sub-segment 211a extending along the first direction X and a second sub-segment 211b extending along the second direction Y. The second sub-segment 211b connects two adjacent first sub-segments 211a. The orthographic projection of one first sub-segment 211a on the substrate 100 overlaps with the orthographic projection of a row of pixel electrode rows 320 on the substrate 100. The orthographic projections of different first sub-segments 211a on the substrate 100 overlap with the orthographic projections of different rows of pixel electrode rows 320 on the substrate 100.

[0040] The visibility of the diagonal bright line is closely related to the ratio of the parasitic capacitance CFIAA between the horizontal trace and the pixel electrode 310 and the total capacitance Cdata of the data signal path. When this ratio is less than a certain critical value 'a', the human eye cannot perceive the diagonal bright line; when the ratio is greater than or equal to 'a', the diagonal bright line is visible. This critical value 'a' can be determined experimentally: multiple sets of test samples with different segment lengths are prepared, their CFIAA and Cdata are measured, and the ratio when the diagonal bright line just disappears is observed, which is then determined as 'a'. In this application, by dividing the first segment 211 of the first signal line 210 into multiple first sub-segments 211a, the parasitic capacitance CFIAA between each first sub-segment 211a and the corresponding row pixel electrode 310 is significantly reduced, thereby satisfying CFIAA / Cdata < a, achieving the purpose of eliminating the diagonal bright line.

[0041] Array substrate 10 according to an embodiment of the present application. The array substrate 10 includes a substrate 100, a first conductive layer 200, and a second conductive layer 300. A first segment 211 of the first signal line 210 located in the display area AA is further split into a first sub-segment 211a and a second sub-segment 211b. The first sub-segment 211a extends along the first direction X and overlaps with the orthographic projection of a row of pixel electrodes 320. The second sub-segment 211b extends along the second direction Y and connects adjacent first sub-segments 211a. Different first sub-segments 211a overlap with different rows of pixel electrodes 320 respectively. In the case where this segmented structure is not adopted, when a row of pixel electrodes 320 is initialized, the first segment 211 will simultaneously overlap with multiple pixel electrodes 310 in this row of pixel electrodes 320 and generate parasitic capacitance. In the case where this segmented structure is adopted, when a row of pixel electrodes 320 is initialized, a certain first sub-segment 211a of the first segment 211 will overlap with the pixel electrodes 310 in this row of pixel electrodes 320 and generate parasitic capacitance. However, the first sub-segment 211a formed by splitting is smaller in length than the first segment 211 that is continuous in the first direction X. The overlapping area between the first sub-segment 211a and the pixel electrodes 310 is smaller, and the generated parasitic capacitance is less. As a result, the ratio of the parasitic capacitance CFIAA between the first sub-segment 211a and the corresponding row of pixel electrodes 310 to the total capacitance Cdata of the data signal path satisfies CFIAA / Cdata < a, where a is the critical ratio for the disappearance of the oblique bright line. And the pixel electrodes 310 corresponding to other first sub-segments 211a have not been initialized yet, and the parasitic capacitance between other first sub-segments 211a and the pixel electrodes 310 is reduced. Therefore, this structure helps to improve the parasitic capacitance coupling problem caused by the first segment 211 of the first signal line 210 continuously spanning multiple pixel electrodes 310 in the first direction X, reduces the interference risk to the first signal line 210 during the single-row initialization or data writing process, and improves the defective problems such as bright lines caused by the interference of the first signal line 210 in the display area AA. At the same time, since part of the routing of the first signal line 210 is included in the display area AA, the line width or the number of lines required to be arranged in the non-display area NA can be reduced, which is beneficial to achieving a narrower border design.

[0042] In addition, the overlap of the first sub-segment 211a with the orthographic projection of the pixel electrode row 320 means that there is an interlayer insulating layer between the first sub-segment 211a and the pixel electrodes 310 in the vertical direction. The insulating layer material is usually silicon oxide, silicon nitride, or an organic planarization layer, and its thickness and dielectric constant directly affect the magnitude of the parasitic capacitance. The present application reduces the capacitance value structurally by segmenting and shortening the overlapping length, which is more flexible than simply adjusting the thickness or material of the insulating layer and does not affect other electrical properties.

[0043] Please refer to Figures 1 to 3 , Figure 3It is an initialization timing diagram of a pixel electrode provided by an embodiment of the present application.

[0044] As Figures 1 to 3 shown, in some optional embodiments, the total scanning time of multiple pixel electrode rows 320 corresponding to the first segment 211 is the total number of rows time m, the initialization period of the pixel electrode 310 is the working period T, and the total number of rows time m is less than the working period T.

[0045] The "total number of rows time m" refers to the cumulative duration required for all pixel electrode rows 320 spanned by a first segment 211 (i.e., having electrical connection or projection overlap therewith), in the order of row-by-row scanning, from the first row to the last row. This duration is equal to the number of rows multiplied by the single-row scanning time. The "working period T" refers to the time interval between two adjacent initialization operations of the pixel electrode 310 initialization control circuit, usually set by the timing of the driving chip, such as initializing once per frame or initializing once per multiple rows.

[0046] In these optional embodiments, the total scanning time of multiple pixel electrode rows 320 corresponding to the first segment 211 is defined as the total number of rows time m, the initialization period of the pixel electrode 310 is defined as the working period T, and the total number of rows time m is less than the working period T. Under this condition, during the sequential scanning of multiple pixel electrode rows 320 spanned by the first segment 211, the initialization operation of the pixel electrode 310 will not occur repeatedly within this time interval, thus avoiding the overlap coupling of the initialization signal and the scanning signal in time, helping to reduce the risk of parasitic capacitance superposition caused by the overlap of the initialization period and the scanning period, and improving the uniformity of the display screen. The overlap coupling of the initialization signal and the scanning signal in time includes the overlap of the initialization signals corresponding to different pixel electrode rows 320, and the overlap of the scanning signals corresponding to different pixel electrode rows 320.

[0047] This condition ensures that in a non-overlapping timing environment, only by meeting the basic segmented capacitance ratio can the skew bright line be eliminated, without further strict segmentation, thus reducing the design complexity.

[0048] Under this condition, due to the absence of coupling superposition caused by timing overlap, only CFIAA / Cdata < a needs to be satisfied. When the total number of rows time m is greater than or equal to the working period T, there will be time overlap of multiple initialization or scanning signals, resulting in the effective interference superposition n times (n is greater than or equal to 2). At this time, a more strict condition CFIAA / Cdata < a / n needs to be satisfied. By controlling the total number of rows time m to be less than the working period T, the present application avoids the superposition effect, thereby reducing the requirements for segmented design.

[0049] In some optional embodiments, within one frame time, the initialization control circuit of a row of pixel electrodes 320 performs more than two initialization operations.

[0050] In these optional embodiments, within one frame time, the initialization control circuit of a row of pixel electrodes 320 performs more than two initialization operations, that is, an initialization strategy with a higher frequency than the conventional one is adopted. This high-frequency initialization is beneficial to improving the potential holding ability of the pixel electrodes 310 within the frame period and reducing the risk of brightness change caused by the leakage of the pixel electrodes 310 or the off-state current of the transistors, and is particularly suitable for low-frequency driving or high-refresh-rate display modes. For example, at a refresh rate of 60 Hz, conventionally, initialization is performed once per frame. If it is changed to perform initialization three times per frame, the working period T is shortened to 1 / 3 of the frame period. At this time, the working period T is shortened. To ensure that the total number of rows time m < T, it is necessary to reduce the number of rows spanned by the first segment 211 or further shorten the length of the first sub-segment 211a (that is, increase the number of segments) to maintain CFIAA / Cdata < a / n (n is the number of superpositions). Those skilled in the art can design according to the actual driving frequency and the value of a.

[0051] In this case, among multiple rows of pixel electrodes 320, there may be at least two rows of pixel electrodes 320 where the corresponding initialization signals or scan signals overlap and couple. Therefore, limiting the total number of rows time m within one working period T can avoid the problem of overlap and coupling of the initialization signals or scan signals.

[0052] In some optional embodiments, the sizes of multiple first sub-segments 211a in the first direction X are the same or different.

[0053] The size of the first sub-segment 211a in the first direction X refers to the length of the first sub-segment 211a along the extension direction of the pixel electrode row 320, and this length determines the overlapping width with multiple pixel electrodes 310 within one row of pixel electrode rows 320. The larger the overlapping width, the larger the parasitic capacitance, but at the same time, the smaller the signal line resistance.

[0054] In these optional embodiments, the sizes of multiple first sub-segments 211a in the first direction X can be set to be the same, so that the parasitic capacitance corresponding to each row of pixel electrode rows 320 is consistent, which helps to simplify the design rules and reduce the layout complexity; they can also be set to be different, so as to adjust the overlapping area between the first sub-segment 211a and the pixel electrode 310 according to the position of each pixel electrode row 320 (such as the distance from the bonding area NA1), realize the differential matching of the parasitic capacitance, and improve the full-screen display consistency.

[0055] Please refer to Figure 4 , Figure 4 which is a top view schematic diagram of an array substrate in another embodiment.

[0056] like Figure 4 As shown, in some optional embodiments, the non-display area NA includes a binding area NA1, which is located on one side of the display area AA in the second direction Y. In the direction from the display area AA to the binding area NA1, the size of the first sub-segment 211a gradually increases in the first direction X.

[0057] The bonding area NA1 refers to the area used to mount the driver chip or flexible circuit board, typically located on the bottom bezel of the display panel. The direction from the display area AA to the bonding area NA1 is the direction from the inside of the display area AA towards the outside of the bonding area NA1.

[0058] In these alternative embodiments, since the first sub-segment 211a, which is closer to the binding area NA1, typically carries a longer signal transmission path, increasing its size helps to reduce trace resistance and improve signal delay. At the same time, since the first sub-segment 211a still overlaps with the corresponding row of pixel electrodes 320, and each first sub-segment 211a covers only one row, even if the size is increased, the risk of parasitic coupling to other rows will not be significantly increased, thus achieving a balance between signal integrity and interference suppression.

[0059] Optionally, in the direction from the display area AA to the binding area NA1, the size of the first sub-segment 211a gradually decreases in the first direction X.

[0060] Please see Figure 5 , Figure 5 This is a top view of the array substrate in another embodiment.

[0061] like Figure 5 As shown, optionally, two adjacent first sub-segments 211a are spaced apart by a preset interval D0 in the first direction X. This interval physically separates the two first sub-segments 211a from each other, further reducing the direct coupling capacitance between adjacent first sub-segments 211a and reducing the risk of display abnormalities caused by signal crosstalk. By staggering the positions of the first sub-segments 211a in adjacent rows, the spatial frequency of the interference can be increased. Utilizing the spatial frequency modulation effect of human vision, residual bright lines can be further masked, making them indistinguishable to the human eye.

[0062] In some optional embodiments, the preset interval D0 corresponding to each two adjacent first segments 211a is equal or unequal.

[0063] In these optional embodiments, when the preset interval D0 between each adjacent first sub-segment 211a is equal, the parasitic capacitance distribution exhibits a uniform pattern, facilitating simulation and compensation. When the preset interval D0 is unequal, a non-uniform layout can be implemented based on the actual interference intensity of each pixel electrode row 320. For example, the interval can be reduced in areas with severe interference to increase the segment density, thereby allowing for more flexible control of inter-row coupling.

[0064] In some optional embodiments, the non-display area NA includes a binding area NA1, which is located on one side of the display area AA in the second direction Y. In the direction from the display area AA to the binding area NA1, the preset interval D0 corresponding to each two adjacent first sub-segments 211a gradually increases.

[0065] In these optional embodiments, the preset interval D0 gradually increases in the direction from the display area AA to the bonding area NA1. Areas closer to the bonding area NA1 typically have dense wiring and frequent initialization operations; using a smaller interval helps increase the number of first segments 211a and reduce the parasitic capacitance of a single first segment 211a. Areas farther from the bonding area NA1 have larger intervals, reducing the number of segments and simplifying wiring. This gradual interval layout is beneficial for adapting to differences in parasitic capacitance sensitivity in different areas, improving overall display quality.

[0066] Optionally, the angle between the second sub-segment 211b and the first direction X is less than 90 degrees. The second sub-segment 211b extends at an angle relative to the first direction X. This angled routing reduces the overlap area between the second sub-segment 211b and the pixel electrode row 320 or pixel electrode 310 on the orthographic projection of the substrate 100, thereby reducing the parasitic capacitance between the second sub-segment 211b and the pixel electrode 310, which helps to further suppress the additional coupling interference introduced by the second sub-segment 211b. It also facilitates the spacing between two adjacent first sub-segments 211a in the first direction X.

[0067] Please see Figures 1 to 7 , Figure 6 This is a partial top view of the array substrate in another embodiment; Figure 7 This is a partial cross-sectional view of an array substrate provided in an embodiment of this application.

[0068] like Figures 1 to 7 As shown, optionally, the array substrate 10 further includes: a third conductive layer 400 located between the substrate 100 and the first conductive layer 200, the third conductive layer 400 further including a second signal line 410, at least a portion of the second signal line 410 being located within the display area AA and extending along the first direction X.

[0069] Optionally, the second signal line 410 is a scan signal line. The scan signal line is used to transmit the gate enable signal line by line. Its potential change amplitude is usually large, and it is easy to couple to the upper first sub-segment 211a through interlayer capacitance.

[0070] In some optional embodiments, the array substrate 10 further includes a fourth conductive layer 500 located between the third conductive layer 400 and the first conductive layer 200. The fourth conductive layer 500 includes a first shielding portion 510, wherein the orthographic projection of the first sub-segment 211a on the substrate 100 at least partially overlaps with the orthographic projection of the first shielding portion 510 on the substrate 100, and the first shielding portion 510 is connected to a fixed potential.

[0071] The fixed potential can be ground potential VSS, DC low potential VGL, or power supply positive potential VDD, as long as the potential remains stable during display operation. VSS is usually chosen to obtain the best AC shielding effect.

[0072] In these optional embodiments, the orthographic projection of the first shield 510 on the substrate 100 at least partially overlaps with the orthographic projection of the first sub-segment 211a, and the first shield 510 is connected to a fixed potential. This first shield 510 effectively blocks the electric field coupling between the second signal line 410 and the first sub-segment 211a, reduces the parasitic capacitance between them, and improves the voltage disturbance caused by scanning signal transitions to the first sub-segment 211a, thereby enhancing display stability.

[0073] Without a segmented structure, when data is written to one row of pixel electrodes 320, the first segment 211 forms a coupling capacitance with the nearby second signal line 410. With a segmented structure, when data is written to one row of pixel electrodes 320, a first sub-segment 211a of the first segment 211 forms a coupling capacitance with the nearby second signal line 410 of that row of pixel electrodes 320. However, the length of the split first sub-segment 211a is smaller than that of the continuous first segment 211 in the first direction X, and the coupling capacitance between the split first sub-segment 211a and the second signal line 410 is smaller. Furthermore, since the pixel electrode rows 320 corresponding to the other first sub-segments 211a have not yet been written to, the coupling capacitance between the other first sub-segments 211a and the second signal line 410 is reduced. Therefore, this structure helps to improve the problem of coupling capacitance between the first segment 211 of the first signal line 210 and the second signal line 410, reduce the risk of interference to the first signal line 210 during single-line data writing, and improve the problem of bright lines and other defects caused by interference to the first signal line 210 in the display area AA.

[0074] Please see Figures 1 to 8 , Figure 8 This is a partial cross-sectional view of the array substrate in another embodiment.

[0075] like Figures 1 to 8 As shown, in some optional embodiments, the array substrate 10 further includes a fifth conductive layer 600 located between the first conductive layer 200 and the second conductive layer 300. The fifth conductive layer 600 includes a second shielding portion 610, and the orthographic projection of the first sub-segment 211a on the substrate 100 at least partially overlaps with the orthographic projection of the second shielding portion 610 on the substrate 100. The second shielding portion 610 is connected to a fixed potential.

[0076] In these alternative embodiments, the second shield 610 is located between the first sub-segment 211a and the pixel electrode 310, which can significantly reduce the parasitic capacitance between the first sub-segment 211a and the pixel electrode 310, reduce the interference of the pixel electrode 310 on the first sub-segment 211a during initialization or data writing, and improve the problem of bright or dark lines caused by parasitic coupling.

[0077] Optionally, the fifth conductive layer 600 can be made of the same metal material as the first conductive layer 200 (such as copper, molybdenum, aluminum, molybdenum, etc.), or it can be made of a transparent conductive oxide such as indium tin oxide. If indium tin oxide is used, it can be reused as both a touch electrode and a common electrode to save on mask costs.

[0078] The second shielding part 610 and the first shielding part 510 can coexist to form a double-layer shielding structure, thereby simultaneously isolating bidirectional interference from the lower scan line and the upper pixel electrode 310.

[0079] In some optional embodiments, the orthographic projections of two adjacent first sub-segments 211a onto the substrate 100 overlap with the orthographic projections of two adjacent pixel electrode rows 320 onto the substrate 100, or one or more rows of pixel electrode rows 320 are provided between two adjacent first sub-segments 211a.

[0080] In these optional embodiments, two adjacent first sub-segments 211a can overlap with two adjacent pixel electrode rows 320 respectively. At this time, the distribution density of the first sub-segments 211a is the highest, which is beneficial to minimize the length of each first sub-segment 211a and thus reduce parasitic capacitance. Alternatively, one or more rows of pixel electrode rows 320 can be set between two adjacent first sub-segments 211a, that is, skipping several rows without setting the first sub-segments 211a. This method can reduce the total number of first sub-segments 211a, simplify the layout and save wiring space.

[0081] When one or more rows of pixel electrode rows 320 are provided between two adjacent first sub-segments 211a, the pixel electrodes 310 of these intermediate rows do not overlap with any of the first sub-segments 211a, and therefore no additional parasitic capacitance is introduced through the first sub-segments 211a. However, in order to ensure that the data signals of these rows can be written normally, other routing methods can be used, such as directly powering the vertical data lines, or obtaining signals from adjacent first sub-segments 211a through jumpers.

[0082] In some alternative embodiments, the number of pixel electrode rows 320 between two adjacent first sub-segments 211a may be equal or unequal.

[0083] In these optional embodiments, when the number of skipped pixel electrode rows 320 between adjacent first sub-segments 211a is equal, the distribution of the first sub-segments 211a exhibits a periodic pattern, which facilitates mask design and timing control; when the number is unequal, a non-uniform distribution can be made according to the interference intensity or narrow bezel requirements of different regions, thereby achieving an optimized configuration between parasitic capacitance suppression and wiring resource consumption.

[0084] Please see Figure 9 and Figure 10 , Figure 9 This is a top view of the array substrate in another embodiment; Figure 10 This is a top view of the array substrate in another embodiment.

[0085] like Figure 9 and Figure 10 As shown, optionally, there are multiple first signal lines 210, and the multiple first signal lines 210 are arranged at intervals.

[0086] Optionally, multiple first signal lines 210 are disposed on both sides of the array substrate 10 in the first direction X.

[0087] In some alternative embodiments, a plurality of first signal lines 210 are symmetrical about a first reference line L1, which extends along a second direction Y.

[0088] In these alternative embodiments, a plurality of first signal lines 210 are symmetrically distributed about a first reference line L1 extending along a second direction Y. The symmetrical layout makes the signal line lengths, loads, and parasitic capacitances on the left and right sides of the display area AA substantially the same, thereby improving the charging consistency of the pixel electrodes 310 on the left and right sides and reducing the risk of vertical brightness gradients caused by signal delay differences, which is particularly suitable for large-size or high-resolution display panels.

[0089] Optionally, the first signal line 210 further includes a second segment 212 and a third segment 213 located in the non-display area NA. The second segment 212 is located on one side of the display area AA in the first direction X, and the third segment 213 is located on one side of the display area AA in the second direction Y. The first signal line 210 can bypass the non-display area NA and enter the display area AA. The third segment 213 is typically used to connect to the driver chip, the second segment 212 is used for data transmission in the non-display area NA, and the first segment 211 is used to implement fan-out routing, which helps to distribute the traces that were originally concentrated on the bottom bezel to the display area AA, thereby reducing the width of the bottom bezel.

[0090] Specifically, the third segment 213 is located in the lower border binding area NA1, the second segment 212 is located in the left or right border, and the first segment 211 passes horizontally through the bottom area of ​​the display area AA and connects to the data lines of each column.

[0091] Optionally, the first signal line 210 is a fan-out signal line. In this solution, the first segment 211 of the fan-out signal line is moved into the display area AA and a segmented overlapping structure is adopted. This retains the narrow bezel effect and controls the parasitic capacitance by overlapping the first sub-segment 211a with the pixel electrode row 320 row by row, thereby improving the display problems that may be caused by the fan-out line being built into the display area AA.

[0092] In some optional embodiments, the array substrate 10 further includes a timing control circuit that, during the scanning time of a row of pixel electrode rows 320, further divides a corresponding first sub-segment 211a into multiple virtual sub-segments and sequentially connects each virtual sub-segment in a time-division manner, such that the length of the first sub-segment 211a involved in coupling at any given time is less than its physical length.

[0093] In these optional embodiments, the scheme does not change the physical mask structure, but only uses time-division multiplexing to divide a whole first sub-segment 211a into multiple segments in time, which is equivalent to further reducing the instantaneous CFIAA. This can compensate for the reduction ratio through timing means when the physical segments are insufficient (e.g., due to limitations in the process that prevent further shortening). At the same time, this timing control can be coordinated with the conditions of the total number of lines time m and the working cycle T to dynamically adjust the number of virtual segments to adapt to different refresh rates or display modes.

[0094] In some optional embodiments, the array substrate 10 further includes a detection unit and an adjustable capacitor array. The detection unit is used to detect the visibility of the oblique bright line in the display area AA or the coupling voltage on the first sub-segment 211a. The adjustable capacitor array is connected in parallel or in series with the first sub-segment 211a. The detection unit adjusts the capacitance value of the adjustable capacitor array according to the detection result so that CFIAA / Cdata is less than the critical value a in real time.

[0095] In these alternative embodiments, the actual parasitic capacitance ratio may deviate from the design value due to process variations, temperature changes, or aging effects. This solution introduces a closed-loop feedback adjustment mechanism that adaptively compensates for deviations, ensuring that the inequality conditions are met under different operating conditions. Compared to a passive fixed segment design, this active calibration structure improves product reliability and yield, and can be applied to high-reliability display products.

[0096] A first aspect of this application provides an array substrate 10, which has a display area AA and a non-display area NA. The non-display area NA is disposed around at least a portion of the display area AA. The array substrate 10 includes: a substrate 100; a first conductive layer 200 located on one side of the substrate 100, the first conductive layer 200 including first signal lines 210 located in the display area AA and the non-display area NA; and a second conductive layer 300 located on the side of the first conductive layer 200 away from the substrate 100, the second conductive layer 300 including a plurality of pixel electrodes 310. The plurality of pixel electrodes 310 are arranged along a first direction X to form a pixel electrode row 320. The pixel electrode rows 320 are arranged along the second direction Y, where the first direction X and the second direction Y intersect. The first signal line 210 includes a first segment 211 located in the display area AA. The first segment 211 includes a first sub-segment 211a extending along the first direction X and a second sub-segment 211b extending along the second direction Y. The second sub-segment 211b connects two adjacent first sub-segments 211a. The orthographic projection of one first sub-segment 211a onto the substrate 100 overlaps with the orthographic projection of a row of pixel electrode rows 320 onto the substrate 100. The orthographic projections of different first sub-segments 211a onto the substrate 100 overlap with the orthographic projections of different rows of pixel electrode rows 320 onto the substrate 100. The total scanning time for the multiple rows of pixel electrode rows 320 corresponding to the first segment 211 is the total row time m. The initialization period of the pixel electrode 310 is the working period T, where the total row time m is less than the working period T. Within one frame, the initialization control circuit for one row of pixel electrode rows 320 performs at least two initialization operations. The array substrate 10 further includes a third conductive layer 400 located between the substrate 100 and the first conductive layer 200. The third conductive layer 400 also includes a second signal line 410, at least a portion of which is located within the display area AA and extends along the first direction X.

[0097] In some possible implementations, this application also provides a display panel that includes the array substrate 10 described in this application. Because this display panel includes the array substrate 10 described in this application, its reliability is higher.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

[0100] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that, The array substrate has a display area and a non-display area, the non-display area being disposed around at least a portion of the display area, and the array substrate includes: Substrate; A first conductive layer is located on one side of the substrate, and the first conductive layer includes a first signal line located in the display area and the non-display area; A second conductive layer is located on the side of the first conductive layer facing away from the substrate. The second conductive layer includes a plurality of pixel electrodes arranged along a first direction to form pixel electrode rows, and a plurality of pixel electrode rows arranged along a second direction, wherein the first direction and the second direction intersect. The first signal line includes a first segment located in the display area. The first segment includes a first sub-segment extending along the first direction and a second sub-segment extending along the second direction. At least a portion of the second sub-segment is connected between two adjacent first sub-segments. The orthographic projection of one first sub-segment on the substrate overlaps with the orthographic projection of a row of pixel electrodes on the substrate. The orthographic projections of different first sub-segments on the substrate overlap with the orthographic projections of different rows of pixel electrodes on the substrate.

2. The array substrate according to claim 1, characterized in that, The total scanning time of the multiple rows of pixel electrodes corresponding to the first segment is the total row time, the initialization period of the pixel electrode is the working period, and the total row time is less than the working period. Preferably, within one frame, the initialization control circuit of one row of pixel electrodes performs an initialization operation more than twice.

3. The array substrate according to claim 1, characterized in that, Multiple first sub-segments may have the same or different dimensions in the first direction; Preferably, the non-display area includes a binding area, which is located on one side of the display area in the second direction. In the direction from the display area to the binding area, the size of the first sub-segment gradually increases in the first direction.

4. The array substrate according to claim 1, characterized in that, Two adjacent first sub-segments are spaced apart in the first direction to form a preset interval; Preferably, the preset intervals corresponding to each pair of adjacent first sub-segments are equal or unequal; Preferably, the non-display area includes a binding area, which is located on one side of the display area in the second direction. In the direction from the display area to the binding area, the preset interval between each pair of adjacent first sub-segments gradually increases. Preferably, the angle between the second sub-segment and the first direction is less than 90 degrees.

5. The array substrate according to claim 1, characterized in that, The array substrate further includes: A third conductive layer is located between the substrate and the first conductive layer. The third conductive layer further includes a second signal line, at least a portion of which is located within the display area and extends along the first direction. Preferably, the second signal line is a scan signal line; Preferably, the array substrate further includes: A fourth conductive layer is located between the third conductive layer and the first conductive layer. The fourth conductive layer includes a first shielding portion. The orthographic projection of the first sub-segment onto the substrate at least partially overlaps with the orthographic projection of the first shielding portion onto the substrate. The first shielding portion is connected to a fixed potential.

6. The array substrate according to claim 1, characterized in that, The array substrate further includes: A fifth conductive layer is located between the first conductive layer and the second conductive layer. The fifth conductive layer includes a second shielding portion. The orthographic projection of the first sub-segment onto the substrate and the orthographic projection of the second shielding portion onto the substrate at least partially overlap. The second shielding portion is connected to a fixed potential.

7. The array substrate according to claim 1, characterized in that, The orthographic projections of two adjacent first sub-segments on the substrate overlap with the orthographic projections of two adjacent pixel electrode rows on the substrate, or one or more rows of pixel electrode rows are provided between two adjacent first sub-segments; Preferably, the number of pixel electrode rows between two adjacent first sub-segments is equal or unequal.

8. The array substrate according to claim 1, characterized in that, There are multiple first signal lines, and the multiple first signal lines are spaced apart; Preferably, the plurality of first signal lines are disposed on both sides of the array substrate in the first direction; Preferably, the plurality of first signal lines are symmetrical about the first reference line, and the first reference line extends along the second direction.

9. The array substrate according to claim 1, characterized in that, The first signal line further includes a second segment and a third segment located in the non-display area, the second segment being located on one side of the display area in the first direction, and the third segment being located on one side of the display area in the second direction; Preferably, the first signal line is a fan-out signal line.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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