Topcon cell and preparation method thereof

Abstract

The application discloses a kind of TopCon battery and preparation method thereof, method includes: providing N-type silicon substrate;N-type silicon substrate includes front surface and back surface;First tunneling oxide layer and first doped layer are prepared on back surface;Second tunneling oxide layer and second doped layer are prepared on front surface;Second tunneling oxide layer and second doped layer of preset texturing area of front surface are removed, to expose part of N-type silicon substrate, and texturing is carried out on the surface of exposed part of N-type silicon substrate, to form the structure of surface texture;First doped layer of back surface and second doped layer of front surface are screen printed and high-temperature sintered, to form first electrode in contact with first doped layer on back surface, and to form second electrode in contact with second doped layer on front surface.Using the above method, the contact resistivity of the electrode and the front surface field layer is reduced, the fill factor of the battery is improved, and the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] This invention relates to the technical field of photovoltaic cells, and more particularly to a TopCon cell and its preparation method. Background Technology

[0002] With the increasing global demand for clean energy, solar energy, as an inexhaustible energy source, has attracted much attention.

[0003] In the development of solar cell technology, TopCon cells typically have polycrystalline silicon layers on the back side, with no polycrystalline silicon layer on the front side, only a front surface field layer, resulting in a single-sided passivation structure. When texturing the front side of this type of cell, a textured structure is usually formed across the entire front surface, allowing the front electrodes to contact only the front surface field layer. However, the doping concentration of the front surface field layer is usually low, increasing the contact resistivity between the electrodes and the front surface field layer, thus reducing the fill factor of the cell. Furthermore, this structure reduces the reflectivity of sunlight on the front side, thereby reducing the current and affecting the cell's power generation efficiency. Summary of the Invention

[0004] This invention provides a TopCon battery and its fabrication method. By forming a textured structure in a predetermined texturing area on the front side and forming a second tunneling oxide layer and a second doped layer in areas outside the predetermined texturing area, the contact resistivity of the electrodes and the reflectivity of sunlight on the front side are reduced, the current and the fill factor of the battery are increased, thereby improving the battery's conversion efficiency.

[0005] In a first aspect, the present invention provides a method for preparing a TopCon battery, comprising:

[0006] Provides N-type silicon substrates; N-type silicon substrates include a front side and a back side;

[0007] Selective passivation contact layers are prepared on the back side and the front side, respectively. The selective passivation contact layer on the back side includes a first tunneling oxide layer and a first doped layer, and the selective passivation contact layer on the front side includes a second tunneling oxide layer and a second doped layer.

[0008] The second tunneling oxide layer and the second doped layer in the pre-defined texturing area on the front side are removed to expose part of the N-type silicon substrate, and texturing is performed on the exposed part of the N-type silicon substrate to form a textured surface structure.

[0009] The first doped layer on the back side and the second doped layer on the front side are screen printed and sintered at high temperature to form a first electrode on the back side that contacts the first doped layer, and a second electrode on the front side that contacts the second doped layer.

[0010] Optionally, the second tunneling oxide layer and the second doped layer in the pre-defined texturing region on the front side are removed to expose a portion of the N-type silicon substrate, and texturing is performed on the exposed portion of the N-type silicon substrate surface to form a textured structure, including:

[0011] Using a pre-defined texturing process, under pre-defined texturing conditions, the second tunneling oxide layer and the second doped layer in the pre-defined texturing area on the front side are removed to expose part of the N-type silicon substrate; and texturing is performed on the surface of the exposed part of the N-type silicon substrate to form a textured surface structure.

[0012] Optionally, the preset texturing conditions are as follows: a mixed solution is formed by introducing a 35%-45% sodium hydroxide solution or potassium hydroxide solution with a volume of 10L-20L, a texturing additive with a volume of 3L-6L, and water with a volume of 450L-500L into the reaction chamber of the texturing process; the preset etching temperature is 75℃-80℃.

[0013] The composition of the flocking additive includes 2%-3% surfactant, 1%-3% defoamer, 1%-1.5% nucleating agent, 4%-6% sodium benzoate, and 85%-95% water by mass.

[0014] Optionally, selective passivation contact layers are prepared on the back side and the front side, respectively, including:

[0015] Using a deposition process, a first tunneling oxide layer is deposited on the back side to form a first tunneling oxide layer, and a second tunneling oxide layer is deposited on the front side to form a second tunneling oxide layer.

[0016] Using a deposition process, a first intrinsic silicon layer is deposited on the surface of the first tunneling oxide layer on the side away from the N-type silicon substrate, and a second intrinsic silicon layer is deposited on the surface of the second tunneling oxide layer on the side away from the N-type silicon substrate.

[0017] Boron diffusion process is used to dope the first intrinsic silicon layer with boron to form a first doped layer and a first mask layer;

[0018] The second intrinsic silicon layer is phosphorus-doped using a phosphorus diffusion process to form a second doped layer and a second mask layer.

[0019] Remove the second mask layer from the pre-set texturing area on the front.

[0020] Optionally, after depositing a first intrinsic silicon layer on the surface of the first tunneling oxide layer facing away from the N-type silicon substrate using a deposition process, and depositing a second intrinsic silicon layer on the surface of the second tunneling oxide layer facing away from the N-type silicon substrate, the process further includes:

[0021] A first mask oxide layer is deposited on the surface of the first intrinsic silicon layer away from the N-type silicon substrate; a second mask oxide layer is deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate.

[0022] Optionally, before forming the first doped layer and the first mask layer, the process further includes boron doping the first intrinsic silicon layer using a boron diffusion process:

[0023] Remove the first mask oxide layer on the back side;

[0024] Before forming the second doped layer and the second mask layer by phosphorus diffusion process, the process also includes:

[0025] Remove the second mask oxide layer on the front side.

[0026] Optionally, a boron diffusion process is used to dope the first intrinsic silicon layer with boron to form a first doped layer and a first mask layer, including:

[0027] Using a boron diffusion process, under preset boron diffusion conditions, the first intrinsic silicon layer is boron-doped to form a first doped layer and a first mask layer;

[0028] The preset boron diffusion conditions include a first low-temperature deposition condition and a boron diffusion condition. The first low-temperature deposition condition involves introducing boron trichloride at a flow rate of 180 sccm / min-220 sccm / min, oxygen at a flow rate of 500 sccm / min-800 sccm / min and a pressure of 120 mbar-180 mbar, and nitrogen at a flow rate of 1500 sccm / min-3000 sccm / min into the low-temperature deposition reaction chamber, with a deposition temperature of 830℃-870℃ and a deposition time of 15 min-30 min. The boron diffusion condition involves introducing oxygen at a flow rate of 1000 sccm / min-3000 sccm / min and a pressure of 700 mbar-900 mbar into the boron diffusion reaction chamber, with a diffusion time of 10 min-30 min and a diffusion temperature of 900℃-950℃.

[0029] Optionally, using a phosphorus diffusion process, the second intrinsic silicon layer is boron-doped to form a second doped layer and a second mask layer, including:

[0030] Using a phosphorus diffusion process, under preset phosphorus diffusion conditions, boron doping is performed on the second intrinsic silicon layer to form a second doped layer and a second mask layer.

[0031] The preset phosphorus diffusion conditions include a second low-temperature deposition condition and a phosphorus diffusion condition. The second low-temperature deposition condition involves introducing phosphorus oxychloride at a flow rate of 1200 sccm / min-1500 sccm / min, oxygen at a flow rate of 500 sccm / min-700 sccm / min and a pressure of 120 mbar-180 mbar, and a deposition time of 10 min-15 min. The phosphorus diffusion condition involves introducing oxygen at a flow rate of 500 sccm / min-1500 sccm / min into the phosphorus diffusion reaction chamber, a diffusion time of 15 min-30 min, and a diffusion temperature of 870℃-890℃.

[0032] Optionally, before removing the second tunneling oxide layer and the second doped layer from the pre-defined texturing region on the front side to expose a portion of the N-type silicon substrate, the method further includes:

[0033] The second mask layer of the pre-set texturing area on the front side is removed using laser etching.

[0034] Optionally, before screen printing and high-temperature sintering the first doped layer on the back side and the second doped layer on the front side to form a first electrode in contact with the first doped layer on the back side and a second electrode in contact with the second doped layer on the front side, the method further includes:

[0035] Remove the first mask layer on the back and the second mask layer outside the preset texturing area on the front.

[0036] Optionally, before screen printing and high-temperature sintering the first doped layer on the back side and the second doped layer on the front side to form a first electrode in contact with the first doped layer on the back side and a second electrode in contact with the second doped layer on the front side, the method further includes:

[0037] A first protective layer is prepared on the surface of the second doped layer and the textured structure on the front side facing away from the N-type silicon substrate, and a second protective layer is prepared on the surface of the first doped layer on the back side facing away from the N-type silicon substrate.

[0038] Optionally, before fabricating the selective passivation contact layers on the back and front sides respectively, the method further includes:

[0039] Double-sided polishing of the N-type silicon substrate.

[0040] In a second aspect, the present invention provides a TopCon battery, including an N-type silicon substrate. The N-type silicon substrate includes a front side and a back side. The back side includes a first tunneling oxide layer, a first doped layer, and a first electrode in contact with the first doped layer. The front side includes a preset texturing region and an electrode region. The preset texturing region is provided with a textured surface structure. The electrode region includes a second tunneling oxide layer, a second doped layer, and a second electrode in contact with the second doped layer.

[0041] Optionally, the TopCon battery also includes a first protective layer and a second protective layer;

[0042] The first protective layer is located on the side of the second doped layer and the textured structure facing away from the N-type silicon substrate; the second protective layer is located on the side of the first doped layer facing away from the N-type silicon substrate.

[0043] The technical solution of this invention provides an N-type silicon substrate, comprising a front side and a back side. Selective passivation contact layers are fabricated on both the front and back sides. The selective passivation contact layer on the back side comprises a first tunneling oxide layer and a first doped layer, and the selective passivation contact layer on the front side comprises a second tunneling oxide layer and a second doped layer. The second tunneling oxide layer and the second doped layer are removed from a predetermined texturing area on the front side to expose a portion of the N-type silicon substrate. Texturing is then performed on the exposed portion of the N-type silicon substrate surface to form a textured structure. The first doped layer on the back side and the second doped layer on the front side are screen-printed and sintered at high temperature to form a first electrode on the back side in contact with the first doped layer, and a second electrode on the front side in contact with the second doped layer. Using this method, by forming a textured structure in a predetermined texturing area on the front side and forming the second tunneling oxide layer and the second doped layer in areas outside the predetermined texturing area, the contact resistivity of the electrodes and the reflectivity of sunlight on the front side are reduced, increasing the current and the fill factor of the battery, thereby improving the battery's conversion efficiency.

[0044] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A flowchart illustrating a method for fabricating a TopCon battery according to an embodiment of the present invention;

[0047] Figure 2 A flowchart illustrating the fabrication process of a TopCon battery according to an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the structure of a TopCon battery provided in an embodiment of the present invention;

[0049] Figure 4A flowchart illustrating a second method for preparing a TopCon battery according to an embodiment of the present invention;

[0050] Figure 5 A flowchart illustrating a third method for preparing a TopCon battery according to an embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, preparation method, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0053] In one embodiment, Figure 1 This is a flowchart illustrating a method for fabricating a TopCon battery according to an embodiment of the present invention. Figure 2 This is a flowchart illustrating the fabrication process of a TopCon battery according to an embodiment of the present invention. Figure 3 This is a schematic diagram of a TopCon battery structure provided by an embodiment of the present invention. This embodiment is applicable to situations where damage to the N-type silicon substrate surface caused by laser shock can be avoided. Figures 1 to 3 As shown, the method includes:

[0054] S110 provides an N-type silicon substrate.

[0055] Among them, reference Figure 2 As shown in Figure a), the N-type silicon substrate 1 includes a front side and a back side.

[0056] S120. Selective passivation contact layers are prepared on the back side and the front side respectively. The selective passivation contact layer on the back side includes a first tunneling oxide layer and a first doped layer, and the selective passivation contact layer on the front side includes a second tunneling oxide layer and a second doped layer.

[0057] The selective passivation contact layer is a structure that combines efficient passivation with excellent electrical contact capabilities. It typically consists of an ultrathin tunneling oxide layer (such as SiOx) and a doped polycrystalline silicon layer. This structure effectively reduces surface recombination and metal-to-metal recombination while allowing efficient transport of photogenerated carriers, thereby improving the conversion efficiency of solar cells. The selective passivation contact layer 2 on the back side includes a first tunneling oxide layer 21 and a first doped layer 22, while the selective passivation contact layer 3 on the front side includes a second tunneling oxide layer 31 and a second doped layer 32. Both the first tunneling oxide layer 21 and the second tunneling oxide layer 22 are very thin insulating layers made of silicon dioxide (SiO2), used to allow majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thus achieving selective carrier collection, reducing surface recombination, increasing the open-circuit voltage and fill factor of the cell, and improving photoelectric conversion efficiency. The first doped layer 22 is a boron-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with boron. It is used to transport charge carriers and provides low contact resistivity with the metal to improve the fill factor. The second doped layer 32 is a phosphorus-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with phosphorus. It is used to transport charge carriers and provides low contact resistivity with the metal to improve the fill factor.

[0058] For details, please refer to Figure 2 As shown in Figure b), when forming the first tunneling oxide layer 21 and the first doped layer 22 on the back side, a deposition process can be used to deposit a complete layer of the first tunneling oxide layer 21 and the first intrinsic silicon layer on the back side. After forming the first intrinsic silicon layer, elemental doping is required to allow the doped element to diffuse into the first intrinsic silicon layer, forming the first doped layer 22. Similarly, when forming the second tunneling oxide layer 31 and the second doped layer 32 on the front side, a deposition process can be used to deposit a complete layer of the second tunneling oxide layer 31 and the second intrinsic silicon layer on the front side. After forming the second intrinsic silicon layer, elemental doping is required to allow the doped element to diffuse into the second intrinsic silicon layer, forming the second doped layer 32. The methods for depositing the first tunneling oxide layer 21, the first intrinsic silicon layer, the second tunneling oxide layer 31, and the second intrinsic silicon layer include, but are not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition, etc., and the specific method can be determined according to the actual situation, without limitation here.

[0059] It should be noted that, in order to save preparation time, a tunneling oxide layer and an intrinsic silicon layer can be deposited simultaneously on the front and back sides. After the intrinsic silicon layer is formed, the intrinsic silicon layer on the back and front sides is then doped with elements to form the first doped layer 22 and the second doped layer 23.

[0060] S130: Remove the second tunneling oxide layer and the second doped layer from the pre-defined texturing area on the front side to expose a portion of the N-type silicon substrate, and perform texturing on the exposed portion of the N-type silicon substrate to form a textured surface structure.

[0061] For details, please refer to Figure 2 As shown in Figure c), after forming a complete second tunneling oxide layer 31 and a second doped layer 32 on the front side, texturing is required on the front side. In this embodiment, texturing is performed only in a predetermined texturing area on the front side, and texturing is not performed in areas outside the predetermined texturing area, retaining the original second tunneling oxide layer 31 and second doped layer 32. Therefore, the second tunneling oxide layer 31 and the second doped layer 32 in the predetermined texturing area on the front side need to be removed to expose the surface of the N-type silicon substrate 1 in the predetermined texturing area. After exposing the N-type silicon substrate 1, texturing is performed on the exposed portion of the N-type silicon substrate 1 surface to form a textured surface structure. The method of removing the second tunneling oxide layer 31 and the second doped layer 32 may include, but is not limited to, alkaline etching removal.

[0062] S140. Screen printing and high-temperature sintering are performed on the first doped layer on the back side and the second doped layer on the front side to form a first electrode in contact with the first doped layer on the back side and a second electrode in contact with the second doped layer on the front side.

[0063] Screen printing is one of the core processes in the manufacturing of TopCon solar cells, primarily used for electrode formation. The purpose of forming the electrodes is to convert photogenerated carriers from solar energy into current that flows to the external circuit. This process utilizes the basic principle that the paste passes through the mesh openings of the screen patterned areas, while the paste does not pass through the non-patterned areas. During printing, the paste is precisely extruded through the mesh openings of the screen onto the N-type silicon substrate 1, forming the desired electrode pattern. Typically, the paste used for screen printing can include, but is not limited to, silver paste or aluminum paste, with silver paste being preferred. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed onto the surface of the solar cell at high temperatures, ensuring good ohmic contact between the metal grid lines and the doped layer.

[0064] For details, please refer to Figure 2As shown in Figure d), during electrode formation, screen printing is performed on the first doped layer 22 on the back side and the second doped layer 32 on the front side to form metal grid lines on the surfaces of the first doped layer 22 and the second doped layer 32, respectively. The metal grid lines include fine grids and main grids. After forming the metal grid lines, they are subjected to high-temperature sintering at a temperature of 780℃-840℃ for 40s-70s. Under these conditions, the sintered metal grid lines penetrate the first doped layer 22 and the second doped layer 32, forming good ohmic contact and improving the battery's electrical performance. Specifically, after high-temperature sintering, a first electrode 6 is formed on the back side, contacting the first doped layer 22, and a second electrode 7 is formed on the front side, contacting the second doped layer 32, thus fabricating a TopCon battery. Furthermore, the first electrode 6 and the second electrode 7 have opposite polarities; when the first electrode 6 is a positive electrode, the corresponding second electrode 7 is a negative electrode; and when the first electrode 6 is a negative electrode, the corresponding second electrode 7 is a positive electrode. In this embodiment, the back side is the p region and the front side is the n region. The first electrode 6 formed in the p region is the positive electrode, and the second electrode 7 formed in the n region is the negative electrode.

[0065] The technical solution of this invention provides an N-type silicon substrate, comprising a front side and a back side. A first tunneling oxide layer and a first doped layer are prepared on the back side. A second tunneling oxide layer and a second doped layer are prepared on the front side. The second tunneling oxide layer and the second doped layer in a predetermined texturing area on the front side are removed to expose a portion of the N-type silicon substrate. Texturing is then performed on the exposed portion of the N-type silicon substrate surface to form a textured structure. The first doped layer on the back side and the second doped layer on the front side are screen-printed and sintered at high temperature to form a first electrode in contact with the first doped layer on the back side and a second electrode in contact with the second doped layer on the front side. Using this method, by forming a textured structure in a predetermined texturing area on the front side and forming the second tunneling oxide layer and the second doped layer in areas outside the predetermined texturing area, the contact resistivity of the electrodes and the reflectivity of sunlight on the front side are reduced, increasing the current and the fill factor of the battery, thereby improving the battery's conversion efficiency.

[0066] Figure 4 This is a flowchart illustrating a second method for fabricating a TopCon battery according to an embodiment of the present invention. This embodiment refines the TopCon battery fabrication method compared to the previous embodiments. For details not covered in this embodiment, please refer to the previous embodiments; further elaboration is not required here. Figure 3 and Figure 4 As shown, the method includes:

[0067] S210 provides an N-type silicon substrate.

[0068] S220, selective passivation contact layers are prepared on the back and front sides respectively.

[0069] The selective passivation contact layer on the back side includes a first tunneling oxide layer and a first doped layer, and the selective passivation contact layer on the front side includes a second tunneling oxide layer and a second doped layer.

[0070] S230. Using a preset texturing process, under preset texturing conditions, the second tunneling oxide layer and the second doped layer in the preset texturing area on the front side are removed to expose part of the N-type silicon substrate; and texturing is performed on the surface of the exposed part of the N-type silicon substrate to form a textured surface structure.

[0071] Specifically, when forming a textured structure on the front side, the second tunneling oxide layer 31 and the second doped layer 32 in the preset texturing area must be removed first before texturing. In this embodiment, a preset texturing process is used. Under preset texturing conditions, a mixed solution consisting of a 35%-45% sodium hydroxide solution or potassium hydroxide solution with a volume of 10L-20L, a 3L-6L texturing additive, and 450L-500L water is introduced into the reaction chamber of the texturing process. Under the texturing conditions of a preset etching temperature of 75℃-80℃, the second tunneling oxide layer 31 and the second doped layer 32 in the preset texturing area are removed. After exposing part of the N-type silicon substrate 1, texturing is performed on the surface of the N-type silicon substrate 1 under the same preset texturing conditions to form a textured structure. The texturing additive can be formed by mixing 2%-3% by mass of surfactant, 1%-3% by mass of defoamer, 1%-1.5% by mass of nucleating agent, 4%-6% by mass of sodium benzoate, and 85%-95% by mass of water.

[0072] S240. Screen printing and high-temperature sintering are performed on the first doped layer on the back side and the second doped layer on the front side to form a first electrode in contact with the first doped layer on the back side and a second electrode in contact with the second doped layer on the front side.

[0073] The technical solution of this invention utilizes a preset texturing process. Under preset texturing conditions, the second tunneling oxide layer and the second doped layer in the preset texturing region on the front side are removed to expose a portion of the N-type silicon substrate. Texturing is then performed on the exposed portion of the N-type silicon substrate surface to form a textured structure. Using this method, the front-side texturing structure and electrode structure are fabricated in separate regions, reducing the reflectivity of sunlight on the front side, increasing current, and thus improving the battery's conversion efficiency.

[0074] Figure 5 This is a flowchart illustrating a third method for fabricating a TopCon battery according to an embodiment of the present invention. This embodiment refines the TopCon battery fabrication method compared to the previous embodiments. For details not covered in this embodiment, please refer to the previous embodiments; further elaboration is not required here. Figure 3and Figure 5 As shown, the method includes:

[0075] S310 provides an N-type silicon substrate.

[0076] S320: Perform double-sided polishing on an N-type silicon substrate.

[0077] Specifically, when performing double-sided polishing on the N-type silicon substrate 1, the N-type silicon substrate 1 can be placed in a mixed solution consisting of 19L-26L of sodium hydroxide solution, 3L-6L of polishing additive, and 450L-500L of water. The N-type silicon substrate 1 is then polished on both sides at a polishing temperature of 70℃-80℃. The polishing additive comprises 2%-3% by mass of surfactant, 2%-3% by mass of defoamer, 2%-4% by mass of antifoaming agent, 2%-3% by mass of glucose, and 85%-95% by mass of water. The surfactant may include, but is not limited to, sodium polyoxyethylene ether sulfate; the defoamer may include, but is not limited to, oxypropylene glycerol ether; and the antifoaming agent may include, but is not limited to, polydimethylsiloxane.

[0078] S330. Using a deposition process, a first tunneling oxide layer is deposited on the back side to form a first tunneling oxide layer, and a second tunneling oxide layer is deposited on the front side to form a second tunneling oxide layer.

[0079] S340. Using a deposition process, a first intrinsic silicon layer is deposited on the surface of the first tunneling oxide layer on the side away from the N-type silicon substrate, and a second intrinsic silicon layer is deposited on the surface of the second tunneling oxide layer on the side away from the N-type silicon substrate.

[0080] Both the first intrinsic silicon layer and the second intrinsic silicon layer are silicon material layers with intrinsic semiconductor properties. Intrinsic semiconductors are semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs within the material itself.

[0081] Specifically, a deposition process, including low-pressure chemical vapor deposition (LPCVD), is used to deposit oxides on both the front and back sides simultaneously. This is achieved by introducing 250-350 L of oxygen into the reaction chamber of the deposition process, and under deposition conditions of 590-610°C, 5-20 min, and 650-900 mbar, forming a first tunneling oxide layer 21 with a thickness of 1.5 nm-2.5 nm and a second tunneling oxide layer 31 with a thickness of 1.5 nm-2.5 nm. After the tunneling oxide layer is formed, a deposition process, such as low-pressure chemical vapor deposition, is used. Silane gas with a flow rate of 800 sccm / min-1200 sccm / min is introduced into the reaction chamber of the deposition process. Under deposition conditions of 600℃-630℃, 800s-1500s, and 25mbar-30mbar, a first intrinsic silicon layer with a thickness of 60nm-110nm is formed on the surface of the first tunneling oxide layer 21 away from the N-type silicon substrate 1, and a second intrinsic silicon layer with a thickness of 60nm-110nm is formed on the surface of the second tunneling oxide layer 31 away from the N-type silicon substrate 1.

[0082] S350, a first mask oxide layer is deposited on the surface of the first intrinsic silicon layer away from the N-type silicon substrate; a second mask oxide layer is deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate.

[0083] The first and second mask oxide layers refer to an oxide layer grown or deposited on the surface of the intrinsic silicon layer. This oxide layer may include, but is not limited to, SiO2, and is a protective layer with a specific pattern formed through photolithography and etching processes. This oxide layer can serve as a mask for subsequent processes, protecting areas not covered by the pattern from chemical or physical effects.

[0084] Specifically, using deposition processes such as low-pressure chemical vapor deposition, oxygen is introduced into the reaction chamber of the deposition process at a flow rate of 10,000 sccm / min-20,000 sccm / min. Under deposition conditions of 800℃-900℃, 800mbar-900mbar, and 20min-40min, a first mask oxide layer with a thickness of 20nm-40nm is deposited on the surface of the first intrinsic silicon layer away from the N-type silicon substrate, and a second mask oxide layer with a thickness of 20nm-40nm is deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate.

[0085] S360, Remove the first mask oxide layer on the back.

[0086] Specifically, before element doping the back side, the first mask oxide layer on the back side needs to be removed to expose the first intrinsic silicon layer on the back side, thereby allowing element doping of the first intrinsic silicon layer. In this embodiment, the N-type silicon substrate 1 is placed back-side down in a chain pickling solution, and the first mask oxide layer generated on the back side is removed by adding hydrofluoric acid with a concentration of 8%-15% to the chain pickling solution.

[0087] It should be noted that the second mask oxide layer on the front side, as a mask layer on the front side, can prevent the second intrinsic silicon layer from being doped simultaneously when the first intrinsic silicon layer on the back side is doped. Therefore, before doping the back side, only the first mask oxide layer on the back side is removed, while the second mask oxide layer on the front side is retained.

[0088] S370. Boron diffusion process is used to dope the first intrinsic silicon layer with boron to form the first doped layer and the first mask layer.

[0089] This step can be further refined as follows: using a boron diffusion process, under preset boron diffusion conditions, the first intrinsic silicon layer is boron-doped to form a first doped layer and a first mask layer; wherein the preset boron diffusion conditions include a first low-temperature deposition condition and a boron diffusion condition. The first low-temperature deposition condition involves introducing boron trichloride at a flow rate of 180 sccm / min-220 sccm / min, oxygen at a flow rate of 500 sccm / min-800 sccm / min and a pressure of 120 mbar-180 mbar, and nitrogen at a flow rate of 1500 sccm / min-3000 sccm / min into the low-temperature deposition reaction chamber, with a deposition temperature of 830℃-870℃ and a deposition time of 15 min-30 min; the boron diffusion condition involves introducing oxygen at a flow rate of 1000 sccm / min-3000 sccm / min and a pressure of 700 mbar-900 mbar into the boron diffusion reaction chamber, with a diffusion time of 10 min-30 min and a diffusion temperature of 900℃-950℃.

[0090] Among them, boron diffusion process is a doping technique used to introduce boron atoms into the first intrinsic silicon layer to form a p-type doped region.

[0091] Specifically, elemental doping of the first intrinsic silicon layer, specifically boron doping, typically involves low-temperature deposition and boron diffusion. This is achieved by introducing boron trichloride at a flow rate of 180 sccm / min-220 sccm / min, oxygen at a flow rate of 500 sccm / min-800 sccm / min and a pressure of 120 mbar-180 mbar, and nitrogen at a flow rate of 1500 sccm / min-3000 sccm / min into the low-temperature deposition chamber. The deposition temperature is 830℃-870℃, and the deposition time is 15 min-3000 sccm / min. Under the first low-temperature deposition condition of 0 min, boron of a certain thickness is formed on the surface of the first intrinsic silicon layer away from the N-type silicon substrate 1. After the formation of boron, it needs to be propelled at high temperature, that is, oxygen is continuously introduced into the boron diffusion reaction chamber at a flow rate of 1000 sccm / min-3000 sccm / min and a pressure of 700 mbar-900 mbar. Under diffusion conditions of 10 min-30 min and diffusion temperature of 900℃-950℃, boron diffuses into the first intrinsic silicon layer at high temperature, forming the first doped layer 22. Because boron cannot completely diffuse into the first intrinsic silicon layer during diffusion, a certain amount of residue will be generated on its surface. The residual boron will react chemically with the introduced oxygen to generate a first mask layer, namely a borosilicate glass layer (BSG). In this embodiment, the thickness of the first mask layer is 30 nm-60 nm. The doping concentration of the first doped layer 22 is 2E19 / cm3-5E19 / cm3.

[0092] S380, Remove the second mask oxide layer on the front side.

[0093] Specifically, after the first doped layer 22 and the first mask layer are formed on the back side, elemental doping is required on the front side. Similar to the back side, the second mask oxide layer on the front side needs to be removed before doping to expose the second intrinsic silicon layer on the front side. In this embodiment, the N-type silicon substrate 1 is placed face down in a chain pickling solution, and the second mask oxide layer formed on the front side is removed by adding hydrofluoric acid with a concentration of 8%-15% to the chain pickling solution. In addition, the first mask layer formed on the back side can prevent elemental doping from entering the back side during front-side doping.

[0094] S390. Using a phosphorus diffusion process, the second intrinsic silicon layer is phosphorus-doped to form a second doped layer and a second mask layer.

[0095] This step can be further refined as follows: using a phosphorus diffusion process, under preset phosphorus diffusion conditions, boron doping is performed on the second intrinsic silicon layer to form a second doped layer and a second mask layer; wherein, the preset phosphorus diffusion conditions include a second low-temperature deposition condition and a phosphorus diffusion condition, the second low-temperature deposition condition is to introduce phosphorus oxychloride at a flow rate of 1200 sccm / min-1500 sccm / min, oxygen at a flow rate of 500 sccm / min-700 sccm / min and a pressure of 120 mbar-180 mbar, and the deposition time is 10 min-15 min; the phosphorus diffusion condition is to introduce oxygen at a flow rate of 500 sccm / min-1500 sccm / min into the phosphorus diffusion reaction chamber, the diffusion time is 15 min-30 min, and the diffusion temperature is 870℃-890℃.

[0096] Phosphorus diffusion is a process that forms an n-region on an N-type silicon substrate 1 through phosphorus diffusion, thereby forming a PN junction. The PN junction is responsible for separating photogenerated carriers (electron-hole pairs) to achieve photoelectric conversion.

[0097] Specifically, when doping the second intrinsic silicon layer with phosphorus, it typically involves low-temperature deposition and phosphorus diffusion. Phosphorus oxychloride is introduced into the low-temperature deposition reaction chamber at a flow rate of 1200 sccm / min-1500 sccm / min, and oxygen at a flow rate of 500 sccm / min-700 sccm / min and a pressure of 120 mbar-180 mbar. Under the second low-temperature deposition conditions with a deposition time of 10 min-15 min, phosphorus of a certain thickness is formed on the surface of the second intrinsic silicon layer away from the N-type silicon substrate 1. After the phosphorus is formed, it needs to be propelled at high temperature. That is, oxygen is introduced into the phosphorus diffusion reaction chamber at a flow rate of 500 sccm / min-1500 sccm / min. Under the diffusion conditions of a diffusion time of 15 min-30 min and a diffusion temperature of 870℃-890℃, phosphorus diffuses into the second intrinsic silicon layer at high temperature, forming the second doped layer 32. Because phosphorus cannot completely diffuse into the second intrinsic silicon layer during diffusion, some residue will remain on its surface. This residual phosphorus will react chemically with the introduced oxygen to form a second mask layer, namely a phosphorosilicate glass (PSG) layer. In this embodiment, the thickness of the second mask layer is 30nm-50nm. The doping concentration of the second doped layer 32 is 4E20 / cm3-6E20 / cm3.

[0098] S400: Using laser etching process, the second mask layer of the pre-set texturing area on the front is removed.

[0099] Specifically, after the second mask layer is formed on the front side, texturing is required on the front side, which requires exposing the N-type silicon substrate 1 of the pre-textured area on the front side. Therefore, the second mask layer of the pre-textured area on the front side needs to be removed first. In this embodiment, the second mask layer of the pre-textured area is removed by using a laser etching process under laser etching conditions with a laser spot width of 600um-850um and a laser power of 5W-10W, exposing the second doped layer 32.

[0100] S410: Remove the second tunneling oxide layer and the second doped layer from the pre-defined texturing area on the front side to expose a portion of the N-type silicon substrate, and perform texturing on the exposed portion of the N-type silicon substrate to form a textured surface structure.

[0101] S420, Remove the first mask layer on the back and the second mask layer outside the preset texturing area on the front.

[0102] Specifically, after forming the textured structure, electrodes need to be formed. Therefore, the second mask layer on the surface of the first mask layer and the second doped layer 32 formed on the back side needs to be removed. In this embodiment, the N-type silicon substrate 1 is placed in a mixed acidic solution of hydrofluoric acid with a volume of 50L-100L and water with a volume of 380L-430L. The first mask layer and the second mask layer are removed during an etching time of 100s-150s, exposing the first doped layer 22 on the back side and the second doped layer 32 on the front side.

[0103] S430. A first protective layer is prepared on the surface of the second doped layer and the textured structure on the front side facing away from the N-type silicon substrate, and a second protective layer is prepared on the surface of the first doped layer on the back side facing away from the N-type silicon substrate.

[0104] Both the first protective layer 4 and the second protective layer 5 include a passivation layer and an anti-reflection layer, used to reduce sunlight reflection, increase sunlight absorption, improve battery conversion efficiency, reduce surface recombination, increase carrier mobility, and improve overall battery performance. Both the first protective layer 4 and the second protective layer 5 include, but are not limited to, a passivation layer and an anti-reflection layer. The passivation layer may contain, but is not limited to, aluminum oxide, silicon oxide, or a combination of aluminum oxide and silicon oxide; the anti-reflection layer may contain, but is not limited to, silicon nitride, a combination of silicon nitride and silicon oxide, or silicon oxynitride.

[0105] Specifically, after forming the textured structure on the front side, a first protective layer 4 needs to be prepared on the surface of the second doped layer 32 on the front side and on the side of the textured structure facing away from the N-type silicon substrate 1. This can be achieved through deposition or other processes, and is not limited here. Additionally, a second protective layer 5 needs to be prepared on the surface of the first doped layer 22 on the back side, away from the N-type silicon substrate 1, to reduce surface reflection of the TopCon cell, increase the surface area of ​​the TopCon cell, reduce sunlight reflection, improve the cell's light trapping effect and absorption rate of sunlight, generate more photogenerated carriers, and improve the conversion efficiency of the TopCon cell. The texturing process can include, but is not limited to, trench texturing, and the processes for preparing the first protective layer 4 and the second protective layer 5 include, but are not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition, etc., and can be determined according to the actual situation, and is not limited here.

[0106] It should be noted that, under normal circumstances, during the preparation of passivation layers on the front and back sides, atomic layer deposition is usually used to deposit passivation layers on both sides simultaneously to reduce the number of processes and shorten the preparation time.

[0107] S440. Screen printing and high-temperature sintering are performed on the first doped layer on the back side and the second doped layer on the front side to form a first electrode in contact with the first doped layer on the back side and a second electrode in contact with the second doped layer on the front side.

[0108] The technical solution of this invention involves double-sided polishing of an N-type silicon substrate; depositing a first tunneling oxide layer on the back side and a second tunneling oxide layer on the front side using a deposition process; depositing a first intrinsic silicon layer on the surface of the first tunneling oxide layer away from the N-type silicon substrate using a deposition process, and depositing a second intrinsic silicon layer on the surface of the second tunneling oxide layer away from the N-type silicon substrate using a deposition process; depositing a first mask oxide layer on the surface of the first intrinsic silicon layer away from the N-type silicon substrate; depositing a second mask oxide layer on the surface of the second intrinsic silicon layer away from the N-type silicon substrate; and removing the first mask oxide layer from the back side. The process involves: 1) Boron diffusion to dope a first intrinsic silicon layer, forming a first doped layer and a first mask layer; 2) Removing the second mask oxide layer on the front side; 3) Phosphorus diffusion to dope a second intrinsic silicon layer, forming a second doped layer and a second mask layer; 4) Laser etching to remove the second mask layer in the pre-defined texturing area on the front side; 5) Removing the first mask layer on the back side and the second mask layer outside the pre-defined texturing area on the front side; 6) Fabricating a first protective layer on the surface of the second doped layer and the textured structure on the front side facing away from the N-type silicon substrate, and fabricating a second protective layer on the surface of the first doped layer on the back side facing away from the N-type silicon substrate. By using the above method, through the fabrication of a passivation contact layer on the front side, boron diffusion on the back side, and phosphorus diffusion on the front side, the reflectivity of the front side to sunlight is reduced, the output current is increased, and thus the photoelectric conversion efficiency of the battery is improved.

[0109] In another specific embodiment, the present invention also provides a method for preparing a TopCon battery, the method comprising:

[0110] S1. Double-sided polishing of the N-type silicon substrate is performed using a mixed solution consisting of 20L NaOH solution, 4L polishing additive, and 470L water, at a polishing temperature of 75℃. The polishing additive comprises: 2.5% surfactant, 2.5% defoamer, 2% antifoaming agent, 3% glucose, and 90% water by mass. The surfactant is sodium polyoxyethylene ether sulfate, the defoamer can be oxypropylene glycerol ether, and the antifoaming agent is polydimethylsiloxane.

[0111] S2. The N-type silicon substrate in S1 is subjected to double-sided LPCVD to grow selective passivation contact structures on the front and back sides. The selective passivation contact structure includes a tunneling oxide layer and a doped layer. By introducing 300L of oxygen into the reaction chamber of the deposition process and setting the oxidation temperature to 603℃, the oxidation time to 10min, and the pressure to 850mbar, a tunneling oxide layer with a thickness of 2.0nm is formed on both the front and back sides.

[0112] Intrinsic silicon layer growth was then carried out by introducing silane at a flow rate of 1150 sccm / min into the reaction chamber of the deposition process. Under the deposition conditions of 610℃ deposition temperature, 1200s deposition time and 28mabr pressure, intrinsic silicon layers with a thickness of 85nm were formed on the surface of the tunneling oxide layer on the front and back sides, respectively.

[0113] Double-sided oxide layers are grown outside the intrinsic silicon layer. Oxygen is then introduced into the reaction chamber of the deposition process at a flow rate of 15000 sccm / min. Under deposition conditions of 850℃, 850mbar, and 30min, mask oxide layers with a thickness of 30nm are formed on the surface of the tunnel oxide layer on both the front and back sides. The main function of this oxide layer is to serve as a mask layer in the subsequent doping process.

[0114] S3. Clean the mask oxide layer on the back side of the N-type silicon substrate. The cleaning method is to pass the N-type silicon substrate with the back side facing down through a chain acid pickling process. The chain acid pickling solution is hydrofluoric acid, and the HF concentration is controlled at 9% to remove the mask oxide layer on the back side.

[0115] S4. Boron diffusion is performed on the back side of an N-type silicon substrate. BCl3 gas (190 sccm / min), oxygen gas (650 sccm / min), and nitrogen gas (2000 sccm / min) are introduced into the diffusion chamber at a diffusion temperature of 850°C, a diffusion pressure of 160 mbar, and a diffusion time of 20 min. This forms a boron layer on the surface of the first intrinsic silicon layer on the back side, away from the N-type silicon substrate. Then, oxygen gas (2000 sccm / min) is introduced into the diffusion chamber at a high-temperature propagation temperature of 920°C, a propagation time of 15 min, and a pressure of 800 mbar. This propagates the boron into the first intrinsic silicon layer on the back side, forming the first doped layer. A first mask layer (BSG) is then formed on the surface of the first doped layer. The thickness of the BSG is 40 nm. The doping concentration of the formed first doped layer is 3.5E19 / cm3. Due to the presence of the mask oxide layer on the front side, no boron doping is performed.

[0116] S5. Clean the mask oxide layer on the front side of the N-type silicon substrate. The cleaning method is to pass the N-type silicon substrate with the front side facing down through a chain acid pickling process. The chain acid pickling solution is hydrofluoric acid, and the HF concentration is controlled at 9% to remove the mask oxide layer on the front side.

[0117] S6. Phosphorus doping is performed on the front side of the N-type silicon substrate. Phosphorus oxychloride at a flow rate of 1400 sccm / min and oxygen at a flow rate of 650 sccm / min are introduced into the diffusion chamber under diffusion conditions of 170 mbar, 13 min, and 796 °C. A phosphorus layer is formed on the surface of the second intrinsic silicon layer on the front side, away from the N-type silicon substrate. Then, oxygen at a flow rate of 1000 sccm / min is introduced into the diffusion chamber, and the phosphorus is advanced into the second intrinsic silicon layer on the front side at a high temperature of 875 °C for 20 min, forming a second doped layer. A second mask layer (PSG) is formed on the surface of the second doped layer, with a PSG thickness of 35 nm and a doping concentration of 5.8E20 / cm3. The back side, due to the presence of the first mask layer (BSG), does not undergo phosphorus-free doping.

[0118] S7. Laser etching of PSG is performed on the pre-defined texturing area on the front side of the N-type silicon substrate. The PSG in the pre-defined texturing area is removed under laser etching conditions with a laser spot width of 800 μm and a laser power of 6 W. The width of the pre-defined texturing area is 988 μm.

[0119] S8. Etching removes the doped layer and tunneling oxide layer of the pre-defined texturing area on the front side and performs texturing. The non-etched area is unaffected by texturing due to the protection of the second mask layer. The reflectivity of the textured surface in the laser area is 9.5% (9%-10%). A mixed solution consisting of 15L of 40% NaOH solution, 4.0L of texturing additive, and 465L of water is introduced into the reaction chamber of the alkaline etching process. Under conditions of 80°C, the doped layer and tunneling oxide layer of the pre-defined texturing area are removed, and a textured structure is formed on the exposed N-type silicon substrate surface. The texturing additive consists of 3% surfactant, 2% defoamer, 1% nucleating agent, 5% sodium benzoate, and 89% water by mass. The surfactant includes sodium polyoxyethylene ether sulfate, the defoamer can be oxypropylene glycerol ether, and the nucleating agent can be sodium citrate.

[0120] S9. Acid etching removes PSG from the front side (excluding the pre-defined texturing area) and BSG from the back side. The front PSG and back BSG are removed by introducing 70L of HF and 410L of water into the acid etching reaction chamber for 120s.

[0121] S10. Perform subsequent double-sided ALD deposition on the N-type silicon substrate to form aluminum oxide with a thickness of 5 nm on the front and back sides, form silicon nitride with a thickness of 76 nm on the surface of the aluminum oxide on the front side, form silicon nitride with a thickness of 80 nm on the surface of the aluminum oxide on the back side, and perform screen printing and high-temperature sintering, wherein the high-temperature sintering temperature is 810°C and the sintering time is 50 s, to form a second electrode in contact with the second doped layer on the front side and a first electrode in contact with the first doped layer on the back side.

[0122] It should be noted that Table 1 is a schematic table illustrating the performance differences between a TopCon battery provided in this embodiment and existing batteries. Referring to Table 1, the doped layer thickness in this embodiment is 85 nm. It can be seen that by improving the structure and adjusting the thickness of the doped layer, the fill factor and on-state voltage are increased, thereby improving the battery's conversion efficiency. Furthermore, a thicker doped layer results in a more significant increase in current, but may reduce the battery's conversion efficiency. Therefore, based on a comprehensive consideration of battery performance, the doped layer thickness is set to 85 nm in this embodiment.

[0123] Table 1

[0124] Doping layer thickness Conversion efficiency (%) Open voltage (mV) Current (A) Fill factor (%) 135 nm 26.45 0.7411 13.930 85.38 85 nm 26.54 0.7443 13.892 85.63 60 nm 26.50 0.7431 13.905 85.51 110 nm 26.53 0.7451 13.868 85.69

[0125] Based on the same inventive concept, continue to refer to Figure 3 The present invention provides a TopCon battery, including an N-type silicon substrate 1. The N-type silicon substrate 1 includes a front side and a back side. The back side includes a first tunneling oxide layer 21, a first doped layer 22, and a first electrode 6 in contact with the first doped layer 22. The front side includes a preset texturing region and an electrode region. The preset texturing region is provided with a textured surface structure. The electrode region includes a second tunneling oxide layer 31, a second doped layer 32, and a second electrode 7 in contact with the second doped layer 32.

[0126] The first tunneling oxide layer 21 and the second tunneling oxide layer 22 are both very thin insulating layers made of silicon dioxide (SiO2). These layers allow majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thus achieving selective carrier collection, reducing surface recombination, increasing the open-circuit voltage and fill factor of the battery, and improving photoelectric conversion efficiency. The first doped layer 22 is a boron-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with boron. It is used to transport carriers and provides low contact resistivity with the metal to improve the fill factor. The second doped layer 32 is a phosphorus-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with phosphorus. It is used to transport carriers and provides low contact resistivity with the metal to improve the fill factor. The first electrode 6 is the positive electrode, and the second electrode 7 is the negative electrode.

[0127] Specifically, the fabrication of the front-side structure of the battery may involve first depositing a continuous second tunneling oxide layer 31 and a second doped layer 32 on the front side. During texturing, texturing is performed only in a predetermined texturing area on the front side; areas outside this area are not texturized, but the original second tunneling oxide layer 31 and second doped layer 32 are retained. Therefore, the second tunneling oxide layer 31 and second doped layer 32 in the predetermined texturing area on the front side need to be removed, exposing the surface of the N-type silicon substrate 1 in the predetermined texturing area. After exposing the N-type silicon substrate 1, texturing is performed on the exposed portion of the N-type silicon substrate 1 surface to form a textured structure. After forming the textured structure, processes such as screen printing and high-temperature sintering are used to form the first electrode 6 in contact with the first doped layer 22 and the second electrode 7 in contact with the second doped layer 32. The width of the predetermined texturing area can be 988 μm. This method of fabricating the doped layer on the front side and texturing only in the predetermined texturing area reduces the contact resistivity of the electrodes and the reflectivity of sunlight on the front side, increases the current and the fill factor of the battery, thereby improving the battery's conversion efficiency.

[0128] Optional, continue to refer to Figure 3 The TopCon cell also includes a first protective layer 4 and a second protective layer 5; the first protective layer 4 is located on the side surface of the second doped layer and textured structure that is away from the N-type silicon substrate; the second protective layer 5 is located on the side surface of the first doped layer that is away from the N-type silicon substrate.

[0129] The first protective layer 4 and the second protective layer 5 both include a passivation layer and an antireflection layer, and the formation methods may include, but are not limited to, ALD deposition and PECVD deposition.

[0130] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0131] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing a TopCon battery, characterized in that, include: Provides N-type silicon substrates; The N-type silicon substrate includes a front side and a back side; Selective passivation contact layers are prepared on the back side and the front side respectively. The selective passivation contact layer on the back side includes a first tunneling oxide layer and a first doped layer, and the selective passivation contact layer on the front side includes a second tunneling oxide layer and a second doped layer. The second tunneling oxide layer and the second doped layer are removed from the pre-defined texturing area on the front side to expose a portion of the N-type silicon substrate, and texturing is performed on the exposed portion of the N-type silicon substrate to form a textured surface structure; The first doped layer on the back side and the second doped layer on the front side are screen printed and sintered at high temperature to form a first electrode in contact with the first doped layer on the back side and a second electrode in contact with the second doped layer on the front side.

2. The preparation method according to claim 1, characterized in that, Removing the second tunneling oxide layer and the second doped layer from the pre-defined texturing area on the front side to expose a portion of the N-type silicon substrate, and texturing the exposed portion of the N-type silicon substrate surface to form a textured structure, including: Using a preset texturing process, under preset texturing conditions, the second tunneling oxide layer and the second doped layer in the preset texturing area on the front side are removed to expose a portion of the N-type silicon substrate; and texturing is performed on the exposed portion of the N-type silicon substrate surface to form the textured surface structure.

3. The preparation method according to claim 2, characterized in that, The preset texturing conditions are as follows: a mixed solution is formed by introducing a 35%-45% sodium hydroxide solution or potassium hydroxide solution with a volume of 10L-20L, a texturing additive with a volume of 3L-6L, and water with a volume of 450L-500L into the reaction chamber of the texturing process; the preset etching temperature is 75℃-80℃. The composition of the flocking additive includes 2%-3% surfactant, 1%-3% defoamer, 1%-1.5% nucleating agent, 4%-6% sodium benzoate, and 85%-95% water by mass.

4. The preparation method according to claim 1, characterized in that, Selective passivation contact layers are prepared on the back side and the front side, respectively, including: Using a deposition process, the first tunneling oxide layer is deposited on the back side to form a first tunneling oxide layer, and the second tunneling oxide layer is deposited on the front side to form a second tunneling oxide layer. Using the deposition process, a first intrinsic silicon layer is deposited on the surface of the first tunneling oxide layer facing away from the N-type silicon substrate, and a second intrinsic silicon layer is deposited on the surface of the second tunneling oxide layer facing away from the N-type silicon substrate. Boron diffusion process is used to dope the first intrinsic silicon layer with boron to form the first doped layer and the first mask layer; The second intrinsic silicon layer is phosphorus-doped using a phosphorus diffusion process to form the second doped layer and the second mask layer. Remove the second mask layer from the pre-defined texturing area on the front side.

5. The preparation method according to claim 4, characterized in that, After depositing a first intrinsic silicon layer on the surface of the first tunneling oxide layer facing away from the N-type silicon substrate using the aforementioned deposition process, and depositing a second intrinsic silicon layer on the surface of the second tunneling oxide layer facing away from the N-type silicon substrate, the process further includes: A first mask oxide layer is deposited on the surface of the first intrinsic silicon layer away from the N-type silicon substrate; a second mask oxide layer is deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate.

6. The preparation method according to claim 5, characterized in that, Before forming the first doped layer and the first mask layer by boron diffusion process, the process further includes: Remove the first mask oxide layer on the back side; Before forming the second doped layer and the second mask layer by phosphorus diffusion process, the process further includes: Remove the second mask oxide layer on the front side.

7. The preparation method according to claim 4, characterized in that, Using a boron diffusion process, the first intrinsic silicon layer is boron-doped to form the first doped layer and the first mask layer, including: Using a boron diffusion process, under preset boron diffusion conditions, the first intrinsic silicon layer is boron doped to form the first doped layer and the first mask layer; The preset boron diffusion conditions include a first low-temperature deposition condition and a boron diffusion condition. The first low-temperature deposition condition involves introducing boron trichloride at a flow rate of 180 sccm / min-220 sccm / min, oxygen at a flow rate of 500 sccm / min-800 sccm / min and a pressure of 120 mbar-180 mbar, and nitrogen at a flow rate of 1500 sccm / min-3000 sccm / min into the low-temperature deposition reaction chamber, with a deposition temperature of 830℃-870℃ and a deposition time of 15 min-30 min. The boron diffusion condition involves introducing oxygen at a flow rate of 1000 sccm / min-3000 sccm / min and a pressure of 700 mbar-900 mbar into the boron diffusion reaction chamber, with a diffusion time of 10 min-30 min and a diffusion temperature of 900℃-950℃.

8. The preparation method according to claim 4, characterized in that, Using a phosphorus diffusion process, the second intrinsic silicon layer is phosphorus-doped to form the second doped layer and the second mask layer, including: Using a phosphorus diffusion process, under preset phosphorus diffusion conditions, the second intrinsic silicon layer is phosphorus-doped to form the second doped layer and the second mask layer. The preset phosphorus diffusion conditions include a second low-temperature deposition condition and a phosphorus diffusion condition. The second low-temperature deposition condition involves introducing phosphorus oxychloride at a flow rate of 1200 sccm / min-1500 sccm / min, oxygen at a flow rate of 500 sccm / min-700 sccm / min and a pressure of 120 mbar-180 mbar, and a deposition time of 10 min-15 min. The phosphorus diffusion condition involves introducing oxygen at a flow rate of 500 sccm / min-1500 sccm / min into the phosphorus diffusion reaction chamber, a diffusion time of 15 min-30 min, and a diffusion temperature of 870℃-890℃.

9. The preparation method according to claim 4, characterized in that, Before removing the second tunneling oxide layer and the second doped layer from the pre-defined texturing region on the front side to expose a portion of the N-type silicon substrate, the method further includes: The second mask layer of the pre-set texturing area on the front side is removed using a laser etching process.

10. The preparation method according to claim 4, characterized in that, Before screen printing and high-temperature sintering the first doped layer on the back side and the second doped layer on the front side to form a first electrode in contact with the first doped layer on the back side, and before forming a second electrode in contact with the second doped layer on the front side, the method further includes: Remove the first mask layer on the back side and the second mask layer outside the preset texturing area on the front side.

11. The preparation method according to claim 1, characterized in that, Before screen printing and high-temperature sintering the first doped layer on the back side and the second doped layer on the front side to form a first electrode in contact with the first doped layer on the back side, and before forming a second electrode in contact with the second doped layer on the front side, the method further includes: A first protective layer is formed on the surface of the second doped layer and the textured structure on the front side facing away from the N-type silicon substrate, and a second protective layer is formed on the surface of the first doped layer on the back side facing away from the N-type silicon substrate.

12. The preparation method according to claim 1, characterized in that, Before fabricating selective passivation contact layers on the back side and the front side respectively, the method further includes: The N-type silicon substrate is polished on both sides.

13. A TopCon battery, characterized in that, The invention includes an N-type silicon substrate, which has a front side and a back side. The back side includes a first tunneling oxide layer, a first doped layer, and a first electrode in contact with the first doped layer. The front side includes a preset texturing region and an electrode region. The preset texturing region has a textured surface structure. The electrode region includes a second tunneling oxide layer, a second doped layer, and a second electrode in contact with the second doped layer.

14. The TopCon battery according to claim 13, characterized in that, It also includes a first protective layer and a second protective layer; The first protective layer is located on the side surface of the second doped layer and the textured structure that is away from the N-type silicon substrate; the second protective layer is located on the side surface of the first doped layer that is away from the N-type silicon substrate.

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