A back contact cell and a method of manufacturing the same, a battery assembly

Abstract

The present application relates to the technical field of back contact cell, and particularly relates to a back contact cell, a preparation method thereof and a battery assembly. The P-type doped layer of the back contact cell adopts a laminated structure comprising at least a first P-type amorphous silicon layer, a P-type microcrystalline silicon layer and a second P-type amorphous silicon layer, which can effectively reduce the contact resistivity, and improve the fill factor and conversion efficiency of the cell.

Description

Technical Field

[0001] This invention relates to the field of back contact battery technology, specifically to a back contact battery and its preparation method and battery assembly. Background Technology

[0002] Back-contact (BC) batteries completely eliminate the shading of sunlight by the front electrode grid lines by transferring all the positive and negative metal contacts to the back of the battery. This allows the front of the battery to absorb more than 95% of the incident light, while reducing series resistance and significantly improving photoelectric conversion efficiency. However, as technology develops towards higher efficiency and lower cost, the back structure design of BC batteries faces a key challenge: the conductivity of the P-type doped amorphous silicon (pa-Si:H) layer is too low, and the contact resistivity with the back transparent conductive film layer (such as ITO or AZO) is relatively high. This results in a low fill factor and low conversion efficiency, becoming a core bottleneck restricting further improvements in battery efficiency. Summary of the Invention

[0003] Based on this, the present invention provides a back contact battery that can effectively reduce contact resistivity and improve the battery fill factor and photoelectric conversion efficiency.

[0004] The present invention also provides a method for preparing a back battery, which can not only reduce contact resistivity but also improve product yield.

[0005] The present invention also provides a battery assembly having a low contact resistivity, a high fill factor, and a high photoelectric conversion efficiency.

[0006] A first aspect of the present invention provides a back contact battery, comprising a substrate, the substrate comprising a front side and a back side;

[0007] A p-type doped layer, located on the back side of the substrate, comprises at least a first p-type amorphous silicon layer, a p-type microcrystalline silicon layer, and a second p-type amorphous silicon layer stacked along a first direction, wherein the p-type doping concentration in the second p-type amorphous silicon layer is 1e. 19 cm -3 -5e 20 cm -3 ;

[0008] The first direction is the direction from the front side of the substrate to the back side.

[0009] In the back contact battery described above, the doping concentration of the P-type dopant in the first P-type amorphous silicon layer is 1e. 18 cm -3 -1e 19 cm -3 .

[0010] The back contact battery described above further includes at least one of C and N as doping elements in the first P-type amorphous silicon layer.

[0011] In the back-contact battery described above, the refractive index of the first P-type amorphous silicon layer is 3.6-4.5.

[0012] In the back contact battery described above, the crystallinity of the P-type microcrystalline silicon layer is 5-80%.

[0013] In the back contact battery described above, the conductivity of the P-type microcrystalline silicon layer is 0.1-5 S / cm.

[0014] The back contact battery described above also includes:

[0015] A first semiconductor layer is disposed on the back side of the substrate, and a second semiconductor opening region is uniformly spaced on the first semiconductor layer. The first semiconductor layer includes a first intrinsic amorphous silicon layer and an N-type amorphous silicon layer in sequence along a first direction.

[0016] The second semiconductor layer is continuously disposed on the outer surface of the first semiconductor layer and within the second semiconductor opening region. The second semiconductor layer has a first semiconductor opening region arranged at intervals from the second semiconductor opening region. The second semiconductor layer includes a second intrinsic amorphous silicon layer and a P-type doped layer.

[0017] In the back contact battery described above, the P-type microcrystalline silicon layer is located in the middle of the second semiconductor opening region and a third P-type amorphous silicon layer is continuously disposed on the side near the first semiconductor layer. The third P-type amorphous silicon layer is disposed in the non-P-type microcrystalline silicon layer region on the surface of the first P-type amorphous silicon layer. The width of the P-type microcrystalline silicon layer is 30-80% of the width of the second semiconductor opening region.

[0018] As described above for the back contact battery, the doping concentration of P-type dopant in the second P-type amorphous silicon layer is greater than that in the third P-type amorphous silicon layer.

[0019] In the back-contact battery described above, the width of the second semiconductor opening region is 400-1000 μm.

[0020] In the back contact battery described above, the doping concentration of the P-type dopant in the third P-type amorphous silicon layer is 5e⁻¹. 18 cm -3 -5e 19 cm -3 .

[0021] In the back contact battery described above, the thickness of the first P-type amorphous silicon layer is 2-8 nm, the thickness of the P-type microcrystalline silicon layer is 10-25 nm, and the thickness of the second P-type amorphous silicon layer is 1-3 nm.

[0022] The back contact battery described above, the first semiconductor layer sequentially includes a first intrinsic amorphous silicon layer and an N-type amorphous silicon layer along the first direction.

[0023] The back contact battery described above further includes:

[0024] A conductive film layer is disposed on the outer surface of the second semiconductor layer and within the first semiconductor opening region, wherein the conductive film layer forms an insulating channel by opening between the first semiconductor opening region and the second semiconductor opening region.

[0025] A metal electrode is located on the outer surface of the conductive film layer and disposed within the first semiconductor opening region and the second semiconductor opening region;

[0026] A front passivation layer, wherein the front passivation layer is located on the front side of the substrate;

[0027] An antireflection layer is located on the surface of the front passivation layer away from the substrate.

[0028] The back contact battery described above further includes a mask layer located in the non-first semiconductor opening region and the second semiconductor opening region between the N-type amorphous silicon layer and the second intrinsic amorphous silicon layer.

[0029] In the back contact battery described above, the thickness of the second intrinsic amorphous silicon layer is 5-15 nm; the thickness of the first intrinsic amorphous silicon layer is 5-15 nm; the thickness of the N-type amorphous silicon layer is 5-25 nm; the thickness of the conductive film layer is 50-100 nm; the thickness of the front passivation layer is 4-20 nm; and the thickness of the antireflection layer is 40-200 nm.

[0030] The substrate of the back contact battery described above is an N-type silicon substrate.

[0031] The present invention also provides a method for preparing the above-mentioned back contact battery, which includes at least the steps of: laser annealing and crystallizing a P-type amorphous silicon film to form a P-type microcrystalline silicon layer, and depositing a second P-type amorphous silicon layer to form the P-type amorphous silicon layer.

[0032] The method for preparing the back contact battery described above includes the following steps:

[0033] A first intrinsic amorphous silicon layer and an N-type amorphous silicon layer are sequentially deposited on the back side of the substrate;

[0034] A second semiconductor opening region is formed by etching an N-type amorphous silicon layer and a first intrinsic amorphous silicon layer on the back side of the substrate.

[0035] The second semiconductor opening region and the front side of the substrate are texturized and cleaned, and then a front passivation layer and an anti-reflection layer are sequentially deposited on the front side of the substrate.

[0036] A second intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, and a third P-type amorphous silicon layer are sequentially deposited on the back side of the substrate.

[0037] The third P-type amorphous silicon layer located in the second semiconductor opening region is subjected to laser annealing and crystallization to obtain a P-type microcrystalline silicon layer, and then the second P-type amorphous silicon layer is deposited on the back side of the substrate.

[0038] The N-type amorphous silicon layer is exposed at the non-second semiconductor opening region on the back side of the substrate to form the first semiconductor opening region;

[0039] A conductive film layer is deposited on the back side of the substrate, and an insulating channel is formed on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region.

[0040] Metal electrodes are fabricated within the regions of the first semiconductor opening and the second semiconductor opening.

[0041] A third aspect of the present invention provides a battery assembly comprising the back contact battery described above or the back contact battery prepared by the above preparation method.

[0042] The back contact battery provided by the present invention employs a P-type doped layer in the second semiconductor layer comprising at least a first P-type amorphous silicon layer, a P-type microcrystalline silicon layer, and a second P-type amorphous silicon layer. The P-type microcrystalline silicon layer has a low resistivity, which can significantly reduce the bulk resistivity of the P-type doped crystalline silicon layer. The first P-type amorphous silicon layer can avoid damage to the second intrinsic amorphous silicon layer during the preparation of the P-type microcrystalline silicon layer, thereby reducing resistivity and improving the fill factor of the battery. The second P-type amorphous silicon layer is formed by heavy doping, which can improve the contact with the conductive film layer and further reduce the contact resistivity. On the other hand, it can also prevent sputtering damage to the P-type microcrystalline silicon layer during the deposition of the conductive film layer. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0044] Figure 1 This is a schematic diagram of the structure of a back contact battery provided in some embodiments of the present invention;

[0045] Figure 2 This is a schematic diagram of the structure after the deposition of the first intrinsic amorphous silicon layer on the substrate in Embodiment 1 of the present invention;

[0046] Figure 3 This is a schematic diagram of the structure after N-type amorphous silicon layer deposition in Embodiment 1 of the present invention;

[0047] Figure 4 This is a schematic diagram of the structure after the mask layer is deposited in Embodiment 1 of the present invention;

[0048] Figure 5 This is a schematic diagram of the structure after etching to form the second semiconductor opening region in Embodiment 1 of the present invention;

[0049] Figure 6 This is a schematic diagram of the structure after the front passivation layer and antireflection layer are deposited on the front side of the substrate in Embodiment 1 of the present invention;

[0050] Figure 7 This is a schematic diagram of the structure after the deposition of the second intrinsic amorphous silicon layer in Embodiment 1 of the present invention;

[0051] Figure 8 This is a schematic diagram of the structure after the deposition of the first P-type amorphous silicon layer in Embodiment 1 of the present invention;

[0052] Figure 9 This is a schematic diagram of the structure after the deposition of the third P-type amorphous silicon layer in Embodiment 1 of the present invention;

[0053] Figure 10 This is a schematic diagram of the structure after laser crystallization to form a P-type microcrystalline silicon layer in Embodiment 1 of the present invention;

[0054] Figure 11 This is a schematic diagram of the structure after the deposition of the second P-type amorphous silicon layer in Embodiment 1 of the present invention;

[0055] Figure 12 This is a schematic diagram of the structure after etching to form the first semiconductor opening region in Embodiment 1 of the present invention;

[0056] Figure 13 This is a schematic diagram of the structure after the conductive film layer is deposited in Embodiment 1 of the present invention;

[0057] Figure 14 This is a schematic diagram of the structure for fabricating the thick isolation groove in Embodiment 1 of the present invention.

[0058] In the attached figure, the substrate is 1, the first intrinsic amorphous silicon layer is 2, the N-type amorphous silicon layer is 3, the mask layer is 4, the front passivation layer is 5, the antireflection layer is 6, the second intrinsic amorphous silicon layer is 7, the first P-type amorphous silicon layer is 8, the third P-type amorphous silicon layer is 9, the P-type microcrystalline silicon layer is 10, the second P-type amorphous silicon layer is 11, the conductive film layer is 12, and the metal electrode is 13. Detailed Implementation

[0059] To enable those skilled in the art to better understand the solutions of this invention, the following provides a more detailed description of this application. The specific embodiments listed below are merely descriptions of the principles and features of this invention; the examples are only for explaining the invention and are not intended to limit its scope. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention.

[0060] To overcome the conductivity limitations of p-Si:H, research has found that introducing a microcrystalline silicon (μc-Si:H) layer to partially or completely replace the p-type amorphous silicon layer is beneficial for improving conductivity and reducing contact resistance. However, during fabrication, the microcrystalline silicon layer is easily damaged during fabrication, and the preparation of the conductive film layer on the microcrystalline silicon layer is easily damaged by sputtering. This leads to resistivity rebound, decreased carrier mobility (i.e., conductivity), or increased interfacial recombination loss, resulting in a decrease in product yield. Based on this, the present invention provides a back contact battery, such as... Figure 1 As shown, the back contact battery includes a substrate 1, which has a front side and a back side; a P-type doped layer located on the back side of the substrate 1, and the P-type doped layer includes at least a first P-type amorphous silicon layer 8, a P-type microcrystalline silicon layer 10, and a second P-type amorphous silicon layer 11 stacked along a first direction, wherein the P-type doping concentration in the second P-type amorphous silicon layer 11 is 1e 19 cm -3 -5e 20 cm -3 .

[0061] The first direction mentioned above is the direction from the front side of substrate 1 to the back side.

[0062] This invention designs a traditional P-type amorphous silicon layer as a structure consisting of at least a first P-type amorphous silicon layer, a P-type microcrystalline silicon layer, and a heavily doped second P-type amorphous silicon layer stacked together. The first P-type amorphous silicon layer avoids damage to the first intrinsic amorphous silicon layer during the fabrication of the P-type microcrystalline silicon layer, preventing resistivity rebound and a decrease in product yield. The second P-type amorphous silicon layer is used to contact the conductive film layer, which not only improves the contact between the microcrystalline silicon layer and the conductive film layer, further reducing contact resistance, increasing the fill factor, and improving battery efficiency, but also reduces or even avoids damage to the P-type microcrystalline silicon layer during the subsequent fabrication of the conductive film layer, thereby improving product yield.

[0063] In some embodiments, the doping concentration of the first p-type amorphous silicon layer 8 is 1e. 18 cm -3 -1e 19 cm -3 .

[0064] In some embodiments, the doping elements in the first P-type amorphous silicon layer 8 also include at least one of C and N elements. Doping with C and N elements helps to increase the refractive index and density, thereby improving the resistance to laser damage.

[0065] In some embodiments, the first P-type amorphous silicon layer 8 has a refractive index of 3.6-4.5. The first P-type amorphous silicon layer 8 has a high density, which can effectively prevent hydrogen escape caused by high laser temperature and reduce laser thermal damage.

[0066] In some embodiments, the crystallinity of the P-type microcrystalline silicon layer 10 is 5-80%. For example, the crystallinity of the P-type microcrystalline silicon layer 10 can be 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or any value between any two of the above ranges. When the crystallinity of the P-type microcrystalline silicon layer 10 is within this range, it has higher electrical conductivity.

[0067] In some embodiments, the conductivity of the P-type microcrystalline silicon layer 10 is 0.1-5 S / cm. Exemplarily, it can be 0.1 S / cm, 0.5 S / cm, 1 S / cm, 2 S / cm, 3 S / cm, 4 S / cm, 5 S / cm, or any value between any two of the above ranges. Controlling the conductivity of the P-type microcrystalline silicon layer 10 within this range can prevent leakage current caused by excessively high conductivity.

[0068] In some embodiments, the back contact battery further includes:

[0069] The first semiconductor layer is disposed on the back side of the substrate 1, and the first semiconductor layer is provided with second semiconductor opening regions evenly spaced on the first semiconductor layer. The first semiconductor layer includes a first intrinsic amorphous silicon layer 2 and an N-type amorphous silicon layer 3 in sequence along the first direction.

[0070] The second semiconductor layer is continuously disposed on the outer surface of the first semiconductor layer and within the second semiconductor opening region. The second semiconductor layer has first semiconductor opening regions arranged at intervals from the second semiconductor opening regions. The second semiconductor layer includes a second intrinsic amorphous silicon layer 7 and the aforementioned P-type doped layer.

[0071] While the P-type microcrystalline silicon layer can improve conductivity as a semiconductor layer, it is prone to leakage problems. Therefore, in some embodiments, a third P-type amorphous silicon layer 9 is continuously disposed in the middle of the second semiconductor opening region W1 and close to the side (usually both sides) of the first semiconductor layer. The third P-type amorphous silicon layer 9 is disposed in the non-P-type microcrystalline silicon layer 10 region on the surface of the first P-type amorphous silicon layer. The width of the P-type microcrystalline silicon layer 10 is 30-80% of the width of the second semiconductor opening region.

[0072] In detail, the third P-type amorphous silicon layer 9 and the P-type microcrystalline silicon layer 10 together constitute the interlayer in the P-type amorphous silicon layer. The longitudinal folding and side boundary area between the P-type microcrystalline silicon layer 10 and the N-type amorphous silicon layer in the first semiconductor layer are prone to leakage problems. The third P-type amorphous silicon layer 9 can effectively suppress this leakage problem.

[0073] It is understandable that within the second semiconductor opening region W1, when the proportion of the P-type microcrystalline silicon layer 10 is relatively large and the proportion of the third P-type amorphous silicon layer 9 is relatively small, the resistivity can be improved significantly, but the leakage problem is more prominent. Conversely, when the proportion of the P-type microcrystalline silicon layer 10 is relatively small and the proportion of the third P-type amorphous silicon layer 9 is relatively large, it is beneficial to improve the leakage problem, but the resistivity decreases more significantly. Studies have shown that when the width of the P-type microcrystalline silicon layer 10 is 30-80% of the width of the second semiconductor opening region W1, the problems of reducing resistance and avoiding leakage can be well balanced.

[0074] In some embodiments, the doping concentration of P-type dopant in the second P-type amorphous silicon layer 11 is greater than the doping concentration of P-type dopant in the third P-type amorphous silicon layer 9. The third P-type amorphous silicon layer 9 uses a smaller doping concentration, which can prevent P-type doped atoms from diffusing into the second intrinsic amorphous silicon layer 7 and affecting the passivation effect of the second intrinsic amorphous silicon layer 7.

[0075] In some implementations, the width of the second semiconductor opening region W1 is 400-1000 μm.

[0076] In some embodiments, the doping concentration of the third p-type amorphous silicon layer 9 can be 5e. 18 cm -3 -5e 19 cm -3 .

[0077] In some embodiments, when the thickness of the first P-type amorphous silicon layer 8 is 2-8 nm, the thickness of the P-type microcrystalline silicon layer 10 is 10-25 nm, and the thickness of the second P-type amorphous silicon layer 11 is 1-3 nm, the resistance can be significantly reduced, the battery efficiency can be improved, and the product yield can be increased simultaneously.

[0078] Specifically, the thickness of the first P-type amorphous silicon layer 8 can be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, or any value between any two of the above ranges. The thickness of the P-type microcrystalline silicon layer 10 can be 10nm, 12nm, 15nm, 18nm, 20nm, 23nm, 25nm, or any value between any two of the above ranges. The thickness of the second P-type amorphous silicon layer 11 can be 1nm, 2nm, 3nm, or any value between any two of the above ranges.

[0079] The thickness of the second intrinsic amorphous silicon layer 7 is not specifically limited and can be set according to conventional thicknesses in the art, such as 5-15nm. More specifically, it can be 5nm, 10nm, 12nm, 15nm, or any value between any two of the above ranges.

[0080] It is also understandable that back-contact batteries include:

[0081] A conductive film layer 12 is disposed on the outer surface of the second semiconductor layer and within the first semiconductor opening region. The conductive film layer forms an insulating channel by opening between the first semiconductor opening region and the second semiconductor opening region.

[0082] Metal electrode 13 is located on the outer surface of conductive film layer 12 and is disposed within the first semiconductor opening region and the second semiconductor opening region.

[0083] Front passivation layer 5, which is located on the front side of substrate 1;

[0084] Anti-reflection layer 6 is located on the side of the front passivation layer 5 away from the substrate 1.

[0085] In the above, the front passivation layer and the antireflection layer are not specifically limited and can be prepared using conventional materials in the art. For example, the front passivation layer can be at least one of silicon oxide, amorphous silicon, and aluminum oxide, and the antireflection layer 6 can be at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0086] The conductive film layer is not specifically limited and can be at least one of indium oxide, tin oxide, and zinc oxide-based films.

[0087] In some embodiments, the back contact battery further includes a mask layer 4, which is located in the region between the N-type amorphous silicon layer 3 and the second intrinsic amorphous silicon layer 7, which is the region between the region between the first semiconductor opening region and the second semiconductor opening region. That is, the mask layer 4 is disposed on the surface of the N-type amorphous silicon layer 3 except for the first semiconductor opening region and the second semiconductor opening region, and the surface of the mask layer 4 is the second intrinsic amorphous silicon layer 7.

[0088] In some embodiments of the present invention, the thickness of the first intrinsic amorphous silicon layer 2 is 5-15 nm, the thickness of the N-type amorphous silicon layer 3 is 5-25 nm, the thickness of the conductive film layer 12 is 50-100 nm, the thickness of the front passivation layer is 4-20 nm, and the thickness of the antireflection layer 6 is 40-200 nm.

[0089] The substrate used in this invention is not specifically limited and can be any material conventional in the art, such as a common N-type silicon substrate.

[0090] The present invention also provides a method for preparing the above-mentioned back contact battery, which includes at least the steps of: laser annealing and crystallizing a P-type amorphous silicon film to form a P-type microcrystalline silicon layer 10, and depositing a second P-type amorphous silicon layer 11 to form a P-type amorphous silicon layer.

[0091] A P-type microcrystalline silicon layer 10 is formed by laser annealing crystallization, and the area and size of the P-type microcrystalline silicon layer are easier to control.

[0092] In some embodiments, the method for preparing a back contact battery includes the following steps:

[0093] A first intrinsic amorphous silicon layer 2 and an N-type amorphous silicon layer 3 are sequentially deposited on the back side of the substrate;

[0094] A second semiconductor opening region W1 is formed by etching an N-type amorphous silicon layer 3 and a first intrinsic amorphous silicon layer 2 on the back side of the substrate.

[0095] The second semiconductor opening region W1 and the front side of the substrate are texturized and cleaned, and then the front passivation layer 5 and the anti-reflection layer 6 are sequentially deposited on the front side of the substrate.

[0096] A second intrinsic amorphous silicon layer 7, a first P-type amorphous silicon layer 8, and a third P-type amorphous silicon layer 9 are sequentially deposited on the back side.

[0097] The third P-type amorphous silicon layer 9 located in the second opening region W1 is subjected to laser annealing and crystallization to obtain a P-type microcrystalline silicon layer 10, and then the second P-type amorphous silicon layer 11 is deposited on the back side of the substrate.

[0098] Etching is performed on the back side of the substrate at the non-first semiconductor opening region until the N-type amorphous silicon layer 3 is exposed, forming the first semiconductor opening region W2;

[0099] A conductive film layer 12 is deposited on the back side of the substrate, and an insulating channel is formed on the conductive film layer 12 between the first semiconductor opening region and the second semiconductor opening region.

[0100] Metal electrodes are fabricated within the first semiconductor opening region and the second semiconductor opening region.

[0101] It is also understandable that in some implementations, the first P-type amorphous silicon layer 8 and the third P-type amorphous silicon layer 9 can have the same doping concentration, and the two can be formed directly by a single deposition.

[0102] The present invention also provides a battery assembly, including the back contact battery described above or the back contact battery prepared by the above preparation method.

[0103] The technical solution of this application will be further explained below with reference to specific embodiments. Experimental methods in the following embodiments that do not specify specific conditions are generally performed under conventional conditions or as recommended by the manufacturer. Unless otherwise specified, all reagents used are commercially available or obtained through public channels.

[0104] Example 1

[0105] This embodiment provides a method for preparing a back contact battery, including the following steps:

[0106] S1 provides an N-type silicon substrate, which, after cleaning and polishing, forms a double-sided smooth substrate 1. On the back side of substrate 1, a 10nm first intrinsic amorphous silicon layer 2, a 15nm N-type amorphous silicon layer 3, and a 200nm SiN layer are sequentially deposited. x Mask layer 4, specifically as follows Figure 2 , Figure 3 , Figure 4 As shown.

[0107] S2, a first etching opening is performed on the back side, removing part of the mask layer 4 to form a second semiconductor opening region. The width of the opening region is 600μm. See details below. Figure 5 ;

[0108] S3, wet removal of the N-type amorphous silicon layer 3 and the first intrinsic amorphous silicon layer 2 in the second semiconductor opening region, followed by texturing of the front side and the second semiconductor opening region;

[0109] S4, a 10nm thick intrinsic amorphous silicon and a 100nm thick silicon nitride are sequentially deposited on the front side of substrate 1 to form a front passivation layer 5 and an antireflection layer 6. See details below. Figure 6 ;

[0110] S5, on the back side of substrate 1, a second intrinsic amorphous silicon layer 7 of 8 nm, a first P-type amorphous silicon layer 8 of 4 nm, and a third P-type amorphous silicon layer 9 of 20 nm are sequentially deposited. See details. Figure 7 , Figure 8 , Figure 9 ;

[0111] Among them, the first P-type amorphous silicon layer 8 is a C-doped P-type amorphous silicon layer with a refractive index of 3.9 and a boron doping concentration of 5e. 18 cm 3 The third p-type amorphous silicon layer 9 is a boron-doped p-type amorphous silicon layer with a doping concentration of 2e⁻¹. 19 cm 3 ;

[0112] S6. A 600nm laser is used to laser anneal and crystallize a portion of the third P-type amorphous silicon layer 9 located within the second semiconductor opening region to form a P-type microcrystalline silicon layer 10. The width of the crystallized region is 300μm, the crystallization depth is 20nm, the conductivity of the P-type microcrystalline silicon layer 10 is 2S / cm, and the crystallization rate is 50%. See details... Figure 10 ;

[0113] S7, a second P-type doped amorphous silicon layer 11 with a thickness of 1 nm is formed on the back side, with a doping concentration of 1e. 20 cm 3 To form a second semiconductor layer, see details. Figure 11 ;

[0114] S8, a second etching opening is performed in the non-second semiconductor region on the back side, forming a first semiconductor opening region W2 that is spaced apart from the second semiconductor opening region. The etching depth is such that the N-type amorphous silicon layer is exposed. See details below. Figure 12 ;

[0115] S9, a conductive film layer 12 is deposited on the back side. This conductive film layer 12 is an indium tin oxide conductive material with a thickness of 80 nm. See details below. Figure 13 ;

[0116] S9 involves laser grooving a portion of the conductive film layer between the first and second semiconductor opening regions on the back side to form an insulating channel, thus insulating the N-region and P-region. See details below. Figure 14 ;

[0117] S10, using screen printing technology, metallic silver electrodes are fabricated in the first semiconductor opening region and the second semiconductor opening region, thus obtaining... Figure 1 The back contact battery is shown.

[0118] Example 2

[0119] The difference between this embodiment and Embodiment 1 is that the first P-type amorphous silicon layer 8 is not doped with C element.

[0120] Example 3

[0121] The difference between this embodiment and Embodiment 1 is that the crystallinity of the P-type microcrystalline silicon layer 10 is 80%, and the electrical conductivity is 5 S / cm.

[0122] Example 4

[0123] The difference between this embodiment and Embodiment 1 is that the width of the P-type microcrystalline silicon layer 10 is 480 μm, accounting for 80% of the second semiconductor opening region W1.

[0124] Example 5

[0125] The difference between this embodiment and Embodiment 1 is that the thickness of the second P-type amorphous silicon layer 11 is 2nm.

[0126] Comparative Example 1

[0127] The difference between this comparative example and Example 1 is that there is no first P-type amorphous silicon layer 8.

[0128] Comparative Example 2

[0129] The difference between this comparative example and Example 1 is that there is no second P-type amorphous silicon layer 11.

[0130] Comparative Example 3

[0131] The conventional HBC back-contact solar cell differs from Example 1 in that the P-type doped layer is a 25nm P-type amorphous silicon layer with a doping concentration of 2e⁻¹. 19 cm 3 .

[0132] Performance testing:

[0133] (1) The photoelectric conversion efficiency of the prepared back contact solar cell was tested. The open circuit voltage (Voc), short circuit current (Jsc), fill factor (FF) and cell efficiency (Eta) of the cell were obtained by scanning the IV curve of the cell. The open circuit voltage, short circuit current, fill factor and cell efficiency in Comparative Example 3 were used as Standard 1. The relative results of the other examples and comparative examples are shown in Table 1 below.

[0134] Table 1

[0135]

[0136] As can be seen from the above results, the present invention adopts a stacked P-type amorphous silicon layer structure, which can effectively improve the fill factor and conversion efficiency of the battery.

[0137] (2) Product yield

[0138] 300 back contact batteries were produced according to the methods of the above embodiments and comparative examples. A battery efficiency of 26% was considered a qualified product. The product yield was calculated, and the results are shown in Table 2 below.

[0139]

[0140] As can be seen from the above results, the present invention adopts a stacked P-type doped layer structure, which can effectively improve the yield of the battery.

[0141] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to what has been described above. Various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A back-contact battery, characterized in that, include: Substrate, the substrate including a front side and a back side; A p-type doped layer, located on the back side of the substrate, comprises at least a first p-type amorphous silicon layer, a p-type microcrystalline silicon layer, and a second p-type amorphous silicon layer stacked along a first direction, wherein the p-type doping concentration in the second p-type amorphous silicon layer is 1e. 19 cm -3 -5e 20 cm -3 ; The first direction is the direction from the front side of the substrate to the back side.

2. The back contact battery according to claim 1, characterized in that, The doping concentration of the P-type dopant in the first P-type amorphous silicon layer is 1e 18 cm -3 -1e 19 cm -3 ; and / or The doping elements in the first P-type amorphous silicon layer also include at least one of C and N.

3. The back contact battery according to claim 1 or 2, characterized in that, The refractive index of the first P-type amorphous silicon layer is 3.6-4.5; and / or The crystallinity of the P-type microcrystalline silicon layer is 5-80%; and / or The electrical conductivity of the P-type microcrystalline silicon layer is 0.1-5 S / cm.

4. The back contact battery according to any one of claims 1-3, characterized in that, Also includes A first semiconductor layer is disposed on the back side of the substrate, and a second semiconductor opening region is uniformly spaced on the first semiconductor layer. The first semiconductor layer includes a first intrinsic amorphous silicon layer and an N-type amorphous silicon layer in sequence along a first direction. The second semiconductor layer is continuously disposed on the outer surface of the first semiconductor layer and within the second semiconductor opening region. The second semiconductor layer has a first semiconductor opening region arranged at intervals from the second semiconductor opening region. The second semiconductor layer includes a second intrinsic amorphous silicon layer and a P-type doped layer.

5. The back contact battery according to claim 4, characterized in that, The P-type microcrystalline silicon layer is located in the middle of the second semiconductor opening region and is continuously disposed on the side of the first semiconductor layer. The third P-type amorphous silicon layer is disposed in the non-P-type microcrystalline silicon layer region on the surface of the first P-type amorphous silicon layer. The width of the P-type microcrystalline silicon layer is 30-80% of the width of the second semiconductor opening region.

6. The back contact battery according to claim 5, characterized in that, The doping concentration of P-type dopant in the second P-type amorphous silicon layer is greater than the doping concentration of P-type dopant in the third P-type amorphous silicon layer; and / or The width of the second semiconductor opening region is 400-1000 μm.

7. The back contact battery according to claim 5 or 6, characterized in that, The doping concentration of the P-type dopant in the third P-type amorphous silicon layer is 5e. 18 cm -3 -5e 19 cm -3 .

8. The back contact battery according to any one of claims 1-7, characterized in that, The thickness of the first P-type amorphous silicon layer is 2-8 nm, the thickness of the P-type microcrystalline silicon layer is 10-25 nm, and the thickness of the second P-type amorphous silicon layer is 1-3 nm.

9. The back contact battery according to any one of claims 4-8, characterized in that, The back contact battery also includes: A conductive film layer is disposed on the outer surface of the second semiconductor layer and within the first semiconductor opening region, wherein the conductive film layer forms an insulating channel by opening between the first semiconductor opening region and the second semiconductor opening region. A metal electrode is located on the outer surface of the conductive film layer and disposed within the first semiconductor opening region and the second semiconductor opening region; A front passivation layer, wherein the front passivation layer is located on the front side of the substrate; An antireflection layer is located on the surface of the front passivation layer away from the substrate.

10. The back contact battery according to claim 9, characterized in that, The back contact battery also includes a mask layer located in the non-first semiconductor opening region and the second semiconductor opening region between the N-type amorphous silicon layer and the second intrinsic amorphous silicon layer.

11. The back contact battery according to claim 9 or 10, characterized in that, The thickness of the second intrinsic amorphous silicon layer is 5-15 nm; The thickness of the first intrinsic amorphous silicon layer is 5-15 nm; The thickness of the N-type amorphous silicon layer is 5-25 nm; The thickness of the conductive film is 50-100 nm; The thickness of the front passivation layer is 4-20 nm; The thickness of the antireflective layer is 40-200 nm.

12. The back contact battery according to any one of claims 1-11, characterized in that, The substrate is an N-type silicon-based substrate.

13. A method for preparing a back contact battery according to any one of claims 1-12, characterized in that, At least including: The steps are as follows: laser annealing and crystallization of a P-type amorphous silicon film to form a P-type microcrystalline silicon layer, and deposition of a third P-type amorphous silicon layer to form the P-type amorphous silicon layer.

14. The method for preparing a back contact battery according to claim 13, characterized in that, Includes the following steps: A first intrinsic amorphous silicon layer and an N-type amorphous silicon layer are sequentially deposited on the back side of the substrate; A second semiconductor opening region is formed by etching an N-type amorphous silicon layer and a first intrinsic amorphous silicon layer on the back side of the substrate. The second semiconductor opening region and the front side of the substrate are texturized and cleaned, and then a front passivation layer and an anti-reflection layer are sequentially deposited on the front side of the substrate. A second intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, and a third P-type amorphous silicon layer are sequentially deposited on the back side of the substrate. The third P-type amorphous silicon layer located in the second semiconductor opening region is subjected to laser annealing and crystallization to obtain a P-type microcrystalline silicon layer, and then the second P-type amorphous silicon layer is deposited on the back side of the substrate. The N-type amorphous silicon layer is exposed at the non-second semiconductor opening region on the back side of the substrate to form the first semiconductor opening region; A conductive film layer is deposited on the back side of the substrate, and an insulating channel is formed on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region. Metal electrodes are fabricated within the regions of the first semiconductor opening and the second semiconductor opening.

15. A battery assembly, characterized in that, Includes the back contact battery according to any one of claims 1-12 or the back contact battery prepared by the preparation method according to claim 13 or 14.

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