Solar cell, method of manufacturing the same, and photovoltaic module

Abstract

The application provides a solar cell, a preparation method thereof and a photovoltaic module, wherein the solar cell comprises a silicon substrate, a first electrode located on one side of the silicon substrate, a second electrode located on a side of the silicon substrate away from the first electrode, an interface transition layer located on a side of the first electrode away from the silicon substrate and on a side of the second electrode away from the silicon substrate, the interface transition layer comprising reduced graphene oxide and forming a covalent bond at a contact with the first electrode and the second electrode, and a graphene layer located on a side of the interface transition layer away from the silicon substrate. The application solves the problem of poor cell performance of the solar cell in the prior art.

Description

Technical Field

[0001] This application relates to the field of photovoltaics, and more specifically, to a solar cell, a method for its fabrication, and a photovoltaic module. Background Technology

[0002] Existing technologies aim to improve the performance of solar cells by utilizing the high electron mobility of graphene and attempting to combine graphene with metal meshes. However, the bonding between graphene and metal interfaces is relatively loose, resulting in high interface resistance. This fails to leverage the conductivity enhancement and anti-oxidation functions of graphene. Current technologies cannot achieve a synergistic improvement in high light transmittance, low resistance, and strong adhesion of metal interconnect structures.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a solar cell, its preparation method, and a photovoltaic module to solve the problem of poor cell performance in existing solar cells.

[0005] To achieve the above objectives, according to one aspect of this application, a solar cell is provided, comprising: a silicon substrate; a first electrode located on one side of the silicon substrate; a second electrode located on the side of the silicon substrate opposite to the first electrode; an interface transition layer located on the side of the first electrode opposite to the silicon substrate and on the side of the second electrode opposite to the silicon substrate, the interface transition layer comprising reduced graphene oxide and forming covalent bonds with the first electrode and the second electrode at the contact point; and a graphene layer located on the side of the interface transition layer opposite to the silicon substrate.

[0006] Optionally, the silicon substrate has a first surface and a second surface opposite to each other, and the silicon substrate has a first doping type. The solar cell further includes: a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer, the first intrinsic amorphous silicon layer being located on the first surface and the second intrinsic amorphous silicon layer being located on the second surface; a first amorphous silicon layer and a second amorphous silicon layer, the first amorphous silicon layer being located on the side of the first intrinsic amorphous silicon layer away from the silicon substrate and electrically connected to the first electrode, the second amorphous silicon layer being located on the side of the second intrinsic amorphous silicon layer away from the silicon substrate, the first amorphous silicon layer having a first doping type and the second amorphous silicon layer having a second doping type, the first doping type being different from the second doping type; a first transparent conductive layer and a second transparent conductive layer, the first transparent conductive layer being located on the side of the first amorphous silicon layer away from the silicon substrate and electrically connected to the first electrode, the second transparent conductive layer being located on the side of the second amorphous silicon layer away from the silicon substrate and electrically connected to the second electrode.

[0007] Optionally, the silicon substrate has a first doping type, and the solar cell further includes: an emitter located in the silicon substrate, wherein the surface of the emitter facing away from the second electrode is in the same plane as the surface of the silicon substrate facing away from the second electrode, the emitter is electrically connected to the first electrode, and the emitter has a second doping type; a tunneling oxide layer located on the side of the silicon substrate facing away from the emitter; a doped conductive layer located on the side of the tunneling oxide layer facing away from the silicon substrate and electrically connected to the second electrode, the doped conductive layer having a first doping type, the first doping type being different from the second doping type; a first passivation layer and a second passivation layer, the first passivation layer being located on the side of the emitter facing away from the silicon substrate, and the second passivation layer being located on the side of the doped conductive layer facing away from the silicon substrate.

[0008] According to another aspect of this application, a method for fabricating a solar cell is provided. The method includes: providing a silicon substrate; forming a first electrode on one side of the silicon substrate; forming a second electrode on the side of the silicon substrate opposite to the first electrode; forming an interface transition layer on the side of the first electrode opposite to the silicon substrate and on the side of the second electrode opposite to the silicon substrate, the interface transition layer comprising reduced graphene oxide and having covalent bonds with the first electrode and the second electrode at the contact point; and forming a graphene layer on the side of the interface transition layer opposite to the silicon substrate.

[0009] Optionally, the silicon substrate has a first surface and a second surface opposite to each other, and the preparation method further includes: sequentially forming a first intrinsic amorphous silicon layer and a second amorphous silicon layer on the first surface; sequentially forming a second intrinsic amorphous silicon layer and a second amorphous silicon layer on the second surface, and performing an annealing treatment at a temperature of 150~200℃; forming a first transparent conductive layer on the side of the first amorphous silicon layer away from the silicon substrate, and forming a second transparent conductive layer on the side of the second amorphous silicon layer away from the silicon substrate, wherein the first transparent conductive layer is electrically connected to the first electrode, and the second transparent conductive layer is electrically connected to the second electrode.

[0010] Optionally, the silicon substrate has a first surface and a second surface opposite to each other, and the preparation method further includes: performing ion implantation on the first surface to form an emitter, and sequentially forming an antireflection layer and a first passivation layer on the side of the emitter away from the silicon substrate, wherein the emitter is electrically connected to the first electrode; and sequentially forming a tunneling oxide layer, a doped conductive layer and a second passivation layer on the second surface, wherein the doped conductive layer is electrically connected to the second electrode.

[0011] Optionally, the steps of forming the first electrode and the second electrode include: providing a first template and etching the first template using a laser etching process to give the first template a first pattern; and using an electrochemical deposition process to form the first electrode and the second electrode on opposite sides of a silicon substrate using the first pattern of the first template and an electroplating solution, wherein the electroplating solution includes at least a salt solution, a complexing agent, and additives, wherein the salt solution includes copper sulfate and silver nitrate, the complexing agent includes disodium ethylenediaminetetraacetate, and the additives include a brightener and a leveling agent.

[0012] Optionally, the step of forming the interface transition layer includes: in the step of forming the first electrode and the second electrode, adding a graphene precursor solution to the electroplating solution, using an electrochemical deposition process to attach graphene oxide in the graphene precursor solution to the surface of the first electrode and the second electrode to form a graphene oxide layer; and using a thermal reduction process to reduce the graphene oxide layer to form the interface transition layer.

[0013] Optionally, the step of forming the first transparent conductive layer and the second transparent conductive layer includes: using a magnetron sputtering process to sputter a target material onto the surface of the first amorphous silicon layer and the second amorphous silicon layer, wherein the target material includes indium tin oxide or indium zinc oxide.

[0014] According to another aspect of this application, a photovoltaic module is provided, comprising a plurality of solar cells prepared by the above-described method for preparing solar cells.

[0015] According to the technical solution of this application, a solar cell includes: a silicon substrate, a first electrode, a second electrode, an interface transition layer, and a graphene layer. The interface transition layer is located on the side of the first electrode facing away from the silicon substrate, and on the side of the second electrode facing away from the silicon substrate. The interface transition layer includes reduced graphene oxide and forms covalent bonds with the first and second electrodes at their contact points. The graphene layer is located on the side of the interface transition layer facing away from the silicon substrate. The chemical bonding between the reduced graphene oxide and the metal electrode can improve the interfacial bonding strength between the interface transition layer and the electrode, effectively eliminating the problems of loose bonding and increased interfacial resistance between the metal mesh and the graphene-containing structure. Reduced graphene oxide has good conductivity and high light transmittance, and together with the upper graphene layer, it can form a low-resistance, high-transmittance conductive network, enabling efficient carrier transport between the electrodes, the interface transition layer, and the graphene layer, reducing series resistance, improving photoelectric conversion efficiency, and thus solving the problem of poor cell performance in existing solar cells. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A cross-sectional structural schematic diagram of a solar cell according to an embodiment of this application is shown;

[0018] Figure 2 A cross-sectional structural schematic diagram of another solar cell according to an embodiment of this application is shown;

[0019] Figure 3 A schematic flowchart of a method for fabricating a solar cell according to an embodiment of this application is shown.

[0020] The above figures include the following reference numerals:

[0021] 10. Silicon substrate; 20. First electrode; 30. Second electrode; 40. Interface transition layer; 50. Graphene layer; 11. First intrinsic amorphous silicon layer; 12. Second intrinsic amorphous silicon layer; 13. First amorphous silicon layer; 14. Second amorphous silicon layer; 15. First transparent conductive layer; 16. Second transparent conductive layer; 21. Emitter; 22. Tunneling oxide layer; 23. Doped conductive layer; 24. First passivation layer; 25. Second passivation layer; 26. First antireflection layer. Detailed Implementation

[0022] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0026] As described in the background section, existing technologies aim to improve the performance of solar cells by utilizing the high electron mobility of graphene. Attempts have been made to combine graphene with metal meshes, but the bonding between graphene and metal interfaces is relatively loose, resulting in high interface resistance. To address the problem of poor cell performance in solar cells, embodiments of this application provide a solar cell, its fabrication method, and a photovoltaic module.

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0028] One embodiment of this application proposes a solar cell, such as Figure 1 and Figure 2 The device includes: a silicon substrate 10; a first electrode 20 located on one side of the silicon substrate 10; a second electrode 30 located on the side of the silicon substrate 10 opposite to the first electrode 20; an interface transition layer 40 located on the side of the first electrode 20 opposite to the silicon substrate 10 and on the side of the second electrode 30 opposite to the silicon substrate 10, the interface transition layer 40 including reduced graphene oxide and forming covalent bonds with the first electrode 20 and the second electrode 30 at the contact point; and a graphene layer 50 located on the side of the interface transition layer 40 opposite to the silicon substrate 10.

[0029] The interface transition layer of the solar cell of this application includes reduced graphene oxide, which forms covalent bonds with the first and second electrodes at the contact points. The graphene layer is located on the side of the interface transition layer facing away from the silicon substrate. The chemical bonding between the reduced graphene oxide and the metal electrode can improve the interfacial bonding strength between the interface transition layer and the electrode, effectively eliminating the problems of loose bonding and increased interfacial resistance between the metal mesh and the graphene-containing structure. The reduced graphene oxide has good conductivity and high light transmittance, and together with the upper graphene layer, it can form a low-resistance, high-transmittance conductive network, enabling efficient carrier transport between the electrodes, the interface transition layer, and the graphene layer, reducing series resistance, improving photoelectric conversion efficiency, and thus solving the problem of poor cell performance in existing solar cells.

[0030] The aforementioned reduced graphene oxide (rGO) is a two-dimensional carbon material prepared by chemically or thermally reducing graphene oxide (GO), which retains the sp[…] of graphene. 2The carbon skeleton structure, while retaining a small number of oxygen-containing functional groups (such as hydroxyl and carboxyl groups), not only makes it easy to disperse in aqueous solution, but also allows it to form stable coordination or covalent bonds with metal atoms (such as Cu and Ag), thereby achieving chemical interface bonding with the metal grid lines; rGO has high electrical conductivity, light transmittance and thermal stability. In this application, it serves as an interface transition layer between the metal electrode and the graphene layer, which can effectively eliminate interface resistance, inhibit metal electrode oxidation and improve adhesion. The in-situ composite of the graphene layer and the metal electrode achieves a synergistic improvement in light transmittance and conductivity.

[0031] In the above embodiments, the silicon substrate can be an N-type monocrystalline silicon substrate. Compared with P-type silicon, N-type monocrystalline silicon has characteristics such as high carrier mobility and long minority carrier lifetime, which can provide a better electrical performance basis for heterojunction solar cells and help improve the conversion efficiency of the cells. The silicon substrate can serve as the main light-absorbing layer and carrier generation region. Using an N-type silicon wafer with high minority carrier lifetime provides low light-induced degradation and excellent impurity tolerance.

[0032] In the above embodiments, the first and second electrodes are typically made of metallic materials (such as silver, copper, etc.) and are used to collect and extract the current generated by the battery. Their shape and size need to be precisely controlled according to the battery design requirements to ensure good conductivity and reasonable current collection capability. The fabrication process of the first and second electrodes can employ methods such as screen printing, electroplating, or vapor deposition to deposit metallic materials (such as silver, copper, etc.) in a tank to prepare grid lines. Taking screen printing as an example, a paste containing metal particles is applied to the tank through a screen printing stencil. After processes such as drying and sintering, the metal particles melt and form continuous conductive grid lines. After the above series of steps, the manufacturing of the heterojunction battery is completed. The heterojunction battery obtained at this time has a complete structure, including a substrate, a transparent conductive oxide layer, an anti-reflective film, and grid lines, which can achieve efficient conversion of light energy into electrical energy.

[0033] The above-described solution can be applied to TOPCon and HJT batteries. In some optional embodiments, the HJT battery is a battery that achieves photoelectric conversion based on a heterojunction structure formed by different materials. It combines the high carrier mobility of crystalline silicon with the excellent passivation and light absorption characteristics of amorphous silicon, and has advantages such as high conversion efficiency and low temperature coefficient. Figure 1 As shown, the silicon substrate 10 has opposing first and second surfaces, the silicon substrate 10 has a first doping type, and the solar cell further includes:

[0034] A first intrinsic amorphous silicon layer 11 and a second intrinsic amorphous silicon layer 12, wherein the first intrinsic amorphous silicon layer 11 is located on a first surface and the second intrinsic amorphous silicon layer 12 is located on a second surface; a first amorphous silicon layer 13 and a second amorphous silicon layer 14, wherein the first amorphous silicon layer 13 is located on the side of the first intrinsic amorphous silicon layer 11 away from the silicon substrate 10 and is electrically connected to the first electrode 20, and the second amorphous silicon layer 14 is located on the side of the second intrinsic amorphous silicon layer 12 away from the silicon substrate 10; the first amorphous silicon layer 13 has a first doping type and the second amorphous silicon layer 14 has a second doping type, the first doping type and the second doping type being different; a first transparent conductive layer 15 and a second transparent conductive layer 16, wherein the first transparent conductive layer 15 is located on the side of the first amorphous silicon layer 13 away from the silicon substrate 10 and is electrically connected to the first electrode 20, and the second transparent conductive layer 16 is located on the side of the second amorphous silicon layer 14 away from the silicon substrate 10 and is electrically connected to the second electrode 30. The thickness of the first transparent conductive layer 15 and / or the second transparent conductive layer 16 can be 10-20 nm.

[0035] In the above optional embodiments, the first intrinsic amorphous silicon layer has a good surface passivation effect, which can effectively reduce the interface recombination rate; the first amorphous silicon layer can be an N-type amorphous silicon layer, which can be formed by phosphorus doping to form an N-type conductive layer and provide an electron transport channel; the second amorphous silicon layer can be a P-type amorphous silicon layer, which can be formed by boron doping to form a P-type conductive layer and provide a hole transport channel; the materials of the first transparent conductive layer and the second transparent conductive layer can be indium tin oxide (ITO) or indium zinc oxide (IZO), which have high light transmittance and low sheet resistance, and can be used as a lateral conductive layer to collect charge carriers and connect metal gate lines.

[0036] In the above-mentioned optional embodiments, an antireflective film can be uniformly deposited on the surfaces of the first and second transparent conductive oxide layers using methods such as physical vapor deposition, chemical vapor deposition, or sol-gel method. Taking chemical vapor deposition as an example, a gas containing an antireflective film material (such as silicon nitride) precursor is introduced into the reaction chamber. Under high temperature or plasma conditions, the precursor undergoes a chemical reaction, generating an antireflective film on the surface of the transparent conductive oxide layer. The antireflective film layer in this application can be replaced by a graphene layer, which can be selected according to the actual situation.

[0037] In the above optional embodiments, the transparent conductive oxide layer includes a grid line contact region and a non-grid line contact region. The thickness of the transparent conductive oxide layer in the non-grid line contact region is less than the thickness of the transparent conductive oxide layer in the grid line contact region. The grid line contact region includes the desired location of the grid line, which is the position where the grid line is expected to be placed, determined according to battery design requirements and electrical performance optimization. It comprehensively considers factors such as the incident angle of light and the uniformity of current distribution on the battery surface, with the aim of enabling the subsequently fabricated grid line to efficiently collect the current generated by various parts of the battery. The grid line contact region is the area at a distance less than a preset range from the grid line, including the portion of the transparent conductive oxide layer that directly contacts the subsequently fabricated grid line, i.e., it includes the desired location of the grid line. This region needs to have good conductivity to ensure smooth current transmission between the grid line and the battery interior, reducing transmission losses. The non-grid line contact region is the portion of the transparent conductive oxide layer other than the grid line contact region. It mainly assists in light transmission, reduces reflection, and participates in the regulation of battery electrical performance to a certain extent, but does not need to conduct a large amount of current through direct contact with the grid line like the grid line contact region.

[0038] In the above optional embodiments, a protective layer may also be provided on the graphene layer. The thickness of the protective layer may be 10-15 nm, and the material may be silicon nitride, to prevent graphene oxidation and mechanical damage.

[0039] In the above optional embodiments, the materials of the first transparent conductive layer and the second transparent conductive layer can be ITO (indium tin oxide) or IZO (indium zinc oxide), and the thickness can be 10-20nm to improve the interface compatibility between the composite grid and the silicon wafer; the thickness within the above range can improve the adhesion between the metal gate line and the silicon wafer and match the energy levels of the silicon wafer and the composite grid.

[0040] In some alternative implementations, TOPCon batteries, such as Figure 2 As shown, the silicon substrate 10 has a first doping type, and the solar cell further includes:

[0041] An emitter 21 is located in the silicon substrate 10. The surface of the emitter 21 facing away from the second electrode 30 is in the same plane as the surface of the silicon substrate 10 facing away from the second electrode 30. The emitter 21 is electrically connected to the first electrode 20 and has a second doping type. A tunneling oxide layer 22 is located on the side of the silicon substrate 10 facing away from the emitter 21. A doped conductive layer 23 is located on the side of the tunneling oxide layer 22 facing away from the silicon substrate 10 and is electrically connected to the second electrode 30. The doped conductive layer 23 has a first doping type, which is different from the second doping type. A first passivation layer 24 and a second passivation layer 25 are located on the side of the emitter 21 facing away from the silicon substrate 10, and the second passivation layer 25 is located on the side of the doped conductive layer 23 facing away from the silicon substrate 10. A first antireflection layer 26 may also be provided on the side of the first passivation layer 24 facing away from the emitter 21.

[0042] In the above optional embodiments, the emitter can be a doped polycrystalline silicon layer, or a structure formed by boron diffusion on the surface of a textured structure; the doped conductive layer can be a doped polycrystalline silicon layer, a silicon carbide layer, or a composite layer of doped polycrystalline silicon and silicon carbide layers. The first passivation layer can suppress carrier recombination at the emitter layer interface, thus avoiding the problem of reduced photocurrent due to carrier recombination, thereby ensuring high battery efficiency. Optionally, the material of the first passivation layer can be a single-layer film or a composite film such as aluminum oxide, silicon nitride, silicon oxide, and silicon oxynitride. The second passivation layer can suppress carrier recombination at the interface, thus avoiding the problem of reduced photocurrent due to carrier recombination, thereby ensuring high photoelectric conversion efficiency of the battery. The material of the second passivation layer can be a single-layer film or a composite film such as silicon nitride, silicon oxide, and silicon oxynitride. The material of the first antireflection layer can be silicon nitride or similar materials, and the first antireflection layer can be a single-layer film or a multilayer film. The material of the tunneling oxide layer can be silicon oxide.

[0043] The TOPCon battery described above has a substrate with a textured surface, which can better reduce reflectivity and scatter light. This causes the light to undergo multiple reflections within the substrate, increasing the path length of the light, improving current output, and increasing short-circuit current.

[0044] Figure 3 This is a flowchart of a method for fabricating a solar cell according to an embodiment of this application. Figure 2 As shown, the method includes the following steps:

[0045] Step S1, providing a silicon substrate;

[0046] Specifically, the battery substrate can be a large-size N-type or P-type monocrystalline silicon wafer of 182×182mm or 210×105mm, which is textured to form a 2~5μm pyramid texture, which can increase the light reflection path and improve photon absorption efficiency.

[0047] Step S2: Form a first electrode on one side of the silicon substrate;

[0048] Step S3: Form a second electrode on the side of the silicon substrate opposite to the first electrode;

[0049] Specifically, the aforementioned electrodes can utilize a copper-silver alloy (copper content can be 95%-98%, silver content can be 2%-5%) to provide the main conductive channels, balancing conductivity and cost in material selection. They can be formed through electrochemical deposition, with an electrode width of 20±0.5μm, a height of 80~120μm, a spacing of 2~3mm, and a grid duty cycle (electrode area / total area) ≤4%. Copper has a lower resistivity than silver; adding 2%-5% silver can improve oxidation resistance and adhesion.

[0050] Step S4: An interface transition layer is formed on the side of the first electrode away from the silicon substrate and on the side of the second electrode away from the silicon substrate. The interface transition layer includes reduced graphene oxide and forms covalent bonds with the first electrode and the second electrode at the contact point.

[0051] Specifically, the interface transition layer can be 1-2 layers of reduced graphene oxide (rGO), with a thickness of 0.34-0.68 nm; the sp of graphene 2 Hybrid orbitals can form coordinate bonds with free electrons on the metal surface, resulting in an interfacial resistance ≤10. -4 Ω cm 2 By bonding with the surface of the metal gate (electrode) through covalent bonds, the interfacial resistance can be eliminated; the interfacial transition layer can also prevent metal atoms from diffusing into the silicon substrate.

[0052] Step S5: A graphene layer is formed on the side of the interface transition layer away from the silicon substrate.

[0053] Specifically, the graphene layer can be 3-5 layers of graphene, with a thickness of 1.02~1.7 nm. The light transmittance of the 3-5 layers of graphene is ≥92%, and the electrical conductivity is ≥1×10⁻⁶. 5 With a resistivity of S / cm, graphene can block the penetration of oxygen and water vapor. The graphene layer can fill the gaps in the metal mesh, preventing oxidation of the grid surface, aiding conductivity, and reducing the overall resistivity. A protective layer can also be formed on the graphene layer. The material of the protective layer can be silicon nitride. The dielectric constant of silicon nitride (7.5) matches that of graphene, and it has good density (porosity ≤0.1%), which can protect the graphene from oxidation and improve the mechanical strength of the composite film.

[0054] The solar cell fabricated by the method of this embodiment includes an interface transition layer comprising reduced graphene oxide, which forms covalent bonds with the first and second electrodes at their contact points. The graphene layer is located on the side of the interface transition layer facing away from the silicon substrate. The chemical bonding between the reduced graphene oxide and the metal electrodes can enhance the interfacial bonding strength between the interface transition layer and the electrodes, effectively eliminating the problems of loose bonding and increased interfacial resistance between the metal mesh and the graphene-containing structure. The reduced graphene oxide has good conductivity and high light transmittance, and together with the upper graphene layer, it can form a low-resistance, high-transmittance conductive network, enabling efficient carrier transport between the electrodes, the interface transition layer, and the graphene layer, reducing series resistance, improving photoelectric conversion efficiency, and thus solving the problem of poor cell performance in existing solar cells.

[0055] In step S1 of the above embodiments, the step of pretreating the silicon substrate includes:

[0056] Place the 182×182mm or 210×105mm silicon wafers into the cleaning tank and perform the following cleaning steps in sequence:

[0057] 1. Alkaline cleaning: A 5% NaOH solution can be used, with reaction conditions of 60℃ and 10min to remove the mechanical damage layer on the silicon wafer surface;

[0058] 2. Pickling: A 10% HCl solution can be used. The reaction conditions are room temperature and 5 minutes to remove residual metal impurities from alkaline cleaning.

[0059] 3. Ultrasonic cleaning: Deionized water can be used for ultrasonic cleaning (power can be 150W, time can be 10min) to remove surface particles.

[0060] 4. Drying: Under a nitrogen atmosphere, at a temperature of 120℃ and a time of 20 minutes, the surface of the silicon wafer will have ≤10 water marks / cm² and a particle size ≤0.5μm after drying.

[0061] 5. Silicon wafer texturing: Plasma texturing can be used. The reaction conditions are as follows: plasma power of 300-400W, reaction gas of SF6 and O2 (volume ratio 3:1), pressure of 50-80Pa, and time of 8-12min. After texturing, a pyramid-shaped textured surface of 2-5μm is formed on the silicon substrate surface, and the reflectivity of light in the 400-800nm ​​wavelength band is ≤12%.

[0062] 6. Surface activation: The texturized silicon substrate is placed in a plasma cleaner and treated with argon plasma (power 200W, pressure 30Pa, time 5min) to increase the hydroxyl content on the silicon wafer surface and enhance the adhesion to the transparent conductive layer of the subsequent HJT cell.

[0063] Silicon wafers that have undergone cleaning, texturing, and activation processes have a high surface cleanliness (metal impurity content ≤1×10⁻⁶). 15 With low reflectivity (≤12%) and high surface activity, the textured surface provides excellent substrate conditions for the deposition of a thin transparent conductive layer in HJT cells. The peel strength of the thin transparent conductive layer in HJT cells is ≥1.5N / mm, which meets the requirements for mass production.

[0064] In the specific implementation process of HJT battery fabrication, after providing the silicon substrate, the silicon substrate has a first surface and a second surface with opposite surfaces. The fabrication method also includes:

[0065] A first intrinsic amorphous silicon layer and a first amorphous silicon layer are sequentially formed on the first surface. First, the first intrinsic amorphous silicon layer is formed by plasma-enhanced chemical vapor deposition (PECVD). The reaction conditions can be a temperature of 150~180℃, a gas ratio of 10~30 sccm for silane and 100~300 sccm for hydrogen (high hydrogen dilution improves passivation quality, reduces dangling bond defects, and increases open-circuit voltage), a radio frequency power of 5~30W (to reduce ion bombardment damage), a gas pressure of 0.5~2 Torr, and a deposition time of 5~15 minutes (a film thickness of 5~15 nm can balance passivation and light absorption). The first amorphous silicon layer is then formed using PECVD. The reaction conditions are as follows: temperature 150–200℃ (to avoid crystallization of amorphous silicon), gas ratio : silane: 5~20 sccm (carbon source), phosphine: 0.5–5 sccm (doping gas, concentration 1~5% PH3 / H2 mixture), hydrogen: 50~200 sccm (dilution gas, to inhibit crystallization), RF power 10~50W (13.56MHz, which can control plasma activity), gas pressure 0.1~1 Torr; deposition time 1–5 minutes (film thickness 5~20nm can ensure sufficient electron transport).

[0066] A second intrinsic amorphous silicon layer and a second amorphous silicon layer are sequentially formed on the second surface and then annealed at a temperature of 150–200°C. The preparation method of the second intrinsic amorphous silicon layer is the same as that of the first intrinsic amorphous silicon layer and will not be repeated. The second amorphous silicon layer can be formed using PECVD, with the following process parameters: temperature 150–200°C (to prevent dopant diffusion into the intrinsic amorphous silicon layer), gas ratio: silane: 5–20 sccm, borane (B₂H₆): 0.5–5 sccm (doping gas, concentration 1–5% B₂H₆ / H₂ mixture, which can control hole concentration), hydrogen: 50–200 sccm, RF power: 10–50 W, gas pressure: 0.1–1 Torr, deposition time: 1–5 minutes (a film thickness of 5–20 nm ensures efficient hole collection). Annealing at 150–200°C for 30–60 minutes (N₂ atmosphere) can activate the dopant and reduce interface states. If the temperature is too high, such as above 200°C, it will cause the amorphous silicon to crystallize, destroying the heterojunction band structure.

[0067] A first transparent conductive layer is formed on the side of the first amorphous silicon layer facing away from the silicon substrate, and a second transparent conductive layer is formed on the side of the second amorphous silicon layer facing away from the silicon substrate. The first transparent conductive layer is electrically connected to the first electrode, and the second transparent conductive layer is electrically connected to the second electrode. The first and second transparent conductive layers are formed by depositing ITO or IZO using a magnetron sputtering process, with the specific parameters as follows:

[0068] Target material selection: ITO target (mass ratio In2O3:SnO2=90:10) or IZO target (mass ratio In2O3:ZnO=80:20), with a target purity ≥99.99% and a density ≥95%.

[0069] Sputtering parameters: Vacuum degree ≤ 5 × 10 -4 Pa; Sputtering gas: Argon and oxygen mixture (volume ratio 95:5); Sputtering power: 80-100W (DC sputtering); Deposition temperature: 150-200℃ (below the 250℃ process limit for HJT cells to avoid silicon wafer performance degradation); Deposition rate: 0.5-1nm / s; Deposition thickness: 10-20nm (the final thickness is 10nm, corresponding to a deposition time of 10-20s; the final thickness is 20nm, corresponding to a deposition time of 20-40s).

[0070] Post-treatment: After deposition, the first transparent conductive layer is annealed in a nitrogen atmosphere (temperature 200℃, time 30min) to improve the crystallinity of the first transparent conductive layer and reduce the resistivity.

[0071] Thin first and second transparent conductive layers are deposited by magnetron sputtering, with a thickness uniformity of ≤±0.5nm (within an 182×182mm silicon wafer) and a resistivity of ≤2×10⁻⁶. -4 Ω With a thickness of cm, a light transmittance of ≥90%, and a peel strength to the silicon wafer of ≥1.5N / mm, it can effectively match the interface between the subsequent metal mesh and the silicon wafer, providing a good adhesion substrate for the deposition of metal gate lines.

[0072] A passivation layer, an electrode, an interface transition layer, a graphene layer, and a protective layer are formed on the first and second transparent conductive layers to obtain an HJT battery. The passivation layer can be formed using conventional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).

[0073] The protective layer can be prepared using the following process:

[0074] Using a custom photomask, the opening is aligned with the grid line area of ​​the solar cell, preventing the deposition of a protective layer (material can be SiNx) in this area. A PECVD process can be used to deposit the silicon nitride protective layer. Specific parameters are as follows: the reaction gas can be a mixture of silane (SiH4) and ammonia (NH3) (volume ratio 1:3), with a flow rate of 20-25 sccm; deposition parameters: power can be 250-300W; deposition temperature can be 80-200℃; deposition pressure can be 20-30Pa; deposition time can be 15-20 min; deposition thickness can be 10-15 nm. The silicon nitride protective layer used above has the characteristics of being dense and non-porous (porosity ≤0.1%), hardness ≥8H, water contact angle ≥110°, and oxygen permeability ≤1×10⁻⁶. -6 cm 3 / (m 2 d (atm) can effectively block oxygen and water vapor penetration, protecting graphene and metal grid lines from oxidation.

[0075] The adhesion between the deposited silicon nitride protective layer and the graphene layer is ≥1.0N / mm, and the light transmittance is ≥90% (400-800nm ​​band), which will not affect the light absorption of the battery. The presence of the protective layer greatly improves the long-term stability of the composite film. After accelerated aging test (85℃, 85% humidity, 1000 hours), the resistivity change rate is ≤5%, which is far better than the metal mesh without a protective layer (change rate ≥30%).

[0076] In the specific implementation of TOPCon cell fabrication, in some optional embodiments, the silicon substrate has a first surface and a second surface, and the fabrication method further includes the following after providing the silicon substrate:

[0077] An emitter is formed by ion implantation into the first surface. An antireflection layer and a first passivation layer are sequentially formed on the side of the emitter away from the silicon substrate. The emitter is electrically connected to the first electrode. The first electrode can penetrate the antireflection layer and the first passivation layer and be connected to the emitter. The doping concentration of the emitter is opposite to that of the silicon substrate. When the silicon substrate is N-type doped, the emitter is P-type doped, and the doping element can be boron; when the silicon substrate is P-type doped, the emitter is N-type doped, and the doping element can be phosphorus.

[0078] A tunneling oxide layer, a doped conductive layer, and a second passivation layer are sequentially formed on the second surface. The doped conductive layer is electrically connected to the second electrode. The second electrode penetrates the second passivation layer and is connected to the doped conductive layer. The tunneling oxide layer can be prepared using a thermal oxidation process. The doping type of the doped conductive layer is the same as that of the silicon substrate; when the silicon substrate is N-type doped, the doped conductive layer is also N-type doped. The antireflection layer, the first passivation layer, and the second passivation layer can be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD), etc., and this application does not specify a particular method.

[0079] In some alternative implementations, the steps of forming the first electrode and the second electrode include:

[0080] A first template is provided, and a laser etching process is used to etch the first template so that the first template has a first pattern;

[0081] Specifically, the substrate for the first template can be polyethylene terephthalate (PET) film as a flexible substrate, with a thickness of 100-150 μm and a width adaptable to 182 mm or 210 mm battery cells. The substrate should have a light transmittance of ≥90%, a tensile strength of ≥150 MPa, and a thermal stability of ≥120℃ (without thermal deformation). The substrate is then subjected to the following steps to form the first template: the PET substrate is immersed in a 0.5% (w / w) perfluorosilane anhydrous ethanol solution for 10-15 minutes. After immersion, it is dried in an 80℃ oven for 30 minutes to form an anti-stick coating (contact angle ≥105°) to prevent the template from being difficult to peel off after subsequent metal deposition. A UV laser etching machine (wavelength 355 nm, power 10-15 W) is used to etch grooves on the PET substrate. The groove pattern can have a groove width of 20μm (consistent with the target grid line width), a groove depth of 80-120μm (consistent with the target grid line height), and a groove spacing of 2-3mm (for example, for a 182×182mm battery cell, the groove spacing can be 2mm, and for a 210×105mm battery cell, the groove spacing can be 2.5mm). The etching rate can be 50-80mm / s, the perpendicularity of the etched groove edge can be ≥90°, and the surface roughness can be Ra≤0.1μm. The etched template is then ultrasonically cleaned sequentially with anhydrous ethanol and deionized water (100W power, 5min) to remove etching residues, and then dried in a nitrogen atmosphere (nitrogen flow rate 10-15L / min, 10min) to obtain a flexible template. The first template prepared by the above laser etching can have a groove size of ±0.5μm, which meets the preparation requirement of 20μm gate line width; the anti-stick coating on the template surface can make the peel force of the subsequent metal deposition layer ≤0.1N / mm, avoiding damage to the gate line; compared with the photolithography and development process, the equipment investment of this step is only 1 / 5 of that of the photolithography and development process, and there is no chemical consumption, making it more environmentally friendly.

[0082] An electrochemical deposition process is used to form a first electrode and a second electrode on opposite sides of a silicon substrate using a first pattern of a first template and an electroplating solution. The electroplating solution includes at least a salt solution, a complexing agent, and additives. The salt solution includes copper sulfate and silver nitrate, the complexing agent includes disodium ethylenediaminetetraacetate, and the additives include a brightener and a leveling agent. Specifically, for an HJT battery, the first electrode and the second electrode are formed on a first transparent conductive layer and a second transparent conductive layer using the first pattern of the first template and the electroplating solution; for a TOPCon battery, the first electrode and the second electrode are formed on a first passivation layer and a second passivation layer using the first pattern of the first template and the electroplating solution. The first electrode penetrates the first passivation layer and contacts the emitter, and the second electrode penetrates the second passivation layer and contacts the doped conductive layer.

[0083] Taking HJT batteries as an example, copper-silver alloy grid lines are deposited on the surface of the first transparent conductive layer, and graphene precursor (graphene oxide, GO) is introduced in situ, laying the foundation for the subsequent covalent bonding of graphene and metal grid lines. The specific process steps and parameters are as follows:

[0084] A continuous electrochemical deposition tank can be used. The cathode consists of a pretreated silicon substrate, intrinsic amorphous silicon, and an amorphous silicon layer. The anode is a platinum electrode. The first template is tightly attached to the surface of the first transparent conductive layer. A femtosecond laser is used to ablate the first template at the grooves in the first pattern, and the anode is volatilized through an organic solvent. The template bonding pressure can be 0.1-0.2 MPa to ensure complete contact between the grooves of the first template and the first transparent conductive layer.

[0085] The formulation of the electroplating solution may include a main salt, a complexing agent, a graphene precursor, and additives. The main salt includes copper sulfate (CuSO4) at a concentration of 200-250 g / L. The electroplating solution contains 5-10 g / L silver nitrate (AgNO3) (corresponding to 2%-5% silver content in copper-silver alloys); the complexing agent includes 150-200 g / L disodium ethylenediaminetetraacetate (EDTA-2Na) to stabilize silver ions and prevent premature precipitation; the graphene precursor includes an aqueous dispersion of graphene oxide (GO) (concentration 0.5-1 mg / mL), added at 5%-10% of the total volume of the electroplating solution, with GO flakes of 500-1000 nm in diameter and an oxidation degree ≥30% (oxygen content ≥20%); the additives include 1-2 g / L brightener (polyethylene glycol, PEG-6000) and 0.1-0.2 g / L leveling agent (2-mercaptobenzimidazole) to promote uniform deposition of metal ions; the pH value of the above electroplating solution can be 4.5-5.5 (adjusted with sulfuric acid or sodium hydroxide).

[0086] Electroplating solution deposition parameters: current density can be 1-2 A / dm³ 2 The deposition temperature can be 40-50℃; the deposition time can be 30-60min (for example, if the gate height is 80μm, the deposition time can be 30min, and if the gate height is 120μm, the deposition time can be 60min); the stirring speed can be 300-500r / min (mechanical stirring) to ensure uniform composition of the electroplating solution.

[0087] After deposition, rinse the surface with deionized water to remove residual electroplating solution (rinsing pressure can be 0.3 MPa, time can be 3 min), and then pre-dry in a nitrogen atmosphere (temperature can be 80℃, time can be 15 min). At this time, the metal grid lines are embedded in the flexible template grooves, and GO has been adsorbed on the surface of the metal grid lines.

[0088] Through the above electrochemical deposition process, copper-silver alloy gate lines with a width of 20 μm and a height of 80-120 μm and an aspect ratio of 4-6 were successfully prepared, which is beneficial to reduce the light-blocking area and improve conductivity. The in-situ introduction of GO precursor forms a uniform GO adsorption layer (thickness can be 0.34-0.68 nm) on the surface of the metal gate line, laying the foundation for the subsequent reduction to form a graphene interface transition layer. This step does not require photoresist protection, simplifies the process by reducing multiple steps, improves the deposition rate, and the oxidation resistance of copper-silver alloy is better than that of pure copper.

[0089] In some alternative implementations, the step of forming the interface transition layer includes:

[0090] In the steps of forming the first electrode and the second electrode, a graphene precursor solution is added to the electroplating solution, and an electrochemical deposition process is used to attach graphene oxide from the graphene precursor solution to the surfaces of the first electrode and the second electrode to form a graphene oxide layer. This step can be performed simultaneously with the preparation of the first electrode and the second electrode. The relevant description has been described during the preparation of the first electrode and the second electrode, and will not be repeated here.

[0091] A thermal reduction process is used to reduce the graphene oxide layer, forming an interfacial transition layer.

[0092] After the first electrode, the second electrode, and the graphene oxide layer are formed, GO (graphene oxide) can be reduced to rGO (reduced graphene oxide, forming an interface transition layer) through a combination of thermal reduction and plasma reduction. At the same time, graphene is deposited (forming a transparent and conductive layer), realizing in-situ composite of graphene and metal grid lines. The specific steps are as follows:

[0093] 1. Thermal reduction of GO (forming a graphene interfacial transition layer): The equipment can be a tube furnace; the atmosphere can be a mixture of argon and hydrogen (volume ratio 95:5), with a flow rate of 20-30 sccm; the heating rate can be 5℃ / min; the reduction temperature can be 200℃; the reduction time can be 30-120 min; the cooling rate can be 10℃ / min, cooling to room temperature. The removal rate of oxygen-containing functional groups (hydroxyl, carboxyl, epoxy groups) in GO is ≥90%, reducing GO to rGO. rGO forms covalent bonds (Cu-C bonds, Ag-C bonds) with copper and silver atoms on the surface of the metal grid, resulting in an interfacial resistance ≤10 Ω·cm. -4 Ω cm 2 .

[0094] 2. Graphene Deposition (Forming a Transparent and Conductive Layer): The equipment can be plasma-enhanced chemical vapor deposition (PECVD); the substrate temperature can be 180℃ (below the upper limit of the thermal stability of HJT silicon wafers); the reaction gas can be a mixture of methane (CH4) and hydrogen (H2) (volume ratio 1:10), with a flow rate of 10-15 sccm; the plasma power can be 150-200W; the deposition pressure can be 10-20 Pa; and the deposition time can be 10-20 min (controlled according to the number of graphene layers: 10 min for 3 layers, 20 min for 5 layers). 3-5 continuous graphene layers are deposited on the surface of the rGO interface transition layer and the transparent conductive layer in the gaps between the metal meshes, achieving a light transmittance ≥92% and an electrical conductivity ≥1×10⁻⁶. 5 S / cm.

[0095] 3. Plasma post-processing: The equipment can be an atmospheric plasma treatment machine; the plasma source can be a mixture of argon and nitrogen (volume ratio 8:2); the power can be 300-400W; the processing time can be 5-10 minutes; the above process can repair defects in the graphene layer (making the defect density ≤10). 10 cm -2 This improves the adhesion between graphene and rGO and TCO layers (peel strength ≥1.2N / mm).

[0096] Through the combined process of thermal reduction, PECVD deposition, and plasma post-treatment, in-situ composite of graphene and metal grid lines was achieved, forming a dual structure of "rGO interface transition layer + CVD graphene transparent and conductive layer". The composite graphene layer and the metal grid line interface are tightly bonded (interface resistance ≤ 10 Ω). -4 Ω cm 2 (), far lower than the 10% of existing stepwise composite processes. -3 Ω cm 2 The light transmittance of the graphene layer can reach ≥92%, and the electrical conductivity can reach ≥1×10⁻⁶. 5 S / cm can effectively fill the gaps in the metal mesh, improving overall light transmittance and conductivity.

[0097] In some alternative embodiments, the steps of forming the first transparent conductive layer and the second transparent conductive layer include:

[0098] Magnetron sputtering is used to sputter a target material, including indium tin oxide (ITO) or indium zinc oxide (IZO), onto the surfaces of a first and second transparent conductive layer. Specific parameters are as follows:

[0099] Target material selection: ITO target (mass ratio In2O3:SnO2=90:10) or IZO target (mass ratio In2O3:ZnO=80:20), with a target purity ≥99.99% and a density ≥95%.

[0100] Sputtering parameters: Vacuum degree: ≤5×10 -4 Pa; Sputtering gas: Argon and oxygen mixture (volume ratio 95:5); Sputtering power: 80-100W (DC sputtering); Deposition temperature: 150-200℃ (below the 250℃ process limit for HJT cells to avoid silicon wafer performance degradation); Deposition rate: 0.5-1nm / s; Deposition thickness: 10-20nm (precisely controlled by deposition time: 10nm corresponds to 10-20s deposition time, 20nm corresponds to 20-40s);

[0101] Post-treatment: After deposition, the first transparent conductive layer is annealed in a nitrogen atmosphere (temperature 200℃, time 30min) to improve the crystallinity of the first transparent conductive layer and reduce the resistivity.

[0102] Thin first and second transparent conductive layers are deposited by magnetron sputtering, with a thickness uniformity of ≤±0.5nm (within an 182×182mm silicon wafer) and a resistivity of ≤2×10⁻⁶. -4 Ω With a thickness of cm, a light transmittance of ≥90%, and a peel strength to the silicon wafer of ≥1.5N / mm, it can effectively match the interface between the subsequent metal mesh and the silicon wafer, providing a good adhesion substrate for the deposition of metal gate lines.

[0103] After preparing the protective layer on the graphene layer, the step of peeling off the first template includes:

[0104] The battery is placed in the stripping groove, and the first template is stripped using a mechanical stripping method. The stripping angle can be 180°, and the stripping speed can be 5-10 mm / s. During the stripping process, nitrogen gas of 0.05-0.1 MPa can be applied for purging (the purging direction is consistent with the stripping direction) to assist the template in detaching and avoid damage to the grid lines.

[0105] After the template is peeled off, it can be ultrasonically cleaned with anhydrous ethanol (power can be 80W, time can be 3min) to remove the residual anti-stick coating and template debris, then rinsed with deionized water (pressure can be 0.2MPa, time can be 2min), and dried with nitrogen.

[0106] The first template peeling success rate using the above steps is ≥99.5%, and the metal grid lines are undamaged and unbroken after peeling (breakage rate ≤0.1%). All performance indicators of the finished composite film meet the design requirements, with light transmittance ≥92% and resistivity ≤5×10⁻⁶. -5 Ω cm, peel strength ≥1.2N / mm, with long-term stability.

[0107] The prepared batteries are subjected to finished product testing. The testing items may include: grid line height (can be measured using a laser confocal microscope), grid line width (can be measured using a laser confocal microscope), light transmittance (can be measured using a UV-Vis spectrophotometer (400-800nm)), resistivity (can be measured using a four-probe method), peel strength (can be measured using an adhesive tape peeling method), oxidation resistance (can be measured using a damp heat aging test), and mechanical stability (can be measured using a bending test).

[0108] According to another aspect of the embodiments of this application, a photovoltaic module is provided, comprising a plurality of solar cells prepared by the above-described method for preparing solar cells. The overall performance of the solar cells prepared according to the method of this application is improved to varying degrees, solving the problem of poor cell performance.

[0109] The preparation method of the solar cell described above in this application will be specifically described below with reference to specific embodiments and comparative examples.

[0110] Example 1

[0111] The manufacturing steps of a photovoltaic module proposed in this application include:

[0112] Step 1, Material Preparation;

[0113] 1. Silicon wafer: 182×182mm, N-type monocrystalline silicon wafer, resistivity 2Ω cm, thickness 120μm;

[0114] 2. The substrate of the first template: 120μm thick, 92% light transmittance, and 160MPa tensile strength;

[0115] 3. Target material for the transparent conductive layer: In2O3:SnO2 = 90:10 (mass ratio), purity 99.99%;

[0116] 4. Electroplating solution raw materials: Copper sulfate (CuSO4) 5H2O), silver nitrate (AgNO3), EDTA-2Na, GO aqueous dispersion (concentration 0.8mg / mL, tablet diameter 800nm, oxidation degree 35%), PEG-6000, 2-mercaptobenzimidazole;

[0117] 5. Graphene raw materials: methane (99.99% purity), hydrogen (99.99% purity);

[0118] 6. Protective layer (silicon nitride) raw materials: silane (purity 99.99%), ammonia (purity 99.99%).

[0119] Step 2, Flexible template preparation:

[0120] Surface modification of PET substrate: Immerse in 0.5% perfluorosilane anhydrous ethanol solution for 12 min, and dry at 80℃ for 30 min;

[0121] Laser etching: Ultraviolet laser etching machine (wavelength 355nm, power 12W), groove width 20μm, depth 100μm, spacing 2mm, etching speed 60mm / s;

[0122] Cleaning and drying: Ultrasonic cleaning with anhydrous ethanol and deionized water for 5 minutes each, followed by drying with nitrogen.

[0123] Step 3, Silicon Wafer Pretreatment:

[0124] Cleaning: First, clean with NaOH solution (5%) at 60℃ for 10 min, then clean with HCl solution (10%) at room temperature for 5 min, then clean with deionized water by ultrasonic cleaning for 10 min, and finally dry with nitrogen at 120℃ for 20 min.

[0125] Texturing: Plasma texturing (SF6:O2=3:1, power 350W, pressure 60Pa, time 10min), the reflectivity of the texturized surface is 11%;

[0126] Activation: Argon plasma treatment (power 200W, pressure 30Pa, time 5min);

[0127] A first intrinsic amorphous silicon layer and a second amorphous silicon layer are formed on the front side of the processed silicon wafer using conventional processes, and a second intrinsic amorphous silicon layer and a second amorphous silicon layer are formed on the back side.

[0128] Step 4: Deposition of the first and second transparent conductive layers:

[0129] Magnetron sputtering parameters: vacuum level 3×10 -4 Pa, Ar:O2=95:5, power is 90W, temperature is 180℃, deposition rate is 0.8nm / s, deposition thickness is 15nm;

[0130] Annealing: Anneal at 200℃ in a nitrogen atmosphere for 30 minutes;

[0131] Step 5, Electrochemical deposition of metal mesh:

[0132] Electroplating solution formula: CuSO4 at a concentration of 220 g / L The electroplating solution contained 5H2O, 8 g / L AgNO3 (8% by volume), 180 g / L EDTA-2Na, 0.8 mg / mL GO aqueous dispersion, 1.5 g / L PEG-6000, 0.15 g / L 2-mercaptobenzimidazole, and pH 5.0.

[0133] Deposition parameters: current density 1.5 A / dm², temperature 45℃, time 45 min, stirring speed 400 r / min;

[0134] Post-treatment: Rinse with deionized water for 3 min, and pre-dry with nitrogen at 80℃ for 15 min;

[0135] Step 6: In-situ graphene recombination and reduction:

[0136] Thermal reduction: Ar:H2=95:5, flow rate 25sccm, heating rate 5℃ / min, reduction at 180℃ for 75min, cooling rate 3℃ / min;

[0137] Graphene deposition: Four layers of graphene were prepared using a PECVD device at a temperature of 180℃, CH4:H2=1:10, flow rate of 12sccm, power of 180W, pressure of 15Pa, and time of 15min.

[0138] Plasma post-treatment: Ar:H2=8:2, power 350W, time 8min;

[0139] Step 7, Deposition of protective layer:

[0140] Silicon nitride was deposited by PECVD with a SiH4:NH3 ratio of 1:3 (volume ratio), a flow rate of 22 sccm, a power of 280 W, a temperature of 180 °C, a pressure of 25 Pa, and a time of 18 min, resulting in a silicon nitride thickness of 12 nm.

[0141] Step 8: Template peeling and finished product inspection:

[0142] Mechanical peeling: peeling angle is 180°, speed is 8 mm / s, and nitrogen purging pressure is 0.08 MPa;

[0143] Cleaning: First, use anhydrous ethanol for ultrasonic cleaning for 3 minutes, then rinse with deionized water for 2 minutes, and finally dry with nitrogen gas;

[0144] Detection: The grid line width is 20.2 μm, the height is 98 μm, the light transmittance is 92.5%, and the resistivity is 4.2 × 10⁻⁶. -5 Ω The peel strength is 1.3 N / mm, and the resistivity change rate after damp heat aging (85℃, 85%RH, 1000h) is 3.8%.

[0145] Step 8: Battery assembly and performance testing:

[0146] Back electrode fabrication: The aluminum back electrode thickness is 1.5 μm, the silver back electrode grid line width is 100 μm, and the spacing is 2 mm;

[0147] Edge isolation: Laser etching width is 1.5mm;

[0148] Component encapsulation: EVA film thickness is 0.5mm, tempered glass thickness is 3.2mm, lamination parameters are temperature 150℃, pressure 0.15MPa, and time 20min.

[0149] Comparative Example 1

[0150] The difference between the preparation steps of the photovoltaic module in Comparative Example 1 and Example 1 is that no graphene raw material is required and step 6 is missing.

[0151] Approximately 100 battery modules prepared in Example 1 and Comparative Example 1 were tested, and the following data were obtained:

[0152] Table 1

[0153]

[0154] Example 2

[0155] The difference from Example 1 is as follows:

[0156] The method for preparing the solar cell in this application includes:

[0157] The silicon wafer used in step 1 is 210×10⁵ mm, an N-type monocrystalline silicon wafer, with a resistivity of 2Ω. cm, thickness 120μm;

[0158] In step 2, the laser etching parameters include a groove width of 20 μm, a depth of 110 μm, a spacing of 2.5 mm, and an etching rate of 55 mm / s.

[0159] The reflectivity after texturing in step 3 is 10.5%;

[0160] The deposition thickness in step 4 is 18 nm;

[0161] In step 5, the electroplating solution contains 7 g / L AgNO3 and 7% GO aqueous dispersion by volume; the deposition time is 50 min.

[0162] The deposition time in step 6 is 18 minutes, and 5 layers of graphene are prepared.

[0163] The thickness of the silicon nitride formed in step 7 is 14 nm;

[0164] The detection results in step 8 are as follows: the grid line width is 19.8 μm, the height is 103 μm, the light transmittance is 92.2%, and the resistivity is 4.5 × 10⁻⁶. -5 Ω The peel strength is 1.25 N / mm, and the resistivity change rate after damp heat aging is 4.2%.

[0165] Comparative Example 2

[0166] The difference between the photovoltaic module preparation steps of Comparative Example 2 and Comparative Example 1 is that the size of the cell used is 210×105mm.

[0167] Approximately 100 battery modules prepared in Example 2 and Comparative Example 2 were tested, and the following data were obtained:

[0168] Table 2

[0169]

[0170] Example 3

[0171] The method for preparing the solar cell in this application includes:

[0172] Step 1: Clean the pile (double-sided pile)

[0173] Process parameters (N-type silica texturing):

[0174] Texturing solution: NaOH (1.5wt%) + isopropanol (IPA, 4wt%) + deionized water; temperature: 82℃; time: 17min; post-texturing treatment: HCl (8wt%) pickling + HF (1.5wt%) pickling to remove surface metal impurities and oxide layer; water washing + drying: multi-stage overflow water washing, drying at 110℃, the surface is hydrophobic.

[0175] Step 2: Frontal boron diffusion (PN junction preparation)

[0176] Process parameters (tubular thermal diffusion, mainstream process): Diffusion source: boron tribromide (BBr3, liquid source, low corrosivity) or trimethyl borate (TMB); Diffusion temperature: 1000℃ (N-type silicon boron diffusion temperature is higher than P-type phosphorus diffusion); Diffusion time: 140min (pre-diffusion 30min + advance 80min + annealing 30min); Process atmosphere: N2+O2 (pre-oxidation), oxygen flow rate 800sccm.

[0177] Step 3: Remove BSG and perform backside etching (alkaline polishing)

[0178] Process parameters: BSG removal: Immerse in HF (8wt%) solution for 2.5 min to remove BSG from the front side; Back side alkaline polishing: NaOH (12wt%) solution, temperature 78℃, time 4 min, to etch the back side silicon layer to 1.5μm; Post-treatment: HCl pickling + HF pickling + deionized water washing, and drying.

[0179] Step 4: Preparation of tunneling oxide layer (SiO2, using the thermal oxidation method of PECVD process)

[0180] Process parameters: dry oxygen / wet oxygen high-temperature oxidation; temperature is 650℃, dry oxygen for 20 min, O2 flow rate is 1.5 slm.

[0181] Step 5, Phosphorus-doped polycrystalline silicon layer (n + poly-Si was deposited using LPCVD.

[0182] Process parameters: Temperature 600℃, Pressure 80Pa, SiH4 flow rate 800sccm, doping source PH3; Deposition rate: 8nm / min, thickness 140nm; Doping method: In-situ doping (PH3 introduced during deposition), doping concentration 10 20 cm -3 .

[0183] Step 6: High-temperature annealing (polycrystallineization and doping activation)

[0184] Process parameters: Annealing temperature: 850℃; Annealing time: 45min; Atmosphere: N2 (99.999%) + trace H2 (2%, providing hydrogen source);

[0185] Step 7: In-situ graphene recombination and reduction:

[0186] Process parameters: Thermal reduction: Ar:H2=95:5, flow rate 25 sccm, heating rate 5℃ / min, reduction at 180℃ for 75 min, cooling rate 3℃ / min; Graphene deposition: PECVD equipment was used, temperature 180℃, CH4:H2=1:10, flow rate 12 sccm, power 180W, pressure 15Pa, time 15 min, to prepare 4 layers of graphene; Plasma post-treatment: Ar:H2=8:2, power 350W, time 8 min;

[0187] Step 8: Frontal alumina (Al2O3) deposition (ALD)

[0188] Process parameters (ALD atomic layer deposition): Precursor: Trimethylaluminum (TMA) + H₂O (vapor); Deposition temperature: 250℃; Deposition rate: 0.1 nm / cycle, number of cycles: 100, thickness uniformity <1%; Fixed negative charge: -10 13 cm-2 Activated after annealing.

[0189] Step 9: Deposition of silicon nitride (SiNx:H) on both sides

[0190] Process parameters (PECVD method):

[0191] (1) Front-side SiNx:H. Precursor: SiH4+NH3+H2; Temperature: 420℃; Power: 1800W; Thickness: 80nm; Refractive index: 2.0; Hydrogen content: 12%.

[0192] (2) Back side SiNx:H. Precursor: SiH4+NH3+H2; Temperature: 420℃; Thickness: 90nm; Refractive index: 1.9.

[0193] Step 10, SE laser doping

[0194] Process parameters: Laser type: nanosecond pulsed laser (wavelength 532nm); power: 15W; scanning speed: 800mm / s.

[0195] Step 11: Screen printing (metallization)

[0196] Process parameters: Printing sequence: Back main grid → Drying → Back secondary grid → Drying → Front main grid → Drying → Front secondary grid → Drying; Printing parameters: Squeegee pressure 100N, screen tension 0N, line width accuracy 1μm; Drying: 180℃, time 8min, to completely remove organic solvents.

[0197] Step 12: High-temperature sintering (ohmic contact formation)

[0198] Process parameters: Sintering temperature: peak 900℃, heating rate 80℃ / s; holding time: peak temperature held for 4s; atmosphere: air + N2 (oxygen controlled, oxygen content 3%).

[0199] Step 13: Battery assembly (using standard assembly process parameters is sufficient)

[0200] Comparative Example 3

[0201] The difference between the preparation steps of the photovoltaic module in Comparative Example 3 and Example 3 is that no graphene raw material is required and step 7 is missing.

[0202] Approximately 100 sets of photovoltaic modules prepared in Example 3 and Comparative Example 3 were tested, and the following data were obtained:

[0203] Table 3

[0204]

[0205] As can be seen from the data in Tables 1 to 3 above, the battery modules prepared by the method of this application have been improved to varying degrees in all aspects, and the overall performance of the battery modules formed using the solar cells of this application has been improved.

[0206] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0207] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, characterized in that, include: Silicon substrate; The first electrode is located on one side of the silicon substrate; The second electrode is located on the side of the silicon substrate opposite to the first electrode; An interface transition layer is located on the side of the first electrode away from the silicon substrate and on the side of the second electrode away from the silicon substrate. The interface transition layer includes reduced graphene oxide and forms covalent bonds with the first electrode and the second electrode at the contact points. A graphene layer is located on the side of the interface transition layer opposite to the silicon substrate.

2. The solar cell according to claim 1, characterized in that, The silicon substrate has opposing first and second surfaces, the silicon substrate has a first doping type, and the solar cell further includes: A first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer, wherein the first intrinsic amorphous silicon layer is located on the first surface and the second intrinsic amorphous silicon layer is located on the second surface; A first amorphous silicon layer and a second amorphous silicon layer, wherein the first amorphous silicon layer is located on the side of the first intrinsic amorphous silicon layer away from the silicon substrate and is electrically connected to the first electrode, and the second amorphous silicon layer is located on the side of the second intrinsic amorphous silicon layer away from the silicon substrate, wherein the first amorphous silicon layer has the first doping type and the second amorphous silicon layer has the second doping type, and the first doping type and the second doping type are different. A first transparent conductive layer and a second transparent conductive layer, wherein the first transparent conductive layer is located on the side of the first amorphous silicon layer opposite to the silicon substrate and is electrically connected to the first electrode, and the second transparent conductive layer is located on the side of the second amorphous silicon layer opposite to the silicon substrate and is electrically connected to the second electrode.

3. The solar cell according to claim 1, characterized in that, The silicon substrate has a first doping type, and the solar cell further includes: An emitter is located in the silicon substrate. The surface of the emitter facing away from the second electrode is in the same plane as the surface of the silicon substrate facing away from the second electrode. The emitter is electrically connected to the first electrode and has a second doping type. A tunneling oxide layer is located on the side of the silicon substrate opposite to the emitter; A doped conductive layer is located on the side of the tunneling oxide layer opposite to the silicon substrate and is electrically connected to the second electrode. The doped conductive layer has the first doping type, which is different from the second doping type. A first passivation layer and a second passivation layer, wherein the first passivation layer is located on the side of the emitter away from the silicon substrate, and the second passivation layer is located on the side of the doped conductive layer away from the silicon substrate.

4. A method for preparing a solar cell, characterized in that, The method for preparing the solar cell according to any one of claims 1 to 3 comprises: Provide silicon substrate; A first electrode is formed on one side of the silicon substrate; A second electrode is formed on the side of the silicon substrate opposite to the first electrode; An interface transition layer is formed on the side of the first electrode away from the silicon substrate and on the side of the second electrode away from the silicon substrate. The interface transition layer includes reduced graphene oxide and forms covalent bonds with the first electrode and the second electrode at the contact point. A graphene layer is formed on the side of the interface transition layer opposite to the silicon substrate.

5. The preparation method according to claim 4, characterized in that, The silicon substrate has opposing first and second surfaces, and the fabrication method further includes: A first intrinsic amorphous silicon layer and a first amorphous silicon layer are sequentially formed on the first surface; A second intrinsic amorphous silicon layer and a second amorphous silicon layer are sequentially formed on the second surface, and then annealed at a temperature of 150~200℃. A first transparent conductive layer is formed on the side of the first amorphous silicon layer facing away from the silicon substrate, and a second transparent conductive layer is formed on the side of the second amorphous silicon layer facing away from the silicon substrate. The first transparent conductive layer is electrically connected to the first electrode, and the second transparent conductive layer is electrically connected to the second electrode.

6. The preparation method according to claim 4, characterized in that, The silicon substrate has opposing first and second surfaces, and the fabrication method further includes: An emitter is formed by ion implantation into the first surface. An antireflection layer and a first passivation layer are sequentially formed on the side of the emitter away from the silicon substrate. The emitter is electrically connected to the first electrode. A tunneling oxide layer, a doped conductive layer, and a second passivation layer are sequentially formed on the second surface, and the doped conductive layer is electrically connected to the second electrode.

7. The preparation method according to claim 4, characterized in that, The steps of forming the first electrode and the second electrode include: A first template is provided, and the first template is etched using a laser etching process to give the first template a first pattern; An electrochemical deposition process is used to form the first electrode and the second electrode on opposite sides of the silicon substrate using the first pattern of the first template and the electroplating solution. The electroplating solution includes at least a salt solution, a complexing agent, and additives. The salt solution includes copper sulfate and silver nitrate, the complexing agent includes disodium ethylenediaminetetraacetate, and the additives include a brightener and a leveling agent.

8. The preparation method according to claim 7, characterized in that, The steps for forming the interface transition layer include: In the step of forming the first electrode and the second electrode, a graphene precursor solution is added to the electroplating solution, and the graphene oxide in the graphene precursor solution is attached to the surface of the first electrode and the second electrode by the electrochemical deposition process to form a graphene oxide layer. A thermal reduction process is used to reduce the graphene oxide layer, forming the interface transition layer.

9. The preparation method according to claim 5, characterized in that, The steps of forming the first transparent conductive layer and the second transparent conductive layer include: A magnetron sputtering process is used to sputter a target onto the surfaces of the first amorphous silicon layer and the second amorphous silicon layer. The target includes indium tin oxide or indium zinc oxide.

10. A photovoltaic module, characterized in that, This includes solar cells prepared by any one of the methods described in claims 4 to 9.

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