Back contact heterojunction solar cell and method of manufacturing the same

Abstract

The application discloses a back contact heterojunction solar cell and a preparation method thereof. The back contact heterojunction solar cell can include: a crystalline silicon substrate, a back surface including alternately arranged first conductive regions and second conductive regions; a first carrier collection layer arranged on the first conductive regions; a second carrier collection layer arranged on the second conductive regions; a conductive transition layer arranged on the outer side of the first carrier collection layer and / or the outer side of the second carrier collection layer, the conductive transition layer including a silicon oxide layer and a discontinuous metal layer; and a transparent conductive film layer arranged on the side of the conductive transition layer away from the crystalline silicon substrate and in contact with the conductive transition layer, which can effectively improve the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

Description

Technical Field

[0001] This invention relates to a back-contact heterojunction solar cell and its fabrication method. Background Technology

[0002] A back-contact heterojunction solar cell (HBC) is a high-efficiency crystalline silicon solar cell that combines heterojunction technology with a back-contact structure. For example, the back side of an N-type crystalline silicon substrate includes N-type and P-type functional regions. A tunneling passivation layer and an N-type doped polycrystalline silicon layer are disposed in the N-type functional region, while an intrinsic amorphous silicon film and a P-type doped amorphous silicon film are disposed in the P-type functional region. Transparent conductive films are disposed on the outer sides of the N-type doped polycrystalline silicon layer in the N-type functional region and the P-type doped amorphous silicon film in the P-type functional region, respectively.

[0003] However, the interfacial contact between the N-type doped polycrystalline silicon layer and the P-type doped amorphous silicon film layer and the transparent conductive film layer is poor, which is not conducive to carrier transport. Therefore, the structure of existing back-contact heterojunction solar cells still needs to be improved. Summary of the Invention

[0004] In view of this, the present invention provides a back-contact heterojunction solar cell and a method for fabricating the same. The back-contact heterojunction solar cell uses a conductive transition layer comprising a silicon oxide layer and a discontinuous metal layer as a bridge between the first carrier collection layer and / or the second carrier collection layer and the transparent conductive film layer. This effectively reduces the interface barrier and interface contact resistance, effectively improves the carrier transport efficiency of the first conductive region and / or the second conductive region, and thus effectively improves the fill factor and photoelectric conversion efficiency of the back-contact heterojunction solar cell.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a back-contact heterojunction solar cell, comprising: A crystalline silicon substrate, the back side of which includes alternating first and second conductive regions; A first carrier collection layer is disposed in the first conductive region, and the first carrier collection layer has the same conductivity type as the crystalline silicon substrate; A second carrier collection layer is disposed in the second conductive region, and the second carrier collection layer has a conductivity type opposite to that of the crystalline silicon substrate; A conductive transition layer is disposed outside the first carrier collection layer and / or outside the second carrier collection layer, wherein the conductive transition layer comprises a silicon oxide layer and a discontinuous metal layer; A transparent conductive film layer is disposed on the side of the conductive transition layer away from the crystalline silicon substrate and is in contact with the conductive transition layer.

[0006] Secondly, embodiments of the present invention provide a method for fabricating a back-contact heterojunction solar cell, comprising: Step S1: Provide a crystalline silicon substrate, the back side of which includes alternating first and second conductive regions; Step S2: A first carrier collection layer is formed in the first conductive region, a second carrier collection layer is formed in the second conductive region, and a conductive transition layer is formed on the outside of the first carrier collection layer and / or the outside of the second carrier collection layer. The conductive transition layer includes a silicon oxide layer and a discontinuous metal layer. The discontinuous metal layer is embedded in the silicon oxide layer or the discontinuous metal layer is located on the side of the silicon oxide layer away from the crystalline silicon substrate. Step S3: A transparent conductive film layer in contact with the conductive transition layer is formed on the outside of the conductive transition layer.

[0007] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: The back-contact heterojunction solar cell provided in this invention is a novel back-contact heterojunction solar cell. It features a conductive transition layer comprising a silicon oxide layer and a discontinuous metal layer on the outer side of a first carrier collection layer and / or a second carrier collection layer, and a transparent conductive film layer on the outer side of the conductive transition layer. This combination of the first carrier collection layer, the conductive transition layer comprising the silicon oxide layer and the discontinuous metal layer, and the transparent conductive film layer, along with / or the second carrier collection layer, allows for a better match between the inner interface of the conductive transition layer and its inner first and / or second carrier collection layers, and a better match between the outer interface of the conductive transition layer and the transparent conductive film layer. This effectively reduces the interface barrier and interface contact resistance, improving the carrier collection efficiency of the first and / or second conductive regions, thereby effectively increasing the fill factor and photoelectric conversion efficiency of the back-contact heterojunction solar cell. Attached Figure Description

[0008] Figure 1 This is a partial cross-sectional structural diagram of a back-contact heterojunction solar cell provided in an embodiment of the present invention; Figure 2 This is a partial cross-sectional structural diagram of another back-contact heterojunction solar cell provided in an embodiment of the present invention; Figure 3 This is a partial cross-sectional structural diagram of another back-contact heterojunction solar cell provided in an embodiment of the present invention; Figure 4This is a partial cross-sectional structural diagram of another back-contact heterojunction solar cell provided in an embodiment of the present invention; Figure 5 This is a schematic cross-sectional view of the first relative relationship between the silicon oxide layer and the metal layer in the conductive transition layer formed based on a polished surface, provided by an embodiment of the present invention. Figure 6 This is a schematic cross-sectional view of a second relative relationship between the silicon oxide layer and the metal layer in a conductive transition layer formed based on a polished surface, provided by an embodiment of the present invention. Figure 7 This is a schematic cross-sectional structure showing a third relative relationship between the silicon oxide layer and the metal layer in a conductive transition layer formed based on a textured structure according to an embodiment of the present invention. Figure 8 This is a schematic cross-sectional view of a fourth relative relationship between the silicon oxide layer and the metal layer in a conductive transition layer formed based on a polished surface, provided by an embodiment of the present invention. Figure 9 This is a schematic cross-sectional view of the fifth relative relationship between the silicon oxide layer and the metal layer in the conductive transition layer formed based on the textured surface structure provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of the main process of a method for fabricating a back-contact heterojunction solar cell according to an embodiment of the present invention; Figure 11 This is a schematic cross-sectional view of the partial structural changes corresponding to each step of the preparation method of the second embodiment of the present invention, including step S2. Figure 12 This is a schematic cross-sectional view of the structural changes corresponding to each step of the preparation method of the third embodiment of the present invention, including step S2.

[0009] The attached figures are labeled as follows: 10-Crystal silicon substrate; 11-First conductive region; 12-Second conductive region; 13-Electrically isolated region; 131-First isolation region; 132-Second isolation region; 20-First carrier collection layer; 21-First passivation layer; 22-Doped polycrystalline silicon layer; 30-Second carrier collection layer; 31-Second passivation layer; 32-Doped silicon-containing film layer; 40-Conductive transition layer; 41-Silicon oxide layer; 42-Metal layer; 50-Transparent conductive film layer; 61-First electrode; 62-Second electrode; 80-Passivation and antireflection layer; 81-Front-side passivation layer; 82-Antireflection layer. Detailed Implementation

[0010] The back-contact heterojunction solar cell involved in the embodiments of the present invention refers to a crystalline silicon solar cell obtained by combining a passivated contact structure with heterojunction technology.

[0011] Existing back-contact heterojunction solar cells have an n-type conductive region and a p-type conductive region on the back side. The n-type conductive region typically features a stacked tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer, while the p-type conductive region typically features an intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer. Metal electrodes are generally fabricated by combining a transparent conductive film layer with a metal electrode, replacing sintered metal paste. However, this structure presents several challenges. Firstly, the transparent conductive film layer is typically a doped oxide layer (such as indium tin oxide or fluorine-doped tin oxide). This structural difference between the transparent conductive film layer and the phosphorus-doped polycrystalline silicon layer, and between the transparent conductive film layer and the boron-doped amorphous silicon layer, leads to structural mismatch and distortion at the interfaces between the transparent conductive film layer and the phosphorus-doped polycrystalline silicon layer, as well as between the transparent conductive film layer and the boron-doped amorphous silicon layer. This results in interface defects, making interfacial carrier recombination more likely and leading to lower carrier transport efficiency. On the other hand, the work function of the n-type transparent conductive film layer (such as indium tin oxide or fluorine-doped tin oxide) commonly used in back-contact heterojunction solar cells is generally around 4.5 eV. In the ~4.9eV range, the work function of boron-doped amorphous silicon layers is generally in the range of 4.3eV to 4.5eV, while that of phosphorus-doped polycrystalline silicon layers is generally in the range of 4.05eV to 4.15eV. The smaller the work function difference between the transparent conductive film layer and the phosphorus-doped polycrystalline silicon layer, and between the transparent conductive film layer and the boron-doped polycrystalline silicon layer, the more beneficial it is to reduce interfacial carrier recombination between the transparent conductive film layer and the boron-doped polycrystalline silicon layer, and between the transparent conductive film layer and the phosphorus-doped polycrystalline silicon layer. However, the work function differences between the n-type transparent conductive film layer and the boron-doped amorphous silicon layer, and between the transparent conductive film layer and the phosphorus-doped polycrystalline silicon layer, which are commonly used in back-contact heterojunction solar cells, are relatively large. In particular, the work function difference between the phosphorus-doped polycrystalline silicon layer and the n-type transparent conductive film layer is even larger. Therefore, there is still room for improvement in existing back-contact heterojunction solar cells.

[0012] In existing technologies, although different transparent conductive film layers can be set for the n-type and p-type conductive regions respectively, this existing technique of setting differentiated transparent conductive film layers leads to a more complex process, is prone to damaging the film layers of the n-type and p-type conductive regions, increases defects in back-contact heterojunction solar cells, and easily causes carrier recombination, resulting in lower fill factor and photoelectric conversion efficiency of back-contact heterojunction solar cells.

[0013] In addition, in the prior art, in order to overcome the problem of relatively complex process caused by setting differentiated transparent conductive film layers, transparent conductive film layers with relatively compromise work functions are selected for back contact heterojunction solar cells. That is, the work function of the selected transparent conductive film layer is greater than that of the phosphorus-doped polycrystalline silicon layer and less than that of the boron-doped amorphous silicon layer, so as to balance the difference between the work function of the transparent conductive film layer and the work functions of the phosphorus-doped polycrystalline silicon layer and the boron-doped amorphous silicon layer. This not only further narrows the range of materials that can be used for transparent conductive film layers, but also does not achieve a better match between the transparent conductive film layer and the phosphorus-doped polycrystalline silicon layer and the boron-doped amorphous silicon layer.

[0014] To address the aforementioned problems with existing back-contact heterojunction solar cells and their fabrication processes, this invention provides a novel back-contact heterojunction solar cell structure and a novel fabrication method for this novel structure. The novel back-contact heterojunction solar cell structure and its fabrication method provided by this invention involve adding a conductive transition layer 40 comprising a silicon oxide layer 41 and a discontinuous metal layer 42. The conductive transition layer 40 serves as a bridge between the first carrier collection layer 20 and the transparent conductive film layer 50, and / or as a bridge between the second carrier collection layer 30 and the transparent conductive film layer 50. The silicon oxide layer 41 enables the conductive transition layer 40 to form a better interface match with the first carrier collection layer 20 and / or the second carrier collection layer 30, thereby reducing interface defects and thus reducing interfacial carrier recombination, thereby improving carrier transport efficiency. In addition, the discontinuous metal layer 42 has a strong bandgap control capability, and its contact with the transparent conductive film layer 50 can achieve a lower interfacial contact resistance. Furthermore, the discontinuous metal layer 42 enables carriers to transport along the thickness direction, reducing or even avoiding lateral carrier transport, thereby further improving carrier transport efficiency and thus increasing the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0015] It should be noted that the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0016] In the embodiments of the present invention, the back side of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 that faces away from sunlight during the operation of the solar cell. The front side of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 that faces sunlight during the operation of the solar cell.

[0017] In the embodiments of this invention, "from the inside out" generally refers to the crystalline silicon substrate 10 as a reference. In the thickness direction of the back-contact heterojunction solar cell, the direction from the position closest to the crystalline silicon substrate 10 to the position furthest away from the crystalline silicon substrate 10 is "from the inside out". Correspondingly, the inner and outer sides of a film layer are also based on the crystalline silicon substrate 10. The side of the film layer closest to the crystalline silicon substrate 10 is the inner side of the film layer, and the side of the film layer furthest from the crystalline silicon substrate 10 is the outer side of the film layer.

[0018] Unless otherwise contradictory, the doping concentration of a film layer in the embodiments of the present invention generally refers to the average number of activated doped atoms contained in a unit volume of the film layer.

[0019] The work function of a film layer involved in the embodiments of the present invention generally refers to the minimum energy required to move an electron at the Fermi level from inside the film layer to outside the film layer under the conditions of absolute zero, thermal equilibrium, and no external field inside the film layer, and the unit is eV.

[0020] The conductivity types involved in the embodiments of this invention are generally divided into n-type conductivity types and p-type conductivity types, where n-type and p-type are two opposite conductivity types. Specifically, n-type conductivity films are generally doped with n-type dopant atoms (such as phosphorus atoms or arsenic atoms), while p-type conductivity films are generally doped with p-type dopant atoms (such as boron atoms or gallium atoms).

[0021] Unless otherwise specified, the discontinuous metal layer 42 in this embodiment of the invention generally refers to metal particles composed of metal atoms randomly distributed within or on the main surface of the silicon oxide layer 41, with at least some of these randomly distributed metal particles having physical spacing between them. Before the transparent conductive film layer 50 is applied, this physical spacing electrically isolates the metal particles, thereby reducing or even preventing the lateral transport of charge carriers in the metal layer 42. Unless otherwise specified, this lateral transport generally refers to the transport of charge carriers along the main surface of the metal layer 42 (which is parallel to the main surface of the first charge carrier collection layer 20 or the second charge carrier collection layer 30). Furthermore, longitudinal transport generally refers to the transport of charge carriers along the thickness direction of each film layer (such as the first charge carrier collection layer 20, the second charge carrier collection layer 30, the silicon oxide layer 41, the metal layer 42, and the transparent conductive film layer 50).

[0022] Specifically, embodiments of the present invention provide a novel back-contact heterojunction solar cell structure. More specifically, as... Figures 1 to 3As shown, the back-contact heterojunction solar cell may include: a crystalline silicon substrate 10, a first carrier collection layer 20, a second carrier collection layer 30, a conductive transition layer 40 including a silicon oxide layer 41 and a discontinuous metal layer 42, and a transparent conductive film layer 50.

[0023] More specifically, such as Figures 1 to 3 As shown, the back surface of the crystalline silicon substrate 10 includes alternating first conductive regions 11 and second conductive regions 12; a first carrier collection layer 20 is disposed in the first conductive region 11, and the first carrier collection layer 20 has the same conductivity type as the crystalline silicon substrate 10; a second carrier collection layer 30 is disposed in the second conductive region 12, and the second carrier collection layer 30 has the opposite conductivity type to the crystalline silicon substrate 10; a conductive transition layer 40 is disposed outside the first carrier collection layer 20 and / or outside the second carrier collection layer 30, wherein the conductive transition layer 40 includes a silicon oxide layer 41 and a discontinuous metal layer 42; a transparent conductive film layer 50 is disposed on the side of the conductive transition layer 40 away from the crystalline silicon substrate 10 and is in contact with the conductive transition layer 40.

[0024] Understandably, the back side of the crystalline silicon substrate 10 does not inherently possess alternating sections of first conductive regions 11 and second conductive regions 12. Instead, these sections are formed after the formation of the first carrier collection layer 20 and the second carrier collection layer 30 on the back side of the crystalline silicon substrate 10, resulting in different conductive regions on the back side of the crystalline silicon substrate 10. Furthermore, adjacent first conductive regions 11 and second conductive regions 12 are electrically isolated from each other. In other words, the first carrier collection layer 20 and the second carrier collection layer 30 on the first conductive region 11 are electrically isolated from each other, which reduces the risk of internal short circuits in the back-contact heterojunction solar cell.

[0025] It should be noted that the back surface of the crystalline silicon substrate 10 of the back-contact heterojunction solar cell provided in any of the above embodiments may have a textured surface in a portion, such as... Figure 3 The second conductive region 12 and the second isolation region 132 shown have a textured surface, while the first conductive region 11 and the second isolation region 131 have polished surfaces. Alternatively, the entire back surface of the crystalline silicon substrate 10 can also be polished, such as... Figure 1 and Figure 2 As shown. The front side of the crystalline silicon substrate 10 can be a textured surface or a polished surface. Preferably, the front side of the crystalline silicon substrate 10 can be a textured surface.

[0026] As can be seen from the above, the embodiments of the present invention provide multiple structures for back-contact heterojunction solar cells. The common structure of these multiple back-contact heterojunction solar cells includes: a crystalline silicon substrate 10, a first carrier collection layer 20, a second carrier collection layer 30, a conductive transition layer 40, and a transparent conductive film layer 50. The conductive transition layer 40 includes a silicon oxide layer 41 and a discontinuous metal layer 42. The back side of the crystalline silicon substrate 10 includes alternating first conductive regions 11 and second conductive regions 12. The first carrier collection layer 20 is disposed in the first conductive region 11, and its conductivity type is the same as that of the crystalline silicon substrate 10. The second carrier collection layer 30 is disposed in the second conductive region 12, and its conductivity type is opposite to that of the crystalline silicon substrate 10. The transparent conductive film layer 50 is disposed on the side of the conductive transition layer 40 away from the crystalline silicon substrate 10 and is in contact with the conductive transition layer 40.

[0027] In this embodiment of the invention, for the conductive transition layer 40, the relative relationship between the discontinuous metal layer 42 and the silicon oxide layer 41 can be that the discontinuous metal layer 42 is located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10. Alternatively, the discontinuous metal layer 42 can be embedded within the silicon oxide layer 41.

[0028] Specifically, the discontinuous metal layer 42 located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10 means that the discontinuous metal layer 42 is formed on the surface of the silicon oxide layer 41 on the side away from the crystalline silicon substrate 10, that is, the discontinuous metal layer 42 is in direct contact with the surface of the silicon oxide layer 41 on the side away from the crystalline silicon substrate 10.

[0029] The discontinuous metal layer 42 embedded within the silicon oxide layer 41 means that the metal particles included in the metal layer 42 are partially embedded within the silicon oxide layer 41. It should be noted that, regarding the structure of the discontinuous metal layer 42 embedded within the silicon oxide layer 41, Figure 5 and Figure 6 The diagram shows a silicon oxide layer 41 formed on a polished surface and a discontinuous metal layer 42 embedded within the silicon oxide layer 41. Figure 7 In addition to the silicon oxide layer 41 formed on the textured surface and the discontinuous metal layer 42 embedded within the silicon oxide layer 41, such as Figures 5 to 7 As shown, the discontinuous metal layer 42 is partially exposed on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10, so as to ensure that the metal layer 42 is in contact with the transparent conductive film layer 50, thereby ensuring the longitudinal transport of charge carriers and avoiding the loss of charge carriers caused by the lateral transport of charge carriers.

[0030] Furthermore, regarding the case where the discontinuous metal layer 42 is embedded within the silicon oxide layer 41, based on the fact that the discontinuous metal layer 42 is partially exposed on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10, it can be as follows: Figure 5 and Figure 7 As shown, the discontinuous metal layer 42 not exposed on the side of the silicon oxide layer 41 near the crystalline silicon substrate 10 can also be as follows: Figure 6 As shown, a discontinuous metal layer 42 is also exposed on the side of the silicon oxide layer 41 near the crystalline silicon substrate 10. Whether the metal particles of the discontinuous metal layer 42 embedded in the silicon oxide layer 41 are exposed on one side or both sides of the main surface of the silicon oxide layer 41 is mainly determined by process control. The specific process control will be described in detail in the subsequent preparation method, and will not be repeated here.

[0031] For the structure where the discontinuous metal layer 42 is located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10, Figure 8 The diagram shows a silicon oxide layer 41 formed on a polished surface and a discontinuous metal layer 42 located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10. Figure 9 The diagram shows a textured silicon oxide layer 41 formed on the textured surface and a discontinuous metal layer 42 located on the side of the textured silicon oxide layer 41 away from the crystalline silicon substrate 10. The discontinuous metal layer 42 is in contact with the transparent conductive film layer 50, thereby ensuring longitudinal transmission.

[0032] It should be noted that the discontinuous metal layer 42 is mainly composed of metal particles. Specifically, the discontinuous metal layer 42 is essentially composed of a large number of randomly distributed conductive units formed by stacking metal particles. The metal particles within the conductive units are interconnected and conductive to achieve longitudinal transport of charge carriers. Physical spacing exists between the randomly distributed conductive units. Due to the existence of this physical spacing, the metal particles between the conductive units are electrically isolated, and the physical particles between the conductive units are electrically isolated, which can avoid charge carrier loss caused by lateral transport of charge carriers.

[0033] It is worth noting that, Figures 5 to 9This illustration merely demonstrates the random distribution of metal particles within the discontinuous metal layer 42. The random distribution of metal particles within the discontinuous metal layer 42 can also be other distribution structures. The random distribution primarily means that the positions and sizes of the conductive units formed by the particle stacking are random, as long as there is a physical spacing between the conductive units formed by the metal particle stacking within the discontinuous metal layer 42. This physical spacing provides electrical isolation between the conductive units (essentially electrical isolation between metal particles of different conductive units). The discontinuous metal layer 42 prevents lateral transport of charge carriers between the charge carrier collection layers (first charge carrier collection layer 20 and / or second charge carrier collection layer 30) and the transparent conductive film layer 50, thus preventing lateral transport of charge carriers within the metal layer 42 and reducing lateral transport losses.

[0034] As can be seen from the above, the main structural differences in the various back-contact heterojunction solar cells provided in the embodiments of the present invention lie in the placement of the conductive transition layer 40 and the relative positional relationship between the silicon oxide layer 41 and the discontinuous metal layer 42 included in the conductive transition layer 40. Figure 1 A cross-sectional structural schematic diagram of the location of the conductive transition layer 40 in the first structure is shown as an example. Figure 2 A cross-sectional structural schematic diagram of the location of the conductive transition layer 40 in the third structure is shown as an example. Figure 3 A cross-sectional structural schematic diagram of the location of the conductive transition layer 40 in the fifth structure is shown as an example. Figure 4 A cross-sectional schematic diagram of the deformed structure with the placement position of the conductive transition layer 40 based on the fifth or sixth structure is shown. Figures 5 to 7 A cross-sectional view of a discontinuous metal layer 42 embedded within a silicon oxide layer 41 is shown as an example. Figure 8 and Figure 9 An exemplary cross-sectional view is shown of a discontinuous metal layer 42 located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10.

[0035] Specifically, in a first structure of a back-contact heterojunction solar cell provided in one embodiment of the present invention, in addition to the above-mentioned common structure, such as... Figure 1 As shown, the conductive transition layer 40 of the back contact heterojunction solar cell is disposed on the outside of the first carrier collection layer 20, but not on the outside of the second carrier collection layer 30, and the discontinuous metal layer 42 of the conductive transition layer 40 is embedded in the silicon oxide layer 41.

[0036] In a second structure of a back-contact heterojunction solar cell provided in one embodiment of the present invention, in addition to the common structure described above, the conductive transition layer 40 of the back-contact heterojunction solar cell is disposed in the same position as the first structure, that is, the conductive transition layer 40 is disposed outside the first carrier collection layer 20 and not outside the second carrier collection layer 30. However, the discontinuous metal layer 42 included in the conductive transition layer 40 is located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10.

[0037] In other words, the first and second structures described above improve the carrier transport efficiency of the first conductive region 11 by cooperating with the first carrier collection layer 20, the conductive transition layer 40 and the transparent conductive film layer 50, and by cooperating with the discontinuous metal layer 42 embedded in the silicon oxide layer 41 or the discontinuous metal layer 42 located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10. This effectively improves the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0038] In a third structure of a back-contact heterojunction solar cell provided in one embodiment of the present invention, in addition to the common structure described above, such as... Figure 2 As shown, the conductive transition layer 40 of the back contact heterojunction solar cell is positioned differently from both the first and second structures. Specifically, the conductive transition layer 40 is disposed outside the second carrier collection layer 30, but not outside the first carrier collection layer 20. However, the relative positional relationship between the discontinuous metal layer 42 and the silicon oxide layer 41 of the conductive transition layer 40 is the same as that of the first structure, i.e., the discontinuous metal layer 42 of the conductive transition layer 40 is embedded within the silicon oxide layer 41.

[0039] In a fourth structure of a back-contact heterojunction solar cell provided in one embodiment of the present invention, in addition to the common structure described above, the conductive transition layer 40 of the back-contact heterojunction solar cell is disposed in the same position as in the third structure, that is, the conductive transition layer 40 is disposed outside the second carrier collection layer 30 and not outside the first carrier collection layer 20. However, the relative positional relationship between the discontinuous metal layer 42 and the silicon oxide layer 41 included in the conductive transition layer 40 is the same as in the second structure, that is, the discontinuous metal layer 42 included in the conductive transition layer 40 is located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10.

[0040] In other words, the third and fourth structures described above improve the carrier transport efficiency of the second conductive region 12 by cooperating with the second carrier collection layer 30, the conductive transition layer 40 and the transparent conductive film layer 50, and by cooperating with the discontinuous metal layer 42 embedded in the silicon oxide layer 41 or the discontinuous metal layer 42 located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10. This effectively improves the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0041] In a fifth structure of a back-contact heterojunction solar cell provided in one embodiment of the present invention, in addition to the common structure described above, such as... Figure 3 As shown, the conductive transition layer 40 of the back contact heterojunction solar cell is positioned differently from the four structures mentioned above. Specifically, the conductive transition layer 40 is disposed outside the second carrier collection layer 30 and outside the first carrier collection layer 20. However, the relative positional relationship between the discontinuous metal layer 42 and the silicon oxide layer 41 included in the conductive transition layer 40 is the same as that in the first and third structures. That is, the discontinuous metal layer 42 included in the conductive transition layer 40 is embedded in the silicon oxide layer 41.

[0042] In a sixth structure of a back-contact heterojunction solar cell provided in one embodiment of the present invention, in addition to the common structure described above, the conductive transition layer 40 of the back-contact heterojunction solar cell is disposed in the same position as the fifth structure described above, that is, the conductive transition layer 40 is disposed outside the second carrier collection layer 30 and outside the first carrier collection layer 20. However, the relative positional relationship between the discontinuous metal layer 42 and the silicon oxide layer 41 included in the conductive transition layer 40 is the same as that in the second and fourth structures, that is, the discontinuous metal layer 42 included in the conductive transition layer 40 is located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10.

[0043] In other words, the fifth and sixth structures described above, through the cooperation between the first carrier collection layer 20, the conductive transition layer 40, and the transparent conductive film layer 50, and the cooperation between the second carrier collection layer 30, the conductive transition layer 40, and the transparent conductive film layer 50, and in cooperation with the discontinuous metal layer 42 embedded in the silicon oxide layer 41 or the discontinuous metal layer 42 located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10, simultaneously improve the carrier transport efficiency of the first conductive region 11 and the second conductive region 12, thereby effectively improving the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0044] It is worth noting that, for the fifth and sixth structures, in addition to being disposed on the outside of the second carrier collection layer 30 and the outside of the first carrier collection layer 20, the conductive transition layer 40 can also be disposed on the electrical isolation region 13. More specifically, the conductive transition layer 40 disposed on the electrical isolation region 13, the conductive transition layer 40 disposed on the outside of the second carrier collection layer 30, and the conductive transition layer 40 disposed on the outside of the first carrier collection layer 20 are integral structures.

[0045] Furthermore, based on the fifth and sixth structures mentioned above, a modified structure can be obtained for the placement position of the conductive transition layer 40, such as... Figure 4 As shown, the conductive transition layer 40 is only disposed on the outside of the second carrier collection layer 30 and the outside of the first carrier collection layer 20, while the electrically isolated region 13 is not provided with the conductive transition layer 40.

[0046] As can be seen from the above, compared with the first, second, third and fourth structures of the back contact heterojunction solar cell, the fifth and sixth structures, as well as the modified structures based on the fifth and sixth structures, can better improve the carrier transport efficiency of the first conductive region 11 and the second conductive region 12, and can also significantly improve the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0047] Understandably, compared to the transparent conductive film layer 50, the silicon oxide layer 41 included in the conductive transition layer 40 is better matched with the interface of the first carrier collection layer 20 and the second carrier collection layer 30, reducing interface defects and interface stress, thereby reducing the risk of the conductive transition layer 40 detaching. Furthermore, the discontinuous metal layer 42, in conjunction with the transparent conductive film layer 50, provides a better structural match between the transparent conductive film layer 50 and the metal layer 42 compared to the first carrier collection layer 20 and the second carrier collection layer 30. This reduces the risk of the transparent conductive film layer 50 detaching, making the back-contact heterojunction solar cell structure more stable and more reliable.

[0048] In summary, the various novel back-contact heterojunction solar cells provided in the embodiments of the present invention achieve this by providing a conductive transition layer 40, comprising a silicon oxide layer 41 and a discontinuous metal layer 42, on the outer side of the first carrier collection layer 20 and / or the outer side of the second carrier collection layer 30, and providing a transparent conductive film layer 50 on the outer side of the conductive transition layer 40. This is achieved through the combination of the first carrier collection layer 20, the conductive transition layer 40 comprising the silicon oxide layer 41 and the discontinuous metal layer 42, and the transparent conductive film layer 50, and / or the second carrier collection layer 30 comprising the silicon oxide layer 41 and the discontinuous metal layer 42. The conductive transition layer 40 and the transparent conductive film layer 50 work together, and the silicon oxide layer 41 and the discontinuous metal layer 42 work together to ensure that the inner interface of the conductive transition layer 40 can form a better match with the first carrier collection layer 20 and / or the second carrier collection layer 30 on its inner side, while the outer interface of the conductive transition layer 40 forms a better match with the transparent conductive film layer 50. This can effectively reduce the interface barrier and interface contact resistance, which is beneficial to improving the carrier collection efficiency of the first conductive region 11 and / or the second conductive region 12, thereby effectively improving the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0049] In addition, while ensuring the longitudinal transport of charge carriers, the discontinuous metal layer 42 allows light to pass through the gaps between the conductive units formed by the metal particles stacked in the metal layer 42. This ensures the light transmittance of the metal layer 42 and reduces the light absorption of the metal layer 42, thereby ensuring the light utilization rate of the back contact heterojunction solar cell.

[0050] In one embodiment of the present invention, for the back-contact heterojunction solar cells of the first and second structures described above, i.e. Figure 1 As shown, when the conductive transition layer 40 is disposed outside the first carrier collection layer 20, the transparent conductive film layer 50 is also disposed outside the second carrier collection layer 30. The transparent conductive film layer 50 disposed outside the second carrier collection layer 30 is disconnected from the transparent conductive film layer 50 disposed outside the conductive transition layer 40 between the first conductive region 11 and the second conductive region 12, so as to ensure that the second conductive region 12 collects and transports carriers.

[0051] In one embodiment of the present invention, for the back-contact heterojunction solar cells of the third and fourth structures described above, i.e. Figure 2 As shown, when the conductive transition layer 40 is disposed outside the second carrier collection layer 30, the transparent conductive film layer 50 is also disposed outside the first carrier collection layer 20, and the transparent conductive film layer 50 disposed outside the first carrier collection layer 20 is disconnected from the transparent conductive film layer 50 disposed outside the conductive transition layer 40 between the first conductive region 11 and the second conductive region 12.

[0052] Understandably, such as Figure 3 As shown, when the conductive transition layer 40 is simultaneously disposed outside the first carrier collection layer 20 and outside the second carrier collection layer 30, the transparent conductive film layer 50 is disposed outside the conductive transition layer 40 corresponding to the first conductive region 11 and outside the conductive transition layer 40 corresponding to the second conductive region 12, and the transparent conductive film layer 50 disposed outside the conductive transition layer 40 of the first conductive region 11 and the transparent conductive film layer 50 disposed outside the conductive transition layer 40 of the second conductive region 12 are disconnected between the first conductive region 11 and the second conductive region 12.

[0053] Based on the structure provided by the back contact heterojunction solar cell in any of the above embodiments, in a preferred embodiment, the silicon oxide layer 41 is a continuous or discontinuous structure formed on the outer surface of the first carrier collection layer 20 and / or the outer surface of the second carrier collection layer 30.

[0054] It should be noted that, for the continuous silicon oxide layer 41, silicon oxide belonging to the silicon oxide layer 41 is essentially uniformly distributed at various positions on the outer surface of the first carrier collection layer 20 and / or the outer surface of the second carrier collection layer 30. This continuous silicon oxide layer 41 can be coupled with a discontinuous metal layer 42 that is not exposed on the side of the silicon oxide layer 41 near the crystalline silicon substrate 10, or it can be coupled with a discontinuous metal layer 42 located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10.

[0055] For the discontinuous silicon oxide layer 41, it is generally paired with a discontinuous metal layer 42 containing metal particles exposed on the side of the silicon oxide layer 41 near the crystalline silicon substrate 10. This discontinuous silicon oxide layer 41 is essentially formed because a portion of the outer surface of the first carrier collection layer 20 and / or the outer surface of the second carrier collection layer 30 is occupied by some of the metal particles included in the metal layer 42, making the silicon oxide layer 41 a discontinuous structure. It should be noted that in the areas of the outer surface of the first carrier collection layer 20 and / or the outer surface of the second carrier collection layer 30 that are not occupied by the metal particles included in the metal layer 42, the silicon oxide in the silicon oxide layer 41 is still uniformly distributed. In other words, the discontinuous silicon oxide layer 41 can be regarded as a complete film layer formed by the oxide layer uniformly distributed on the outer surface of the first carrier collection layer 20 and / or the outer surface of the second carrier collection layer 30. Due to the partial occupation of some positions by some metal particles included in the metal layer 42, the complete film layer has independent pores (i.e., the positions occupied by the metal particles included in the metal layer 42). These independent pores make the silicon oxide layer 41 a discontinuous structure. It should be noted that the silicon oxide layers 41 in the regions not occupied by the metal particles included in the metal layer 42 are interconnected.

[0056] Understandably, based on the first and second structures described above, preferably, the silicon oxide layer 41 is a continuous or discontinuous structure formed on the outer surface of the first carrier collection layer 20. Based on the third and fourth structures described above, preferably, the silicon oxide layer 41 is a continuous or discontinuous structure formed on the outer surface of the second carrier collection layer 30. Based on the fifth and sixth structures described above, preferably, the silicon oxide layer 41 is a continuous or discontinuous structure formed on the outer surfaces of the first and second carrier collection layers 20 and 30. By setting the silicon oxide layer 41 to a continuous or discontinuous structure, while ensuring passivation of the outer surfaces of the first and / or second carrier collection layers 20 and 30, the work function of the conductive transition layer 40 (which cooperates with the discontinuous metal layer 42) and the transparent conductive film layer 50 are kept relatively small, thereby further improving carrier transport efficiency.

[0057] Based on the structure provided by the back contact heterojunction solar cell in any of the above embodiments, in a more preferred embodiment, the silicon oxide layer 41 includes amorphous silicon oxide to ensure electrical isolation between metal particles with physical spacing in the discontinuous metal layer 42, thereby ensuring the longitudinal transport of charge carriers in the conductive transition layer 40.

[0058] Furthermore, the silicon oxide layer 41 also includes doped atoms. Specifically, when the silicon oxide layer 41 is formed on the outer surface of the first carrier collection layer 20, the doping type of the doped atoms in the silicon oxide layer 41 is the same as the doping type of the first carrier collection layer 20; when the silicon oxide layer 41 is formed on the outer surface of the second carrier collection layer 30, the doping type of the doped atoms in the silicon oxide layer 41 is the same as the doping type of the second carrier collection layer 30, to further improve the interface matching between the silicon oxide layer 41 and the first carrier collection layer 20 and / or the second carrier collection layer 30. More specifically, the silicon oxide layer 41 is formed by bonding oxygen atoms with silicon atoms on the surface of the first carrier collection layer 20 and / or the second carrier collection layer 30, further ensuring the structural matching between the silicon oxide layer 41 and the first carrier collection layer 20 and / or the second carrier collection layer 30.

[0059] The thickness of the silicon oxide layer 41 is 0.1 nm to 2 nm. For example, the thickness of the silicon oxide layer 41 can be 0.1 nm, 0.2 nm, 0.5 nm, 0.8 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm or 2 nm. By controlling the thickness of the silicon oxide layer 41, the interface matching between the silicon oxide layer 41 and the first carrier collection layer 20 and / or the second carrier collection layer 30 can be ensured. At the same time, it can ensure that the carriers can tunnel through the silicon oxide layer 41, and ensure the uniformity of the silicon oxide layer 41 and the formation of a discontinuous metal layer 42 on the silicon oxide layer 41.

[0060] In one embodiment of the present invention, the metal layer 42 comprises an elemental metal or a mixture of an elemental metal and a metal oxide, to ensure the conductivity of the metal layer 42 and its compatibility with the transparent conductive film layer 50. That is, the metal layer 42 may comprise metal particles formed from an elemental metal, metal particles formed from a mixture of an elemental metal and a metal oxide, or a mixture of metal particles formed from an elemental metal and metal oxides.

[0061] In an optional embodiment, the metal layer 42 includes at least one of the following metals: Ni, Al, Cu, Ti and Ag. By selecting one or more of these metals, the conductivity of the metal layer 42 can be guaranteed while forming a better match with the transparent conductive film layer 50.

[0062] In an optional embodiment, the metal layer 42 comprises a metallic element and a metal oxide. The metallic element can be one or more of Ni, Al, Cu, Ti, and Ag, and the metal oxide includes at least one of the following: nickel oxide, aluminum oxide, copper oxide, titanium oxide, and silver oxide. The inclusion of a metallic element and a metal oxide in the metal layer 42 ensures the conductivity of the conductive transition layer 40 formed by the metal layer 42 and the silicon oxide layer 41, while also reducing the work function difference between the metal layer 42 and the transparent conductive film layer 50. This improves the interface matching between the conductive transition layer 40 and the transparent conductive film layer 50, ensuring longitudinal carrier transport.

[0063] In an optional embodiment, the thickness of the metal layer 42 is greater than or equal to 0.01 nm and less than or equal to 0.5 nm. The thickness of the metal layer 42 can be 0.01 nm, 0.05 nm, 0.10 nm, 0.15 nm, 0.20 nm, 0.3 nm, 0.35 nm, 0.4 nm, 0.45 nm, or 0.5 nm, etc. By controlling the thickness of the metal layer 42, the discontinuity of the metal layer 42 can be ensured, and a reliable and stable electrical connection can be formed between the metal layer 42 and the transparent conductive film layer 50.

[0064] like Figures 1 to 3 As shown, the back-contact heterojunction solar cell provided in any of the above embodiments includes a first carrier collection layer 20 comprising a first passivation layer 21 and a doped polycrystalline silicon layer 22 stacked from the inside out. The second carrier collection layer 30 comprises a second passivation layer 31 and a doped silicon-containing film layer 32 stacked from the inside out, wherein the conductivity type of the doped polycrystalline silicon layer 22 is opposite to that of the doped silicon-containing film layer 32. The first passivation layer 21 can be a silicon oxide layer or a silicon nitride layer. The thickness of the first passivation layer 21 can be 0.5 nm to 3 nm, for example, 0.5 nm, 0.8 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm, to ensure that carriers can tunnel through the first passivation layer 21.

[0065] In an optional embodiment, the doped silicon-containing film 32 may include silicon particles with a particle size of 1 nm to 100 nm, and may further include one or more of amorphous silicon, silicon oxide, and silicon carbide. By including silicon particles with a particle size of 1 nm to 100 nm in the doped silicon-containing film 32, the conductivity of the doped silicon-containing film 32 can be improved, thereby improving carrier transport efficiency. For example, the particle size of the silicon particles included in the doped silicon-containing film 32 may be 1 nm, 5 nm, 10 nm, 20 nm, 40 nm, 50 nm, 70 nm, 90 nm, or 100 nm, etc. Furthermore, the thickness of the doped silicon-containing film 32 can be from 1 nm to 50 nm. For example, the thickness of the doped silicon-containing film 32 can be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 30 nm, 40 nm, or 50 nm. By controlling the thickness of the doped silicon-containing film 32, it can be ensured that the doped silicon-containing film 32 is relatively uniform, thereby avoiding contact between the conductive transition layer 40 and the second passivation layer 31. Understandably, if the particle size of the silicon particles included in the doped silicon-containing film 32 is greater than the thickness of the doped silicon-containing film 32, it will cause a highly uneven surface to appear on the doped silicon-containing film 32. In a preferred embodiment, the particle size of the silicon particles included in the doped silicon-containing film 32 is not greater than the thickness of the doped silicon-containing film 32, so as to ensure the flatness of the surface of the doped silicon-containing film 32.

[0066] In any embodiment of the present invention, the back contact solar cell includes a transparent conductive film layer 50 that may include a metal oxide or a nitride and doping atoms. The doping atoms in the transparent conductive film layer 50 may include one or more of indium, tin, calcium, aluminum, cadmium, zinc, cerium and fluorine. The metal oxide in the transparent conductive film layer 50 may include one or more of indium oxide, tin oxide, zinc oxide and cadmium oxide. The nitride in the transparent conductive film layer 50 may be titanium nitride.

[0067] In one embodiment of the present invention, such as Figures 1 to 4As shown, the back side of the crystalline silicon substrate 10 further includes an electrically isolated region 13 disposed between adjacent first conductive regions 11 and second conductive regions 12, wherein the first passivation layer 21, the doped polysilicon layer 22, the second passivation layer 31, and the doped silicon-containing film layer 32 extend to the electrically isolated region 13 and are stacked from the inside to the outside. More specifically, as shown... Figure 3 As shown, the electrical isolation region 13 includes a first isolation region 131 near the first conductive region 11 and a second isolation region 132 near the second conductive region 12; a first passivation layer 21 and a doped polysilicon layer 22 extend to the first isolation region 131; a second passivation layer 31 and a doped silicon-containing film layer 32 extend to the second isolation region 132 and the first isolation region 131, and in the first isolation region 131, the second passivation layer 31 and the doped silicon-containing film layer 32 are located outside the doped polysilicon layer 22. It can be understood that in the first isolation region 131, the first passivation layer 21, the doped polysilicon layer 22, the second passivation layer 31, and the doped silicon-containing film layer 32 are stacked from the inside to the outside.

[0068] In an optional embodiment, such as Figure 3 As shown, the conductive transition layer 40 extends into the electrically isolated region 13 and is located outside the doped silicon-containing film layer 32. In the electrically isolated region 13, since some areas do not have a transparent conductive film layer 50, even though the conductive transition layer 40 extends into the electrically isolated region 13, electrical isolation between the first conductive region 11 and the second conductive region 12 can still be guaranteed. In other words, in the structure provided by the embodiment of the present invention, the conductive transition layer 40 and the transparent conductive film layer 50 cooperate to realize the vertical transport of charge carriers. Since the discontinuous metal layer 42 of the conductive transition layer 40 on the electrically isolated region 13 can prevent the lateral transport of charge carriers on the electrically isolated region 13, short circuits can be avoided in the electrically isolated region 13.

[0069] More specifically, the width of the first conductive region 11 is 150μm to 500μm; the width of the second conductive region 12 is 150μm to 700μm; and the width of the electrically isolated region 13 is 10μm to 150μm. For example, the width of the first conductive region 11 can be 150μm, 200μm, 300μm, 400μm or 500μm, the width of the second conductive region 12 can be 150μm, 200μm, 300μm, 500μm, 600μm or 700μm, and the width of the electrically isolated region 13 can be 10μm, 20μm, 50μm, 80μm, 100μm, 120μm or 150μm. By controlling the width of the first conductive region 11 and the width of the second conductive region 12, on the one hand, it is to ensure the operability and feasibility of the process, and on the other hand, it can enable the conductive transition layer 40 and the transparent conductive film layer 50 to cooperate with the first carrier collection layer 20 and / or the second carrier collection layer 30, so that the carriers collected and transported by the first conductive region 11 and the carriers collected and transported by the second conductive region 12 are kept as balanced as possible. In addition, controlling the width of the electrical isolation region 13 ensures the reliability of electrical isolation while satisfying process operability and process feasibility.

[0070] In addition, such as Figures 1 to 3 As shown, the back-contact heterojunction solar cell provided in any of the above embodiments may further include: a passivation antireflection layer 80 disposed on the front side of the crystalline silicon substrate 10, wherein, as Figure 3 As shown, the passivation antireflection layer 80 may include a front passivation layer 81 and an antireflection layer 82 stacked from the inside out to improve the light utilization rate of the back contact heterojunction solar cell. The front passivation layer 81 may be a single layer or a stacked structure, and may include an intrinsic silicon-containing thin film or a combination of an intrinsic silicon-containing thin film and an n-type doped silicon-containing thin film. Alternatively, the front passivation layer 81 may include one or more of silicon oxide, silicon oxynitride, aluminum oxide, gallium oxide, and titanium oxide. The antireflection layer 82 may include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, indium tin oxide, and zinc oxide. The thickness of the antireflection layer 82 may be 40 nm to 200 nm, for example, 40 nm, 50 nm, 70 nm, 80 nm, 100 nm, 150 nm, or 200 nm.

[0071] Furthermore, such as Figures 1 to 3 As shown, any of the above-described back-contact heterojunction solar cells may further include: a first electrode 61 disposed on a transparent conductive film layer 50 on the outside of the first carrier collection layer 20; and a second electrode 62 disposed on a transparent conductive film layer 50 on the outside of the second carrier collection layer 30.

[0072] In an optional embodiment, the width ratio of the first conductive region 11 to the width ratio of the first electrode 61 is (1-15):1. For example, the width ratio of the first conductive region 11 to the width ratio of the first electrode 61 can be 1:1, 2:1, 3:1, 5:1, 8:1, 10:1, 12:1, or 15:1, ensuring a reliable connection between the first electrode 61 and the transparent conductive film layer 50 of the first conductive region 11, and that the cooperation between the first electrode 61 and the transparent conductive film layer 50 of the first conductive region 11 has a high efficiency in collecting and transporting charge carriers. In addition, if the width ratio of the first conductive region 11 to the width ratio of the first electrode 61 is greater than 1:1, it can allow backlight to pass through the first conductive region 11 into the crystalline silicon substrate 10, improving the bifacial light efficiency.

[0073] In an optional embodiment, the width ratio of the second conductive region 12 to the width ratio of the second electrode 62 is (1-30):1. For example, the width ratio of the second conductive region 12 to the second electrode 62 can be 1:1, 5:1, 10:1, 15:1, 20:1, 25:1, or 30:1, ensuring a reliable connection between the second electrode 62 and the transparent conductive film layer 50 of the second conductive region 12, and that the cooperation between the second electrode 62 and the transparent conductive film layer 50 of the second conductive region 12 has a high efficiency in collecting and transporting charge carriers. Furthermore, a width ratio of the second conductive region 12 to the second electrode 62 greater than 1:1 allows back-side light to pass through the second conductive region 12 into the crystalline silicon substrate 10, improving the bifacial light efficiency.

[0074] Furthermore, the width of the second electrode 62 is generally the same as the width of the first electrode 61, and the ratio of the width of the second conductive region 12 to the width of the second electrode 62 is greater than the ratio of the width of the first conductive region 11 to the width of the first electrode 61, so as to increase the effective area of ​​the PN junction of the back contact heterojunction solar cell, thereby improving the photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0075] Furthermore, embodiments of the present invention provide a method for fabricating a back-contact heterojunction solar cell. For example... Figure 10 As shown, the preparation method may include: Step S1: Provide a crystalline silicon substrate 10, the back side of which includes alternating first conductive regions 11 and second conductive regions 12.

[0076] The silicon substrate 10 can be either an n-type or p-type silicon substrate. The first conductive region 11 and the second conductive region 12 are different regions defined for the subsequent preparation of different film layers, so as to facilitate the precise positioning and preparation of each film layer in the subsequent steps.

[0077] Step S2: A first carrier collection layer 20 is formed in the first conductive region 11, a second carrier collection layer 30 is formed in the second conductive region 12, and a conductive transition layer 40 is formed on the outside of the first carrier collection layer 20 and / or the outside of the second carrier collection layer 30. The conductive transition layer 40 includes a silicon oxide layer 41 and a discontinuous metal layer 42. The discontinuous metal layer 42 is embedded in the silicon oxide layer 41 or the discontinuous metal layer 42 is located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10.

[0078] In this step S2, a conductive transition layer 40 may be formed on the outside of the first carrier collection layer 20, or on the outside of the second carrier collection layer 30, or the conductive transition layer 40 may be formed on the outside of both the first carrier collection layer 20 and the second carrier collection layer 30 simultaneously.

[0079] The formation of the first carrier collection layer 20 and the second carrier collection layer 30 can be achieved by deposition methods such as low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0080] Step S3: A transparent conductive film layer 50 is formed on the outside of the conductive transition layer 40, which is in contact with the conductive transition layer 40.

[0081] It should be noted that step S3 can simultaneously form a transparent conductive film layer 50 in the first conductive region 11 and the second conductive region 12. More specifically, step S3 can simultaneously form a full-layer transparent conductive film layer 50 in the first conductive region 11, the second conductive region 12, and the electrically isolated region 13. Then, a portion of the transparent conductive film layer 50 in the electrically isolated region 13 is removed by laser etching or mask chemical etching, i.e., the transparent conductive film layer 50 is cut in the electrically isolated region 13 to prevent short circuits in the electrically isolated region 13. The structural change corresponding to step S3 is as follows: Figure 11 and Figure 12 As shown. It is worth noting that if a conductive transition layer 40 exists in the electrically isolated region 13, step S3 can be adjusted by changing process parameters (such as laser parameters or chemical etching solution) to remove or not remove the conductive transition layer 40 as needed. As mentioned above, since the discontinuous metal layer 42 in the conductive transition layer 40 prevents lateral transport of charge carriers, a short circuit will not occur in the electrically isolated region 13 even if the conductive transition layer 40 is not removed.

[0082] The back-contact heterojunction solar cell prepared by the method provided in this embodiment of the invention comprises a conductive transition layer 40 including a silicon oxide layer 41 and a discontinuous metal layer 42 formed on the outside of the first carrier collection layer 20 and / or the outside of the second carrier collection layer 30, and a transparent conductive film layer 50 disposed on the outside of the conductive transition layer 40. That is, the first carrier collection layer 20, the conductive transition layer 40 including the silicon oxide layer 41 and the discontinuous metal layer 42, and the transparent conductive film layer 50 are combined, and / or the second carrier collection layer 30 includes the conductive transition layer 40 including the silicon oxide layer 41 and the discontinuous metal layer 42. The layer 40 and the transparent conductive film layer 50 are combined, and the silicon oxide layer 41 and the discontinuous metal layer 42 are combined, so that the inner interface of the conductive transition layer 40 can form a better match with the first carrier collection layer 20 and / or the second carrier collection layer 30 inside it, while the outer interface of the conductive transition layer 40 forms a better match with the transparent conductive film layer 50. This can effectively reduce the interface barrier and interface contact resistance, which is beneficial to improving the carrier collection efficiency of the first conductive region 11 and / or the second conductive region 12, thereby effectively improving the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0083] Specifically, the implementation of step S2 may include: based on a metal target, performing magnetron sputtering in an oxygen-containing atmosphere to simultaneously form a silicon oxide layer 41 and a discontinuous metal layer 42. More specifically, an oxygen-containing atmosphere may be introduced for a certain period of time before the electric and magnetic fields of the magnetron sputtering equipment are turned on, so that the plasma generated by the oxygen can first form silicon oxide with silicon atoms on the surface of the first carrier collection layer 20 and / or the second carrier collection layer 30, ensuring that the formed silicon oxide layer is uniformly distributed. Subsequently, while silicon oxide is forming, metal atoms generated by the metal target are deposited on the silicon oxide layer to form randomly distributed metal particles. Since the oxide layer continues to form while the metal particles are forming, the metal particles are embedded within the silicon oxide layer. In addition, after introducing an oxygen-containing atmosphere for a certain period of time, the electric and magnetic fields of the magnetron sputtering equipment are turned on so that the plasma generated by the oxygen can first form silicon oxide with the silicon atoms on the surface of the first carrier collection layer 20 and / or the second carrier collection layer 30, and ensure that the formed silicon oxide layer is uniformly distributed. Then, the oxygen-containing atmosphere is replaced with an inert gas atmosphere, and then randomly distributed metal particles are deposited on the surface of the silicon oxide layer, so that the metal layer 42 is located on the side of the silicon oxide layer 41 away from the crystalline silicon substrate 10.

[0084] More specifically, the conditions for magnetron sputtering include: an oxygen volume content of 0.1% to 2% in the introduced atmosphere, a magnetron sputtering energy of 0.01 W / cm² to 1 W / cm², and a magnetron sputtering time of 30 s to 240 s. For example, the volume content of oxygen in the introduced atmosphere can be 0.1%, 0.5%, 1%, 1.5%, or 2%, etc., the magnetron sputtering energy can be 0.01 W / cm², 0.05 W / cm², 0.1 W / cm², 0.5 W / cm², 0.8 W / cm², or 1 W / cm², etc., and the magnetron sputtering time can be 30 s, 50 s, 60 s, 90 s, 120 s, 180 s, or 240 s, etc. By controlling the magnetron sputtering conditions, the random distribution of the formed metal layer 42 and the thickness of the silicon oxide layer 41 can be effectively controlled, so as to ensure that the formed metal layer 42 and silicon oxide layer 41 can work together to improve the fill factor and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0085] There are two specific implementation schemes for step S2 above, each resulting in a different structure.

[0086] The first implementation of step S2 may include steps S21-1 to S24-1: Step S21-1: Form a full-surface first carrier collection layer 20 on the back side of the crystalline silicon substrate 10.

[0087] In step S21-1, a first passivation layer 21 and a doped polysilicon layer 22 can be sequentially stacked. In addition, in step S21-1, a doped silicon glass layer (not shown in the figure) can also be formed on the outside of the doped polysilicon layer 22.

[0088] In addition, during the formation of the first passivation layer 21, the doped polysilicon layer 22 and the doped silicon glass layer, a first wrap-around coating corresponding to the first passivation layer 21, a second wrap-around coating corresponding to the doped polysilicon layer 22 and a third wrap-around coating corresponding to the doped silicon glass layer may be formed simultaneously on the front side of the crystalline silicon substrate 10. The first wrap-around coating, the second wrap-around coating and the third wrap-around coating can be removed before the formation of the conductive transition layer 40.

[0089] Step S22-1: Remove the first carrier collection layer 20 corresponding to the second conductive region 12.

[0090] Understandably, in this step S22-1, the doped silicon glass layer corresponding to the second conductive region 12 can also be removed simultaneously.

[0091] Specifically, the doped silicon glass layer corresponding to the second conductive region 12 can be removed first by laser etching, and then the first carrier collection layer 20 corresponding to the second conductive region 12 can be removed by alkaline solution etching. This step can also form a textured structure in the second conductive region. In addition, this step can also simultaneously remove the doped silicon glass layer and the first carrier collection layer 20 corresponding to the second isolation region 132 in the electrical isolation region 13.

[0092] Step S23-1: A second carrier collection layer 30 and a conductive transition layer 40 including a silicon oxide layer 41 and a discontinuous metal layer 42 are formed on the outside of the second conductive region 12 and the remaining first carrier collection layer 20.

[0093] Understandably, as described above, there is a doped silicon glass layer on the outside of the first carrier collection layer 20. The step of forming a second carrier collection layer 30 and a conductive transition layer 40 on the outside of the remaining first carrier collection layer 20 is essentially forming a second carrier collection layer 30 and a conductive transition layer 40 on the remaining doped silicon glass layer.

[0094] The second carrier collection layer 30 formed in this step includes a second passivation layer 31 and a doped silicon-containing film layer 32 stacked from the inside to the outside.

[0095] Step S24-1: Use laser etching to remove the conductive transition layer 40 and the second carrier collection layer 30 corresponding to the first conductive region 11.

[0096] Since there is a doped silicon glass layer on the outside of the first carrier collection layer 20, after laser etching, step S24-1 can also use HF solution cleaning to remove the doped silicon glass layer corresponding to the first conductive region 11.

[0097] Alternatively, the conductive transition layer 40 corresponding to the electrical isolation region 13 can be removed simultaneously in this step, or the conductive transition layer 40 of the electrical isolation region 13 can be retained.

[0098] One type of structural change corresponding to steps S21-1 to S24-1 above is as follows: Figure 11 As shown.

[0099] A second implementation of step S2 may include steps S21-2 to S25-2: Step S21-2: Form a full-surface first carrier collection layer 20 on the back side of the crystalline silicon substrate 10.

[0100] In step S21-2, a doped silicon glass layer can also be formed on the outside of the first carrier collection layer 20.

[0101] Step S22-2: Remove the first carrier collection layer 20 corresponding to the second conductive region 12.

[0102] In step S22-2, the doped silicon glass layer corresponding to the second conductive region 12 can also be removed.

[0103] Step S23-2: A second carrier collection layer 30 is formed on the outside of the second conductive region 12 and the remaining first carrier collection layer 20.

[0104] Since a doped silicon glass layer still exists outside the remaining first carrier collection layer 20 after step S22-2, the formation of the second carrier collection layer 30 outside the remaining first carrier collection layer 20 in step S23-2 is essentially the formation of the second carrier collection layer 30 on the doped silicon glass layer.

[0105] Steps S21-2 to S23-2 are the same as steps S21-1 to S23-1, and will not be repeated here.

[0106] Step S24-2: Use laser etching to remove the second carrier collection layer 30 corresponding to the first conductive region 11.

[0107] After step S24-2, the doped silicon glass layer corresponding to the first conductive region 11 can also be removed by cleaning with HF solution.

[0108] Step S25-2: A conductive transition layer 40, comprising a silicon oxide layer 41 and a discontinuous metal layer 42, is formed on the outside of the first carrier collection layer 20 corresponding to the first conductive region 11 and on the outside of the second carrier collection layer 30 corresponding to the second conductive region 12.

[0109] Understandably, in step S25-2, a conductive transition layer 40 comprising a silicon oxide layer 41 and a discontinuous metal layer 42 may also be formed in the electrically isolated region 13, and the conductive transition layer 40 formed in the electrically isolated region 13 does not need to be removed.

[0110] The structural changes corresponding to steps S21-2 to S25-2 above are as follows: Figure 12 As shown.

[0111] Furthermore, the preparation method provided in any of the above embodiments may further include: forming a first electrode 61 on the outside of the transparent conductive film layer 50 corresponding to the first conductive region 11, and forming a second electrode 62 on the outside of the transparent conductive film layer 50 corresponding to the second conductive region 12. The first electrode 61 and the second electrode 62 may be a stacked electrode formed by stacking one or more of the following: a silver electrode, a silver alloy electrode, a copper electrode, a copper alloy electrode, and a nickel / copper / silver multilayer electrode.

[0112] The fabrication method provided in this embodiment of the invention can utilize existing equipment, which helps reduce production costs. Compared to the first embodiment of step S2, the second embodiment of step S2 omits the process of specifically removing the conductive transition layer 40. Furthermore, steps S21-2 to S24-2 in the second embodiment of step S2 can be directly completed using existing fabrication processes, requiring only the addition of a magnetron sputtering step after step S24-2. The entire process is simple, easy to control, and easy to implement. In addition, the second embodiment of step S2 can yield back-contact heterojunction solar cells with superior performance (fill factor and photoelectric conversion efficiency), and the entire process is more stable and controllable, with lower fabrication costs and easier mass production.

[0113] The above steps are provided only to help understand the method, structure, and core ideas of this invention. Those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A back-contact heterojunction solar cell, characterized in that, include: The crystalline silicon substrate (10) has an alternating arrangement of a first conductive region (11) and a second conductive region (12) on its back side. The first carrier collection layer (20) is disposed in the first conductive region (11); A second carrier collection layer (30) is disposed in the second conductive region (12), and the second carrier collection layer (30) has the opposite conductivity type to the first carrier collection layer (20); A conductive transition layer (40) is disposed on the outside of the first carrier collection layer (20) and / or the outside of the second carrier collection layer (30), wherein the conductive transition layer (40) includes a silicon oxide layer (41) and a discontinuous metal layer (42). A transparent conductive film layer (50) is disposed on the side of the conductive transition layer (40) away from the crystalline silicon substrate (10) and is in contact with the conductive transition layer (40).

2. The back-contact heterojunction solar cell according to claim 1, characterized in that, The discontinuous metal layer (42) is embedded within the silicon oxide layer (41) or the discontinuous metal layer (42) is located on the side of the silicon oxide layer (41) away from the crystalline silicon substrate (10); Optionally, in the case where the discontinuous metal layer (42) is embedded in the silicon oxide layer (41), the discontinuous metal layer (42) is partially exposed on the side of the silicon oxide layer (41) away from the crystalline silicon substrate (10). Optionally, in the case where the discontinuous metal layer (42) is embedded in the silicon oxide layer (41), the discontinuous metal layer (42) is not exposed on the side of the silicon oxide layer (41) near the crystalline silicon substrate (10), or a portion of the discontinuous metal layer (42) is exposed on the side of the silicon oxide layer (41) near the crystalline silicon substrate (10). And / or, When the conductive transition layer (40) is disposed on the outside of the first carrier collection layer (20), the transparent conductive film layer (50) is also disposed on the outside of the second carrier collection layer (30), and the transparent conductive film layer (50) disposed on the outside of the second carrier collection layer (30) and the transparent conductive film layer (50) disposed on the outside of the conductive transition layer (40) are disconnected between the first conductive region (11) and the second conductive region (12); or, When the conductive transition layer (40) is disposed outside the second carrier collection layer (30), the transparent conductive film layer (50) is also disposed outside the first carrier collection layer (20), and the transparent conductive film layer (50) disposed outside the first carrier collection layer (20) and the transparent conductive film layer (50) disposed outside the conductive transition layer (40) are disconnected between the first conductive region (11) and the second conductive region (12).

3. The back-contact heterojunction solar cell according to claim 1 or 2, characterized in that, The silicon oxide layer (41) is a continuous or discontinuous structure formed on the outer surface of the first carrier collection layer (20) and / or the outer surface of the second carrier collection layer (30); Optionally, the silicon oxide layer (41) includes amorphous silicon oxide; Optionally, the silicon oxide layer (41) further includes doping atoms, wherein, when the silicon oxide layer (41) is formed on the outer surface of the first carrier collection layer (20), the doping type of the doping atoms included in the silicon oxide layer (41) is the same as the doping type of the first carrier collection layer (20); and when the silicon oxide layer (41) is formed on the outer surface of the second carrier collection layer (30), the doping type of the doping atoms included in the silicon oxide layer (41) is the same as the doping type of the second carrier collection layer (30). Optionally, the thickness of the silicon oxide layer (41) is 0.1 nm to 2 nm.

4. The back-contact heterojunction solar cell according to claim 3, characterized in that, The metal layer (42) comprises an elemental metal, or a mixture of an elemental metal and a metal oxide; Optionally, the metallic element is at least one of the following metals: Ni, Al, Cu, Ti, and Ag; Optionally, the metal oxide includes at least one of the following metal oxides: nickel oxide, aluminum oxide, copper oxide, titanium oxide, and silver oxide; Optionally, the thickness of the metal layer (42) is greater than or equal to 0.01 nm and less than or equal to 0.5 nm.

5. The back-contact heterojunction solar cell according to any one of claims 1-4, characterized in that, The first carrier collection layer (20) includes a first passivation layer (21) and a doped polysilicon layer (22) stacked from the inside to the outside. The second carrier collection layer (30) includes a second passivation layer (31) and a doped silicon-containing film layer (32) stacked from the inside to the outside. The conductivity type of the doped polysilicon layer (22) is opposite to that of the doped silicon-containing film layer (32). Optionally, the doped silicon-containing film (32) includes crystalline silicon particles with a particle size of 1 nm to 100 nm, and the doped silicon-containing film (32) further includes one or more of amorphous silicon, silicon oxide and silicon carbide.

6. The back-contact heterojunction solar cell according to claim 5, characterized in that, The back side of the crystalline silicon substrate (10) further includes an electrically isolated region (13) disposed between adjacent first conductive regions (11) and second conductive regions (12). The first passivation layer (21), the doped polysilicon layer (22), the second passivation layer (31) and the doped silicon-containing film layer (32) extend to the electrically isolated region (13) and are stacked from the inside to the outside; Optionally, the electrical isolation region (13) includes a first isolation region (131) near the first conductive region (11) and a second isolation region (132) near the second conductive region (12). The first passivation layer (21) and the doped polysilicon layer (22) extend to the first isolation region (131); The second passivation layer (31) and the doped silicon-containing film layer (32) extend to the second isolation region (132) and the first isolation region (131), and in the first isolation region (131), the second passivation layer (31) and the doped silicon-containing film layer (32) are located outside the doped polysilicon layer (22); Optionally, the conductive transition layer (40) extends to the electrically isolated region (13) and is located outside the doped silicon-containing film layer (32); Optionally, the width of the first conductive region (11) is 150μm~500μm; Optionally, the width of the second conductive region (12) is 150 μm to 700 μm; Optionally, the width of the electrical isolation region (13) is 10μm to 150μm.

7. The back-contact heterojunction solar cell according to claim 2, characterized in that, Also includes: The first electrode (61) is disposed on the transparent conductive film layer (50) on the outside of the first carrier collection layer (20). The second electrode (62) is disposed on the transparent conductive film layer (50) on the outside of the second carrier collection layer (30). Optionally, the width ratio of the first conductive region (11) to the width ratio of the first electrode (61) is (1-15):1; Optionally, the width ratio of the second conductive region (12) to the width ratio of the second electrode (62) is (1-30):

1.

8. A method for fabricating a back-contact heterojunction solar cell, characterized in that, include: Step S1: Provide a crystalline silicon substrate (10) with alternating first conductive regions (11) and second conductive regions (12) on the back side; Step S2: A first carrier collection layer (20) is formed in the first conductive region (11), a second carrier collection layer (30) is formed in the second conductive region (12), and a conductive transition layer (40) is formed on the outside of the first carrier collection layer (20) and / or the outside of the second carrier collection layer (30). The conductive transition layer (40) includes a silicon oxide layer (41) and a discontinuous metal layer (42). The discontinuous metal layer (42) is embedded in the silicon oxide layer (41) or the discontinuous metal layer (42) is located on the side of the silicon oxide layer (41) away from the crystalline silicon substrate (10). Step S3: A transparent conductive film layer (50) is formed on the outside of the conductive transition layer (40) and in contact with the conductive transition layer (40).

9. The preparation method according to claim 8, characterized in that, Step S2 includes: performing magnetron sputtering on a metal target in an oxygen-containing atmosphere to simultaneously form the silicon oxide layer (41) and the discontinuous metal layer (42).

10. The preparation method according to claim 8 or 9, characterized in that, Step S2 includes steps S21-1 to S24-1: Step S21-1: Form a full-surface first carrier collection layer (20) on the back side of the crystalline silicon substrate (10). Step S22-1: Remove the first carrier collection layer (20) corresponding to the second conductive region (12); Step S23-1: A second carrier collection layer (30) and a conductive transition layer (40) including a silicon oxide layer (41) and a discontinuous metal layer (42) are formed on the outside of the second conductive region (12) and the remaining first carrier collection layer (20). Step S24-1: Use laser etching to remove the conductive transition layer (40) and the second carrier collection layer (30) corresponding to the first conductive region (11). or, Step S2 includes steps S21-2 to S25-2: Step S21-2: Form a full-surface first carrier collection layer (20) on the back side of the crystalline silicon substrate (10). Step S22-2: Remove the first carrier collection layer (20) corresponding to the second conductive region (12); Step S23-2: A second carrier collection layer (30) is formed on the outside of the second conductive region (12) and the remaining first carrier collection layer (20). Step S24-2: Use laser etching to remove the second carrier collection layer (30) corresponding to the first conductive region (11); Step S25-2: A conductive transition layer (40) comprising a silicon oxide layer (41) and a discontinuous metal layer (42) is formed on the outside of the first carrier collection layer (20) corresponding to the first conductive region (11) and on the outside of the second carrier collection layer (30) corresponding to the second conductive region (12).

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