Wafer bonding method

Abstract

The application provides a wafer bonding method, by increasing the thickness of the oxide layer of the edge area of the pixel wafer and the logic wafer before bonding, and reducing the thickness difference of the edge area and the center area of the pixel wafer and the logic wafer after chemical mechanical polishing, the metal exposure of the bonded wafer is reduced, the concentration of metal ions in the etching solution is greatly reduced, and the formation of small pit defects is inhibited. In the process after bonding, by reducing the time of wet etching, the generation of small pit defects is reduced, the polishing amount of chemical mechanical polishing is increased, and the number of silicon loss defects on the surface of the bonded wafer is significantly reduced. The method controls the metal exposure from the source and optimizes the repair process in the later stage, significantly improves the yield and reliability of the hybrid bonding process, and has low process cost, good compatibility, easy to quickly introduce and popularize on the production line, and good economic efficiency and operation convenience.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a wafer bonding method. Background Technology

[0002] Unlike traditional back-illuminated (BSI) products that use oxide-oxide (OX-OX) bonding, hybrid bonding introduces direct metal-metal bonding, using metal as the primary conductive path to achieve electrical interconnection between wafers. However, this change leads to gray edges or peeling at the wafer edges, resulting in exposed metal.

[0003] In the subsequent first wet etching process, a hydrofluoric acid-nitric acid-acetic acid mixture (HNA) is often used to rapidly etch the silicon surface. Because the HNA solution is recycled during mass production, the exposed metal at the edges gradually dissolves, generating metal ions that enter the reaction tank. These metal ions catalyze and accelerate the etching process, leading to an abnormally high local etching rate and resulting in numerous small pits on the silicon surface.

[0004] Even with subsequent chemical mechanical polishing (CMP) processes, it is difficult to completely eliminate these small pits. Conventional silicon CMP has limited removal capacity, and the pit depth may exceed the removal range, leaving a large amount of residue after polishing.

[0005] The subsequent second wet etching process uses a tetramethylammonium hydroxide (TMAH) solution. TMAH solution exhibits anisotropic etching properties for silicon, with a much higher etching rate on the (100) crystal plane than on the (111) crystal plane. When the etching solution encounters a pre-existing pit, it rapidly laterally etches along the (100) crystal plane, magnifying the original pit into a visible rhomboid defect, i.e., a silicon loss defect.

[0006] Currently, the number of silicon loss defects on each wafer generally exceeds 1,000, far exceeding industry standards. These numerous defects lead to decreased bonding interface strength, increased interconnect resistance, and increased leakage current, sometimes rendering the entire wafer unusable. The industry has attempted various solutions, such as optimizing pre-bonding chemical mechanical polishing, adding metal ion complexing agents, and increasing polishing volume, but these solutions have limited effectiveness or significantly increased costs, failing to fundamentally solve the problem. Therefore, this defect has become a key technological bottleneck restricting the large-scale mass production of hybrid bonding products and urgently needs to be addressed. Summary of the Invention

[0007] The purpose of this invention is to provide a wafer bonding method to solve the problem in hybrid bonding processes where exposed copper ions at the wafer edge contaminate the etching solution, leading to an excessive number of silicon loss defects.

[0008] To address the above problems, the present invention provides a wafer bonding method, comprising:

[0009] A device wafer and a carrier wafer are provided, wherein a first metal interconnect structure is formed on the device wafer and a second metal interconnect structure is formed on the carrier wafer;

[0010] A first bonding oxide layer and a second bonding oxide layer are formed. The first bonding oxide layer is located on the first metal interconnect structure of the device wafer, and the second bonding oxide layer is located on the second metal interconnect structure of the carrier wafer. The thickness of the first bonding oxide layer in the edge region of the device wafer and the thickness of the second bonding oxide layer in the edge region of the carrier wafer are both a first thickness.

[0011] A first metal contact plug and a second metal contact plug are formed. The first metal contact plug is located within the first bonding oxide layer and is electrically connected to the first metal interconnect structure. The second metal contact plug is located within the second bonding oxide layer and is electrically connected to the second metal interconnect structure.

[0012] A first chemical mechanical polishing process is performed so that the thickness difference between the edge and center of the first bonded oxide layer on the device wafer and the thickness difference between the edge and center of the second bonded oxide layer on the carrier wafer are both the second thickness.

[0013] A bonding process is performed to bond the carrier wafer and the device wafer to form a bonded wafer;

[0014] A thinning process is performed, which includes at least two sub-processes. The thinning amount of the sub-processes is adjusted so that the number of defects on the surface of the bonded wafer meets a preset standard.

[0015] Optionally, the first thickness is 3500 Å to 4000 Å, and the second thickness is less than 100 Å.

[0016] Optionally, the thinning process includes a two-step process: a first wet etching process and a second chemical mechanical polishing process.

[0017] Optionally, the etching time of the first wet etching process is 180 seconds to 240 seconds.

[0018] Optionally, the grinding depth of the second chemical mechanical polishing process is 0.95µm to 1.15µm.

[0019] Optionally, the device wafer is a pixel wafer, and the carrier wafer is a logic wafer.

[0020] Optionally, the process for forming the first bonded oxide layer and the second bonded oxide layer includes a chemical vapor deposition process.

[0021] Optionally, the process for forming the first metal contact plug and the second metal contact plug includes an electrochemical deposition process.

[0022] Optionally, the defects on the surface of the bonded wafer are silicon loss defects.

[0023] Optionally, the preset standard is that the number of defects on the surface of the bonded wafer is less than 30.

[0024] In the wafer bonding method provided by this invention, by increasing the oxide layer deposition thickness at the edges of the pixel wafer and logic wafer before bonding, and reducing the thickness difference between the edge and center regions of the pixel and logic wafers after chemical mechanical polishing, gray edge defects on the bonded wafer are effectively reduced, metal exposure is reduced, and the concentration of metal ions in the etching solution is significantly reduced, thus inhibiting the formation of small pit defects exacerbated by metal ion catalysis. In the post-bonding process, by adjusting the thinning amount of the sub-process in the thinning process, the number of defects on the surface of the bonded wafer meets a preset standard. Furthermore, by reducing the wet etching time, the generation of small pit defects on the surface of the bonded wafer is effectively reduced, and by increasing the polishing amount of chemical mechanical polishing, the residual small pit defects on the surface of the bonded wafer are effectively reduced, ultimately significantly reducing the number of silicon loss defects on the surface of the bonded wafer. The wafer bonding method provided by this invention significantly improves the yield and reliability of hybrid bonding processes, and has low process cost, good compatibility, and is easy to quickly implement and promote on production lines, exhibiting good economic efficiency and ease of operation. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of small pit defects on the surface of a bonded wafer after a chemical mechanical polishing process in the prior art.

[0026] Figure 2 This is a scanning electron microscope (SEM) image of silicon loss defects on the surface of the bonded wafer after the second wet etching process in the existing process.

[0027] Figure 3 This is a flowchart of a wafer bonding method according to an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram of the structure of the device wafer and the carrier wafer in an embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of small pit defects on the surface of the bonded wafer after the second chemical mechanical polishing process according to an embodiment of the present invention.

[0030] The labels in the attached figures are explained as follows:

[0031] Figures 1-2 In the middle: 1-bonded wafer; 2-small pit defect; 3-silicon loss defect.

[0032] Figures 4-5 In the diagram: 101-Device wafer; 102-First bonding oxide layer; 103-Second bonding oxide layer; 104-Carrier wafer; 11-Effective pad area; 12-Metal wiring area; 13-Pixel array area; 14-First metal contact plug; 15-Second metal contact plug; 16-Metal of the first pseudo-bonding pad area; 17-Metal of the second pseudo-bonding pad area; 18-Bonding wafer; 19-Small pit defect. Detailed Implementation

[0033] The wafer bonding method provided by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may have different emphases and sometimes use different scales. It should be understood that relative terms such as "above," "below," "top," and "bottom" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between various components, elements, steps, etc.

[0034] As described in the background section, the bonding process for hybrid bonding products has shifted from oxide-oxide bonding to metal-metal bonding, and the interconnection method has changed from relying on dielectric materials to using metal as the primary conductive path. However, this process change leads to varying degrees of graying or peeling at the edges of the bonded wafers, resulting in exposed metal. This embodiment uses copper-copper bonding as an example for illustration.

[0035] The inventors discovered that in existing processes, after the first wet etching step, some copper ions remain in the etching solution because the etching solution is recycled during the process. These copper ions act as metal-catalyzed oxidation agents during the etching process using a hydrofluoric acid-nitric acid-acetic acid mixture: copper ions undergo localized electrochemical reactions with the silicon surface, accelerating the oxidation and dissolution of silicon. Therefore, the originally uniform wet etching becomes non-uniform; that is, in areas where copper ions are attached or concentrated, the etching rate is significantly higher than the surrounding areas, resulting in small pit defects on the surface of the bonded wafer.

[0036] Figure 1 This is a schematic diagram illustrating small pit defects on the surface of bonded wafers after chemical mechanical polishing (CMP) in existing processes. Figure 1 As shown, after chemical mechanical polishing in the existing process, a large number of such small pit defects 2 still remain on the surface of the bonding wafer 1. Figure 2 This is a scanning electron microscope (SEM) image of silicon loss defects on the surface of the bonded wafer after the second wet etching process in the existing technology. Figure 2 As shown, in the existing process, after the second wet etching process, a rhomboid silicon loss defect 3 is finally formed.

[0037] Based on this, the core idea of ​​this invention is to provide a wafer bonding method that, by increasing the oxide layer deposition thickness at the edges of the pixel wafer and logic wafer before bonding, and reducing the thickness difference between the edge and center regions of the pixel and logic wafers after chemical mechanical polishing, effectively reduces gray edge defects in the bonded wafer, reduces metal exposure, and thus significantly reduces the metal ion concentration in the etching solution, inhibiting the formation of small pit defects exacerbated by metal ion catalysis. In the post-bonding process, by adjusting the thinning amount of the sub-process in the thinning process, the number of defects on the surface of the bonded wafer meets a preset standard. Furthermore, by reducing the wet etching time, the generation of small pit defects on the surface of the bonded wafer is effectively reduced, and by increasing the polishing amount of chemical mechanical polishing, the residual small pit defects on the surface of the bonded wafer are effectively reduced, ultimately significantly reducing the number of silicon loss defects on the surface of the bonded wafer. The wafer bonding method provided by this invention significantly improves the yield and reliability of hybrid bonding processes, and has low process cost, good compatibility, and is easy to quickly implement and promote on production lines, exhibiting good economic efficiency and ease of operation.

[0038] Figure 3 This is a schematic flowchart of the wafer bonding method in this embodiment, as shown below. Figure 3 As shown, this embodiment provides a wafer bonding method, including:

[0039] Step S1: A device wafer and a carrier wafer are provided, wherein a first metal interconnect structure is formed on the device wafer and a second metal interconnect structure is formed on the carrier wafer;

[0040] Step S2: Form a first bonding oxide layer and a second bonding oxide layer. The first bonding oxide layer is located on the first metal interconnect structure of the device wafer, and the second bonding oxide layer is located on the second metal interconnect structure of the carrier wafer. The thickness of the first bonding oxide layer in the edge region of the device wafer and the thickness of the second bonding oxide layer in the edge region of the carrier wafer are a first thickness.

[0041] Step S3: Form a first metal contact plug and a second metal contact plug. The first metal contact plug is located within the first bonding oxide layer and is electrically connected to the first metal interconnect structure. The second metal contact plug is located within the second bonding oxide layer and is electrically connected to the second metal interconnect structure.

[0042] Step S4: Perform a first chemical mechanical polishing process to make the thickness difference between the edge and center of the first bonded oxide layer on the device wafer and the thickness difference between the edge and center of the second bonded oxide layer on the carrier wafer both the second thickness.

[0043] Step S5: Perform a bonding process to bond the carrier wafer and the device wafer to form a bonded wafer;

[0044] Step S6: Perform a thinning process, which includes at least two sub-processes. Adjust the thinning amount of the sub-processes in the thinning process so that the number of defects on the surface of the bonding wafer meets a preset standard.

[0045] Figure 4 This is a schematic diagram of the device wafer and the carrier wafer according to an embodiment of the present invention. Please continue to refer to... Figure 3 and Figure 4 In step S1, the device wafer 101 is a pixel wafer, and the carrier wafer 104 is a logic wafer. A first metal interconnect structure is formed on the pixel wafer. Figure 4 (Not shown in the image), a second metal interconnect structure is formed on the logic wafer ( Figure 4 (Not shown in the image).

[0046] Please continue to refer to this. Figure 3 and Figure 4Step S2 is performed during the pre-bonding preparation stage of the pixel wafer and the logic wafer. In step S2, for example, a chemical vapor deposition (CVD) process is used to deposit the first bonding oxide layer 102 on the first metal interconnect structure of the pixel wafer, and simultaneously deposit the second bonding oxide layer 103 on the second metal interconnect structure of the logic wafer. The materials of the first bonding oxide layer 102 and the second bonding oxide layer 103 are, for example, silicon oxide. The CVD process parameters are, for example, a deposition temperature of 300℃~450℃, reactant gases SiH4 and O2, RF power of 100W~300W, and deposition rate of 100Å / min~300Å / min. The edge regions of the pixel wafer and the logic wafer are annular regions extending 3 mm~5 mm from the physical edge of the wafer towards the center, and the edge regions of the pixel wafer and the logic wafer include effective pad areas 11. In existing processes, the thickness of the first bonding oxide layer 102 in the pixel wafer edge region and the second bonding oxide layer 103 in the logic wafer edge region is 2500 Å to 3000 Å. In this embodiment, the first thickness of the first bonding oxide layer 102 in the pixel wafer edge region and the second bonding oxide layer 103 in the logic wafer edge region is increased to 3500 Å to 4000 Å, so that the pixel wafer and the logic wafer can be bonded more tightly in subsequent bonding.

[0047] Please continue to refer to this. Figure 3 and Figure 4In step S3, interconnect vias and metal wiring (PBV and PBM) are formed on the back side of the pixel wafer, and interconnect vias and metal wiring (LBV and LBM) are formed on the back side of the logic wafer. A first metal contact plug 14 is formed in the first bonding oxide layer 102, and a second metal contact plug 15 is formed in the second bonding oxide layer 103, such that the first metal contact plug 14 is electrically connected to the first metal interconnect structure, and the second metal contact plug 15 is electrically connected to the second metal interconnect structure. The step of forming the second metal contact plug 15 in the second bonding oxide layer 103 includes: performing an etching process to form the first interconnect via and the second interconnect via, wherein the first interconnect via is located in the first bonding oxide layer 102 and the second interconnect via is located in the second bonding oxide layer 103; performing a deposition process to form the first metal contact plug 14 in the first interconnect via and the second metal contact plug 15 in the second interconnect via. The deposition process is, for example, an electrochemical deposition (ECD) process. The electrochemical deposition parameters are, for example,: a barrier layer TaN thickness of 100 Å to 200 Å; a seed layer Cu thickness of 1000 Å to 1500 Å; a CuSO4 concentration in the electroplating solution of 60 g / L to 80 g / L; and a current density of 10 mA / cm². 2 ~20mA / cm 2 The electroplating temperature is 25℃; the electroplating time is 120s~150s; the annealing atmosphere is N2 / H2 (95:5) atmosphere, the annealing temperature is 350℃~400℃, and the annealing time is 60min~90min.

[0048] Please continue to refer to this. Figure 4The pixel wafer and the logic wafer include a pad area 11, a metal shielding area 12, and a pixel array area 13. The first metal contact plug 14 is located in the effective pad area 11 of the pixel wafer, and the second metal contact plug 15 is located in the effective pad area 11 of the logic wafer. To achieve uniform stress distribution during bonding of the pixel wafer and the logic wafer, and to avoid warping or voids caused by uneven distribution of the effective pad area 11, dummy bond pads are simultaneously formed in the metal wiring area 12 and pixel array area 13 of the pixel wafer and the logic wafer when forming the first metal contact plug 14 and the second metal contact plug 15. The dummy bond pads include a first dummy bond pad 16 and a second dummy bond pad 17. The first dummy bond pad 16 is located within the first bonding oxide layer 102, and the second dummy bond pad 17 is located within the second bonding oxide layer 103. The dummy bond pads do not participate in electrical connection. The first metal contact plug 14, the second metal contact plug 15, and the dummy bond pads provide bonding metal for the bonding of the pixel wafer and the logic wafer.

[0049] Please continue to refer to this. Figure 3 and Figure 4 In step S4, a first chemical mechanical polishing (CMP) process is performed to planarize the bonding interface between the pixel wafer and the logic wafer. The first CMP process is performed such that the thickness difference between the edge and center of the first bonding oxide layer 102 on the pixel wafer and the thickness difference between the edge and center of the second bonding oxide layer 103 on the logic wafer are both a second thickness, which is less than 100 Å. The parameters of the first CMP process are, for example: a polyurethane-based hard polishing pad; pH 9-11; a SiO2-based polishing slurry flow rate of 200 mL / min-400 mL / min; a pressure of 1.0 psi-2.0 psi; a polishing table speed of 80 rpm-100 rpm; a polishing head speed of 90 rpm-110 rpm; and a polishing time of 60-90 seconds. In this embodiment, optical interferometry is used to monitor the polishing endpoint.

[0050] Please continue to refer to this. Figure 3 and Figure 4In step S5, a bonding process is performed to bond the pixel wafer and the logic wafer to form a bonded wafer. This embodiment uses copper-copper bonding as an example. The copper-copper bonding process conditions are, for example: bonding temperature of 300℃~400℃; bonding pressure of 10kN~30kN; bonding time of 30 seconds~180 seconds; and bonding atmosphere of N2. After bonding, an annealing treatment is performed, for example, in an N2 atmosphere for 30 minutes~120 minutes at an annealing temperature of 300℃~400℃, to promote the diffusion of copper atoms across the interface to form reliable metallic bonds.

[0051] Before performing the bonding process, firstly, by increasing the thickness of the first bonding oxide layer 102 in the edge region of the pixel wafer and the second bonding oxide layer 103 in the edge region of the logic wafer, the pixel wafer and the logic wafer are bonded more tightly in subsequent bonding. Secondly, in the chemical mechanical polishing process, by reducing the thickness difference between the edge and center of the first bonding oxide layer 102 on the pixel wafer and the thickness difference between the edge and center of the second bonding oxide layer 103 on the logic wafer to form a smoother bonding interface, the gray edge defect of the bonded wafer is, for example, less than 0.4 mm, significantly reducing the problem of exposed copper metal.

[0052] Please continue to refer to this. Figure 3 In step S6, a thinning process is performed to thin the bonding wafer. This thinning process includes at least two sub-processes. In this embodiment, the thinning process includes a first wet etching process and a second chemical mechanical polishing process. Furthermore, the thinning process also includes a second wet etching process. The etching time of the first wet etching process is, for example, 180 seconds to 240 seconds. By reducing the etching time of the first wet etching process, the interaction between the etching solution and the exposed copper metal is reduced, thus reducing the generation of copper ions and consequently reducing small pit defects on the surface of the bonding wafer. Figure 5 This is a schematic diagram of the small pit defects on the surface of the bonded wafer after the second chemical mechanical polishing (CMP) process according to an embodiment of the present invention. The small pit defects 19 are effectively removed by increasing the polishing amount of the second CMP process; the polishing amount of the second CMP process is, for example, 0.95 μm to 1.15 μm. After the subsequent second wet etching process, the small pit defects 19 are further removed, forming silicon loss defects. The number of silicon loss defects on the surface of the bonded wafer 18 meets a preset standard. The preset standard is that the number of silicon loss defects on the surface of the bonded wafer 18 is less than 30.

[0053] Please continue to refer to this. Figure 5First, the bonding wafer 18 is subjected to a wet etching process. For example, a mixture of hydrofluoric acid, nitric acid, and acetic acid is used as the etching solution for the first wet etching process. The parameters of the first wet etching process are, for example, the volume ratio of the etching solution is HF:HNO3:CH3COOH = 1:5:3; the temperature of the etching solution is controlled at 25°C; a single-wafer rotating spray method is used; the flow rate of the etching solution is 500 mL / min to 60 mL / min; and the etching time is 180 seconds to 240 seconds. After the first wet etching process is completed, the wafer is rinsed with deionized water for 90 seconds to 120 seconds and then rotated to dry.

[0054] Due to the reduction in gray edge defects of the bonding wafer 18, the exposure of copper metal is significantly reduced. Furthermore, by reducing the etching time of the first wet etching process, the interaction between copper metal and the etching solution of the first wet etching process is reduced. Therefore, in this embodiment, the copper ion concentration in the etching solution of the first wet etching process is less than 0.5 ppm. No abnormal increase in small pits is observed on the surface of the bonding wafer 18. The density of small pit defects 19 is reduced by 70% to 90% compared to conventional processes, providing a good surface condition for subsequent processes.

[0055] Please continue to refer to this. Figure 5 Next, the bonding wafer 18 is subjected to the second chemical mechanical polishing (CMP) process to remove some of the small pit defects 19 on the surface of the bonding wafer 18. After the second CMP process, the small pit defects 19 on the surface of the bonding wafer 18 are reduced by, for example, 60% to 80%. The process conditions for the second CMP process are, for example, as follows: a soft polishing pad is used; the polishing slurry is a silicon CMP slurry; the polishing slurry flow rate is 150 mL / min to 200 mL / min; the polishing head pressure is 2.0 psi to 3.0 psi; the polishing table speed is 60 rpm to 90 rpm; the polishing head speed is 75 rpm to 90 rpm; and the polishing depth is controlled at 0.95 μm to 1.15 μm. The polishing endpoint is monitored in real time using laser interferometry. After polishing, the wafer is rinsed with deionized water on both sides for 60 seconds and then spun dry.

[0056] Please continue to refer to this. Figure 5Finally, the second wet etching process is performed on the bonding wafer 18 to further remove the small pit defects 19 and form the silicon loss defects. The process conditions for the second wet etching process are, for example: using tetramethylammonium hydroxide solution as the etching solution; etching solution concentration of 25 wt.%~40 wt.%; etching temperature of 70℃~80℃; etching time of 120 seconds~240 seconds; and etching rate of 0.5 μm / min~0.8 μm / min. Since the preceding second chemical mechanical polishing process has essentially eliminated some of the small pit defects 19, only a small number of rhomboid silicon loss defects are ultimately formed on the surface of the bonding wafer 18. Scanning with a defect detector, the number of silicon loss defects on the surface of the bonding wafer 18 is, for example, less than 30, meeting the preset standard.

[0057] After performing the thinning process on the bonding wafer 18, a deep trench isolation (DTI) process is performed on the bonding wafer 18 to electrically isolate adjacent pixels and reduce crosstalk. In this embodiment, the deep trench pattern is first defined by a photolithography process; after the photolithography process is completed, residual polymer is removed, for example, by wet cleaning; then trench filling is performed, and the trench filling step is, for example, growing a silicon dioxide pad layer by thermal oxidation to passivate the sidewalls, and then filling with a high dielectric constant material or silicon dioxide using a high-density plasma chemical vapor deposition (HDP-CVD) or atomic layer deposition (ALD) process.

[0058] After performing a deep trench isolation process on the bonding wafer 18, a backside metal layer (BSL), a first backside pad (BPAD1), and a ball array pad (BALPAD) process are performed on the bonding wafer 18 to fabricate backside metal interconnects and pads. In this embodiment, the backside metal layer, the first backside pad, and the ball array pad process are as follows: First, a titanium and copper (Ti and Cu) seed layer is sequentially deposited on the back side of the bonding wafer 18 using physical vapor deposition (PVD); the pattern of the first backside pad is defined by photolithography, and then copper electroplating is performed to thicken it; after removing the photoresist, the exposed seed layer is removed by wet etching. Subsequently, the ball array pad is fabricated; finally, tin-silver-copper (SAC305) solder balls are formed on the ball array pads by ball-planting process or stencil printing and reflow.

[0059] After performing backside metal layer, first backside pad, and ball grid array pad processes on the bonding wafer 18, a backside metal redistribution layer (BSLR) and backside ground (BSGND) process is performed on the bonding wafer 18 to fabricate backside metal wiring and a ground layer. In this embodiment, the steps of the backside metal redistribution layer / backside ground process are, for example, as follows: First, polyimide (PI) or photosensitive benzocyclobutene (BCB) is spin-coated on the back side of the bonding wafer 18 as a dielectric layer; then, for example, titanium and copper seed layers are deposited sequentially using physical vapor deposition, and copper is electroplated to thicken to 3μm~5um to form the redistribution wiring layer and the backside ground layer; after removing the photoresist, excess seed layers are removed, for example, using rapid wet etching; finally, for example, silicon nitride is deposited as a passivation layer using chemical vapor deposition, and photolithographic openings are made in the ground pad and redistribution pad areas.

[0060] After performing the backside metal redistribution layer and backside grounding processes on the bonding wafer 18, the bonding wafer 18 is then subjected to backside metal grid (BMG) and second backside pad (BPAD2) processes to fabricate the backside metal grid structure and secondary pads. In this embodiment, the steps of the backside metal grid and second backside pad processes are as follows: First, a silicon dioxide buffer layer is deposited on the backside of the bonding wafer 18 using, for example, chemical vapor deposition; then, for example, a titanium, aluminum, and titanium (Ti, Al, and Ti) metal stack is sequentially deposited using physical vapor deposition to form an initial metal layer; the metal grid pattern and secondary pad openings are defined using photolithography, for example, by using chloride-based reactive ion etching to remove excess metal layers, forming the backside metal grid structure and the second backside pad; after the photolithography etching, the surface is rinsed with deionized water and dried with nitrogen; finally, for example, a silicon oxide layer is deposited as a protective layer using chemical vapor deposition, and photolithographic openings are made in the area of ​​the second backside pad.

[0061] In summary, this embodiment provides a wafer bonding method that effectively reduces gray edge defects in the bonded wafers and reduces metal exposure by increasing the oxide layer deposition thickness at the edge regions of the pixel wafers and logic wafers before bonding, and reducing the thickness difference between the edge regions and the center regions after chemical mechanical polishing. This significantly reduces the concentration of metal ions in the etching solution and inhibits the formation of small pit defects catalyzed by metal ions. In the post-bonding process, reducing the wet etching time effectively reduces the generation of small pit defects on the bonded wafer surface, and increasing the polishing amount of chemical mechanical polishing effectively reduces the residue of small pit defects on the bonded wafer surface, ultimately significantly reducing the number of silicon loss defects on the bonded wafer surface. The wafer bonding method provided in this embodiment significantly improves the yield and reliability of hybrid bonding processes, and has low process cost, good compatibility, and is easy to quickly implement and promote on production lines, exhibiting good economic efficiency and ease of operation.

[0062] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A wafer bonding method, characterized in that, include: A device wafer and a carrier wafer are provided, wherein a first metal interconnect structure is formed on the device wafer and a second metal interconnect structure is formed on the carrier wafer; A first bonding oxide layer and a second bonding oxide layer are formed. The first bonding oxide layer is located on the first metal interconnect structure of the device wafer, and the second bonding oxide layer is located on the second metal interconnect structure of the carrier wafer. The thickness of the first bonding oxide layer in the edge region of the device wafer and the thickness of the second bonding oxide layer in the edge region of the carrier wafer are both a first thickness. A first metal contact plug and a second metal contact plug are formed. The first metal contact plug is located within the first bonding oxide layer and is electrically connected to the first metal interconnect structure. The second metal contact plug is located within the second bonding oxide layer and is electrically connected to the second metal interconnect structure. A first chemical mechanical polishing process is performed so that the thickness difference between the edge and center of the first bonded oxide layer on the device wafer and the thickness difference between the edge and center of the second bonded oxide layer on the carrier wafer are both the second thickness. A bonding process is performed to bond the carrier wafer and the device wafer to form a bonded wafer; A thinning process is performed, which includes at least two sub-processes. The thinning amount of the sub-processes is adjusted so that the number of defects on the surface of the bonded wafer meets a preset standard.

2. The wafer bonding method as described in claim 1, characterized in that, The first thickness is 3500 Å to 4000 Å, and the second thickness is less than 100 Å.

3. The wafer bonding method as described in claim 1, characterized in that, The thinning process includes a two-step process: a first wet etching process and a second chemical mechanical polishing process.

4. The wafer bonding method as described in claim 3, characterized in that, The etching time for the first wet etching process is 180 to 240 seconds.

5. The wafer bonding method as described in claim 3, characterized in that, The grinding amount of the second chemical mechanical polishing process is 0.95um~1.15um.

6. The wafer bonding method as described in claim 1, characterized in that, The device wafer is a pixel wafer, and the carrier wafer is a logic wafer.

7. The wafer bonding method as described in claim 1, characterized in that, The process for forming the first bonded oxide layer and the second bonded oxide layer includes a chemical vapor deposition process.

8. The wafer bonding method as described in claim 1, characterized in that, The process for forming the first metal contact plug and the second metal contact plug includes an electrochemical deposition process.

9. The wafer bonding method as described in claim 1, characterized in that, The defects on the surface of the bonded wafer are silicon loss defects.

10. The wafer bonding method as described in claim 1, characterized in that, The preset standard is that the number of defects on the surface of the bonded wafer is less than 30.

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