High fill factor front-illuminated large array tdi ccd structure

Abstract

This invention discloses a high fill factor, positive illumination, small pixel, large array TDICCD structure, comprising a pixel array composed of pixel units arranged in an array. Each pixel unit has multiple transfer gate electrodes built in it. A series selection gate is disposed at the boundary position of the integral series segment in the pixel array. Multiple metal wirings are evenly spaced and obliquely arranged within the pixel array. These metal wirings are connected to corresponding transfer gate electrodes or series selection gates according to connected bus signals. This invention employs an oblique wiring design, which can significantly reduce the photosensitive area occupied, significantly improve the pixel fill factor, quantum efficiency, and imaging sensitivity, and solve the problem of decreased photosensitive performance caused by conventional dense wiring. High performance can be achieved using only conventional positive illumination processes without the need for complex back-illumination processes.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and in particular relates to a high fill factor, positive illumination of a small pixel large array TDICCD structure. Background Technology

[0002] With the development of aerospace remote sensing, high-resolution Earth observation, and other fields, higher demands are being placed on TDICCD (Time Delayed and Integration CCD) devices for small pixels, large arrays, high quantum efficiency, and high line frequency response performance. Existing front-illuminated large-pixel TDICCDs typically employ dense metal wiring designs to meet the RC time constant and line frequency requirements under large array conditions. This type of wiring occupies a large portion of the pixel's photosensitive area, directly leading to a reduction in the pixel fill factor and a significant decrease in device quantum efficiency and imaging sensitivity. To compensate for the loss of fill factor, current technologies mostly use back-illuminated processes to fabricate TDICCDs. However, back-illuminated processes are complex, difficult to process, and have low yields, significantly increasing the device's production cost and hindering large-scale mass production applications. Furthermore, some improved wiring structures are prone to poor device response uniformity, failing to adapt to the line-by-line accumulation working principle of TDICCDs, resulting in uneven final images and making it difficult to simultaneously meet the core requirements of high fill factor, high line frequency response, uniform imaging, and low cost. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a high fill factor, positive illumination small pixel large array TDICCD structure.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A high fill factor front-illuminated small pixel large array TDICCD structure includes a pixel array composed of pixel units arranged in an array. Each pixel unit has multiple transfer gate electrodes built in it. A series gating gate is set at the boundary position of the integral series segment in the pixel array. Multiple metal wirings are arranged at equal intervals and at an angle in the pixel array. The metal wirings are connected to the corresponding transfer gate electrodes or series gating gates according to the connected bus signals.

[0005] Furthermore, the metal wiring is inclined at 45° to the row or column direction of the pixel array; the metal wiring is arranged at equal intervals along the row and column directions of the pixel array.

[0006] Furthermore, the metal wiring is arranged at intervals of N pixel unit widths along both the row and column directions of the array.

[0007] Furthermore, the value of N is selected based on the array size of the TDICCD and the target operating line frequency.

[0008] Furthermore, based on the joint iteration of electrical simulation and process constraints of the TDICCD structure, the line width W of each metal wiring and the spacing S between adjacent metal wirings are set to ensure that the parasitic resistance and inter-line parasitic capacitance parameters of each metal wiring are highly consistent, and the total RC time constant of the global wiring network matches the target line frequency operating requirements of the large array TDICCD.

[0009] Furthermore, the metal wiring is grouped and laid out according to the pixel array arrangement period. The metal wiring in each period group includes transfer gate wiring connected to the transfer gate electrode and stage selection wiring connected to the time delay integral stage selection CSSx bus. Each transfer gate wiring in the same period group is connected to each transfer gate electrode in a one-to-one correspondence, and each stage selection wiring in the same period group is connected to each time delay integral stage selection CSSx bus in a one-to-one correspondence.

[0010] Furthermore, the pixel array is a linear array or a planar array, the pixel unit adopts a shallow junction buried trench structure, and the size of the pixel unit is 3 to 7 μm.

[0011] Furthermore, the time delay integration level of the TDICCD structure is 16 to 128 levels.

[0012] Furthermore, the TDICCD structure is fabricated using a conventional positive illumination semiconductor process.

[0013] Furthermore, the transfer gate electrodes of pixel units in the same phase and in the same column are connected vertically through polysilicon gate strips, while the transfer gate electrodes of pixel units in the same phase but in different columns are connected together through metal wiring.

[0014] This invention employs a tilted wiring design, which significantly reduces the occupancy of the photosensitive area, substantially improves the pixel fill factor, quantum efficiency, and imaging sensitivity, and solves the problem of decreased photosensitive performance caused by conventional dense wiring. The use of 45° equally spaced tilted metal wiring allows for precise control of RC characteristics through uniform spacing, ensuring signal transmission stability under high line frequency operation of the large-array TDICCD. Furthermore, relying on the line-by-line accumulation principle of TDICCD, it achieves uniform response across the entire array, balancing high-speed response and high-quality imaging requirements. This invention eliminates the need for complex back-illumination processes, achieving high performance using only conventional front-illumination processes, simplifying the fabrication process, reducing processing difficulty and production costs, and improving mass production feasibility and market competitiveness. Moreover, the wiring interval of N pixels can be flexibly selected according to the device array size and line frequency requirements, adapting to different specifications of small-pixel and large-array TDICCD device designs, thus having a wide range of applications. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of an embodiment of the high fill factor orthogonal small pixel large array TDICCD structure of the present invention.

[0016] Figure 2 This is a schematic diagram of the metal wiring method in the existing forward-facing TDICCD structure.

[0017] Figure 3 This is a schematic diagram of the metal wiring method of the large array TDICCD structure of the present invention.

[0018] Figure 4 This is a wiring diagram of a 6144×96 orthogonal small pixel large array TDICCD structure.

[0019] Figure 5 This is a schematic diagram comparing the pixel fill factor of a conventional TDICCD dense wiring structure with that of the present invention.

[0020] Figure 6 This is a schematic diagram comparing the quantum efficiency of a conventional TDICCD dense wiring structure with that of the present invention.

[0021] The diagrams in the instruction manual are labeled as follows: Pixel array 100; pixel unit 110; metal wiring 120; contact hole 130; horizontal CCD 200; amplifier unit 300. Detailed Implementation

[0022] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0023] Please see Figure 1 , Figure 1This is a schematic diagram of an embodiment of the high fill factor positive illumination small pixel large array TDICCD structure of the present invention. The high fill factor positive illumination small pixel large array TDICCD structure of this embodiment includes a pixel array 100 composed of pixel units 110 arranged in an array. It also includes other necessary structures such as a horizontal CCD 200 and an amplifier unit 300, which are irrelevant to the innovation of this invention and therefore will not be described in detail. The pixel array 100 can be a linear array or a planar array, with a width of 4096, 6144, 8192 pixels, or even higher. The size of the pixel unit 110 can be 3–7 μm; for example, the size of the pixel unit 110 can be 3 μm, 4 μm, 5 μm, 6 μm, or 7 μm. The pixel unit 110 can adopt a shallow junction buried trench structure to improve charge collection efficiency. The time delay integration stage of the TDICCD structure is 16–128 stages, supporting multi-stage integration to improve the signal-to-noise ratio; for example, the time delay integration stage can be 16, 32, 64, or 128 stages. The TDICCD structure is fabricated using conventional front-illuminated semiconductor processes, eliminating the need for back-illuminated thinning, back-side photolithography, and back-side passivation back-illuminated processes.

[0024] The pixel unit 110 has multiple built-in transfer gate electrodes (not shown in the figure). It also has a built-in accumulation gate (not shown in the figure). The accumulation gate is used for the integration, collection, and potential well storage of the photogenerated signal charge generated by the pixel unit 110. The transfer gate electrodes are used to receive the driving timing voltage signal, regulate the channel barrier, and realize the sequential row-by-row transfer of signal charge according to the TDI timing sequence. The transfer gate electrodes and the accumulation gate work together to complete the entire process of single-pixel photoelectric conversion, charge accumulation, isolation and maintenance, and controlled transfer, together forming a complete pixel-level charge control unit. In this embodiment, the pixel unit 110 has four built-in transfer gate electrodes: a first vertical driving phase transfer gate, a second vertical driving phase transfer gate, a third vertical driving phase transfer gate, and a fourth vertical driving phase transfer gate.

[0025] The pixel array 100 has level gates at the boundaries of the integral stages. These level gates are not configured in every pixel unit 110, but rather at the boundaries of the vertical charge transfer channels. The number of level gates is determined by the integral stage intervals of the TDICCD structure; each boundary between two adjacent stage intervals corresponds to one level gate CSSx bus. The more stage intervals there are, the more stages can be selected, and the more level gate CSSx buses there are.

[0026] The pixel array 100 is provided with multiple metal wirings 120 arranged at equal intervals and at an angle. These metal wirings 120 are connected to corresponding transfer gate electrodes or stage-select gates according to connected bus signals. This allows the transfer gate electrodes of pixel units 110 in the same phase and column to be vertically connected via polysilicon gate strips, and the transfer gate electrodes of pixel units 110 in the same phase but different columns to be connected together via the metal wirings 120. Specifically, the metal wirings 120 can be connected to the transfer gate electrodes or stage-select gates through contact holes 130 pre-set above the pixel array 100.

[0027] Please see Figure 2 This is a dense wiring structure of a conventional TDICCD structure, with pixel units 110 arranged in a grid. Each pixel unit 110 has metal wiring 120, and its fill factor is approximately 62%. The pixel fill factor refers to the ratio of the effective photosensitive area within a single pixel unit 110 to the total area of ​​the entire pixel unit 110 layout, expressed as a percentage; it represents the proportion of the effective area in the pixel that can receive light signals and generate photocharge to the total area of ​​the pixel. The non-photosensitive areas in the pixel unit 110 include the areas blocked by the metal wiring 120, the areas blocked by the transfer gate electrode and the accumulation gate, the contact hole 130, the isolation trench, the wiring channel, etc.; the photosensitive areas in the pixel unit 110 include the exposed silicon active area and the photosensitive area.

[0028] Therefore, the more numerous and denser the metal wiring 120, the larger the photosensitive area of ​​the pixel unit 110 is covered, and the lower the fill factor. A lower fill factor results in more metal / gate obstruction, weaker light sensitivity, and poorer low-light / remote sensing imaging performance. Conversely, a higher fill factor results in greater light intake, higher quantum efficiency, higher signal-to-noise ratio, and brighter and more sensitive imaging. In this embodiment, the metal wiring 120 adopts a tilted wiring design, breaking away from the conventional design concept of horizontal / vertical wiring. While meeting the wiring connectivity and electrical performance requirements of large array devices, it significantly reduces the proportion of the wiring occupying the pixel's photosensitive area.

[0029] In this embodiment, the metal wiring 120 is grouped and arranged according to the arrangement period of the pixel array 100. The metal wiring 120 in each period group includes transfer gate wiring connected to the transfer gate electrode and stage selection wiring connected to the time delay integral stage selection CSSx bus. Each transfer gate wiring in the same period group is connected to each transfer gate electrode of the pixel unit 110 in a one-to-one correspondence. Each stage selection wiring in the same period group is connected to each time delay integral stage selection CSSx bus (hereinafter referred to as stage selection CSSx bus) in a one-to-one correspondence, thereby realizing that each driving phase signal and stage selection control signal are regularly distributed to the pixel units 110 of the entire array in a periodic manner.

[0030] For example, in this embodiment, the pixel unit 110 has four transfer gate electrodes built in. Therefore, each period group includes four transfer gate wirings. Correspondingly, the TDICCD structure has four driving phase signals, which are transmitted through the first phase vertical driving φ1 bus (hereinafter referred to as vertical driving φ1 bus), the second phase vertical driving φ2 bus (hereinafter referred to as vertical driving φ2 bus), the third phase vertical driving φ3 bus (hereinafter referred to as vertical driving φ3 bus), and the fourth phase vertical driving φ4 bus (hereinafter referred to as vertical driving φ4 bus), respectively. The first transfer gate wiring of each cycle group is connected to the vertical drive φ1 bus and is connected to the first vertical drive phase transfer gate of each pixel unit 110 on its wiring path through the contact hole 130. The second transfer gate wiring of each cycle group is connected to the vertical drive φ2 bus and is connected to the second vertical drive phase transfer gate of each pixel unit 110 on its wiring path through the contact hole 130. The third transfer gate wiring of each cycle group is connected to the vertical drive φ3 bus and is connected to the third vertical drive phase transfer gate of each pixel unit 110 on its wiring path through the contact hole 130. The fourth transfer gate wiring of each cycle group is connected to the vertical drive φ4 bus and is connected to the fourth vertical drive phase transfer gate of each pixel unit 110 on its wiring path through the contact hole 130.

[0031] Assuming the TDICCD structure has four level-select control signals, which are transmitted through four level-select CSSx buses respectively; then each cycle group includes four level-select wirings. The four level-select wirings in the same cycle group are connected one-to-one with the four level-select CSSx buses respectively, and are connected to the corresponding level-select gates on their wiring paths through contact holes 130.

[0032] In this embodiment, the metal wiring 120 is preferably inclined at 45° to the row or column direction of the pixel array 100, and the metal wiring 120 is arranged at equal intervals along the row and column directions of the pixel array 100. 45° is chosen as the preferred inclination angle, rather than other angles, because in the geometry of the square pixel array 100, the 45° diagonal direction can provide the longest linear projection distance while meeting the minimum safety spacing, thereby maximizing the effective photosensitive area (fill factor) of the pixels. Simultaneously, the symmetrical distribution at 45° ensures that the occlusion effect of the wiring on each pixel is consistent, avoiding the uneven response that may be caused by asymmetrical angles. Furthermore, the 45° oblique wiring can effectively interrupt long-distance parallel traces, reduce inter-line parasitic capacitance, optimize the RC time constant, and balance optical and electrical performance.

[0033] The metal wiring 120 is arranged at intervals of N pixel units 110 along both the row and column directions of the array. The value of N can be 4, 8, or 16. The value of N is generally selected based on the array size of the TDICCD and the target operating row frequency, as follows: Based on the joint iteration of electrical simulation and process constraints of the TDICCD structure, the line width W of each metal wiring 120 and the spacing S between adjacent metal wirings 120 are set to ensure that the parasitic resistance and inter-line parasitic capacitance parameters of each metal wiring 120 are highly consistent, and the total RC time constant of the entire wiring network matches the target row frequency operating requirements of the large array TDICCD.

[0034] Please see Figure 3 This is a magnified view of a portion of the metal wiring 120 when it is tilted at 45° and the wiring interval is 8 pixels. The metal wiring 120 runs through the array area at a 45° tilt angle, with one metal wiring 120 placed after every 8 pixel rows / columns. Each tilted metal wiring 120 extends along the 45° direction, corresponding to the vertical path of 8 consecutive pixel columns. The metal wires are directly connected to the transfer gate electrodes of the corresponding column through an array of contact holes 130 pre-set above the non-photosensitive area of ​​each column of pixels. This ensures that the in-phase transfer gate electrodes of the 8 pixel columns covered by the same wiring are electrically connected one by one. The number of pixels between adjacent tilted metal wirings 120 remains constant. The connection relationship of metal wiring 120-contact hole 130-transfer gate electrode in the entire array range exhibits a highly regular periodic distribution with no local connection offset or parameter dispersion.

[0035] In this embodiment, the specific pixel-to-pixel interconnection logic is as follows: the transfer gate electrode of each pixel unit 110 is connected to the 45° inclined metal wiring 120 belonging to that column through the dedicated contact hole 130 corresponding to its column. The in-phase transfer gate electrodes of all pixel columns covered by the same metal wiring 120 are synchronously electrically interconnected, ensuring that in-phase drive signals can be simultaneously applied to the transfer gate electrodes of the corresponding pixels in the entire array during the TDICCD row-by-row integration and charge transfer process. Through this periodic interconnection structure, the transfer gate electrodes of all pixel units 110 in the entire array are incorporated into a unified wiring network, with no isolated pixel units 110 or connection breaks, thereby realizing the full-domain synchronous electrical interconnection of the corresponding transfer gate electrodes of the entire device.

[0036] Based on this, the wiring width W and spacing S meet the RC time constant design requirements: through joint iteration of device electrical simulation and process constraints, the line width W of each metal wiring 120 and the spacing S of adjacent wiring are precisely set, so that the parasitic resistance and inter-line parasitic capacitance parameters of each metal wiring 120 are kept highly consistent. The total RC time constant of the entire wiring network fully matches the target line frequency operating requirements of the large array TDICCD, avoiding problems such as drive signal delay, signal crosstalk, and timing offset caused by the discrete wiring parameters, and ensuring signal integrity at the target line frequency.

[0037] In this embodiment, the metal wiring 120 is arranged with a fixed uniform interval of 4 / 8 / 16 pixels in both row and column directions. This avoids the fill factor loss caused by dense wiring and accurately matches the resistance and capacitance characteristics of the wiring. This structure achieves uniform control over key parameters such as wiring length, line width, and line spacing through a regularized, equally spaced wiring arrangement. This ensures consistent impedance characteristics across the entire wiring, matching the signal transmission and driving timing requirements of large-array TDICCD devices, effectively optimizing the device's RC time constant, and ensuring that the device's RC time constant fully meets the high line frequency operating requirements of large-array TDICCD. Based on the working principle of TDICCD's line-by-line integration and accumulation, the occlusion effect of the uniformly spaced 45° inclined metal wiring 120 on the photosensitive area is evenly distributed during the line-by-line accumulation process, preventing local response differences and, in principle, avoiding the impact of wiring design on the uniformity of device response.

[0038] In this embodiment, the tilt angle of the metal wiring 120 is preferably 45°, rather than other tilt angles (such as 30°, 60°, etc.), mainly based on the following considerations of physical geometry and semiconductor process: Firstly, this is to maximize the utilization of wiring spacing and optimize the fill factor (optical and geometric advantages). According to the principle of longest diagonal, in a square or rectangular pixel grid, the diagonal direction (45°) connecting adjacent pixel vertices provides the maximum linear spacing in the plane. Furthermore, when wiring traverses the pixel array 100 at a 45° angle, its "duty cycle" in the horizontal or vertical projection direction is minimized. Compared to horizontal or vertical wiring, 45° wiring covers a longer distance within the same pixel cycle, thus minimizing the occlusion of individual pixel photosensitive areas while maintaining electrical isolation (preventing short circuits / crosstalk), maximizing the fill factor, and achieving optimal avoidance.

[0039] Secondly, it ensures uniform response and eliminates directional differences (optical advantage). The 45° angled wiring, distributed in a diamond or staggered grid pattern within the array, ensures uniform and symmetrical edge-cutting of pixels in all directions, achieving isotropic coverage. If a non-45° angle (such as 30° or 60°) is used, the projection of the wiring in the horizontal and vertical directions will exhibit periodic differences, resulting in varying degrees of occlusion of pixels at different locations, leading to non-uniform responses (such as moiré fringes or uneven brightness). Therefore, the symmetrical 45° design ensures consistent response across the entire field of view and avoids grid effects.

[0040] Thirdly, it optimizes the RC time constant and parasitic capacitance (an electrical advantage). In integrated circuit design, capacitance is mainly composed of parallel plates or edge electric fields. The 45° angled routing breaks the traditional "orthogonal grid" layout, minimizing the parallel overlap area between long-distance transmission lines and reducing parallel coupling. Furthermore, reducing the length of parallel segments effectively lowers the inter-line parasitic capacitance (C), thereby reducing the RC time constant, increasing charge transfer speed, reducing crosstalk and delay, and meeting high line frequency requirements. Therefore, 45° is the most natural geometric angle for achieving "de-parallelization."

[0041] Fourthly, there is the convenience and compatibility of process implementation (process advantages). A 45° angle is a common pattern design rule in CCD / CMOS processes, which is easy to achieve through standard photolithography and etching processes. Furthermore, the diamond-shaped grid formed by 45° angles is highly symmetrical, which is beneficial for the algorithm implementation of automated routing tools, and does not require complex angle correction, thus simplifying layout design.

[0042] Please see Figure 4 This embodiment describes a 6144×96 orthogonal small-pixel large-array TDICCD structure, with pixel units 110 measuring 7μm×7μm, classifying it as a small-pixel large-array imaging device. The metal wiring 120 of the pixel array 100 serves as the vertical transfer drive wiring and signal readout wiring for the device, all arranged at a 45° angle. The metal wiring 120 is evenly spaced at 8 pixel units 110 along the column direction, meaning a 45° angled metal wiring 120 is provided every 8 pixel units 110. Simultaneously, the even spacing of the 8 pixel units 110 is synchronously matched in the row direction, ensuring uniform distribution of wiring throughout the array.

[0043] Please see Figure 5 Through the above structural design, the TDICCD pixel fill factor in this embodiment is increased from 62% in conventional dense wiring structures to 81%. Please refer to... Figure 6Thanks to the improved fill factor, the quantum efficiency of the device at the 600nm characteristic wavelength is improved by more than 45%; at the same time, the RC time constant of the device is ≤10ns, which fully meets the working requirements of 10kHz line frequency; based on the line-by-line accumulation working mode of TDICCD, the device response non-uniformity is ≤1.5%, which is not significantly different from the ideal device without wiring obstruction; the TDICCD of this embodiment can be fabricated using conventional positive illumination CCD process, without the need for complex back illumination processes, reducing the fabrication cost by more than 40%.

[0044] This embodiment has the following beneficial effects: 1. Transfer gate electrodes significantly improve imaging performance. The design of uniformly spaced metal wiring 120 at 45° angles greatly reduces the area occupied by the metal wiring 120 in the pixel's photosensitive area, significantly improving the pixel fill factor, thereby enhancing the quantum efficiency and imaging sensitivity of the TDICCD device and fundamentally solving the problem of decreased photosensitive performance caused by conventional dense wiring. 2. The transferred gate electrode balances high-speed response and uniform imaging. The uniformly spaced wiring design can precisely control the RC characteristics of the device, ensuring the signal transmission stability of the large array TDICCD in high line frequency operation mode. At the same time, based on the line-by-line accumulation working principle of TDICCD, the response uniformity of the entire array of the device is achieved, which meets the dual requirements of high-speed operation and high-quality imaging. 3. The transfer gate electrode significantly reduces production costs. This invention eliminates the need for complex back-illumination processes such as back-illumination thinning and back-illumination lithography, achieving high performance solely through conventional front-illumination processes. This simplifies the fabrication process, reduces processing difficulty, effectively compresses device production costs, and enhances mass production feasibility and market competitiveness. 4. High flexibility in transfer gate electrode adaptation. The wiring spacing of 4, 8, or 16 pixels can be flexibly selected according to the device array size and line frequency requirements, adapting to the design of small-pixel and large-array TDICCD devices of different specifications, with a wide range of applications.

[0045] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A high fill factor, positively illuminated, small-pixel, large-array TDICCD structure, characterized in that: The pixel array comprises pixel units arranged in an array, each pixel unit having multiple transfer gate electrodes built in it, and a series gating gate being provided at the boundary position of the integral series segment in the pixel array; multiple metal wirings are arranged at equal intervals and at an angle within the pixel array, and the metal wirings are connected to the corresponding transfer gate electrodes or series gating gates according to the connected bus signals.

2. The high fill factor, positive illumination, small pixel, large array TDICCD structure as described in claim 1, characterized in that: The metal wiring is inclined at 45° to the row or column direction of the pixel array; the metal wiring is arranged at equal intervals along the row and column directions of the pixel array.

3. The high fill factor, positive illumination, small pixel, large array TDICCD structure as described in claim 2, characterized in that: The metal wiring is arranged at intervals of N pixel units along both the row and column directions of the array.

4. The high fill factor, positive illumination, small pixel, large array TDICCD structure as described in claim 3, characterized in that: The value of N is selected based on the array size of the TDICCD and the target operating line frequency.

5. The high fill factor, positive illumination, small pixel, large array TDICCD structure as described in claim 3, characterized in that: Based on the joint iteration of electrical simulation and process constraints of the TDICCD structure, the line width W of each metal wiring and the spacing S between adjacent metal wirings are set to ensure that the parasitic resistance and inter-line parasitic capacitance parameters of each metal wiring are highly consistent, and the total RC time constant of the global wiring network matches the target line frequency operating requirements of the large array TDICCD.

6. The high fill factor, positive illumination, small pixel, large array TDICCD structure as described in claim 1, characterized in that: The metal wiring is grouped and laid out according to the pixel array arrangement period. The metal wiring in each period group includes transfer gate wiring connected to the transfer gate electrode and stage selection wiring connected to the time delay integral stage selection CSSx bus. Each transfer gate wiring in the same period group is connected to each transfer gate electrode in a one-to-one correspondence. Each stage selection wiring in the same period group is connected to each time delay integral stage selection CSSx bus in a one-to-one correspondence.

7. The high fill factor, positive illumination, small pixel, large array TDICCD structure as described in claim 1, characterized in that: The pixel array is a linear array or a planar array, the pixel unit adopts a shallow junction buried trench structure, and the size of the pixel unit is 3 to 7 μm.

8. The high fill factor, positive illumination, small pixel, large array TDICCD structure as described in claim 1, characterized in that: The time delay integration level of the TDICCD structure is 16 to 128 levels.

9. The high fill factor, positive illumination, small pixel, large array TDICCD structure as described in claim 1, characterized in that: The TDICCD structure is fabricated using conventional positive illumination semiconductor processes.

10. The high fill factor orthogonal small pixel large array TDICCD structure as described in any one of claims 1 to 9, characterized in that: The transfer gate electrodes of pixel units with the same phase and in the same column are connected vertically through polysilicon gate strips, while the transfer gate electrodes of pixel units with the same phase but in different columns are connected together through metal wiring.

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