A silicon photomultiplier

Abstract

This invention discloses a silicon photomultiplier, comprising a semiconductor substrate and a semiconductor epitaxial layer thereon. Multiple microcells are formed in the epitaxial layer and connected in parallel. Each microcell includes: a second doped region and a third doped region forming a high-field region to generate an avalanche electrical signal; a trench structure surrounding the outer periphery of the second doped region; a third insulating layer disposed on the inner sidewall of the trench; a conductive material filling the trench and insulated from the epitaxial layer by the third insulating layer, and in direct contact with the substrate to form an electrical connection; a quenching element connected in series with the second doped region; a first electrode electrically connected to the second doped region through the quenching element for front-side signal extraction; and a second electrode electrically connected to the conductive material to form an electrical isolation boundary for front-side substrate potential extraction. This invention enables the trench structure to provide both optical and electrical isolation functions, ensuring consistent gain between edge microcells and internal microcells, while improving corner breakdown voltage, thereby enhancing the device's response uniformity and reliability.

Description

Technical Field

[0001] This invention relates to the field of photoelectric detection technology, and in particular to a silicon photomultiplier. Background Technology

[0002] A silicon photomultiplier (SiPM) is a high-gain, high-photon-detection-efficiency photoelectric conversion device composed of multiple single-photon avalanche photodiodes (SPADs) connected in parallel. Each microcell includes an avalanche photodiode operating in Geiger mode and a quenching element connected in series with it to quench the avalanche current so that the microcell can detect the next photon.

[0003] In existing technologies, trench isolation structures are typically used to reduce optical crosstalk between micro-units, providing optical isolation functionality. However, traditional trench designs have some drawbacks, leading to differences in the operating states of micro-units located at the edges compared to those inside, resulting in inconsistent micro-unit gains and affecting signal uniformity.

[0004] Furthermore, with the development of back-attribution processes, dual-electrode take-off from the front side is typically required. Conventional processes create a highly doped region inside the trench (near the high-field region) with the same doping type as the epitaxial substrate as the electrode take-off. However, because this region is close to the high-field region and is highly doped, it is prone to premature edge breakdown, and the highly doped region also leads to a reduction in the effective fill factor. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a silicon photomultiplier.

[0006] The technical solution adopted by this invention to solve its technical problem is: constructing a silicon photomultiplier, comprising: Semiconductor substrate; A semiconductor epitaxial layer is located on the semiconductor substrate; Multiple micro-units are formed in the semiconductor epitaxial layer and connected in parallel, each micro-unit comprising: A second doped region is formed within the semiconductor epitaxial layer; The third doped region is formed within the semiconductor epitaxial layer, located below the second doped region, and forms a high field region with the second doped region to generate avalanche current. The trench structure extends downward from the upper surface of the semiconductor epitaxial layer, at least partially surrounding the outer periphery of the second doped region; A third insulating layer is disposed on the inner sidewall of the trench structure; A conductive material is filled in the trench structure and insulated from the semiconductor epitaxial layer by the third insulating layer, and in direct contact with the semiconductor substrate, thereby forming an electrical connection with the semiconductor substrate and forming an optical isolation structure with the third insulating layer; A quenching element is connected in series with the second doped region to quench the generated avalanche current; The first electrode is electrically connected to the second doped region through the quenching element and is used to extract signals from the front. The second electrode is electrically connected to the conductive material to form an electrically isolated boundary with the conductive material, and is used to draw out the potential of the semiconductor substrate from the front side.

[0007] Furthermore, the silicon photomultiplier is a back-incident structure; the thickness of the semiconductor substrate is less than 2 μm, the bottom of the conductive material is exposed outside the semiconductor substrate, and forms a surface micro-nano structure; a microlens is also provided on the back side of the semiconductor substrate to focus the incident light onto the semiconductor epitaxial layer.

[0008] Furthermore, the silicon photomultiplier has a normal incidence structure and also includes a third electrode layer disposed at the bottom of the semiconductor substrate as a back-side lead-out electrode.

[0009] Furthermore, the trench structure penetrates the semiconductor epitaxial layer and extends into the interior of the semiconductor substrate, with the bottom of the trench structure located inside the semiconductor substrate.

[0010] Furthermore, it also includes a first doped region formed within the semiconductor epitaxial layer and surrounding the second doped region, for improving the corner breakdown voltage.

[0011] Furthermore, the second doped region has the same doping type as the first doped region, and the second doped region has a first doping concentration, while the first doped region has a second doping concentration lower than the first doping concentration.

[0012] Furthermore, the trench structure is a continuous closed ring structure surrounding the outer periphery of the first doped region.

[0013] Furthermore, the third doped region has a different doping type than the second doped region, while having the same doping type as the semiconductor substrate and the semiconductor epitaxial layer.

[0014] Furthermore, it also includes a first insulating layer and a second insulating layer disposed above the semiconductor epitaxial layer, wherein the first insulating layer is located inside the second insulating layer, and the top of the second doped region is in contact with the bottom of the first insulating layer.

[0015] Furthermore, the third insulating layer includes an oxide layer in contact with the semiconductor epitaxial layer and a high dielectric constant material layer located inside the oxide layer.

[0016] By implementing this invention, the following beneficial effects are achieved: The silicon photomultiplier of this invention, by filling the trench structure with conductive material and forming an electrical connection through direct contact with the semiconductor substrate, enables the trench structure to not only provide optical isolation, effectively reducing optical crosstalk, but also electrical isolation, thereby ensuring gain consistency between edge microcells and internal microcells. Simultaneously, the conductive material is led out from the front through a second electrode, and a second doped region is formed within the semiconductor epitaxial layer. This avoids the premature edge breakdown problem caused by high doping between the trench structure and the second doped region in conventional processes, thus improving the device's breakdown voltage and fill factor. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a schematic diagram of the silicon photomultiplier according to Embodiment 1 of the present invention, which includes two micro-units; Figure 2 yes Figure 1 A top view of a silicon photomultiplier, which includes a microcell, a first lead-out electrode, and a second lead-out electrode; Figure 3 This is a schematic diagram of the silicon photomultiplier according to Embodiment 2 of the present invention. Detailed Implementation

[0018] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0019] In the description of the invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of the invention, unless otherwise stated, "a plurality of" means two or more.

[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or a chemical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0021] Example 1: See Figure 1 and Figure 2 Embodiment 1 of the present invention discloses a silicon photomultiplier, including a semiconductor substrate 12, a semiconductor epitaxial layer 11, and a plurality of micro-units formed in the semiconductor epitaxial layer 11, wherein the plurality of micro-units are connected in parallel to form an array structure.

[0022] The semiconductor substrate 12 serves as the mechanical support base for the device and also provides electrical connection paths. In this embodiment, the semiconductor substrate 12 is a silicon substrate of a first conductivity type (e.g., P-type). In other embodiments, an N-type substrate may also be used.

[0023] The semiconductor epitaxial layer 11 is located on the semiconductor substrate 12 and is a single-crystal silicon layer used to form the active region of the microcell. The semiconductor epitaxial layer 11 has the same conductivity type (e.g., P-type) as the semiconductor substrate 12, but its doping concentration is lower than that of the semiconductor substrate 12, and its thickness is approximately 2-15 μm.

[0024] Multiple micro-units are formed in the semiconductor epitaxial layer 11 and connected in parallel. The number of micro-units can be set according to actual needs, and can be in the range of tens, hundreds, millions or tens of millions. A single micro-unit can be square, rectangular, hexagonal, octagonal or disc-shaped. Each micro-unit includes a second doped region 7, a third doped region 8, a trench structure, a third insulating layer 10, a conductive material 9, a quenching element 3, a first electrode 1 and a second electrode 2, etc.

[0025] The second doped region 7 is formed within the semiconductor epitaxial layer 11 and has a second conductivity type (e.g., N-type) opposite to that of the semiconductor substrate 12. The second doped region 7 is used to form an ohmic contact (electrical contact) and collect avalanche signals. When incident light enters the epitaxial layer, photogenerated carriers are generated, triggering avalanche breakdown and forming a detectable current pulse.

[0026] The third doped region 8, formed within the semiconductor epitaxial layer 11, is located below the second doped region 7 and forms a high-field region with the second doped region 7 to generate avalanche current. The third doped region 8 has the same conductivity type as the semiconductor substrate 12, such as P-type. Its function is to form a high-field region with the second doped region 7 to trigger the avalanche effect and guide photogenerated carriers towards the second doped region 7. The third doped region 8 is particularly important for back-incident structures because it helps collect photogenerated carriers entering from the back side.

[0027] The trench structure extends downward from the upper surface of the semiconductor epitaxial layer 11, at least partially surrounding the outer periphery of the second doped region 7. The main function of the trench structure is to isolate adjacent micro-cells and prevent optical and electrical crosstalk. The depth of the trench structure is determined according to the isolation requirements. Preferably, the trench structure penetrates the semiconductor epitaxial layer 11 and extends into the interior of the semiconductor substrate 12, with its bottom located inside the semiconductor substrate 12 to ensure adequate isolation.

[0028] A third insulating layer 10 is disposed on the inner sidewall of the trench structure. The function of the third insulating layer 10 is to electrically insulate the subsequently filled conductive material 9 from the semiconductor epitaxial layer 11. The third insulating layer 10 may be a silicon oxide layer. In a preferred embodiment, the third insulating layer 10 includes an oxide layer in contact with the semiconductor epitaxial layer 11 and a high-dielectric-constant material layer located inside the oxide layer. High-dielectric-constant materials, such as aluminum oxide, silicon nitride, hafnium oxide, etc., can optimize the optical effects inside the trench structure and further improve the corner breakdown voltage.

[0029] Conductive material 9 fills the trench structure and is insulated from the semiconductor epitaxial layer 11 by the third insulating layer 10. Conductive material 9 is in direct contact with the semiconductor substrate 12, thus forming an electrical connection and having the same potential. Conductive material 9 can be a metallic material, such as tungsten (W), copper (Cu), or aluminum (Al), or it can be a conductive material such as polycrystalline silicon. Conductive material 9 and the third insulating layer 10 together form an optical isolation structure, preventing secondary photons generated by one microcell from entering adjacent microcells and causing false triggering. Simultaneously, because conductive material 9 is at the same potential as the semiconductor substrate 12, it also provides a defined electrical boundary for each microcell, ensuring that the electrical environment of edge microcells is consistent with that of internal microcells in a multi-microcell structure, thereby solving the problem of uneven edge gain.

[0030] The quenching element 3 is connected in series with the second doped region 7 to quench the second doped region 7 and the resulting avalanche current. The quenching element 3 can be a polysilicon resistor integrated on-chip, with a typical resistance range of 100kΩ to 100MΩ. In other embodiments, the quenching element 3 can also be an externally introduced quenching resistor or an active quenching circuit. The function of the quenching element 3 is to reduce the voltage across the second doped region 7 and the substrate 12 below the breakdown voltage after an avalanche occurs, thereby quenching the avalanche and enabling the microcell to recover and detect the next photon.

[0031] The first electrode 1 is electrically connected to the second doped region 7 via the quenching element 3, and is used to extract signals from the front side. The first electrode 1 can be a metal pad, such as an aluminum (Al) pad, located on the front side of the device. The first electrode 1 is also connected to a first lead-out electrode 1a, which is used to further extract the signal from the first electrode 1 to an external circuit. When the microcell detects a photon and generates an avalanche current, the current flows through the quenching element 3 to the first electrode 1, and is then detected by the external readout circuit via the lead-out electrode of the first electrode 1.

[0032] The second electrode 2 is electrically connected to the conductive material 9 and is used to extract the potential of the semiconductor substrate 12 from the front side. The second electrode 2 and the conductive material 9 together form an electrical isolation boundary. The second electrode 2 can be a metal pad, such as an aluminum (Al) pad. The second electrode 2 is also connected to a second lead-out electrode 2a, which is used to further extract the potential of the second electrode 2 to an external circuit. Since the conductive material 9 and the semiconductor substrate 12 are at the same potential, applying a voltage through the second electrode 2 can make the entire trench structure an active electrical shield, ensuring that the electrical environment of each microcell is independent and uniform.

[0033] Example 2: like Figure 3 As shown, this embodiment, based on Embodiment 1, further specifies that the silicon photomultiplier is a back-incident structure. In the back-incident structure, light is incident from the back side of the semiconductor substrate 12.

[0034] To achieve back-incidence light, the semiconductor substrate 12 undergoes back-side thinning treatment, with a thickness of less than 2 μm, preferably around 1 μm. Theoretically, the thinner the substrate, the smaller the absorption loss of back-incidence light, and the higher the photon detection efficiency. While ensuring the mechanical strength of the device, the substrate thickness should be as thin as possible, for example, less than 1 μm.

[0035] After thinning, the bottom of the conductive material 9 is exposed outside the semiconductor substrate 12. In the back-side thinning process, when the conductive material 9 is exposed, it indicates that the predetermined thickness has been reached. Therefore, it can be used as a thickness reference point for the thinning process to achieve precise thickness control. On the other hand, the semiconductor substrate 12 can be formed into micro-nano structures, such as inverted pyramids and capillary structures, to reduce light reflection.

[0036] A microlens 14 is also disposed on the back side of the semiconductor substrate 12. The microlens 14 is used to focus incident light onto the semiconductor epitaxial layer 11, thereby improving photon detection efficiency. The microlens 14 can be a spherical lens, an aspherical lens, or a diffractive lens, and the material can be photoresist, silicon oxide, silicon nitride, etc. The size of the microlens 14 matches the microcell, with a typical size of several micrometers to tens of micrometers. The microlens 14 can be formed by photolithography and thermal reflow processes, or by nanoimprinting or etching processes.

[0037] The back-incident structure, combined with a thinned substrate and microlens 14, can significantly improve photon detection efficiency, making it particularly suitable for applications requiring high sensitivity, such as lidar and biofluorescence detection.

[0038] Example 3: like Figure 1 As shown, this embodiment, based on Embodiment 1, further defines the silicon photomultiplier as a normal incidence structure. In a normal incidence structure, light enters from the front of the device.

[0039] The forward incident structure also includes a third electrode layer 13, disposed at the bottom of the semiconductor substrate 12, serving as a back-side lead-out electrode. The third electrode layer 13 can be a metal layer, such as aluminum (Al), titanium (Ti), nickel (Ni), gold (Au), etc., or good ohmic contact and adhesion can be achieved through multilayer metal stacking. The third electrode layer 13 is electrically connected to the conductive material 9 through the semiconductor substrate 12, forming a complete electrical circuit.

[0040] Normal incidence structures are suitable for traditional front illumination applications, such as scintillator detectors and positron emission tomography.

[0041] Example 4: like Figure 1 and Figure 2 As shown, this embodiment further defines other structures based on Embodiment 1, Embodiment 2 or Embodiment 3.

[0042] Furthermore, in some embodiments, the trench structure penetrates the semiconductor epitaxial layer 11 and extends into the interior of the semiconductor substrate 12, with the bottom of the trench structure located inside the semiconductor substrate 12. This depth design ensures that the trench completely isolates the optical and electrical paths of adjacent microcells. If the trench only extends into the epitaxial layer, some light or charge carriers may still diffuse through the substrate to adjacent microcells, causing crosstalk. By extending the trench into the substrate, the crosstalk path can be completely cut off, achieving optimal isolation. The depth of the trench structure is determined based on the epitaxial layer thickness and the required isolation effect, while the width of the trench can be determined based on process capabilities and filler materials.

[0043] Furthermore, in some embodiments, the silicon photomultiplier further includes a first doped region 6 formed within the semiconductor epitaxial layer 11 and surrounding the second doped region 7. The first doped region 6 is used to improve the corner breakdown voltage. The first doped region 6 may partially or completely surround the second doped region 7. The second doped region 7 and the first doped region 6 have the same doping type, such as N-type, but the first doped region 6 has a lower doping concentration. The first doped region 6 acts as a protective ring, attracting and dispersing the electric field at the edge of the second doped region 7, preventing premature breakdown due to electric field concentration at the edge. When the first doped region 6 works synergistically with the conductive material 9, the electric field distribution at the edge of the second doped region 7 can be further optimized, improving the corner breakdown voltage.

[0044] The second doped region 7 has a first doping concentration, and the first doped region 6 has a second doping concentration lower than the first doping concentration. This concentration gradient causes the electric field peak to shift from the edge of the second doped region 7 to the first doped region 6, while the first doped region 6 is designed to withstand a higher electric field, thereby protecting the sensitive second doped region 7.

[0045] The depth of the first doped region 6 can be the same as or slightly deeper than the second doped region 7 to provide better protection. In terms of layout, the first doped region 6 closely surrounds the second doped region 7, and there may be slight overlap or direct contact between them.

[0046] Furthermore, in some embodiments, the trench structure is a continuous closed loop structure surrounding the outer periphery of the first doped region 6. A continuous closed loop structure means that the trench completely surrounds the first doped region 6 without any interruption. This design maximizes isolation, ensuring that the microcells have uniform electrical boundaries in all directions. In contrast, if the trench is segmented or discontinuous, weak points in isolation may exist in some directions, leading to crosstalk or electrical inhomogeneity. Continuous closed loop trenches can be achieved through photolithography and etching processes. In layout design, the trench pattern is a closed loop surrounding each microcell, and trenches of adjacent microcells can be shared to improve integration density.

[0047] Furthermore, in some embodiments, the doping concentration of the third doped region 8 may be the same as or different from that of the semiconductor epitaxial layer 11. The doping concentration of the third doped region 8 can be optimized according to the desired breakdown voltage and gain. For example, the doping concentration of the third doped region 8 may be slightly higher than that of the epitaxial layer to form a concentration gradient and enhance the guidance of charge carriers.

[0048] Preferably, the third doped region 8 has a larger horizontal dimension than the second doped region 7, thus completely covering the area below the second doped region 7 in the vertical projection. This ensures that photogenerated carriers entering from any angle can be effectively guided to the second doped region 7.

[0049] The third doped region 8 and the second doped region (7) are spaced apart in the vertical direction, and the vertical distance between them needs to be carefully designed. If the distance is too small, it may lead to excessive electric field coupling, affecting the breakdown characteristics; if the distance is too large, it may reduce the carrier collection efficiency.

[0050] Furthermore, in some embodiments, the silicon photomultiplier also includes a first insulating layer 4 and a second insulating layer 5 disposed above the semiconductor epitaxial layer 11, with the first insulating layer 4 located inside the second insulating layer 5. The top of the second doped region 7 contacts the bottom of the first insulating layer 4. This structure forms a precise contact window, ensuring reliable connection between the second doped region 7 and the electrodes or interconnect structures above it.

[0051] The first insulating layer 4 can be an antireflection layer, used in a normal incidence structure to reduce the reflection of incident light and improve photon detection efficiency. The material of the first insulating layer 4 can be silicon oxide, silicon nitride, aluminum oxide, or other composite materials, and the thickness is optimized according to the required antireflection wavelength.

[0052] The second insulating layer 5 can be a field oxide layer, used to isolate the electrodes and interconnects of different micro-units. The material of the second insulating layer 5 can be silicon oxide, with a relatively large thickness to provide good electrical isolation.

[0053] The combined structure of the first insulating layer 4 and the second insulating layer 5 provides both a precise contact window and excellent optical and electrical isolation. In the manufacturing process, the second insulating layer 5 can be deposited first, then an opening can be etched out, the first insulating layer 4 can be formed inside the opening, and finally, the top of the second doped region 7 can be exposed in a specific area by photolithography to form a contact.

[0054] Furthermore, in some embodiments, the third insulating layer 10 includes an oxide layer in contact with the semiconductor epitaxial layer 11 and a high-dielectric-constant material layer located inside the oxide layer. The oxide layer can be silicon oxide formed by thermal oxidation. The oxide layer has a high interface quality with silicon and a low defect density, which can effectively reduce the interface state density and dark count. The high-dielectric-constant material layer can be silicon nitride, aluminum oxide, hafnium oxide, etc. High-dielectric-constant materials have high dielectric constants and refractive indices, which can optimize the optical effects inside the trench, reduce light reflection and scattering at the trench boundaries, and further improve the corner breakdown voltage.

[0055] This multilayer third insulating layer 10 combines the high-quality interface of the oxide layer with the optical and electrical advantages of high dielectric constant materials, enabling simultaneous achievement of low dark count, high optical isolation, and high breakdown voltage.

[0056] By implementing this invention, the following beneficial effects are achieved: Gain uniformity improvement: By filling the trench with conductive material 9 and making it at the same potential as the substrate, a defined electrical boundary is provided for each micro-unit, so that the electrical environment of the edge micro-units is consistent with that of the inner micro-units, thus solving the problem of uneven edge gain in traditional structures.

[0057] Improved edge breakdown voltage: By using conductive material 9 instead of the traditional highly doped region as the electrode lead-out, the problem of premature edge breakdown caused by high doping between the trench structure and the second doped region is avoided. At the same time, the first doped region 6 acts as a guard ring to further attract and disperse the edge electric field, thereby improving the corner breakdown voltage.

[0058] Improved fill factor: The conductive material 9 fills the trenches, integrating electrode lead-out and electrical isolation functions without the need for additional highly doped regions, thereby improving the effective fill factor.

[0059] Enhanced optical isolation: The conductive material 9 and the third insulating layer 10 form an optical isolation structure, effectively preventing optical crosstalk.

[0060] Wide range of applications: It supports both back-incident and front-incident modes, and can be applied to a variety of application scenarios such as lidar, PET, and biological imaging.

[0061] It is understood that the above embodiments only illustrate preferred embodiments of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that for those skilled in the art, the above embodiments or technical features can be freely combined, and several modifications and improvements can be made without departing from the concept of the present invention. These all fall within the protection scope of the present invention. That is, the embodiments described "in some embodiments" can be freely combined with any of the embodiments above and below. Therefore, all equivalent transformations and modifications made within the scope of the claims of the present invention should fall within the scope of the claims of the present invention.

Claims

1. A silicon photomultiplier, characterized in that, include: Semiconductor substrate (12); A semiconductor epitaxial layer (11) is located on the semiconductor substrate (12); Multiple micro-units are formed in the semiconductor epitaxial layer (11) and connected in parallel, each micro-unit comprising: A second doped region (7) is formed within the semiconductor epitaxial layer (11); The third doped region (8) is formed in the semiconductor epitaxial layer (11), located below the second doped region (7), and forms a high field region with the second doped region (7) to generate avalanche current; The trench structure extends downward from the upper surface of the semiconductor epitaxial layer (11) and at least partially surrounds the outer periphery of the second doped region (7); A third insulating layer (10) is disposed on the inner sidewall of the trench structure; A conductive material (9) is filled in the trench structure and is insulated from the semiconductor epitaxial layer (11) through the third insulating layer (10), and is in direct contact with the semiconductor substrate (12), thereby forming an electrical connection with the semiconductor substrate (12) and forming an optical isolation structure with the third insulating layer (10); The quenching element (3) is connected in series with the second doped region (7) to quench the avalanche current; The first electrode (1) is electrically connected to the second doped region (7) through the quenching element (3) for drawing out signals from the front. The second electrode (2) is electrically connected to the conductive material (9), and together with the conductive material (9) forms an electrical isolation boundary, and is used to draw out the potential of the semiconductor substrate (12) from the front.

2. The silicon photomultiplier according to claim 1, characterized in that, The silicon photomultiplier is a back-incident structure; the thickness of the semiconductor substrate (12) is less than 2 μm, the bottom of the conductive material (9) is exposed outside the semiconductor substrate (12) and forms a surface micro-nano structure; a microlens (14) is also provided on the back side of the semiconductor substrate (12) to focus the incident light onto the semiconductor epitaxial layer (11).

3. The silicon photomultiplier according to claim 1, characterized in that, The silicon photomultiplier has a positive incident structure and also includes a third electrode layer (13) disposed at the bottom of the semiconductor substrate (12) as a back-side lead-out electrode.

4. The silicon photomultiplier according to any one of claims 1-3, characterized in that, The trench structure penetrates the semiconductor epitaxial layer (11) and extends into the interior of the semiconductor substrate (12), with the bottom of the trench structure located inside the semiconductor substrate (12).

5. The silicon photomultiplier according to any one of claims 1-3, characterized in that, It also includes a first doped region (6) formed within the semiconductor epitaxial layer (11) and surrounding the second doped region (7) to improve the corner breakdown voltage.

6. The silicon photomultiplier according to claim 5, characterized in that, The second doped region (7) has the same doping type as the first doped region (6), and the second doped region (7) has a first doping concentration, while the first doped region (6) has a second doping concentration lower than the first doping concentration.

7. The silicon photomultiplier according to claim 5, characterized in that, The trench structure is a continuous closed ring structure surrounding the outer periphery of the first doped region (6).

8. The silicon photomultiplier according to claim 1, characterized in that, The third doped region (8) has a different doping type than the second doped region (7), but has the same doping type as the semiconductor substrate (12) and the semiconductor epitaxial layer (11).

9. The silicon photomultiplier according to any one of claims 1-3, characterized in that, It also includes a first insulating layer (4) and a second insulating layer (5) disposed above the semiconductor epitaxial layer (11), wherein the first insulating layer (4) is located inside the second insulating layer (5), and the top of the second doped region (7) is in contact with the bottom of the first insulating layer (4).

10. The silicon photomultiplier according to any one of claims 1-3, characterized in that, The third insulating layer (10) includes an oxide layer in contact with the semiconductor epitaxial layer (11) and a high dielectric constant material layer located inside the oxide layer.

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