Secondary surface texturing method for silicon wafers and bc cells

Abstract

The application provides a secondary surface texturing method of a silicon wafer and a BC battery, and relates to the field of solar cells. The secondary surface texturing method of the silicon wafer comprises the following steps: depositing a protective layer on the back surface of the silicon wafer; immersing the silicon wafer with the deposited protective layer into an alkaline solution to perform primary texturing, so as to form a micron-textured surface on the front surface of the silicon wafer; performing plasma oxidation treatment on the silicon wafer subjected to the primary texturing, so as to deposit a passivation layer on the micron-textured surface; immersing the structure with the passivation layer into an acidic solution while performing ultrasonic treatment, so as to perform secondary texturing; and removing the protective layer on the back surface of the silicon wafer. The method provided by the application can reduce reflectivity, improve passivation effect, and improve light absorption efficiency, and solves the problems of poor uniformity of the existing technology, high energy consumption, and limited efficiency gain.

Description

Technical Field

[0001] This application relates to the field of solar cells, and more particularly to a secondary surface texturing method for silicon wafers and BC cells. Background Technology

[0002] BC (Browser-Coated) cells have no grid lines obstructing the front surface, allowing for ample sunlight exposure and significantly improving light utilization efficiency, thus achieving high conversion efficiency. Furthermore, BC cells offer an aesthetically pleasing appearance, expanding their potential applications. However, the high reflectivity of the silicon surface on the front of BC cells reduces light absorption efficiency, limiting further improvements in conversion efficiency. To address this issue, surface texturing technology, also known as texturing, has been introduced into the BC cell manufacturing process.

[0003] Traditional single-pass texturing processes typically rely solely on acidic or alkaline etching steps. However, single-pass texturing faces a key technological bottleneck: achieving an ideal balance between enhancing the light-trapping effect and improving surface passivation.

[0004] Current secondary texturing processes generally use the same etching solution for two treatments, which easily leads to a decrease in the uniformity of the texturized surface, resulting in localized over- or under-etching and thus affecting the consistency of battery performance. Furthermore, repeated etching processes may introduce new surface defects, further reducing battery conversion efficiency.

[0005] Furthermore, existing secondary texturing processes are more complex, adding a high-temperature annealing step before secondary texturing. However, high-temperature annealing is a complex process that requires sophisticated equipment and precise control of parameters such as annealing temperature, time, and atmosphere. Moreover, the high energy consumption of high-temperature annealing increases production costs, limiting its application and promotion in large-scale industrial production. Summary of the Invention

[0006] The purpose of this application is to provide a secondary surface texturing method for silicon wafers and a BC cell to solve the above-mentioned problems.

[0007] To achieve the above objectives, this application adopts the following technical solution: A method for secondary surface texturing of a silicon wafer, comprising: A protective layer is deposited on the back side of the silicon wafer; The silicon wafer with the protective layer deposited is immersed in an alkaline solution to perform a texturing process, forming a micron-textured surface on the front side of the silicon wafer. The silicon wafer that has undergone the first texturing process is subjected to plasma oxidation treatment to deposit a passivation layer on the micron-textured surface; The structure with the passivation layer is immersed in an acidic solution and simultaneously subjected to ultrasonic treatment for secondary texturing. Remove the protective layer on the back of the silicon wafer.

[0008] According to an embodiment of this application, the alkaline solution comprises NaOH solution and isopropanol, wherein the concentration of the NaOH solution is 2wt%-5wt%, and the volume ratio of the NaOH solution to the isopropanol is 1:(2-5).

[0009] According to an embodiment of this application, the temperature of the first texturing process is 60-80°C.

[0010] According to an embodiment of this application, the time for one fabrication process is 1.5-2.5 minutes.

[0011] According to an embodiment of this application, the plasma oxidation treatment is performed at a temperature of 20°C-25°C; And / or, the thickness of the passivation layer is 5-15 nm.

[0012] According to an embodiment of this application, the acidic solution contains HF, HNO3, water, and a corrosion inhibitor. The volume ratio of HF to HNO3 and water in the acidic solution is 1:(2-4):(5-10). The corrosion inhibitor accounts for 0.1%-0.5% of the total mass of the acidic solution. The corrosion inhibitor includes benzotriazole and thiourea.

[0013] According to an embodiment of this application, the frequency of the ultrasonic treatment is 18-22 kHz.

[0014] According to an embodiment of this application, the secondary texturing time is 0.5-1.5 min; And / or, the temperature of the secondary texturing is 55-65℃.

[0015] This application also provides a BC battery, which includes a product obtained by the secondary surface texturing method of the silicon wafer described above.

[0016] Compared with the prior art, the beneficial effects of this application include: The method of this application can improve the passivation effect and light absorption efficiency while reducing reflectivity, thus improving the problems of poor surface uniformity, high energy consumption and limited efficiency gain in the prior art. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.

[0018] Figure 1 This is a flowchart of the secondary surface texturing method for silicon wafers in this application; Figure 2 This is a schematic diagram of the structure of the product obtained by the secondary surface texturing method of the silicon wafer in this application; Figure 3 The image shown is the SEM image of Example 1 after secondary texturing. Detailed Implementation

[0019] As used in this article: "Prepared from" is synonymous with "comprising". The terms "comprising", "including", "having", "containing", or any other variations thereof as used herein are intended to cover non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not necessarily limited to those elements, but may include other elements not expressly listed or elements inherent to such composition, step, method, article, or apparatus.

[0020] The conjunction "composed of..." excludes any unspecified elements, steps, or components. If used in a claim, this phrase makes the claim closed, excluding materials other than those described, except for associated conventional impurities. When the phrase "composed of..." appears in a clause of the body of a claim rather than immediately following it, it limits only the elements described in that clause; other elements are not excluded from the claim as a whole.

[0021] When a quantity, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pair of any upper or preferred value with any lower or preferred value, regardless of whether the range is disclosed individually. For example, when the range “1–5” is disclosed, the described range should be interpreted as including ranges “1–4”, “1–3”, “1–2”, “1–2 and 4–5”, “1–3 and 5”, etc. When numerical ranges are described herein, unless otherwise stated, the range is intended to include its endpoints and all integers and fractions within that range.

[0022] In these embodiments, unless otherwise specified, the portions and percentages are all by weight.

[0023] "Parts by mass" refers to the basic unit of measurement that expresses the mass ratio of multiple components. One part can represent any unit mass, such as 1g or 2.689g. If we say that component A has "a" parts by mass and component B has "b" parts by mass, it means the ratio of the mass of component A to the mass of component B is a:b. Alternatively, it can mean that the mass of component A is aK and the mass of component B is bK (where K is any number representing a multiplier). It is important to understand that, unlike parts by mass, the sum of the mass parts of all components is not limited to 100 parts.

[0024] "And / or" is used to indicate that one or both of the described situations may occur, for example, A and / or B includes (A and B) and (A or B).

[0025] To better illustrate the technical solution provided in this application, the technical solution will be described in its entirety before the embodiments, as follows: A secondary surface texturing method for silicon wafers, referenced Figure 1 ,include: A protective layer is deposited on the back side of the silicon wafer; The silicon wafer with the protective layer deposited is immersed in an alkaline solution to perform a texturing process, forming a micron-textured surface on the front side of the silicon wafer. The silicon wafer that has undergone the first texturing process is subjected to plasma oxidation treatment to deposit a passivation layer on the micron-textured surface; The structure with the passivation layer is immersed in an acidic solution and simultaneously subjected to ultrasonic treatment for secondary texturing. Remove the protective layer on the back of the silicon wafer.

[0026] The method of this application can improve the passivation effect and light absorption efficiency while reducing reflectivity, thus improving the problems of poor surface uniformity, high energy consumption and limited efficiency gain in the prior art.

[0027] Moreover, the method described in this application is simple to operate, omitting the complex process of high-temperature annealing. In addition, the method described in this application has the advantage of process compatibility, as it is compatible with existing production line equipment (texturing tank, ultrasonic equipment), resulting in low modification costs.

[0028] According to an embodiment of this application, the alkaline solution comprises NaOH solution and isopropanol, wherein the concentration of the NaOH solution is 2%-5%, and the volume ratio of the NaOH solution to the isopropanol is 1:(2-5).

[0029] Isopropanol can adsorb onto the silicon wafer surface to form a protective film, slowing down the corrosion rate of silicon by NaOH. Specifically, the hydrophilic groups (-OH) in the isopropanol molecule bind to the silicon surface, while the lipophilic groups (-CH3) form a hydrophobic layer, which can inhibit excessive corrosion, reduce surface roughness, and optimize surface morphology. Furthermore, as a solvent, isopropanol can reduce the evaporation rate of NaOH, maintain solution concentration stability, and avoid sudden changes in localized corrosion rates caused by water evaporation. Simultaneously, the polar properties of isopropanol can promote the uniform dispersion of NaOH molecules, improving the consistency of the textured surface morphology.

[0030] When the concentration of NaOH solution is 2%-5%, it ensures that isopropanol molecules are fully adsorbed onto the silicon surface, forming a continuous protective film. If the concentration of NaOH solution is too low, the protective film coverage will be insufficient, the corrosion rate will be high, and the textured surface formation will be affected. If the concentration of NaOH solution is too high, isopropanol residue will remain, contaminating the subsequent passivation layer, and the density of interfacial states (DIT) will decrease from 3.8 × 10⁻⁶. 9 Increased to 1.2×10 10 cm -2 ·eV -1 This affects the passivation effect.

[0031] For example, the concentration of the NaOH solution can be 2%, 3%, 4%, 5%, or any value between 2% and 5%.

[0032] According to embodiments of this application, the temperature of the primary texturing process is 60-80°C. Primary texturing can generate micron-scale pyramid structures, reducing surface damage and effectively avoiding silicon wafer surface damage and dislocation multiplication caused by traditional high-temperature texturing, thus reducing carrier recombination. The primary texturing process of this application is performed at a lower temperature, which has the advantage of reduced energy consumption, avoids thermal stress damage to the silicon wafer, reduces lattice defects, and improves minority carrier lifetime (τ≥10μs).

[0033] For example, the temperature for a single flocking process can be any value between 60℃, 62℃, 65℃, 67℃, 70℃, 72℃, 75℃, 77℃, 80℃, or 60-80℃.

[0034] According to an embodiment of this application, the time for one fabrication cycle is 1.5-2.5 minutes. For example, the time for one fabrication cycle can be any value between 1.5 minutes, 2 minutes, 2.5 minutes, or 1.5-2.5 minutes.

[0035] In some embodiments, the angle between the base and the hypotenuse of the pyramid in the microtextured surface is 50°-58°. This pyramid structure, serving as the first light-trapping structure of the battery, has a reflectivity of approximately 15% for incident light, effectively enhancing the battery's light absorption capacity. The pyramid in the microtextured surface of this application has a large tilt angle; after light is reflected from the pyramid surface, its propagation direction changes, making it more likely to enter the battery and be absorbed, rather than being directly reflected back to the outside. This reduces "ineffective light blocking" caused by direct reflection of light from the battery surface.

[0036] In some embodiments, micron-textured refers to a textured surface with a base size in the micrometer range.

[0037] According to embodiments of this application, the plasma oxidation treatment is performed at a temperature of 20-25°C, which can avoid the damage to the textured surface caused by traditional high-temperature annealing. Furthermore, the plasma oxidation treatment performed at 20-25°C can replace the traditional high-temperature annealing (850°C H2 annealing) process, avoiding the collapse of the textured surface at high temperatures, while generating a high-quality passivation layer.

[0038] And / or, the thickness of the passivation layer is 5-15 nm. The amorphous silicon layer passivates the dangling bonds on the silicon surface through chemical bonding, and the silicon oxide layer reduces interface defects through physical barriers. When the thickness of the passivation layer is within the above range, the Dit can be reduced to 1.5 × 10⁻⁶. 11 cm -2 The following measures reduce interfacial recombination. Furthermore, when the passivation layer thickness is within the aforementioned range, electrons can tunnel through the passivation layer, reducing carrier recombination losses and increasing Voc by 3-4 mV.

[0039] For example, the thickness of the passivation layer can be any value between 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, or 5-15nm.

[0040] Furthermore, the passivation layer includes a stacked amorphous silicon layer and a silicon oxide layer, as shown in the reference. Figure 2 The amorphous silicon layer is located between the micron-textured surface and the silicon oxide layer. The passivation layer can further reduce the interface state density, reduce carrier recombination, and increase the open-circuit voltage (Voc).

[0041] In some embodiments, the thickness of the amorphous silicon layer is 3-10 nm, and the thickness of the silicon oxide layer is 2-5 nm.

[0042] For example, the thickness of the amorphous silicon layer can be any value between 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm or 3-10nm, and the thickness of the silicon oxide layer can be any value between 2nm, 3nm, 4nm, 5nm or 2-5nm.

[0043] According to an embodiment of this application, the acidic solution contains HF, HNO3, water, and a corrosion inhibitor. The volume ratio of HF to HNO3 and water in the acidic solution is 1:(2-4):(5-10). The corrosion inhibitor accounts for 0.1%-0.5% of the total mass of the acidic solution. The corrosion inhibitor includes benzotriazole and thiourea.

[0044] Isotropic etching can be formed in the acidic solution of this application. Specifically, HF can dissolve silicon oxide (SiO₂). x HNO3 selectively removes surface defects in the passivation layer. HNO3 provides an oxidizing environment, promoting the formation of a SiO2 mask on the silicon surface and controlling the etching morphology. The mixed acid solution of HF and HNO3 is highly corrosive to the metallized areas of the silicon wafer (electrodes, edges). The corrosion inhibitor forms a protective film on the metal surface by adsorbing onto the metal, which can reduce the corrosion caused by HNO3. + The corrosion inhibitor prevents increased contact resistance and leakage risks from metal corrosion. Furthermore, the inhibitor preferentially adsorbs on defect areas (scratches, grain boundaries), suppressing localized over-etching and ensuring uniform texture. Additionally, the inhibitor reduces HNO3 volatilization in acid mist, lowering the environmental toxicity of the operation. When the content of each component in the acidic solution is within the above-mentioned range, it can uniformly remove protrusions on the passivation layer surface, forming a uniform nanoscale texture. Moreover, HNO3 preferentially oxidizes silicon, and HF selectively dissolves the oxide layer, preventing excessive corrosion.

[0045] If the HF content in the acidic solution is too low, the passivation layer defects cannot be effectively removed, and the surface state density (Dit) increases to 5 × 10⁻⁶. 11 cm -2 This leads to increased carrier recombination and a 4mV decrease in Voc. If the HF content in the acidic solution is too high, it can easily penetrate the passivation layer and damage the silicon interface, increasing the interface recombination rate and resulting in an excessively fast etching rate (>200nm / min), forming irregular nanostructures, increasing reflectivity, and affecting the etching effect.

[0046] For example, the volume ratio of HF to HNO3 and water in the acidic solution can be any value between 1:2:5, 1:2:10, 1:4:5, 1:4:10, 1:3:5, 1:3:7, 1:3:10 or 1:(2-4):(5-10).

[0047] The corrosion inhibitor accounts for any value between 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, or 0.1%-0.5% of the total mass of the acidic solution.

[0048] In some embodiments, the mass ratio of benzotriazole to thiourea can be 1:1.

[0049] According to embodiments of this application, the frequency of the ultrasonic treatment is 18-22 kHz. Ultrasonic waves induce the formation and collapse of cavitation bubbles. When the ultrasonic frequency is within the aforementioned range, the microjets generated by the collapse of cavitation bubbles can efficiently scour the silicon surface. Compared to traditional static etching methods, which easily form striped textured surfaces on the silicon surface, leading to localized over-etching, the scouring mechanism based on the ultrasonic cavitation effect of this application can effectively avoid localized over-etching of the silicon surface, thereby ensuring the uniformity and quality of the silicon surface treatment.

[0050] Specifically, when the ultrasonic frequency is within the aforementioned range, the cavitation bubble size is relatively large (approximately 100-300 μm), and the collapse generates a high-intensity microjets (velocity >10 m / s), which can efficiently scour the passivation layer defects on the silicon surface, avoiding the striped textured surface of traditional static etching. Furthermore, under the action of ultrasound within the aforementioned frequency range, the cavitation effect and chemical corrosion are synergistically enhanced in acidic solutions. The microjets preferentially peel away the protruding parts of the passivation layer, avoiding excessive corrosion in flat areas. Cavitation vibrations promote the formation of a dense SiO2 mask on the HNO3 silicon oxide surface, reducing lateral etching. If the ultrasonic treatment frequency is too low, the cavitation bubble diameter will be >300 μm, and the collapse impact force will be too strong (>15 m / s). Excessive scouring will cause micro-pits on the silicon surface, disrupting the regularity of the textured surface. If the ultrasonic treatment frequency is too high, the cavitation bubble diameter will be <50 μm, and the collapse impact force will be weak (<5 m / s). Insufficient microjets will result in ineffective removal of passivation layer defects, and the remaining protrusions will lead to increased light reflectivity.

[0051] In some embodiments, the frequency of ultrasonic processing can be any value between 18 kHz, 19 kHz, 20 kHz, 21 kHz, 22 kHz, or 18-22 kHz.

[0052] According to an embodiment of this application, the time for the secondary texturing is 0.5-1.5 min; for example, the time for the secondary texturing can be any value between 0.5 min, 1 min, 1.5 min, or 0.5-1.5 min.

[0053] And / or, the temperature of the secondary texturing is 55-65°C. For example, the temperature of the secondary texturing can be any value between 55°C, 57°C, 60°C, 62°C, 65°C, or 55-65°C.

[0054] In some embodiments, a nano-textured surface can be formed through secondary texturing, where the size of the base of the texturized surface is at the nanometer level.

[0055] Through secondary texturing, nanoscale random pyramids can be formed on the passivation layer, constructing a multi-scale composite textured surface structure. Specifically, through acid etching, nanoparticles with a size of approximately 200-500 nm can be formed, creating multi-scale light scattering paths with the micron-structure and extending the optical path. This application utilizes multiple reflections of light at the micron-nano interface to reduce the reflectivity of incident light to below 3%, further enhancing the battery's light absorption capacity. Simultaneously, the nanostructure passivates surface dangling bonds.

[0056] In some embodiments, the material forming the protective layer includes phosphosilicate glass; The thickness of the protective layer is 10-30 nm; The protective layer can be formed by chemical vapor deposition. Removing the protective layer from the back of the silicon wafer includes immersing the silicon wafer, which has undergone the secondary texturing, in a 5wt%-10wt% aqueous HF solution.

[0057] Before texturing, this application deposits a protective layer on the back side of the silicon wafer to protect the back side of the wafer, allowing the front side of the wafer to be exposed to alkaline or acidic solutions. After texturing is completed, the protective layer on the back side of the silicon wafer can be removed by wet etching.

[0058] This application also provides a BC battery, which includes a product obtained by the secondary surface texturing method of the silicon wafer described above.

[0059] Furthermore, the reflectivity of the textured surface on the front of the BC battery is ≤3%, and Jsc ≥ 41 mA / cm². 2 .

[0060] The implementation schemes of this application will be described in detail below with reference to specific embodiments. However, those skilled in the art will understand that the following embodiments are only for illustrating this application and should not be regarded as limiting the scope of this application. Unless otherwise specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments used without specified manufacturers are all conventional products that can be purchased commercially.

[0061] Example 1 Example 1 provides a secondary surface texturing method for silicon wafers, comprising: (1) Deposition of protective layer: After the silicon wafer is pre-cleaned, a phosphosilicate glass film with a thickness of 20 nm is deposited on the back of the silicon wafer by chemical vapor deposition. (2) Texturing in one step: The silicon wafer with the protective layer deposited is immersed in an alkaline solution, which includes NaOH solution and isopropanol. The concentration of NaOH solution is 4wt%, and the volume ratio of NaOH solution to isopropanol is 1:3.5. The wafer is treated at 70℃ for 2 minutes to form a micron-textured surface. (3) Forming a passivation layer: At 22°C, a 10nm passivation layer is generated by plasma oxidation. The passivation layer includes an amorphous silicon layer with a thickness of 7nm and a silicon oxide layer with a thickness of 3nm. (4) Secondary texturing: The silicon wafer treated in step (3) is immersed in an acidic solution, which includes HF, HNO3, water and corrosion inhibitor. The volume ratio of HF to HNO3 and water is 1:3:7. The corrosion inhibitor accounts for 0.4% of the total mass of the acidic solution. The corrosion inhibitor includes benzotriazole and thiourea in a mass ratio of 1:1. At a temperature of 60°C, it is treated with 20kHz ultrasound for 1 min to form a nanotextured surface. (5) Remove the protective layer: Immerse the silicon wafer treated in step (4) in an 8wt% HF aqueous solution and perform wet etching to remove the protective layer.

[0062] Figure 3 This is the SEM image of Example 1 after secondary texturing. Figure 3 It includes a micron-sized tower base (1.5µm) after primary texturing and a nano-sized tower base (200nm-500nm) after secondary texturing.

[0063] Example 2 Example 2 provides a secondary surface texturing method for silicon wafers, comprising: (1) Deposition of protective layer: After the silicon wafer is pre-cleaned, a phosphosilicate glass film with a thickness of 10 nm is deposited on the back of the silicon wafer by chemical vapor deposition. (2) Texturing in one step: The silicon wafer with the protective layer deposited is immersed in an alkaline solution, which includes NaOH solution and isopropanol. The concentration of NaOH solution is 4wt%, and the volume ratio of NaOH solution to isopropanol is 1:3.5. The wafer is treated at 70℃ for 1.5 min to form a micron-textured surface. (3) Forming a passivation layer: At 20°C, a 5nm passivation layer is generated by plasma oxidation. The passivation layer includes an amorphous silicon layer with a thickness of 3nm and a silicon oxide layer with a thickness of 2nm. (4) Secondary texturing: The silicon wafer treated in step (3) is immersed in an acidic solution, which includes HF, HNO3, water and corrosion inhibitor. The volume ratio of HF to HNO3 and water is 1:2:5. The corrosion inhibitor accounts for 0.4% of the total mass of the acidic solution. The corrosion inhibitor includes benzotriazole and thiourea in a mass ratio of 1:1. At a temperature of 55°C, it is treated with 18kHz ultrasound for 30s to form a nanotextured surface. (5) Remove the protective layer: Immerse the silicon wafer treated in step (4) in a 5wt% HF aqueous solution and perform wet etching to remove the protective layer.

[0064] Example 3 Example 3 provides a secondary surface texturing method for silicon wafers, comprising: (1) Deposition of protective layer: After the silicon wafer is pre-cleaned, a phosphosilicate glass film with a thickness of 30 nm is deposited on the back of the silicon wafer by chemical vapor deposition. (2) One-time texturing: The silicon wafer with the protective layer deposited is immersed in an alkaline solution, which includes NaOH solution and isopropanol. The concentration of NaOH solution is 4wt%, and the volume ratio of NaOH solution to isopropanol is 1:3.5. The wafer is treated at 70℃ for 2.5 min to form a micron-textured surface. (3) Forming a passivation layer: At 25°C, a 15nm passivation layer is generated by plasma oxidation. The passivation layer includes an amorphous silicon layer with a thickness of 10nm and a silicon oxide layer with a thickness of 5nm. (4) Secondary texturing: The silicon wafer treated in step (3) is immersed in an acidic solution, which includes HF, HNO3, water and corrosion inhibitor. The volume ratio of HF to HNO3 and water is 1:4:10. The corrosion inhibitor accounts for 0.4% of the total mass of the acidic solution. The corrosion inhibitor includes benzotriazole and thiourea in a mass ratio of 1:1. The wafer is treated with 18kHz ultrasound for 1.5 minutes at 65°C to form a nanotextured surface. (5) Remove the protective layer: Immerse the silicon wafer treated in step (4) in a 10wt% HF aqueous solution and perform wet etching to remove the protective layer.

[0065] Comparative Example 1 (1) Deposition of protective layer: After the silicon wafer is pre-cleaned, a phosphosilicate glass film with a thickness of 15 nm is deposited on the back of the silicon wafer by chemical vapor deposition. (2) Immerse the silicon wafer with the protective layer deposited in an alkaline solution, the alkaline solution being a NaOH solution with a concentration of 5 wt%, and treat at 80°C for 3 min to form a textured surface; (3) HNO3 / HF static etching: The silicon wafer treated in step (2) is immersed in an acidic solution, which includes HF, HNO3 and water. The volume ratio of HF to HNO3 and water is 1:3:5. The wafer is treated at 72°C for 5 minutes. (4) Remove the protective layer: Immerse the silicon wafer treated in step (3) in an 8wt% HF aqueous solution and perform wet etching to remove the protective layer.

[0066] Comparative Example 2 The other parameters are the same as in Example 1, except that ultrasonic treatment was not used in step (4) of Comparative Example 2.

[0067] The products prepared in Examples 1-3 and Comparative Examples 1-2 were subsequently passivated, metallized, and tested. The test results are shown in Table 1.

[0068] Table 1. Comparison of test results between Examples 1-3 and Comparative Examples 1-2

[0069] The reflectance of Examples 1-3 is lower than that of Comparative Examples 1-2, while the Jsc of Examples 1-3 is higher than that of Comparative Examples 1-2. This indicates that the method of this application can improve the passivation effect and enhance the light absorption efficiency while reducing reflectance.

[0070] Specifically, compared with Comparative Example 1, the reflectivity of Example 1 decreased by 81%, and the Jsc increased by 4.5%.

[0071] Compared with Comparative Example 2, Example 1 uses ultrasonic assistance, which can reduce surface defects by 44% and reduce carrier recombination.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0073] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the foregoing claims, any of the claimed embodiments can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

Claims

1. A method for secondary surface texturing of a silicon wafer, characterized in that, include: A protective layer is deposited on the back side of the silicon wafer; The silicon wafer with the protective layer deposited is immersed in an alkaline solution to perform a texturing process, forming a micron-textured surface on the front side of the silicon wafer. The silicon wafer that has undergone the first texturing process is subjected to plasma oxidation treatment to deposit a passivation layer on the micron-textured surface; The structure with the passivation layer is immersed in an acidic solution and simultaneously subjected to ultrasonic treatment for secondary texturing. Remove the protective layer on the back of the silicon wafer.

2. The secondary surface texturing method for silicon wafers according to claim 1, characterized in that, The alkaline solution comprises NaOH solution and isopropanol, wherein the concentration of the NaOH solution is 2wt%-5wt% and the volume ratio of the NaOH solution to the isopropanol is 1:(2-5).

3. The secondary surface texturing method for silicon wafers according to claim 1, characterized in that, The temperature for the first fabrication process is 60-80℃.

4. The secondary surface texturing method for silicon wafers according to claim 3, characterized in that, The time for one pass of the flocking process is 1.5-2.5 minutes.

5. The secondary surface texturing method for silicon wafers according to claim 1, characterized in that, The plasma oxidation treatment is carried out at a temperature of 20℃-25℃; And / or, the thickness of the passivation layer is 5-15 nm.

6. The secondary surface texturing method for silicon wafers according to claim 1, characterized in that, The acidic solution contains HF, HNO3, water, and a corrosion inhibitor. The volume ratio of HF to HNO3 and water in the acidic solution is 1:(2-4):(5-10). The corrosion inhibitor accounts for 0.1%-0.5% of the total mass of the acidic solution. The corrosion inhibitor includes benzotriazole and thiourea.

7. The secondary surface texturing method for silicon wafers according to claim 1, characterized in that, The frequency of the ultrasonic treatment is 18-22 kHz.

8. The secondary surface texturing method for silicon wafers according to claim 1, characterized in that, The secondary texturing time is 0.5-1.5 minutes.

9. The secondary surface texturing method for silicon wafers according to any one of claims 1-8, characterized in that, The temperature for the secondary texturing process is 55-65℃.

10. A BC battery, characterized in that, The BC battery includes products obtained by the secondary surface texturing method of the silicon wafer according to any one of claims 1-9.

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