A back contact cell LPCVD polysilicon deposition method based on turbulence suppression and interface optimization, a BC cell and a photovoltaic system

Abstract

The application provides a back contact cell LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization, a BC cell and a photovoltaic system, and relates to the field of solar cells. The method comprises the following steps: a tunneling oxide layer is arranged on the back surface of the N-type CZ silicon wafer, and a super-dense polycrystalline silicon transition layer is arranged on the surface of the tunneling oxide layer through a rapid pressure reduction stage and a super-dense layer deposition stage; and then a main body polycrystalline silicon layer is arranged on the surface of the super-dense polycrystalline silicon transition layer through a main body layer deposition stage. The method establishes a high-density transition layer in the super-dense layer deposition stage, and realizes grain gradient growth in the main body layer deposition stage, and has the advantages of suppressing turbulence effect, optimizing interface structure, and improving the uniformity and density of the polycrystalline silicon layer.

Description

Technical Field

[0001] This application relates to the field of solar cells, and more particularly to a back-contact LPCVD polycrystalline silicon deposition method for solar cells based on turbulence suppression and interface optimization, as well as BC cells and photovoltaic systems. Background Technology

[0002] In the manufacturing process of back contact (BC) cells, such as interdigitated back contact (TBC) or heterojunction back contact (IBC) cells, the polycrystalline silicon layer serves as a key functional layer for efficient carrier transport and surface passivation. The uniformity and density of this layer have a decisive impact on the final cell conversion efficiency. Currently, the industry commonly uses low-pressure chemical vapor deposition (LPCVD) to prepare this polycrystalline silicon layer. To improve production efficiency, traditional LPCVD processes typically employ high-speed deposition modes (deposition rates greater than 5 nm / min). However, under these high-speed deposition conditions, the airflow within the reaction chamber easily forms turbulence (Reynolds number Re > 3000) at the substrate edge region, leading to the following technical problems:

[0003] Film quality defects: The direct impact effect of gas caused by turbulence causes the density of the polycrystalline silicon layer to be significantly reduced in a specific area (such as within about 5 mm of the substrate edge) (porosity greater than 5%), forming a visually visible white edge defect.

[0004] Electrical performance degradation: The aforementioned defective regions lead to a significant decrease in local minority carrier lifetime (below 100 μs) and an increase in contact resistance (above 5 mΩ·cm). 2 This causes electrical losses;

[0005] Insufficient process stability: Turbulent disturbances cause unstable deposition rates (fluctuation range of approximately ±15%), and film thickness uniformity deteriorates to over 8%.

[0006] Existing technologies have significant limitations in addressing the aforementioned problems. For example, attempts to improve film density by increasing deposition temperature (above 600℃) significantly increase the thermal budget and may lead to substrate warping. Multi-step deposition methods have also been used to mitigate uniformity issues; however, these methods significantly increase the complexity and control difficulty of the process steps. Therefore, there is an urgent need to solve the problems of uneven film thickness and poor film density caused by deposition. Summary of the Invention

[0007] The purpose of this application is to provide a back-contact LPCVD polycrystalline silicon deposition method for solar cells based on turbulence suppression and interface optimization, as well as BC cells and photovoltaic systems, to solve the above-mentioned problems.

[0008] To achieve the above objectives, this application adopts the following technical solution:

[0009] This application provides a back-contact solar cell LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization, the method comprising:

[0010] A tunneling oxide layer is formed on the back side of the N-type CZ silicon wafer, and an ultra-dense polycrystalline silicon transition layer is formed on the surface of the tunneling oxide layer after a rapid voltage reduction stage and an ultra-dense layer deposition stage; then a main polycrystalline silicon layer is formed on the surface of the ultra-dense polycrystalline silicon transition layer after a main layer deposition stage.

[0011] Furthermore, the rapid depressurization phase reduces the pressure from atmospheric pressure to 5-20 Pa within 5 seconds.

[0012] Furthermore, in the ultra-dense layer deposition stage, the reaction temperature is 480-520℃, the pressure is reduced to 10-15Pa at a rate of 2Pa / s, the deposition time is 1-4min, the flow ratio of SiH4 to H2 is 1:9.7-10.3, and the partial pressure of H2 accounts for no less than 90%.

[0013] Furthermore, during the main layer deposition stage, the reaction temperature is 480-580℃, the pressure is 20.5-21.5Pa, and the reaction time is 60-90min.

[0014] This application also provides a BC battery, which is prepared according to the back contact battery LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization.

[0015] Furthermore, the thickness of the ultra-dense polycrystalline silicon transition layer is 1-5 nm.

[0016] Furthermore, the thickness of the main polycrystalline silicon layer is 180-220 nm.

[0017] Furthermore, the grain size of the ultra-dense polycrystalline silicon transition layer is 5-8 nm, and the density is not less than 98%.

[0018] Furthermore, the grain size of the main polycrystalline silicon layer is 10-30 nm, and the grain size gradually increases from the ultra-dense polycrystalline silicon transition layer to the surface layer of the main polycrystalline silicon layer.

[0019] Furthermore, the uniformity of the film thickness of the BC battery is no higher than 3%.

[0020] This application also provides a photovoltaic system including the BC cell.

[0021] Compared with the prior art, the beneficial effects of this application include:

[0022] This application provides a back-contact LPCVD polycrystalline silicon deposition method, BC cell, and photovoltaic system based on turbulence suppression and interface optimization. By controlling the deposition parameters in stages, turbulence formation is effectively suppressed during the rapid voltage reduction stage, a highly dense transition layer is established during the ultra-dense layer deposition stage, and grain gradient growth is achieved during the main layer deposition stage. This method has the advantages of suppressing turbulence effects, optimizing interface structure, and improving the uniformity and density of the polycrystalline silicon layer. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.

[0024] Figure 1 This is a schematic diagram of the BC battery structure provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the process flow for preparing a back contact battery based on turbulence suppression and interface optimization, provided for an example.

[0026] The main label information in the attached figure is as follows:

[0027] 1-N-type CZ silicon wafer; 2-Flint-penetrating oxide layer; 3-Ultra-dense polycrystalline silicon transition layer; 4-Main polycrystalline silicon layer. Detailed Implementation

[0028] As used in this article:

[0029] "Prepared from" is synonymous with "comprising". The terms "comprising", "including", "having", "containing", or any other variations thereof as used herein are intended to cover non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not necessarily limited to those elements, but may include other elements not expressly listed or elements inherent to such composition, step, method, article, or apparatus.

[0030] The conjunction "composed of..." excludes any unspecified elements, steps, or components. If used in a claim, this phrase makes the claim closed, excluding materials other than those described, except for associated conventional impurities. When the phrase "composed of..." appears in a clause of the body of a claim rather than immediately following it, it limits only the elements described in that clause; other elements are not excluded from the claim as a whole.

[0031] When a quantity, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pair of any upper or preferred value with any lower or preferred value, regardless of whether the range is disclosed individually. For example, when the range “1–5” is disclosed, the described range should be interpreted as including ranges “1–4”, “1–3”, “1–2”, “1–2 and 4–5”, “1–3 and 5”, etc. When numerical ranges are described herein, unless otherwise stated, the range is intended to include its endpoints and all integers and fractions within that range.

[0032] In these embodiments, unless otherwise specified, the portions and percentages are all by weight.

[0033] "Parts by mass" refers to the basic unit of measurement that expresses the mass ratio of multiple components. One part can represent any unit mass, such as 1g or 2.689g. If we say that component A has "a" parts by mass and component B has "b" parts by mass, it means the ratio of the mass of component A to the mass of component B is a:b. Alternatively, it can mean that the mass of component A is aK and the mass of component B is bK (K is any number representing a multiplier). It is important to understand that, unlike the number of parts by mass, the sum of the mass parts of all components is not limited to 100 parts.

[0034] "And / or" is used to indicate that one or both of the described situations may occur, for example, A and / or B includes (A and B) and (A or B).

[0035] In existing technologies, the deposition process of polycrystalline silicon layers in the manufacturing of back-contact solar cells faces challenges such as film quality defects caused by turbulence, degradation of electrical performance, and insufficient process stability. Traditional methods attempt to improve film performance by increasing deposition temperature or adding process steps, but these methods suffer from drawbacks such as excessively high thermal budgets or increased process complexity, making it difficult to balance efficiency and quality. For example, in high-speed deposition modes, turbulence at the edges of the reaction chamber leads to a decrease in film density, resulting in visible defects and affecting electrical performance.

[0036] To address these issues, the inventors discovered that turbulence formation is closely related to the rate of pressure change; slow depressurization easily generates pressure gradients, which in turn induce gas flow turbulence. Simultaneously, insufficient interfacial bonding strength exacerbates stress concentration in the film. Therefore, a staged deposition strategy needs to be designed to suppress turbulence generation through rapid depressurization and to construct an ultra-dense transition layer to optimize interfacial bonding. Further consideration is given to the synergistic control of process parameters to improve film uniformity while maintaining the deposition rate.

[0037] To better explain the technical solution of this application, an overall description of the technical solution will be given before proceeding with specific implementation methods.

[0038] This application provides a back-contact solar cell LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization, the method comprising:

[0039] A tunneling oxide layer is formed on the back side of the N-type CZ silicon wafer, and an ultra-dense polycrystalline silicon transition layer is formed on the surface of the tunneling oxide layer after a rapid voltage reduction stage and an ultra-dense layer deposition stage; then a main polycrystalline silicon layer is formed on the surface of the ultra-dense polycrystalline silicon transition layer after a main layer deposition stage.

[0040] Specifically, after constructing a tunneling oxide layer on the surface of an N-type CZ silicon wafer, a rapid depressurization stage is first used to eliminate the pressure gradient in the traditional depressurization process, suppressing gas turbulence generation. Subsequently, in the ultra-dense layer deposition stage, a transition layer with high bonding strength is formed by precisely controlling the proportion of reactive gases and temperature conditions. This transition layer serves as the substrate for subsequent deposition, effectively reducing the density of interface defects. Finally, optimized pressure parameters are used in the main layer deposition stage to achieve uniform deposition while suppressing turbulence recurrence. Through the synergistic effect of these three stages, turbulence suppression and interface optimization are simultaneously achieved under high-speed deposition conditions.

[0041] Compared with existing technologies, current solutions often employ single deposition parameters or add auxiliary process steps, failing to fundamentally solve the coupling problem between turbulence and interfacial stress. This solution eliminates turbulence generation conditions in the early stages of the process by controlling deposition parameters in stages, while simultaneously constructing an ultra-dense transition layer to strengthen interfacial bonding. This avoids the risk of substrate deformation caused by high-temperature processing and eliminates the need for additional process steps.

[0042] Through the above technical solutions, this application effectively suppresses turbulence disturbances during polycrystalline silicon deposition, eliminates film defects at substrate edges, and improves film thickness uniformity. The construction of the transition layer enhances interfacial bonding strength, reduces contact resistance, and improves carrier transport efficiency. The synergistic control of process parameters ensures the deposition rate while simultaneously optimizing film density and electrical properties.

[0043] In an optional implementation, the rapid depressurization phase reduces the pressure from atmospheric pressure to 5-20 Pa within 5 seconds.

[0044] Specifically, during the initial stage of the deposition process, when the chamber pressure drops abruptly from atmospheric pressure to 15 Pa within 5 seconds, gas molecules experience high-speed directional flow due to the abrupt change in pressure gradient. At this moment, the mean free path of the gas molecules rapidly expands from the micrometer level to the millimeter level, resulting in a sharp decrease in the frequency of intermolecular collisions. This state allows the reactive gas to form a uniform laminar flow coverage on the substrate surface, avoiding eddy currents caused by local pressure fluctuations. Simultaneously, the instantaneous high pressure differential created by the rapid pressure drop drives the silane-hydrogen mixture to deposit perpendicularly along the substrate normal, eliminating the turbulence initiation conditions caused by gas stagnation in the edge regions.

[0045] Through the above technical solution, this application establishes a stable laminar flow environment in the early stage of polycrystalline silicon deposition, eliminating the turbulent initiation conditions caused by insufficient pressure change rate. This technique enables the reactive gas to form a uniformly distributed adsorption layer on the substrate surface, avoiding film defects caused by gas impact effects in the edge areas, while improving the stability and repeatability of the deposition process.

[0046] In an optional embodiment, during the ultra-dense layer deposition stage, the reaction temperature is 480-520℃, the pressure is reduced to 10-15Pa at a rate of 2Pa / s, the deposition time is 1-4min, the flow ratio of SiH4 to H2 is 1:9.7-10.3, and the partial pressure of H2 accounts for no less than 90%.

[0047] Optionally, in the ultra-dense layer deposition stage: the reaction temperature can be 480℃, 485℃, 490℃, 495℃, 500℃, 505℃, 510℃, 515℃, 520℃, or any value between 480℃ and 520℃; the pressure can be reduced to 10Pa, 11Pa, 12Pa, 13Pa, 14Pa, 15Pa, or any value between 10℃ and 15Pa; the deposition time can be 1min, 1.5min, 2min, 2.5min, 3min, ... 3.5 min, 4 min, or any value between 1 and 4 min; the flow ratio of SiH4 to H2 can be 1:9.7, 1:9.8, 1:9.9, 1:10, 1:10.1, 1:10.2, 1:10.3, or any value between 1:9.7 and 10.3; the partial pressure ratio of H2 can be 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 99%, 100%, or any value not less than 90%.

[0048] Controlling the reaction temperature between 480-520℃ refers to balancing the silane decomposition rate and the crystal nucleation rate through temperature regulation. This can be achieved using a segmented temperature control process. The lower temperature limit ensures sufficient silane decomposition to form dense crystal nuclei, while the upper temperature limit prevents intensified gas thermal motion from inducing turbulence. Controlling the reaction time between 1-4 minutes involves controlling the transition layer thickness through a time window to ensure the formation of a continuously covering nanoscale transition layer. Subsequently, the chamber pressure is reduced from the initial value to 12 Pa at a linear rate of 2 Pa / s. This gradient depressurization effectively reduces the mean free path of gas molecules, allowing the reactant gases to form a laminar flow state on the substrate surface. Controlling the reaction pressure between 10-15 Pa involves suppressing local impact effects by reducing the mean free path of gas molecules. The lower pressure limit maintains a sufficient gas diffusion rate, while the upper pressure limit restricts turbulence formation. Controlling the SiH4 to H2 flow ratio between 1:9.7-10.3 optimizes the competition between surface migration and gas-phase nucleation through precise proportioning, while a high proportion of hydrogen dilutes the reactant gas concentration. The H2 partial pressure ratio of not less than 90% means that the gas dilution effect is enhanced by controlling the partial pressure. Specifically, this can be achieved by using a partial pressure sensor for real-time monitoring. A high-concentration hydrogen environment inhibits gas phase reactions and enhances the migration ability of surface adsorbed atoms.

[0049] Specifically, within the reaction temperature range of 480-520℃, silane molecules acquire sufficient activation energy to achieve controlled decomposition, forming high-density nuclei on the substrate surface without triggering violent gas convection. When the reaction pressure is maintained at 10-15 Pa, the mean free path of gas molecules is shortened to the millimeter level, significantly reducing the airflow impact energy in the edge region. By precisely controlling the SiH4 to H2 flow ratio at 1:9.7-10.3, while maintaining the H2 partial pressure at over 90%, the reactive gas concentration is diluted below the critical nucleation concentration, forcing silicon atoms to preferentially migrate on the substrate surface rather than agglomerate in the gas phase. This combination of parameters puts the deposition process in a surface reaction-dominated mode, forming an ultra-dense transition layer with controllable thickness within 1-4 minutes. Its continuous and complete interface structure provides a smooth substrate for subsequent high-speed deposition.

[0050] Through the above technical solution, this application achieves synergistic control of turbulence suppression and surface reaction under high-speed deposition conditions, effectively eliminating the difference in film density at the substrate edge region and forming a defect-free ultrathin transition layer. This transition layer provides an atomically smooth interface for the uniform growth of the subsequent main layer, while avoiding film thickness fluctuations caused by turbulence disturbances in traditional processes, thus fundamentally improving the stability of the overall deposition process.

[0051] In one optional embodiment, during the main layer deposition stage, the reaction temperature is 480-580℃, the pressure is 20.5-21.5Pa, and the reaction time is 60-90min.

[0052] Optionally, the reaction temperature during the main layer deposition stage can be 480℃, 485℃, 490℃, 495℃, 500℃, 505℃, 510℃, 515℃, 520℃, 530℃, 540℃, 550℃, 560℃, 570℃, or 580℃, or any value between 480℃ and 580℃; the reaction pressure can be 20.5Pa, 20.6Pa, 20.7Pa, 20.8Pa, 20.9Pa, 21Pa, 21.1Pa, 21.2Pa, 21.3Pa, 21.4Pa, or 21.5Pa, or any value between 20.5℃ and 21.5Pa; the reaction time during the main layer deposition stage can be 60min, 63min, 66min, 69min, 72min, 75min, 78min, 81min, 84min, 87min, or 90min, or any value between 60min and 90min.

[0053] Specifically, during the main layer deposition stage, the reaction temperature was set at 480-520℃. By precisely controlling the silane decomposition rate, the migration ability and nucleation density of silicon atoms on the substrate surface were optimized, thereby reducing grain boundary defects. The pressure was controlled within the range of 20.5-21.5 Pa. By suppressing gas turbulence formation, the airflow impact effect at the substrate edge was reduced, improving the uniformity of the reactant gas distribution on the substrate surface. The reaction time was limited to 60-90 minutes. This ensured that the polycrystalline silicon layer reached the target thickness while avoiding excessive grain growth and film stress accumulation caused by prolonged deposition. The synergistic effect of temperature, pressure, and time parameters enabled the stable deposition of the polycrystalline silicon layer in a low-turbulence environment, with a controllable gradient change in grain size along the thickness direction.

[0054] Compared to existing technologies, which typically employ deposition pressures below 20 Pa to increase deposition rates, this pressure range easily induces gas turbulence, leading to deterioration of film edge density. Simultaneously, existing technologies often use substrate deposition temperatures exceeding 550°C, which, while increasing the deposition rate, exacerbate the risk of thermal stress on the substrate. This proposed solution significantly improves gas flow stability and thermal management efficiency while maintaining a reasonable deposition rate by increasing the deposition pressure to 20.5-21.5 Pa and decreasing the temperature to 480-520°C.

[0055] Through the above technical solution, this application solves the problems of poor film thickness uniformity and insufficient density caused by turbulence during high-speed deposition. By optimizing the combination of temperature-pressure-time parameters, a uniformly distributed dense crystal structure of polycrystalline silicon layer is formed on the substrate surface, while avoiding thermal damage to the substrate and improving process stability and consistency of film electrical properties.

[0056] Secondly, this application also provides a BC battery, which is prepared according to the back contact battery LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization.

[0057] In one optional implementation, the thickness of the ultra-dense polycrystalline silicon transition layer is 1-5 nm. The thickness of the main polycrystalline silicon layer is 180-220 nm.

[0058] Optionally, the thickness of the ultra-dense polycrystalline silicon transition layer can be 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, or any value between 1 and 5nm; optionally, the thickness of the main polycrystalline silicon layer can be 180nm, 182nm, 184nm, 186nm, 188nm, 190nm, 192nm, 194nm, 196nm, 198nm, 200nm, 202nm, 204nm, 206nm, 208nm, 210nm, 212nm, 214nm, 216nm, 218nm, 220nm, or any value between 180 and 220nm.

[0059] Specifically, the ultra-thin design of the ultra-dense polycrystalline silicon transition layer enables the formation of a continuous and defect-free dense structure at the interface. This reduces the interference of turbulent gas on the deposition process through physical barriers, thereby reducing porosity formation. The thickness of the main polycrystalline silicon layer is controlled to ensure the integrity of the carrier transport path while avoiding stress concentration caused by excessive thickness. The synergistic effect of these two layers is achieved through a hierarchical deposition strategy: the ultra-dense layer prioritizes repairing interface defects and suppressing turbulent disturbances, while the main layer subsequently achieves high-quality growth in a stable deposition environment.

[0060] Compared to existing technologies, traditional single-layer polycrystalline silicon deposition processes lack a transition layer structure, making it difficult to effectively mitigate edge defects caused by turbulence, and the overall film thickness uniformity is significantly affected by deposition rate fluctuations. This solution introduces a dual-layer structure of an ultra-dense transition layer and a main layer, establishing a stable interface environment in the early stages of deposition, reducing the interference of turbulence on subsequent deposition stages. Simultaneously, optimizing the thickness of the main layer achieves a balance between the overall mechanical and electrical properties of the film. This application can significantly reduce the porosity of the polycrystalline silicon layer in the substrate edge region, improve film thickness uniformity, reduce localized electrical performance degradation caused by turbulence impact, and avoid stress accumulation problems caused by excessive film thickness, thereby improving the carrier transport efficiency and long-term reliability of the back-contact solar cell.

[0061] In one optional embodiment, the grain size of the ultra-dense polycrystalline silicon layer is 5-8 nm, and the density is not less than 98%. The grain size of the main polycrystalline silicon layer is 10-30 nm, and the grain size gradually increases from the ultra-dense polycrystalline silicon transition layer to the surface of the main polycrystalline silicon transition layer.

[0062] Optionally, the grain size of the ultra-dense polycrystalline silicon transition layer can be 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, or any value between 5 and 8nm; the density of the ultra-dense polycrystalline silicon transition layer can be 98%, 98.1%, 98.2%, 98.3%, 98.4%, 98.5%, 98.6%, 98.7%, 98.8%, 98.9%, 99%, 99.1%, 99.2%, 99.3%, 99.4%, or 99.5%. The percentages are 99.6%, 99.7%, 99.8%, 99.9%, 100%, or any value not less than 98%; the grain size of the main polycrystalline silicon layer can be 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 6nm, 17nm, 18nm, 19nm, 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 6nm, 7nm, 28nm, 29nm, 30nm, or any value between 10-30nm.

[0063] Specifically, in the ultra-dense polycrystalline silicon layer deposition stage, by controlling the reaction temperature below 500℃ and employing a mixed gas with precisely controlled partial pressure ratios, silane molecules achieve orderly adsorption and decomposition on the substrate surface, forming a continuous and dense nanocrystalline structure. During the main layer deposition process, by increasing the reaction pressure and extending the deposition time, the grains preferentially grow along specific crystal orientations under thermodynamic drive, forming a smooth transition from a dense underlying structure to a coarser surface structure. This process ensures uniformity of grain size gradient and film thickness by suppressing local gas concentration fluctuations caused by turbulence.

[0064] Compared with existing technologies, traditional processes suffer from discrete grain size distribution due to turbulent disturbances in high-speed deposition modes, and lack a grain growth correlation mechanism between the transition layer and the main layer. This approach overcomes the problem of interfacial stress accumulation caused by abrupt grain growth in existing technologies by controlling the gradient growth of grain size, thereby maintaining deposition efficiency and achieving controllable evolution of the grain boundary structure.

[0065] Through the above technical solution, this application effectively suppresses the abnormal increase in porosity of the polycrystalline silicon layer caused by turbulence, reducing the interface defect density to a negligible level. The gradual change in grain size optimizes the continuity of carrier transport paths and avoids abrupt changes in potential barriers at grain boundaries, thereby improving the uniformity of contact resistance distribution.

[0066] In an optional implementation, the uniformity of the film thickness of the BC battery is no higher than 3%.

[0067] Thirdly, this application also provides a photovoltaic system including the BC battery.

[0068] The implementation schemes of this application will be described in detail below with reference to specific embodiments. However, those skilled in the art will understand that the following embodiments are only for illustrating this application and should not be regarded as limiting the scope of this application. Unless otherwise specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments used without specified manufacturers are all conventional products that can be purchased commercially.

[0069] Example 1

[0070] This embodiment provides a back-contact solar cell LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization. The fabrication process is as follows: Figure 1 As shown, the specific steps are as follows:

[0071] A 2 nm flint oxide layer 2 is grown on the back side of an N-type CZ silicon wafer 1 with a resistivity of 1-10 Ωcm using conventional methods.

[0072] Rapid pressure reduction stage: The silicon wafer is placed in the LPCVD reaction chamber and SiH4 is introduced at a flow rate of 500 sccm; within 5 seconds, the pressure in the LPCVD reaction chamber is reduced from atmospheric pressure to 15 Pa.

[0073] Ultra-dense polycrystalline silicon transition layer 3 deposition stage: The pressure in the chamber is reduced to 12 Pa at a rate of 2 Pa / s, and ultra-dense polycrystalline silicon transition layer 3 is deposited at 500℃ for 4 minutes. During the deposition process, the flow ratio of SiH4 to H2 is 1:9.8, and the partial pressure of H2 accounts for 92%.

[0074] The main polycrystalline silicon layer 4 deposition stage: increase the chamber pressure to 21 Pa, raise the temperature to 560 ℃, increase the SiH4 flow rate to 800 sccm, and the deposition time is 70 minutes.

[0075] This embodiment also provides a BC battery, the structure of which is as follows: Figure 2 As shown:

[0076] On the back side of the N-type CZ silicon wafer 1, in the direction away from the N-type CZ silicon wafer 1, the following are sequentially arranged:

[0077] Flint-penetrating oxide layer 2: 2 nm thick;

[0078] Ultra-dense polycrystalline silicon transition layer 3: 4 nm thick; verified by HR-TEM, the grain size of ultra-dense polycrystalline silicon transition layer 3 is 6 nm;

[0079] The main polycrystalline silicon layer 4 has a thickness of 180 nm. HR-TEM verification shows that the grain size gradient of the main polycrystalline silicon layer 4 extends to 28 nm.

[0080] The fabricated BC battery, measured at multiple points using an elliptic polarimeter, showed an average film thickness of 2.7%; the contact resistance, measured by TLM, was 0.75 mΩ·cm. 2 The percentage of abnormal white edges verified by appearance has decreased from 10% to below 0.1%.

[0081] Example 2

[0082] This embodiment provides a back-contact solar cell LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization. The specific steps are as follows:

[0083] A 2 nm flint oxide layer 2 is grown on the back side of an N-type CZ silicon wafer 1 with a resistivity of 1-10 Ωcm using conventional methods.

[0084] Rapid pressure reduction stage: The silicon wafer is placed in the LPCVD reaction chamber and SiH4 is introduced at a flow rate of 500 sccm; within 5 seconds, the pressure in the LPCVD reaction chamber is reduced from atmospheric pressure to 15 Pa.

[0085] Ultra-dense polycrystalline silicon transition layer 3 deposition stage: The pressure in the chamber is reduced to 12 Pa at a rate of 2 Pa / s, and ultra-dense polycrystalline silicon transition layer 3 is deposited at 500℃ for 4 minutes. During the deposition process, the flow ratio of SiH4 to H2 is 1:9.9, and the partial pressure of H2 accounts for 95%.

[0086] The main polycrystalline silicon layer 4 deposition stage: increase the chamber pressure to 21 Pa, raise the temperature to 560 ℃, increase the SiH4 flow rate to 800 sccm, and the deposition time is 70 minutes.

[0087] This embodiment also provides a BC battery:

[0088] On the back side of N-type CZ silicon wafer 1, in the direction away from N-type CZ silicon wafer 1, the following are arranged sequentially:

[0089] Flint-penetrating oxide layer 2: 2 nm thick;

[0090] Ultra-dense polycrystalline silicon transition layer 3: 4 nm thick; verified by HR-TEM, the results are as follows. Figure 2 As shown, the grain size of the ultra-dense polycrystalline silicon transition layer 3 is 6 nm;

[0091] The main polycrystalline silicon layer 4 has a thickness of 208 nm, and the grain size gradient of the main polycrystalline silicon layer 4 extends to 22 nm.

[0092] The average film thickness of the fabricated BC cell, measured at multiple points using an ellipsometry, was 215 ± 10 nm. Visual inspection showed that the percentage of abnormal white edges decreased from 10% to 1%.

[0093] Example 3

[0094] This embodiment provides a back-contact solar cell LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization. The specific steps are as follows:

[0095] A 2 nm flint oxide layer 2 is grown on the back side of an N-type CZ silicon wafer 1 with a resistivity of 1-10 Ωcm using conventional methods.

[0096] Rapid pressure reduction stage: The silicon wafer is placed in the LPCVD reaction chamber and SiH4 is introduced at a flow rate of 500 sccm; within 5 seconds, the pressure in the LPCVD reaction chamber is reduced from atmospheric pressure to 15 Pa.

[0097] Ultra-dense polycrystalline silicon transition layer 3 deposition stage: The pressure in the chamber is reduced to 12 Pa at a rate of 2 Pa / s, and ultra-dense polycrystalline silicon transition layer 3 is deposited at 500℃ for 4 minutes. During the deposition process, the flow ratio of SiH4 to H2 is 1:10, and the partial pressure of H2 accounts for 97%.

[0098] The main polycrystalline silicon layer 4 deposition stage: increase the chamber pressure to 21 Pa, raise the temperature to 575 °C, increase the SiH4 flow rate to 800 sccm, and the deposition time is 70 minutes.

[0099] This embodiment also provides a BC battery:

[0100] On the back side of N-type CZ silicon wafer 1, in the direction away from N-type CZ silicon wafer 1, the following are arranged sequentially:

[0101] Flint-penetrating oxide layer 2: 2 nm thick;

[0102] Ultra-dense polycrystalline silicon transition layer 3: 5 nm thick; verified by HR-TEM, the results are as follows. Figure 2 As shown, the grain size of the ultra-dense polycrystalline silicon transition layer 3 is 7 nm;

[0103] The main polycrystalline silicon layer 4 has a thickness of 215 nm, and the grain size gradient of the main polycrystalline silicon layer 4 extends to 24 nm.

[0104] The average film thickness of the fabricated BC cell was measured at multiple points using an ellipsometry, and was found to be 200 ± 20 nm. Visual inspection showed that the percentage of abnormal white edges decreased from 10% to below 0.5%.

[0105] Comparative Example 1

[0106] This comparative example provides a conventional LPCVD polycrystalline silicon deposition method for back-contact solar cells, with the specific steps as follows:

[0107] Substrate loading: Load the silicon wafers vertically or horizontally into the quartz boat, ensuring uniform inter-wafer spacing (to avoid shading effects). Place the wafers into the LPCVD reactor and seal the chamber.

[0108] Vacuuming: Use mechanical and molecular pumps to reduce the chamber pressure to a basic vacuum (<1 Pa) to avoid contamination by residual gas.

[0109] Preheating: Heat to the deposition temperature (500-580℃) at a rate of 10℃ / min (to prevent thermal stress from causing silicon wafer warping).

[0110] Gas introduction: The main reactive gas is silane (SiH4) at a flow rate of 145 sccm, with a purity ≥99.999%. The reaction pressure is maintained at 30 Pa. The deposition time is 75 minutes, the deposition rate is 3 nm / min, and the deposition thickness is 225 nm. The furnace temperature fluctuation is <2℃ to ensure that the film thickness uniformity of the entire batch of silicon wafers does not exceed 3%.

[0111] Gas switching and purging: Turn off the SiH4 gas and purge with N2 for 5-10 minutes to remove residual reaction gases.

[0112] Comparative Example 2

[0113] This comparative example provides a method for LPCVD polycrystalline silicon deposition in a back-contact battery, and the specific steps are as follows:

[0114] Conventional methods are used to grow a 2 nm flint oxide layer on the back side of an N-type CZ silicon wafer with a resistivity of 1-10 Ωcm.

[0115] Rapid pressure reduction stage: The silicon wafer is placed in the LPCVD reaction chamber and SiH4 is introduced at a flow rate of 500 sccm; within 5 seconds, the pressure in the LPCVD reaction chamber is reduced from atmospheric pressure to 15 Pa.

[0116] Ultra-dense layer deposition stage: The pressure in the chamber is reduced to 12 Pa at a rate of 2 Pa / s, and an ultra-dense polycrystalline silicon transition layer is deposited at 500°C for 4 minutes. During the deposition process, the flow ratio of SiH4 to H2 is 1:9.8, and the partial pressure of H2 accounts for 92%.

[0117] This comparative example also provides a BC battery:

[0118] On the back side of the N-type CZ silicon wafer, sequentially arranged in the direction away from the N-type CZ silicon wafer:

[0119] Flint-penetrating oxide layer: 2 nm thick;

[0120] Ultra-dense polycrystalline silicon transition layer: thickness is nm; verified by HR-TEM, the grain size of the ultra-dense polycrystalline silicon transition layer is 6 nm;

[0121] The fabricated BC battery, measured at multiple points using an elliptic polarimeter, showed an average film thickness of 220 nm; the contact resistance, measured by TLM, was 1.9 mΩ·cm. 2 .

[0122] Comparative Example 3

[0123] This comparative example provides a back-contact solar cell LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization. The specific steps are as follows:

[0124] Conventional methods are used to grow a 2 nm flint oxide layer on the back side of an N-type CZ silicon wafer with a resistivity of 1-10 Ωcm.

[0125] Rapid pressure reduction stage: The silicon wafer is placed in the LPCVD reaction chamber and SiH4 is introduced at a flow rate of 500 sccm; within 5 seconds, the pressure in the LPCVD reaction chamber is reduced from atmospheric pressure to 15 Pa.

[0126] Main layer deposition stage: Increase the cavity pressure to 21 Pa, raise the temperature to 560 ℃, increase the SiH4 flow rate to 800 sccm, and the deposition time is 70 minutes.

[0127] This comparative example also provides a BC battery:

[0128] On the back side of the N-type CZ silicon wafer, sequentially arranged in the direction away from the N-type CZ silicon wafer:

[0129] Flint-penetrating oxide layer: 2 nm thick;

[0130] Main polycrystalline silicon layer: 180nm thick, with grain size gradient extending to 27nm.

[0131] The fabricated BC battery, measured at multiple points using an elliptic polarimeter, had an average film thickness of 215 nm; the contact resistance, measured by TLM, was 1.4 mΩ·cm. 2 The percentage of abnormal white edges verified by appearance has decreased from 10% to below 1.4%.

[0132] Comparative Example 4

[0133] This comparative example provides a back-contact solar cell LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization. The specific steps are as follows:

[0134] Conventional methods are used to grow a 2 nm flint oxide layer on the back side of an N-type CZ silicon wafer with a resistivity of 1-10 Ωcm.

[0135] Ultra-dense layer deposition stage: The pressure in the chamber is reduced to 12 Pa at a rate of 2 Pa / s, and an ultra-dense polycrystalline silicon transition layer is deposited at 500°C for 4 minutes. During the deposition process, the flow ratio of SiH4 to H2 is 1:9.8, and the partial pressure of H2 accounts for 92%.

[0136] Main layer deposition stage: Increase the cavity pressure to 21 Pa, raise the temperature to 560 ℃, increase the SiH4 flow rate to 800 sccm, and the deposition time is 70 minutes.

[0137] This embodiment also provides a BC battery:

[0138] On the back side of the N-type CZ silicon wafer, sequentially arranged in the direction away from the N-type CZ silicon wafer:

[0139] Flint-penetrating oxide layer: 2 nm thick;

[0140] Ultra-dense polycrystalline silicon transition layer: 4nm thick; verified by HR-TEM, results are as follows. Figure 2 As shown, the grain size of the ultra-dense polycrystalline silicon transition layer is 6 nm;

[0141] Main polycrystalline silicon layer: 200nm thick, with grain size gradient of the main polycrystalline silicon layer extended to 5nm.

[0142] The fabricated BC battery, measured at multiple points using an elliptic polarimeter, showed an average film thickness of 218 nm; the contact resistance, measured by TLM, was 1.3 mΩ·cm. 2 The percentage of abnormal white edges verified by appearance inspection decreased from 10% to below 1.1%.

[0143] In the BC batteries provided in the embodiments and comparative examples, the multi-point measurement film thickness information is as follows: Figure 1 As shown:

[0144] Figure 1 The thickness of the BC battery film prepared in the examples and comparative examples

[0145] Site 1 Site 2 Site 3 Site 4 Site 5 Example 1 209 209 214 214 206 Example 1 212 213 216 215 216 Example 3 209 207 208 210 205 Comparative Example 1 209 208 209 215 216 Comparative Example 2 211 209 210 217 208 Comparative Example 3 211 216 210 208 209 Comparative Example 4 210 208 211 215 211

[0146] The electrical properties of the BC batteries prepared in the examples and comparative examples are shown in Table 2:

[0147] Table 2 shows the electrical performance of the BC batteries prepared in the examples and comparative examples.

[0148] Contact resistance Low birth rate life expectancy Example 1 1.9 10000 Example 2 1.8 10362 Example 3 1.6 10784 Comparative Example 1 2.1 9400 Comparative Example 2 2.4 8500 Comparative Example 3 2.4 8569 Comparative Example 4 2.0 9300

[0149] As can be seen from Tables 1 and 2, the overall film thickness does not change much, the minority carrier lifetime gain is about 1000, and the contact resistance is lower than that of the control group.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0151] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the foregoing claims, any of the claimed embodiments can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

Claims

1. A method for polycrystalline silicon deposition via LPCVD for back-contact solar cells based on turbulence suppression and interface optimization, characterized in that, include: A flint oxide layer is formed on the back side of an N-type CZ silicon wafer, and an ultra-dense polycrystalline silicon transition layer is formed on the surface of the flint oxide layer after a rapid voltage reduction stage and an ultra-dense layer deposition stage; then a main polycrystalline silicon layer is formed on the surface of the ultra-dense polycrystalline silicon transition layer after a main layer deposition stage.

2. The LPCVD polycrystalline silicon deposition method for back contact solar cells based on turbulence suppression and interface optimization according to claim 1, characterized in that, The rapid depressurization phase reduces the pressure from atmospheric pressure to 5-20 Pa within 5 seconds.

3. The LPCVD polycrystalline silicon deposition method for back-contact solar cells based on turbulence suppression and interface optimization according to claim 1, characterized in that, During the ultra-dense layer deposition stage, the reaction temperature is 480-520℃, the pressure is reduced to 10-15Pa at a rate of 2Pa / s, the deposition time is 1-4min, the flow ratio of SiH4 to H2 is 1:9.7-10.3, and the partial pressure of H2 accounts for no less than 90%.

4. The LPCVD polycrystalline silicon deposition method for back-contact solar cells based on turbulence suppression and interface optimization according to any one of claims 1-3, characterized in that, During the main layer deposition stage, the reaction temperature is 480-580℃, the pressure is 20.5-21.5Pa, and the reaction time is 60-90min.

5. A BC battery, characterized in that, The back contact solar cell was prepared by LPCVD polycrystalline silicon deposition method based on turbulence suppression and interface optimization according to any one of claims 1-4.

6. The BC battery according to claim 5, characterized in that, At least one of the following conditions must be met: a. The thickness of the ultra-dense polycrystalline silicon transition layer is 1-5 nm; b. The thickness of the main polycrystalline silicon layer is 180-220 nm.

7. The BC battery according to claim 6, characterized in that, The grain size of the ultra-dense polycrystalline silicon transition layer is 5-8 nm, and the density is not less than 98%.

8. The BC battery according to claim 6, characterized in that, The grain size of the main polycrystalline silicon layer is 10-30 nm, and the grain size gradually increases from the ultra-dense polycrystalline silicon transition layer to the surface layer of the main polycrystalline silicon layer.

9. The BC battery according to any one of claims 5-8, characterized in that, The uniformity of the film thickness of the BC battery is no higher than 3%.

10. A photovoltaic system, characterized in that, Includes the BC battery as described in any one of claims 5-9.

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