A tbc cell and method of making the same

Abstract

This invention discloses a TBC battery and its fabrication method. The method includes: providing a process wafer; removing a first doped layer and a first mask layer from a first region, the front side, and the side surface, and a first tunneling oxide layer from the first region; fabricating a stacked second tunneling oxide layer, a second doped layer, and a second mask layer on the back side, and stacked second doped layers and second mask layers on the front side and the side surface, respectively; removing the second doped layer and the second mask layer from a second region, the front side, and the side surface, and the second tunneling oxide layer from the second region, and forming a textured structure on the front side; removing the second mask layer from the first region and the first mask layer from the second region; screen printing and high-temperature sintering on the first and second regions to form a first electrode in contact with the second doped layer in the first region, and a second electrode in contact with the first doped layer in the second region. Using the above method, selective etching removal of the doped layer and mask layer formed by around-plating on the front and side surfaces is achieved.

Description

Technical Field

[0001] This invention relates to the technical field of TBC batteries, and more particularly to a TBC battery and its preparation method. Background Technology

[0002] With the increasing global demand for clean energy, solar energy, as an inexhaustible energy source, has attracted much attention. The working principle of solar cells is to absorb photons from sunlight, generating electron-hole pairs, and thus forming an electric current. In actual production, a polycrystalline silicon layer is often coated around the edge of the low-voltage double-socket cell. Removing this coating is crucial to ensuring the photoelectric conversion efficiency of the cell and improving product yield. A significant color difference exists between the coated area and the non-coated area of ​​the cell, resulting in poor cell appearance. If the coating cannot be completely removed, it will affect contact isolation, reduce passivation performance, and may even damage critical structures such as the N+ emitter in subsequent processes, significantly reducing the overall yield of the cell.

[0003] Existing methods for removing the polycrystalline silicon layer from the wire-wound coating commonly involve adding strong oxidizing agents such as HNO3 to a chain of HF (high-frequency ion exchange). The strong oxidizing properties of HNO3 oxidize the polycrystalline silicon layer into silicon dioxide, which is then removed by the HF, thus removing the wire-wound coating. However, this method lacks selectivity for both the polycrystalline silicon layer and the uncoated monocrystalline silicon layer in the normal area. Both layers are oxidized and etched by the HF, resulting in excessive weight reduction in the solar cell. Furthermore, current silicon wafers are generally thin, and significant weight reduction leads to thinner cells, reduced rigidity, and problems such as microcracks during fabrication, lowering product yield. Additionally, the introduction of HNO3 generates nitrogen-containing wastewater (nitrate, nitrite, and nitrogen oxide exhaust gases), requiring complex wastewater treatment and exhaust gas absorption systems, resulting in significant environmental impact and compliance costs. Another approach involves inserting a rough polishing process between the chain-type HF and texturing processes. This process uses a mixed solution of KOH / NaOH and additives to remove the polycrystalline silicon layer around the wire through alkaline etching. This method is relatively cumbersome and requires additional equipment and tanks. It also has strict requirements on the additives, time, temperature, and other process parameters of the rough polishing process. Furthermore, it often faces problems such as incomplete removal of the wire coating or excessive etching of the phosphosilicate glass (PSG) layer on the back side after the wire coating is removed, leading to texturing in the N-zone. The processing window is narrow and it is not suitable for large-scale mass production. Summary of the Invention

[0004] This invention provides a TBC battery and its fabrication method. By selectively etching away the doped layer and mask layer formed on the front and side surfaces of the wafer through a first preset process and a second preset process, the additional weight loss caused by acid etching is greatly reduced, and the N-type silicon substrate is not made too thin, effectively ensuring the yield of the battery cell during the fabrication process. In addition, compared with the existing rough polishing process, it is not necessary to add additional tanks or equipment, making it more suitable for mass production. This ensures the contact resistance and passivation effect of the TBC battery and improves the photoelectric conversion efficiency.

[0005] In a first aspect, the present invention provides a method for preparing a TBC battery, comprising: A process wafer is provided; the process wafer includes an N-type silicon substrate, the N-type silicon substrate includes a front side, a side side and a back side, the front side and the side side each include a stacked first doped layer and a first mask layer, the back side includes a first region and a second region arranged in an interdigitated space, and the back side includes a first tunneling oxide layer, a first doped layer and a first mask layer stacked sequentially. The first preset process is used to remove the first doped layer and the first mask layer in the first region, the front side and the side side, as well as the first tunneling oxide layer in the first region. A second tunneling oxide layer, a second doped layer, and a second mask layer are sequentially stacked on the back side, and a second doped layer and a second mask layer are stacked on the front and side sides. The second preset process is used to remove the second doped layer and the second mask layer in the second region, the front side and the side, as well as the second tunneling oxide layer in the second region, and to form a textured structure on the front side. Remove the second mask layer of the first region and the first mask layer of the second region, and prepare a first protective layer on the side surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and prepare a second protective layer on the textured surface. The first and second regions are screen-printed and sintered at high temperature to form a first electrode in the first region that contacts the second doped layer, and a second electrode in the second region that contacts the first doped layer, thereby obtaining a TBC battery.

[0006] Optionally, a first preset process is used to remove the first doped layer and the first mask layer in the first region, the front side and the side side, as well as the first tunneling oxide layer in the first region, including: The first etching process is used to remove the first mask layer in the first region, the front side and the side side under the first etching conditions; Using a second etching process, under second etching conditions, the first doped layer in the first region, the front side, and the side side is removed; The first tunneling oxide layer in the first region is removed using a third etching process under third etching conditions.

[0007] Optionally, the first etching conditions include introducing a 10%-20% hydrofluoric acid solution into the reaction chamber of the first etching process; and / or, the second etching conditions include introducing a 10%-20% hydrofluoric acid solution and a 5%-15% micro-etching additive mixed solution into the reaction chamber of the second etching process, with an etching temperature of 20℃-25℃ and an etching time of 0.5min-2min; and / or, the third etching conditions include introducing a 10%-20% sodium hydroxide or potassium hydroxide solution and a 0.5%-2% alkaline etching additive mixed solution into the reaction chamber of the third etching process, with an etching temperature of 50℃-90℃.

[0008] Optionally, a second preset process is used to remove the second doped layer and the second mask layer in the second region, the front side, and the side surface, as well as the second tunneling oxide layer in the second region, and to form a textured structure on the front side, including: The fourth etching process is used to remove the second mask layer in the second region, the front side and the side side under the fourth etching conditions; Using the fifth etching process, under the fifth etching conditions, the second doped layer in the second region, the front side and the side side is removed; Using the sixth etching process, under the sixth etching conditions, the second tunneling oxide layer in the second region is removed, and a textured structure is formed on the front side.

[0009] Optionally, the fourth etching condition includes introducing a 5%-10% hydrofluoric acid solution into the reaction chamber of the fourth etching process; and / or, the fifth etching condition includes introducing a 5%-10% hydrofluoric acid solution and a 3%-10% micro-etching additive mixed solution into the reaction chamber of the fifth etching process, with an etching temperature of 20℃-25℃ and an etching time of 0.5min-2min; and / or, the sixth etching condition includes introducing a 1%-3% sodium hydroxide or potassium hydroxide solution and a 0.5%-2% alkaline etching additive mixed solution into the reaction chamber of the sixth etching process, with an etching temperature of 50℃-90℃.

[0010] Optionally, before removing the first doped layer and the first mask layer of the first region, the front side, and the side side, and the first tunneling oxide layer of the first region using the first preset process, the process further includes: A first photoresist layer is formed on one side of the process wafer; The first photoresist layer is pre-treated to remove the first photoresist layer in the first region and retain the first photoresist layer in the second region. In addition to removing the first doped layer and the first mask layer of the first region, the front and side surfaces, and the first tunneling oxide layer of the first region, the process also includes: Using the seventh etching process, the first photoresist layer in the second region is removed under the seventh etching conditions.

[0011] Optionally, a second preset process is employed to remove the second doped layer and the second mask layer in the second region, the front side, and the side surface, as well as the second tunneling oxide layer in the second region. Before forming the textured structure on the front side, the process further includes: A second photoresist layer is prepared on the side of the second mask layer on the back side away from the N-type silicon substrate; The second photoresist layer is pre-treated to remove the second photoresist layer in the second region, while retaining the second photoresist layer in the first region. The process includes removing the second doped layer and the second mask layer in the second region, the front side, and the side surface, as well as the second tunneling oxide layer in the second region, and forming a textured structure on the front side, while also including: Using the seventh etching process, under the seventh etching conditions, the second photoresist layer in the first region is removed.

[0012] Optionally, the seventh etching conditions include introducing a mixed solution of sodium hydroxide or potassium hydroxide solution with a concentration of 1%-5% and sodium hydroxide solution with a concentration of 1%-7% into the reaction chamber of the seventh etching process, and the etching temperature is 50℃-90℃.

[0013] Optionally, process slices may be provided, including: Using a deposition process, a first tunneling oxide layer and a first intrinsic silicon layer are sequentially formed on the back side; Using a boron diffusion process, the first intrinsic silicon layer is boron doped to form a first doped layer and a first mask layer, and the first doped layer and the first mask layer are stacked on the front and side sides. A second tunneling oxide layer, a second doped layer, and a second mask layer are sequentially stacked on the back side, and a second doped layer and a second mask layer are stacked on the front and side sides, including: Using a deposition process, a second tunneling oxide layer and a second intrinsic silicon layer are sequentially formed on the back side; Using a phosphorus doping process, the second intrinsic silicon layer is phosphorus doped to form a stacked second doped layer and a second mask layer, and a stacked second doped layer and a second mask layer are formed on the front and side sides.

[0014] Secondly, the present invention provides a TBC battery, which is prepared based on the above-described TBC battery preparation method.

[0015] The technical solution of this invention provides a process wafer; the process wafer includes an N-type silicon substrate, the N-type silicon substrate includes a front side, a side side, and a back side, the front side and the side side each include a stacked first doped layer and a first mask layer, the back side includes a first region and a second region arranged in an interdigitated pattern, and the back side includes a first tunneling oxide layer, a first doped layer, and a first mask layer stacked sequentially; using a first preset process, the first doped layer and the first mask layer of the first region, the front side and the side side, and the first tunneling oxide layer of the first region are removed; a second tunneling oxide layer, a second doped layer, and a second mask layer stacked sequentially are formed on the back side, and a second doped layer and a first mask layer stacked on the front side and the side side are formed. The second mask layer is then used. A second preset process is employed to remove the second doped layer and the second mask layer in the second region, the front side, and the side surface, as well as the second tunneling oxide layer in the second region, forming a textured structure on the front side. The second mask layer in the first region and the first mask layer in the second region are removed. A first protective layer is prepared on the side of the first and second doped layers on the back side facing away from the N-type silicon substrate, and a second protective layer is prepared on the textured structure surface. The first and second regions are then screen-printed and sintered at high temperature to form a first electrode in contact with the second doped layer in the first region and a second electrode in contact with the first doped layer in the second region, thus obtaining a TBC cell. Using the above method, through the first and second preset processes, the doped layers and mask layers formed on the front and side surfaces are selectively etched away, significantly reducing the additional weight loss caused by acid etching and preventing the N-type silicon substrate from becoming too thin, effectively ensuring the yield during the cell fabrication process. Furthermore, compared to existing rough polishing processes, no additional tanks or equipment are required, making it more suitable for mass production, ensuring the contact resistance and passivation effect of the TBC cell, and improving the photoelectric conversion efficiency.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a method for preparing a TBC battery according to an embodiment of the present invention; Figure 2 yes Figure 1 A flowchart of the manufacturing process of a corresponding TBC battery; Figure 3 yes Figure 2 A three-dimensional schematic diagram of the TBC battery manufacturing process corresponding to Figure a in the middle; Figure 4 yes Figure 2 A three-dimensional schematic diagram of the TBC battery manufacturing process corresponding to Figure c; Figure 5 A flowchart of another method for preparing TBC provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] In one embodiment, Figure 1 This is a flowchart of a TBC battery preparation method provided in an embodiment of the present invention. Figure 2 yes Figure 1 A flowchart of a corresponding TBC battery manufacturing process. Figure 3 yes Figure 2 Figure a shows a three-dimensional schematic diagram of the TBC battery manufacturing process. Figure 4 yes Figure 2 The diagram in Figure c shows a three-dimensional schematic of the TBC cell fabrication process. This embodiment is applicable to selective etching of the doped layer and mask layer generated by the front and side plating, without causing over-etching of the front side of the N-type silicon substrate, thus improving the cell production yield. Figures 1 to 4 As shown, the method includes: S110, provides process footage.

[0022] The process wafer 10 includes an N-type silicon substrate 1, which includes a front side, a side side, and a back side. The front side and the side side each include a first doped layer and a first mask layer stacked together. The back side includes a first region N and a second region P arranged in an interdigitated pattern. The back side also includes a first tunneling oxide layer, a first doped layer, and a first mask layer stacked sequentially.

[0023] Among them, reference Figure 2 a) diagram and Figure 3 As shown, process wafer 10 is an intermediate wafer formed during the fabrication of a tunneled oxide back contact (TBC) cell. In this embodiment, process wafer 10 includes an N-type silicon substrate 1, which includes a front side, a side side, and a back side. The back side includes a first region and a second region arranged in an alternating interdigitated pattern, with a spacer region between the first region and the second region. Typically, the first region can be an N-region or a P-region, and correspondingly, the second region can be a P-region or an N-region. In this embodiment, the first region is an N-region, the second region is a P-region, and the region between the N-region and the P-region is a spacer region.

[0024] Furthermore, the N-type silicon substrate 1 includes a first doped layer 22 and a first mask layer 23 stacked on both its front and side sides, and a first tunneling oxide layer 21, a first doped layer 22, and a first mask layer 23 stacked sequentially on its back side. The first tunneling oxide layer 21 is typically a very thin insulating layer composed of silicon dioxide (SiO2), used to allow majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thereby achieving selective collection of carriers, reducing surface recombination, improving the open-circuit voltage and fill factor of the battery, and enhancing photoelectric conversion efficiency. The first doped layer 22 is a boron-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with boron. The first mask layer 23 is a borosilicate glass (BSG) layer, a mask layer formed by the chemical reaction between the residual boron after boron doping and the oxygen diffused into the boron layer; it also serves as a protective layer.

[0025] Specifically, an N-type silicon substrate 1 is provided, and a first tunneling oxide layer 21 and a first intrinsic silicon layer are deposited on the back side of the N-type silicon substrate 1. After the formation of the first intrinsic silicon layer, elemental doping is required to diffuse the doped elements into the first intrinsic silicon layer, forming a first doped layer 22 and a first mask layer 23. Since the elemental doping of the N-type silicon substrate 1 is performed using single or double intercalation, the first doped layer 22 and the first mask layer 23 will also be formed on the front and side sides of the N-type silicon substrate 1 through around-plating after doping. It should be noted that... Figure 3 The membrane structure shown is only an example of one side; the same structure as the one on the right side of the diagram is formed on the other side (i.e., the left side), which is described here.

[0026] S120. Using a first preset process, remove the first doped layer and the first mask layer of the first region, the front and side surfaces, and the first tunneling oxide layer of the first region.

[0027] The first preset process is a process flow set in advance to remove the film layer at a preset position. It can be an acidic solution, an alkaline solution, a micro-etching additive, or a mixed solution formed by an acidic solution and a micro-etching additive, an alkaline solution, or a mixed solution formed by a micro-etching additive, etc. The specific process can be determined according to the actual situation and is not limited here.

[0028] Specifically, after the preparation and formation of process piece 10, refer to Figure 2 As shown in Figure b), since the front and side surfaces of the N-type silicon substrate 1 have a first doped layer 22 and a first mask layer 23 formed by circumferential plating, a first preset process is adopted. By sequentially introducing a certain concentration of acidic solution, a mixed solution formed by acidic solution and micro-etching additive, and an alkaline solution mixture into the process chamber of the first preset process, the first doped layer 22 and the first mask layer 23 of the first region, the front and side surfaces, and the first tunneling oxide layer 21 of the first region can be removed by utilizing the chemical reaction between ions.

[0029] It should be noted that when removing the first doped layer 22 and the first mask layer 23 formed by the wire-wound plating, the first mask layer 23 can be removed first, followed by the first doped layer 22, or they can be removed simultaneously. The specific method can be determined based on the actual situation and is not limited here. Furthermore, during the removal of the wire-wound plating, since the backside deposition of the N-type silicon substrate 1 is a whole-layer deposition forming the first tunneling oxide layer 21, the first doped layer 22, and the first mask layer 23, it is necessary to remove all of the first tunneling oxide layer 21, the first doped layer 22, and the first mask layer 23 deposited in the first region to provide a basis for the subsequent fabrication of the second doped layer in the first region. When removing the first tunneling oxide layer 21, the first doped layer 22, and the first mask layer 23 in the first region, they can be removed simultaneously with the removal of the wire-wound first doped layer 22 and the first mask layer 23, or the wire-wound first doped layer 22 and the first mask layer 23 can be removed first, followed by the removal of the first tunneling oxide layer 21, the first doped layer 22, and the first mask layer 23 in the first region. The specific method can be determined based on the actual situation and is not limited here.

[0030] S130. A second tunneling oxide layer, a second doped layer, and a second mask layer are sequentially prepared on the back side, and a second doped layer and a second mask layer are formed on the front and side sides.

[0031] The second tunneling oxide layer 31 is typically a very thin insulating layer composed of silicon dioxide (SiO2). It allows majority carriers (electrons) to pass through smoothly via the tunneling effect while preventing the recombination of minority carriers (holes), thus achieving selective carrier collection, reducing surface recombination, increasing the open-circuit voltage and fill factor of the battery, and improving photoelectric conversion efficiency. The second doped layer 32 is a phosphorus-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with phosphorus. The second mask layer 33 is a phosphorosilicate glass (PSG) layer, a mask layer formed by the chemical reaction between residual phosphorus after phosphorus doping and oxygen diffused into the phosphorus, and also serves as a protective layer.

[0032] Specifically, after removing the first doped layer 22 and the first mask layer 23 in the first region, the front side, and the side side, as well as the first tunneling oxide layer 21 in the first region, the resulting structure has the first tunneling oxide layer 21, the first doped layer 22, and the first mask layer 23 only present in the second region on the back side of the N-type silicon substrate 1. (Refer to...) Figure 2 In Figure b), the first mask layer 23 can serve as a protective layer to ensure that the subsequent etching process does not affect the first doped layer 22 in the second region. Furthermore, after forming the above structure, a second tunneling oxide layer 31, a second doped layer 32, and a second mask layer 33 need to be fabricated in the first region on the back side. In this embodiment, the second tunneling oxide layer 31 and the second intrinsic silicon layer are first deposited in an entire layer on the back side of the N-type silicon substrate 1. After forming the second intrinsic silicon layer, it needs to be elementally doped to allow the doped elements to diffuse into the second intrinsic silicon layer, forming the second doped layer 32 and the second mask layer 33. Since the element doping of the N-type silicon substrate 1 is performed using single or double insertion, the second doped layer 32 and the second mask layer 33 will also be formed on the front and side sides of the N-type silicon substrate 1 after doping. (Refer to...) Figure 2 Figure c) and Figure 4 As shown. It should be noted that, Figure 4 The membrane structure shown is only an example of one side; the same structure as the one on the right side of the diagram is formed on the other side (i.e., the left side), which is described here.

[0033] S140. Using the second preset process, the second doped layer and the second mask layer of the second region, the front side and the side side are removed, as well as the second tunneling oxide layer of the second region, and a textured structure is formed on the front side.

[0034] The second preset process is a pre-set process flow for removing the film layer at a preset position and simultaneously achieving texturing on the front side. It can be an acidic solution, alkaline solution, or micro-etching additive of a certain concentration, etc. The specific process can be determined according to the actual situation and is not limited here.

[0035] Specifically, after the preparation and formation of process piece 10, refer to Figure 2 As shown in Figure d), since the front and side surfaces of the N-type silicon substrate 1 have a second doped layer 32 and a second mask layer 33 formed by wire bonding, it is necessary to remove the second doped layer 32 and the second mask layer 33 formed by wire bonding. In this embodiment, a second preset process is adopted. By sequentially introducing a certain concentration of acidic solution, a mixed solution formed by acidic solution and micro-etching additive, and an alkaline solution mixture into the process chamber of the second preset process, the second doped layer 32 and the second mask layer 33 of the second region, the front and side surfaces, and the second tunneling oxide layer 31 of the second region can be removed by utilizing the chemical reaction between ions. At the same time, texturing is also achieved on the front surface of the N-type silicon substrate 1 in the above-mentioned alkaline solution environment to form a textured structure.

[0036] It should be noted that when removing the second doped layer 32 and the second mask layer 33 formed by the wire-wound plating, the second mask layer 33 can be removed first, followed by the second doped layer 32, or they can be removed simultaneously. The specific method can be determined based on the actual situation and is not limited here. Furthermore, during the removal of the wire-wound plating, since the second tunneling oxide layer 31, the second doped layer 32, and the second mask layer 33 are deposited in their entirety on the back side of the N-type silicon substrate 1, it is necessary to remove all of the second tunneling oxide layer 31, the second doped layer 32, and the second mask layer 33 deposited in the second region. When removing the second tunneling oxide layer 31, the second doped layer 32, and the second mask layer 33 in the second region, they can be removed simultaneously with the removal of the second doped layer 32 and the second mask layer 33 formed by the wire-wound plating, or the wire-wound second doped layer 32 and the second mask layer 33 can be removed first, followed by the removal of the second tunneling oxide layer 31, the second doped layer 32, and the second mask layer 33 in the second region. The specific method can be determined based on the actual situation and is not limited here.

[0037] S150, Remove the second mask layer of the first region and the first mask layer of the second region, and prepare a first protective layer on the side surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and prepare a second protective layer on the textured surface.

[0038] The first protective layer 4 and the second protective layer 5 both include a passivation layer and an anti-reflection layer, which are used to reduce the reflection of sunlight, increase the absorption of sunlight, improve the conversion efficiency of TBC cells, reduce surface recombination, increase the mobility of charge carriers, and improve the overall performance of TBC cells.

[0039] Specifically, the structure formed at this time includes a textured structure on the front side, a first tunneling oxide layer 21, a first doped layer 22, and a first mask layer 23 formed in the second region on the back side, and a second tunneling oxide layer 31, a second doped layer 32, and a second mask layer 33 formed in the first region on the back side. (See reference...) Figure 2As shown in Figure d). Before forming the first protective layer 4 and the second protective layer 5, it is necessary to remove the second mask layer 33 formed in the first region and the first mask layer 23 formed in the second region. Specifically, the N-type silicon substrate 1 can be placed in an acid pickling tank, and the first mask layer 23 and the second mask layer 33 can be removed under preset acid pickling conditions by adding a mixed solution of hydrofluoric acid and nitric acid of a certain concentration to the acid pickling tank, thus preparing for the subsequent preparation of the first protective layer 4 and the second protective layer 5.

[0040] Furthermore, after removing the first mask layer 23 and the second mask layer 33, only the textured structure exists on the front side, and only the tunneling oxide layer and doped layer exist on the back side. Therefore, a first protective layer 4 can be prepared on the surface of the first doped layer 22 and the second doped layer 32 on the back side facing away from the N-type silicon substrate 1. This can be achieved through processes such as deposition, and is not limited here. Additionally, a second protective layer 5 needs to be prepared on the textured surface of the front side to reduce surface reflection of the TBC cell, increase the surface area of ​​the TBC cell, reduce sunlight reflection, improve the cell's light trapping effect and absorption rate of sunlight, generate more photogenerated carriers, and improve the conversion efficiency of the TBC cell. (Refer to...) Figure 2 As shown in Figure e). The process for preparing the first protective layer 4 and the second protective layer 5 includes, but is not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition, etc. The specific process can be determined according to the actual situation and is not limited here.

[0041] In an optional embodiment, when forming the first protective layer 4, an atomic layer deposition process can be used to deposit a passivation layer of a certain thickness on the back side, and then a plasma-enhanced chemical vapor deposition process can be used to deposit an anti-reflection layer on the surface of the alumina passivation layer away from the N-type silicon substrate 1. The method for forming the second protective layer 5 on the front side is the same as that for the first protective layer 4, and will not be described again here. The components of the passivation layer may include, but are not limited to, alumina, silicon oxide, or a combination of alumina and silicon oxide, and the components of the anti-reflection layer may include, but are not limited to, silicon nitride, or a combination of silicon nitride and silicon oxide, or silicon oxynitride. It should be noted that, typically, during the preparation of the passivation layers on the front and back sides, atomic layer deposition is usually used to deposit the passivation layers simultaneously on both sides to reduce the number of process steps and shorten the preparation time.

[0042] S160. Screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the second doped layer in the first region and a second electrode in contact with the first doped layer in the second region, thereby obtaining a TBC battery.

[0043] Screen printing is one of the core processes in the manufacturing of TBC solar cells, primarily used for electrode forming. This process utilizes the basic principle that the paste passes through the mesh openings of the screen in the patterned areas, while the paste does not pass through the mesh openings in the non-patterned areas. During printing, the paste is precisely extruded through the mesh openings of the screen onto the N-type silicon substrate 1, forming the desired electrode pattern. Typically, the paste used for screen printing can include, but is not limited to, silver paste or aluminum paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed onto the surface of the solar cell at high temperatures, ensuring good ohmic contact between the metal grid lines and the N-type silicon substrate 1.

[0044] For details, please refer to Figure 2 As shown in Figure f), the purpose of forming electrodes on the back side is to convert photogenerated carriers generated by solar energy into current that flows to the external circuit. In this embodiment, after forming the first protective layer 4 and the second protective layer 5, electrodes need to be formed, i.e., screen printing is performed on the first and second regions on the back side to form metal grid lines on the surfaces of the first and second regions. After forming the metal grid lines, the formed metal grid lines are sintered at high temperature so that the sintered metal grid lines can contact the first doped layer 22 and the second doped layer 32 to form an ohmic contact. In this embodiment, after high-temperature sintering, a first electrode 6 is formed in the first region that contacts the second doped layer 32, and a second electrode 7 is formed in the second region that contacts the first doped layer 22, thereby fabricating a TBC battery. In addition, the first electrode 6 and the second electrode 7 have opposite polarities. When the first electrode 6 is a positive electrode, the corresponding second electrode 7 is a negative electrode; when the first electrode 6 is a negative electrode, the corresponding second electrode 7 is a positive electrode. In this embodiment, the first region is an N-region, and the second region is a P-region. The first electrode 6 formed in the N-region is a negative electrode, and the second electrode 7 formed in the P-region is a positive electrode.

[0045] The technical solution of this invention provides a process wafer; the process wafer includes an N-type silicon substrate, the N-type silicon substrate includes a front side, a side side, and a back side, the front side and the side side each include a stacked first doped layer and a first mask layer, the back side includes a first region and a second region arranged in an interdigitated pattern, and the back side includes a first tunneling oxide layer, a first doped layer, and a first mask layer stacked sequentially; using a first preset process, the first doped layer and the first mask layer of the first region, the front side and the side side, and the first tunneling oxide layer of the first region are removed; a second tunneling oxide layer, a second doped layer, and a second mask layer stacked sequentially are formed on the back side, and a second doped layer and a first mask layer stacked on the front side and the side side are formed. The second mask layer is then used. A second preset process is employed to remove the second doped layer and the second mask layer in the second region, the front side, and the side surface, as well as the second tunneling oxide layer in the second region, forming a textured structure on the front side. The second mask layer in the first region and the first mask layer in the second region are removed. A first protective layer is prepared on the side of the first and second doped layers on the back side facing away from the N-type silicon substrate, and a second protective layer is prepared on the textured structure surface. The first and second regions are then screen-printed and sintered at high temperature to form a first electrode in contact with the second doped layer in the first region and a second electrode in contact with the first doped layer in the second region, thus obtaining a TBC cell. Using the above method, through the first and second preset processes, the doped layers and mask layers formed on the front and side surfaces are selectively etched away, significantly reducing the additional weight loss caused by acid etching and preventing the N-type silicon substrate from becoming too thin, effectively ensuring the yield during the cell fabrication process. Furthermore, compared to existing rough polishing processes, no additional tanks or equipment are required, making it more suitable for mass production, ensuring the contact resistance and passivation effect of the TBC cell, and improving the photoelectric conversion efficiency.

[0046] In another specific embodiment, Figure 5 This is a flowchart of another TBC preparation method provided by an embodiment of the present invention. This embodiment refines the specific implementation of S120 in the above embodiment, which involves using a first preset process to remove the first doped layer and the first mask layer in the first region, the front side, and the side side, as well as the first tunneling oxide layer in the first region, as follows: The first etching process is used to remove the first mask layer in the first region, the front side and the side side under the first etching conditions; Using a second etching process, under second etching conditions, the first doped layer in the first region, the front side, and the side side is removed; The first tunneling oxide layer in the first region is removed using a third etching process under third etching conditions.

[0047] Furthermore, the specific implementation of S140 in the above embodiment, which employs a second preset process to remove the second doped layer and the second mask layer of the second region, the front side and the side side, as well as the second tunneling oxide layer of the second region, and to form a textured structure on the front side, is refined as follows: The fourth etching process is used to remove the second mask layer in the second region, the front side and the side side under the fourth etching conditions; Using the fifth etching process, under the fifth etching conditions, the second doped layer in the second region, the front side and the side side is removed; Using the sixth etching process, under the sixth etching conditions, the second tunneling oxide layer in the second region is removed, and a textured structure is formed on the front side.

[0048] Furthermore, before step S120, which employs the first preset process to remove the first doped layer and the first mask layer of the first region, the front and side surfaces, and the first tunneling oxide layer of the first region, the following step is added: A first photoresist layer is formed on one side of the process wafer; The first photoresist layer is pre-treated to remove the first photoresist layer in the first region and retain the first photoresist layer in the second region. In addition to step S120, which involves removing the first doped layer and the first mask layer of the first region, the front and side surfaces, and the first tunneling oxide layer of the first region, the following steps are also added: Using the seventh etching process, the first photoresist layer in the second region is removed under the seventh etching conditions.

[0049] Furthermore, in S140, before using the second preset process to remove the second doped layer and the second mask layer of the second region, the front side and the side, as well as the second tunneling oxide layer of the second region, and before forming the textured structure on the front side, the following steps are added: A second photoresist layer is prepared on the side of the second mask layer on the back side away from the N-type silicon substrate; The second photoresist layer is pre-treated to remove the second photoresist layer in the second region, while retaining the second photoresist layer in the first region. Furthermore, in step S140, while removing the second doped layer and the second mask layer of the second region, the front and side surfaces, and the second tunneling oxide layer of the second region, and forming a textured structure on the front surface, the following steps are added: Using the seventh etching process, under the seventh etching conditions, the second photoresist layer in the first region is removed.

[0050] For details not covered in this embodiment, please refer to the above embodiments; no limitations are imposed here.

[0051] refer to Figure 5 As shown, the method includes: S201, Provide process footage.

[0052] S202, A first photoresist layer is formed on one side of the process wafer.

[0053] S203. Pre-process the first photoresist layer to remove the first photoresist layer in the first region and retain the first photoresist layer in the second region.

[0054] The first photoresist layer is a polymer material sensitive to specific wavelengths of light (such as ultraviolet light, deep ultraviolet light, extreme ultraviolet light, or electron beams). It is formed into a uniform thin film by coating it onto the wafer surface.

[0055] In this embodiment, after forming the process wafer 10, a first photoresist layer is formed on one side of the process wafer 10. This is actually formed on the back surface of the N-type silicon substrate 1 using methods such as spin coating to create a first photoresist layer of a certain thickness. The first photoresist layer is pre-treated, which may include exposure and development using a mask to remove the first photoresist layer in the first region, retaining the first photoresist layer in the second region. Under pre-treatment conditions where the UV lamp power in the photoresist curing oven is 30%-70% and the tape speed is 8m / min-15m / min, the first photoresist layer in the second region is cured, providing an opening for subsequent removal of the first mask layer 23, the first doped layer 22, and the first tunneling oxide layer 21 in the first region. The width of the first region can be 400um-500um.

[0056] S204. Using the first etching process, under the first etching conditions, remove the first mask layer of the first region, the front side and the side side.

[0057] The first etching process is a chain acid etching process. The first etching conditions include introducing a 10%-20% hydrofluoric acid solution into the reaction chamber of the first etching process.

[0058] Specifically, after removing the first photoresist layer in the first region, a first etching process is adopted. A hydrofluoric acid solution with a concentration of 10%-20% is introduced into the reaction chamber of the first etching process. Under the first etching conditions, the etching is carried out for a preset time. The chemical reaction between the acidic solution and the first mask layer 23 is used to remove the first mask layer 23 on the back side, front side and side of the N-type silicon substrate 1.

[0059] S205. Using a second etching process, under the second etching conditions, remove the first doped layer in the first region, the front side, and the side side.

[0060] The second etching conditions include introducing a 10%-20% hydrofluoric acid solution and a 5%-15% micro-etching additive mixed solution into the reaction chamber of the second etching process, with an etching temperature of 20℃-25℃ and an etching time of 0.5min-2min.

[0061] Specifically, after removing the first mask layer 23, a second etching process is adopted. A mixed solution consisting of a 10%-20% hydrofluoric acid solution and a 5%-15% micro-etching additive is introduced into the reaction chamber of the second etching process. Etching is carried out under the second etching conditions of an etching temperature of 20℃-25℃ and an etching time of 0.5min-2min. The chemical reaction between the mixed solution and the first doped layer 22 is used to remove the first doped layer 22 on the back side, front side and side of the N-type silicon substrate 1.

[0062] It should be noted that the liquid-carrying roller in the micro-etching additive can selectively etch and remove the first doped layer 22 deposited on the front and side sides, ensuring that the surface of the N-type silicon substrate 1 is not corroded during the etching process, thus protecting the N-type silicon substrate 1. Moreover, the liquid-carrying roller is in contact with the front side. Compared with the existing chain-reinforced nitric acid solution method, it can achieve selective etching of the doped layer, greatly reducing the additional weight reduction caused by acid etching, and preventing the N-type silicon substrate 1 from becoming too thin. This can effectively ensure the yield during the cell fabrication process.

[0063] S206. Using the seventh etching process, under the seventh etching conditions, remove the first photoresist layer in the second region.

[0064] The seventh etching condition includes introducing a 1%-5% sodium hydroxide or potassium hydroxide solution and a 1%-7% sodium hydroxide solution into the reaction chamber of the seventh etching process to form a mixed solution, and the etching temperature is 50℃-90℃.

[0065] Specifically, after removing the first doped layers 22 from the back side, front side, and side surfaces of the N-type silicon substrate 1, the remaining structure includes the first tunneling oxide layer 21 in the first region on the back side of the N-type silicon substrate 1, the first tunneling oxide layer 21 in the second region, the first doped layer 22, the first mask layer 23, and the first photoresist layer. The first photoresist layer is then removed. In this embodiment, a seventh etching process is used. A mixed solution consisting of a 1%-5% sodium hydroxide or potassium hydroxide solution and a 1%-7% sodium hydroxide solution is introduced into the reaction chamber of the seventh etching process. Under the seventh etching conditions of an etching temperature of 50℃-90℃, the first photoresist layer remaining on the surface of the first mask layer 23 in the second region is removed.

[0066] S207. Using the third etching process, under the third etching conditions, the first tunneling oxide layer in the first region is removed.

[0067] The third etching condition includes introducing a 10%-20% sodium hydroxide or potassium hydroxide solution and a 0.5%-2% alkaline etching additive solution into the reaction chamber of the third etching process, and the etching temperature is 50℃-90℃.

[0068] Specifically, after removing the first photoresist layer, the structure at this point includes a first tunneling oxide layer 21 in the first region of the back side of the N-type silicon substrate 1, a first tunneling oxide layer 21 in the second region, a first doped layer 22, and a first mask layer 23. Finally, a third etching process is used. A mixed solution consisting of a 10%-20% sodium hydroxide or potassium hydroxide solution and a 0.5%-2% alkaline etching additive is introduced into the reaction chamber of the third etching process. Under the third etching conditions at an etching temperature of 50℃-90℃, the first tunneling oxide layer 21 in the first region is removed by chemical reaction between the alkaline solution and the first tunneling oxide layer 21. In addition, the etching method described above may result in incomplete etching of the first doped layer 22 and the first mask layer 23 on the front and side sides, leaving some of the first doped layer 22 and the first mask layer 23 on the front and side sides. In this case, the third etching process can be used to further etch the remaining first doped layer 22 and the first mask layer 23, reduce the difference in corrosion between the edge plating area and the normal area of ​​the cell, and thus further enhance the completeness of the cleaning plating.

[0069] S208. A second tunneling oxide layer, a second doped layer, and a second mask layer are sequentially prepared on the back side, and a second doped layer and a second mask layer are formed on the front and side sides.

[0070] S209. Prepare a second photoresist layer on the side of the second mask layer on the back side away from the N-type silicon substrate.

[0071] S210. Pre-process the second photoresist layer to remove the second photoresist layer in the second region and retain the second photoresist layer in the first region.

[0072] The meaning of the second photoresist layer is the same as that of the first photoresist layer, and will not be repeated here.

[0073] Specifically, after forming a second tunneling oxide layer 31, a second doped layer 32, and a second mask layer 33 sequentially on the back side, and forming a second doped layer 32 and a second mask layer 33 sequentially on the front and side sides, a second photoresist layer is formed on the side of the second mask layer 33 facing away from the N-type silicon substrate 1. In practice, a second photoresist layer of a certain thickness is formed on the surface of the second mask layer 33 on the back side of the N-type silicon substrate 1 by spin coating or other methods. The second photoresist layer is pre-treated, which may include exposure and development using a mask to remove the second photoresist layer in the second region, retaining the second photoresist layer in the first region. Under pre-treatment conditions of a UV lamp power of 30%-70% and a tape speed of 8m / min-15m / min in the photoresist curing oven, the second photoresist layer in the first region is cured, providing an opening for subsequent removal of the second mask layer 33, the second doped layer 32, and the second tunneling oxide layer 31 in the second region. The width of the second region can be 300um-400um.

[0074] S211. Using the fourth etching process, under the fourth etching conditions, the second mask layer of the second region, the front side and the side side is removed.

[0075] The fourth etching condition includes introducing a 5%-10% hydrofluoric acid solution into the reaction chamber of the fourth etching process.

[0076] Specifically, after removing the second photoresist layer in the second region, a fourth etching process is adopted. A hydrofluoric acid solution with a concentration of 5%-10% is introduced into the reaction chamber of the fourth etching process. Under the fourth etching conditions, the etching is carried out for a preset time. The chemical reaction between the acidic solution and the second mask layer 33 is used to remove the second mask layer 33 on the back side, front side and side of the N-type silicon substrate 1.

[0077] S212. Using the fifth etching process, under the fifth etching conditions, remove the second doped layer in the second region, the front side and the side side.

[0078] The fifth etching conditions include introducing a 5%-10% hydrofluoric acid solution and a 3%-10% micro-etching additive solution into the reaction chamber of the fifth etching process, with an etching temperature of 20℃-25℃ and an etching time of 0.5min-2min.

[0079] Specifically, after removing the second mask layer 33, a fifth etching process is adopted. A mixed solution consisting of a 5%-10% hydrofluoric acid solution and a 3%-10% micro-etching additive is introduced into the reaction chamber of the fifth etching process. The etching is carried out under the fifth etching conditions of an etching temperature of 20℃-25℃ and an etching time of 0.5min-2min. The chemical reaction between the mixed solution and the second doped layer 32 is used to remove the second doped layer 32 on the back side, front side and side of the N-type silicon substrate 1.

[0080] It should be noted that the liquid-carrying roller in the micro-etching additive can selectively etch and remove the second doped layer 32 deposited on the front and side surfaces, ensuring that the surface of the N-type silicon substrate 1 is not corroded during the etching process, thus protecting the N-type silicon substrate 1. Furthermore, the liquid-carrying roller is in frontal contact with the substrate. Compared to the existing chain-reinforced nitric acid solution method, this allows for selective etching of the doped layer, significantly reducing the additional weight loss caused by acid etching and preventing the N-type silicon substrate 1 from becoming too thin, effectively ensuring the yield during the cell fabrication process. In addition, in this embodiment, the micro-etching additive is mainly hydrogen peroxide (H2O2). Hydrogen peroxide is a strong oxidant that can oxidize silicon to silicon dioxide. The generated silicon dioxide then reacts with HF to form soluble fluorosilicic acid, which can effectively etch the polycrystalline silicon layers (i.e., the first and second doped layers) formed by phosphorus doping or boron doping without the addition of traditional oxidants (such as HNO3). Specifically, regardless of whether the polycrystalline silicon layer is formed by phosphorus doping or boron doping, its substrate is silicon. Hydrogen peroxide reacts with silicon to produce silicon dioxide and water, with the chemical reaction formula being Si + 2H₂O₂ = SiO₂ + 2H₂O. Under the action of HF solution, the generated silicon dioxide (SiO₂) then reacts with hydrofluoric acid (HF) to produce water-soluble hexafluorosilicic acid (H₂SiF₆), thus achieving the etching of the polycrystalline silicon layer using HF and hydrogen peroxide. The chemical equation for this process is: SiO₂ + 6HF = H₂SiF₆ + 2H₂O, and the overall chemical equation is: Si + 2H₂O₂ + 6HF = H₂SiF₆ + 4H₂O. In other words, this embodiment utilizes the oxidizing power provided by hydrogen peroxide (H₂O₂) and the dissolving power provided by HF to construct a highly efficient "oxidation-dissolution" cycle system, which can effectively etch polycrystalline silicon layers formed by phosphorus doping or boron doping without the addition of traditional oxidants (such as HNO₃).

[0081] S213. Using the seventh etching process, under the seventh etching conditions, remove the second photoresist layer in the first region.

[0082] The seventh etching condition includes introducing a 1%-5% sodium hydroxide or potassium hydroxide solution and a 1%-7% sodium hydroxide solution into the reaction chamber of the seventh etching process to form a mixed solution, and the etching temperature is 50℃-90℃.

[0083] Specifically, after removing the second doped layers 32 from the second region on the back side, the front side, and the sides of the N-type silicon substrate 1, the remaining structure includes the second tunneling oxide layer 31, the second doped layer 32, the second mask layer 33, and the second photoresist layer in the first region on the back side of the N-type silicon substrate 1, and the first tunneling oxide layer 21, the first doped layer 22, the first mask layer 23, and the second tunneling oxide layer 31 in the second region. The second photoresist layer is then removed. In this embodiment, a seventh etching process is used. A mixed solution consisting of a 1%-5% sodium hydroxide or potassium hydroxide solution and a 1%-7% sodium hydroxide solution is introduced into the reaction chamber of the seventh etching process. Under the seventh etching conditions with an etching temperature of 50℃-90℃, the second photoresist layer remaining on the surface of the second mask layer 33 in the first region is removed.

[0084] S214. Using the sixth etching process, under the sixth etching conditions, the second tunneling oxide layer in the second region is removed, and a textured structure is formed on the front side.

[0085] The sixth etching condition includes introducing a 1%-3% sodium hydroxide or potassium hydroxide solution and a 0.5%-2% alkaline etching additive solution into the reaction chamber of the sixth etching process, and the etching temperature is 50℃-90℃.

[0086] Specifically, after removing the second photoresist layer, the structure at this point includes a second tunneling oxide layer 31, a second doped layer 32, and a second mask layer 33 in the first region on the back side of the N-type silicon substrate 1, and a first tunneling oxide layer 21, a first doped layer 22, a first mask layer 23, and a second tunneling oxide layer 31 in the second region. Finally, a sixth etching process is used. This involves introducing a mixed solution of 1%-3% sodium hydroxide or potassium hydroxide solution and 0.5%-2% alkaline etching additive into the reaction chamber of the sixth etching process. Under the sixth etching conditions of 50℃-90℃, the second tunneling oxide layer 31 in the second region is removed through a chemical reaction between the alkaline solution and the second tunneling oxide layer 31. Furthermore, the alkaline solution can simultaneously be used to create a textured surface structure on the front side. In addition, the etching method described above may result in incomplete etching of the second doped layer 32 and the second mask layer 33 on the front and side surfaces, leaving some of the second doped layer 32 and the second mask layer 33 remaining on the front and side surfaces. In this case, the sixth etching process can be used to further etch the remaining second doped layer 32 and the second mask layer 33. The difference in etching amount between the edge plating position and the normal area in the middle of the N-type silicon substrate 1 is small, ensuring that the front surface is in the silicon substrate state during the texturing process, and can be etched simultaneously without discrimination, ultimately completely removing the edge plating, improving the surface morphology of the N-type silicon substrate 1, and increasing the light absorption efficiency.

[0087] S215, Remove the second mask layer of the first region and the first mask layer of the second region, and prepare a first protective layer on the side surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and prepare a second protective layer on the textured surface.

[0088] S216. Screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the second doped layer in the first region and a second electrode in contact with the first doped layer in the second region, thereby obtaining a TBC battery.

[0089] The technical solution of this invention utilizes a mixed solution formed by an acidic solution and micro-etching additives to remove the doped layer and mask layer formed by wire bonding. This ensures that the surface of the N-type silicon substrate is not corroded during the etching process, protecting the N-type silicon substrate. Furthermore, the front-facing contact roller with liquid provides excellent contact isolation, improves passivation, and enhances photoelectric conversion efficiency. Compared to existing chain-reinforced nitric acid solutions, this method allows for selective etching of the doped layer, significantly reducing the additional weight loss caused by acid etching and preventing the N-type silicon substrate from becoming too thin. This effectively ensures the yield during the cell fabrication process. On the other hand, compared to rough polishing processes, it eliminates the need for additional tanks or equipment. Moreover, the TBC cell with photolithography has photoresist protection on the back, allowing for adjustment of the process window during front-facing wire bonding. The process parameter requirements are relatively low, making it more suitable for mass production.

[0090] In another specific embodiment, optionally, S110, providing a process slice, includes: Using a deposition process, a first tunneling oxide layer and a first intrinsic silicon layer are sequentially formed on the back side.

[0091] The deposition process includes thermal oxidation, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, etc., and the specific method can be determined according to the situation, without limitation. The first intrinsic silicon layer is a silicon material layer with intrinsic semiconductor properties. Intrinsic semiconductors refer to semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs within the material itself.

[0092] Specifically, using a thermal oxidation process, by introducing a certain flow rate of oxygen into the reaction chamber of the thermal oxidation process, an ultrathin first tunneling oxide layer 21 can be deposited on the back side, with a thickness of 1nm-2nm. After forming the first tunneling oxide layer 21, a deposition process, such as low-pressure chemical vapor deposition, is used to introduce a certain flow rate of silane into the reaction chamber of the deposition process, and at a preset deposition temperature, a first intrinsic silicon layer is deposited on the surface of the first tunneling oxide layer 21 on the side facing away from the N-type silicon substrate 1, with a thickness of 100nm-400nm.

[0093] It should be noted that before forming the first tunneling oxide layer 21 and the first doped layer 22 on the back side of the N-type silicon substrate 1, double-sided polishing of the N-type silicon substrate 1 is required to obtain a surface with high flatness and low surface roughness to meet the requirements of subsequent micro-nano fabrication. First, an N-type single-crystal silicon wafer with resistivity strictly controlled within the range of 0.5 Ω·cm to 30 Ω·cm is selected, as this resistivity range can balance good conductivity and device isolation performance. Subsequently, the front and back sides of the single-crystal silicon wafer are processed simultaneously through a combination of multi-step mechanical grinding and chemical mechanical polishing (CMP): first, rough grinding is performed using diamond abrasive to remove the cutting damage layer and control the total thickness, then fine grinding and precision grinding are performed to gradually reduce the surface roughness; finally, alkaline or neutral CMP slurry (such as polishing slurry containing silicon dioxide or cerium oxide) is used for final polishing to achieve atomic-level smoothness (Ra < 0.2 nm). Throughout the process, it is necessary to precisely control the polishing pressure, rotation speed, slurry flow rate and time, and to cooperate with online thickness and warpage monitoring to ensure that the size of the tower base (i.e. the effective device area) is stable within the range of 5mm-30mm, while maintaining the overall parallelism and surface cleanliness of the monocrystalline silicon wafer, and finally obtain an N-type silicon substrate that meets the requirements of high-end semiconductor or photovoltaic applications.

[0094] Using a boron diffusion process, the first intrinsic silicon layer is boron-doped to form a first doped layer and a first mask layer, and the first doped layer and the first mask layer are stacked on the front and side sides.

[0095] Boron diffusion is a doping technique used to introduce boron atoms into the first intrinsic silicon layer to form a P-type doped region. In this embodiment, the boron diffusion process may include ion implantation, etc.

[0096] Specifically, using a boron diffusion process, boron trichloride and oxygen are introduced into the reaction chamber. The chemical reaction between boron trichloride, oxygen, and the first intrinsic silicon layer allows a layer of boron to be deposited at low temperature on the surface of the first intrinsic silicon layer away from the N-type silicon substrate 1. After boron deposition, high-temperature propulsion is applied to diffuse the boron doping into the first intrinsic silicon layer, forming a first doped layer 22. After the first doped layer 22 is formed by high-temperature doping in the first region, since the boron in the doping process usually does not completely react into the first intrinsic silicon layer, some residual organic matter is generated during the reaction. To prevent this residual organic matter from affecting the first doped layer 22, it can be post-oxidized. A certain flow rate of oxygen is introduced into the post-oxidation reaction chamber, allowing the residual organic matter to react with oxygen to form a first mask layer. Typically, the first mask layer is a borosilicate glass layer.

[0097] Further, in step S130, a second tunneling oxide layer, a second doped layer, and a second mask layer are sequentially stacked on the back side, and a second doped layer and a second mask layer are stacked on the front and side sides, including: Using a deposition process, a second tunneling oxide layer and a second intrinsic silicon layer are sequentially formed on the back side.

[0098] The deposition process includes thermal oxidation, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, etc., and the specific method can be determined according to the situation, without limitation. The second intrinsic silicon layer is a silicon material layer with intrinsic semiconductor properties. Intrinsic semiconductors refer to semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs within the material itself.

[0099] Specifically, using a thermal oxidation process, by introducing a certain flow rate of oxygen into the reaction chamber of the thermal oxidation process, an ultrathin second tunneling oxide layer 31 can be deposited on the back side. The thickness of the second tunneling oxide layer 31 is 1nm-2nm. After the formation of the second tunneling oxide layer 31, a deposition process, such as low-pressure chemical vapor deposition, is used. By introducing a certain flow rate of silane into the reaction chamber of the deposition process and at a preset deposition temperature, a second intrinsic silicon layer is deposited on the surface of the second tunneling oxide layer 31 on the side facing away from the N-type silicon substrate 1. The thickness of the second intrinsic silicon layer is 100nm-400nm.

[0100] Using a phosphorus doping process, the second intrinsic silicon layer is phosphorus doped to form a stacked second doped layer and a second mask layer, and a stacked second doped layer and a second mask layer are formed on the front and side sides.

[0101] Phosphorus diffusion is a process that forms an N-region on an N-type silicon substrate 1 through phosphorus diffusion, thereby forming a PN junction. The PN junction is responsible for separating photogenerated carriers (electron-hole pairs) to achieve photoelectric conversion.

[0102] Specifically, similar to the formation process of the first doped layer 22, a certain flow rate of nitrogen and oxygen is introduced into the reaction chamber of the low-temperature deposition process. The nitrogen is doped with phosphorus oxychloride, which serves as the dopant source for the phosphorus diffusion process. Under preset deposition conditions, a layer of phosphorus can be deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate 1 through a chemical reaction between phosphorus oxychloride, oxygen, and the second intrinsic silicon layer. After phosphorus formation, it is propagated at high temperature. By setting the propagation temperature, phosphorus diffuses into the second intrinsic silicon layer, forming the second doped layer 32. After the second doped layer 32 is formed, residual organic matter generated during the doping process is post-oxidized. A certain flow rate of oxygen is introduced into the post-oxidation reaction chamber, causing the residual organic matter to react with oxygen to form a second mask layer. Typically, the second mask layer is a phosphorus-silicon glass layer.

[0103] Based on the same inventive concept, the present invention provides a TBC battery, which is prepared by the above-described TBC battery preparation method and has the same functional modules and beneficial effects as the method described above.

[0104] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0105] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing a TBC battery, characterized in that, include: A process wafer is provided; the process wafer includes an N-type silicon substrate, the N-type silicon substrate includes a front side, a side side and a back side, the front side and the side side each include a stacked first doped layer and a first mask layer, the back side includes a first region and a second region arranged in an interdigitated space, and the back side includes a first tunneling oxide layer, the first doped layer and the first mask layer stacked sequentially. The first preset process is used to remove the first doped layer and the first mask layer in the first region, the front side and the side side, as well as the first tunneling oxide layer in the first region. A second tunneling oxide layer, a second doped layer, and a second mask layer are sequentially stacked on the back side, and a second doped layer and a second mask layer are stacked on the front side and the side side. Using a second preset process, the second doped layer and the second mask layer in the second region, the front side and the side side, as well as the second tunneling oxide layer in the second region, are removed, and a textured structure is formed on the front side; Remove the second mask layer in the first region and the first mask layer in the second region, and prepare a first protective layer on the side surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and prepare a second protective layer on the textured surface; The first region and the second region are screen printed and sintered at high temperature to form a first electrode in the first region that contacts the second doped layer, and a second electrode in the second region that contacts the first doped layer, thereby obtaining the TBC battery.

2. The preparation method according to claim 1, characterized in that, Using a first preset process, the first doped layer and the first mask layer in the first region, the front side, and the side side, as well as the first tunneling oxide layer in the first region, are removed, including: Using a first etching process and under first etching conditions, the first mask layer of the first region, the front side, and the side side is removed; Using a second etching process, under second etching conditions, the first doped layer in the first region, the front side, and the side side is removed; The first tunneling oxide layer in the first region is removed using a third etching process under third etching conditions.

3. The preparation method according to claim 2, characterized in that, The first etching conditions include introducing a 10%-20% hydrofluoric acid solution into the reaction chamber of the first etching process; and / or, the second etching conditions include introducing a 10%-20% hydrofluoric acid solution and a 5%-15% micro-etching additive mixed solution into the reaction chamber of the second etching process, with an etching temperature of 20℃-25℃ and an etching time of 0.5min-2min; and / or, the third etching conditions include introducing a 10%-20% sodium hydroxide or potassium hydroxide solution and a 0.5%-2% alkaline etching additive mixed solution into the reaction chamber of the third etching process, with an etching temperature of 50℃-90℃.

4. The preparation method according to claim 1, characterized in that, A second preset process is employed to remove the second doped layer and the second mask layer in the second region, the front side, and the side surface, as well as the second tunneling oxide layer in the second region, and to form a textured structure on the front side, including: The second mask layer of the second region, the front side, and the side side is removed by a fourth etching process under the fourth etching conditions. Using a fifth etching process, under fifth etching conditions, the second doped layer in the second region, the front side, and the side side is removed; Using a sixth etching process, under the sixth etching conditions, the second tunneling oxide layer in the second region is removed, and the textured structure is formed on the front side.

5. The preparation method according to claim 4, characterized in that, The fourth etching condition includes introducing a 5%-10% hydrofluoric acid solution into the reaction chamber of the fourth etching process; and / or, the fifth etching condition includes introducing a 5%-10% hydrofluoric acid solution and a 3%-10% micro-etching additive mixed solution into the reaction chamber of the fifth etching process, with an etching temperature of 20℃-25℃ and an etching time of 0.5min-2min; and / or, the sixth etching condition includes introducing a 1%-3% sodium hydroxide or potassium hydroxide solution and a 0.5%-2% alkaline etching additive mixed solution into the reaction chamber of the sixth etching process, with an etching temperature of 50℃-90℃.

6. The preparation method according to claim 1, characterized in that, Before removing the first doped layer and the first mask layer in the first region, the front side, and the side side, and the first tunneling oxide layer in the first region using the first preset process, the process further includes: A first photoresist layer is formed on one side of the process wafer; The first photoresist layer is pre-treated to remove the first photoresist layer in the first region and retain the first photoresist layer in the second region. In addition to removing the first doped layer and the first mask layer in the first region, the front side, and the side side, as well as the first tunneling oxide layer in the first region, the process also includes: The first photoresist layer in the second region is removed using the seventh etching process under the seventh etching conditions.

7. The preparation method according to claim 6, characterized in that, The process employs a second preset process to remove the second doped layer and the second mask layer in the second region, the front side, and the side surface, as well as the second tunneling oxide layer in the second region. Before forming the textured structure on the front side, the process further includes: A second photoresist layer is prepared on the side of the second mask layer on the back side away from the N-type silicon substrate; The second photoresist layer is pre-treated to remove the second photoresist layer in the second region, while retaining the second photoresist layer in the first region. The process includes removing the second doped layer and the second mask layer from the second region, the front side, and the side surface, as well as the second tunneling oxide layer from the second region, and forming a textured structure on the front side, while also including: Using the seventh etching process, under the seventh etching conditions, the second photoresist layer in the first region is removed.

8. The preparation method according to claim 7, characterized in that, The seventh etching conditions include introducing a 1%-5% sodium hydroxide or potassium hydroxide solution and a 1%-7% sodium hydroxide solution into the reaction chamber of the seventh etching process to form a mixed solution, and the etching temperature is 50℃-90℃.

9. The preparation method according to claim 1, characterized in that, Provide process footage, including: Using a deposition process, the first tunneling oxide layer and the first intrinsic silicon layer are sequentially formed on the back side; Boron diffusion process is used to dope the first intrinsic silicon layer with boron to form the first doped layer and the first mask layer, and the first doped layer and the first mask layer are stacked on the front side and the side side. A second tunneling oxide layer, a second doped layer, and a second mask layer are sequentially stacked on the back side, and a second doped layer and a second mask layer are stacked on the front and side sides, including: Using the aforementioned deposition process, a second tunneling oxide layer and a second intrinsic silicon layer are sequentially formed on the back side; The second intrinsic silicon layer is phosphorus-doped using a phosphorus doping process to form a stacked second doped layer and a second mask layer, and the stacked second doped layer and the second mask layer are formed on the front side and the side side.

10. A TBC battery, characterized in that, The TBC battery is prepared according to the preparation method of any one of claims 1-9.

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