A method for manufacturing a tbc battery and a tbc battery

Abstract

This invention discloses a method for fabricating a TBC (Transient Carbon Burger) battery and the TBC battery itself. First, a central region and an edge region are defined on one side surface of an N-type silicon substrate. The central region includes a first region and a second region. Then, using photolithography and wet etching, a first tunneling oxide layer and a boron diffusion-doped layer are sequentially fabricated on the surface of the N-type silicon substrate corresponding to the first region. A second tunneling oxide layer and a phosphorus diffusion-doped layer are sequentially fabricated on the surface of the N-type silicon substrate corresponding to the second region. Next, a first passivation film is fabricated on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and a second passivation film is fabricated on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer. Finally, screen printing and sintering are performed on both sides of the first and second passivation films to obtain the TBC battery. This effectively prevents photoresist from spreading from the edge of the back side of the N-type silicon substrate to the front side of the N-type silicon substrate from the source.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more particularly to a method for preparing a TBC cell and the TBC cell itself. Background Technology

[0002] TBC (Tunnel Oxide Passivated Contact) cells are crystalline silicon solar cells with a tunnel oxide passivated contact back contact structure. They combine TOPCon (Tunnel Oxide Passivated Contact) with BC (Back Contact) technology, forming high-quality, interdigitated P-regions and N-regions on the back of the cell. A key feature of TBC cells is that both the PN junction and the metal contact are located on the back of the cell, with no metal grid lines obstructing the front (light-receiving surface). This results in higher short-circuit current, and the back side allows for wider metal grid lines, reducing series resistance and improving the fill factor.

[0003] Currently, the division of the P-region and N-region on the back of a TBC cell is generally achieved by photoresist coating. However, since TBC cells are usually thin (e.g., 130μm), the liquid photoresist is very likely to migrate and accumulate towards the edge of the back of the N-type silicon substrate. More importantly, some of the liquid photoresist may also crawl from the edge of the back of the N-type silicon substrate across the edge line and spread to the front of the N-type silicon substrate. This kind of photoresist overflow on the back edge of the N-type silicon substrate will cause a series of serious problems: (1) It will cause abnormal appearance of the front side of the N-type silicon substrate: the photoresist residue on the edge of the front side of the N-type silicon substrate will form a smudge ring, affecting the aesthetics of the product. This is a fatal defect for applications such as double-glass modules that emphasize appearance; (2) There is a risk of structural damage: the photoresist overflow on the back edge of the N-type silicon substrate may contaminate the front side of the N-type silicon substrate. In the subsequent removal or cleaning process, it will also cause damage to the passivation film layer, which will lead to the performance degradation or failure of the TBC battery; (3) It will reduce the reliability of the fabrication process: the photoresist overflow on the back edge of the N-type silicon substrate will cause the corresponding photolithography pattern to be deformed, affecting the electrode isolation or contact performance.

[0004] Furthermore, existing technologies primarily address the aforementioned edge overflow phenomenon by optimizing photoresist printing parameters or using cleaning solutions. However, optimizing photoresist printing parameters has limited effectiveness, failing to eliminate the physical climb of the liquid photoresist, meaning it cannot effectively prevent the liquid photoresist from spreading from the back edge of the N-type silicon substrate to the front edge. Using cleaning solutions is mainly for treating residual photoresist at the edges of the back edge of the N-type silicon substrate; for photoresist that has already spread to the front edge, cleaning is ineffective in removing it completely and may even cause secondary damage to the passivation film and other structures on the front edge of the N-type silicon substrate. Summary of the Invention

[0005] This invention provides a method for fabricating a TBC battery and a TBC battery, which achieves photoresist edge blocking technology through a pre-set edge region, effectively preventing the photoresist from spreading from the edge of the back side of the N-type silicon substrate to the front side of the N-type silicon substrate from the source, thereby effectively improving the manufacturing yield and product quality of the fabricated TBC battery.

[0006] In a first aspect, embodiments of the present invention provide a method for preparing a TBC battery, comprising: A middle region and an edge region are defined on one side surface of an N-type silicon substrate; wherein the edge region is arranged around the middle region, and the width of the edge region at any position ranges from 50 to 200 μm; the middle region includes a first region and a second region arranged alternately in an interdigitated pattern. A first tunneling oxide layer and a boron diffusion doped layer are sequentially prepared on the surface of the N-type silicon substrate corresponding to the first region using photolithography and wet etching, and a second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially prepared on the surface of the N-type silicon substrate corresponding to the second region. A first passivation film is formed on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and a second passivation film is formed on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer. The TBC battery is fabricated by screen printing and sintering on one side of the first passivation film layer and the other side of the second passivation film layer to form an electrode structure.

[0007] Optionally, an adhesive overflow barrier structure is provided in the edge region.

[0008] Optionally, a first tunneling oxide layer and a boron diffusion doped layer are sequentially formed on the surface of the N-type silicon substrate corresponding to the first region using photolithography and wet etching, and a second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially formed on the surface of the N-type silicon substrate corresponding to the second region, including: The first tunneling oxide layer and the first intrinsic silicon layer are prepared on the surface of the N-type silicon substrate; The side of the first intrinsic silicon layer away from the first tunneling oxide layer is subjected to boron diffusion doping to form the boron diffusion doped layer; The boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region are removed by photolithography and wet etching, and the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed. A second tunneling oxide layer and a second intrinsic silicon layer are formed on the surface of the N-type silicon substrate on the side away from the boron diffusion doping layer; The side of the second intrinsic silicon layer away from the second tunneling oxide layer is subjected to phosphorus diffusion doping to form the phosphorus diffusion doped layer; The phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region are removed by photolithography and wet etching, and the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed.

[0009] Optionally, photolithography and wet etching are used to remove the boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region, exposing the surface of the N-type silicon substrate corresponding to the second region and the edge region, including: A first photoresist layer is formed on the side of the boron diffusion doped layer corresponding to the first region that is away from the first tunneling oxide layer; The boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region are subjected to wet etching until the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed.

[0010] Optionally, after performing wet etching on the boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region until the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed, the process further includes: The first photoresist layer corresponding to the first region is subjected to wet etching until the surface of the boron diffusion doped layer corresponding to the first region is exposed.

[0011] Optionally, photolithography and wet etching are used to remove the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region, exposing the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region, including: A second photoresist layer is formed on the side of the phosphorus diffusion doped layer corresponding to the second region that is away from the second tunneling oxide layer; The phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region are subjected to wet etching until the surface of the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed.

[0012] Optionally, after performing wet etching on the phosphorus diffusion-doped layer and the second tunneling oxide layer corresponding to the first region and the edge region until the surface of the boron diffusion-doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed, the process further includes: The second photoresist layer corresponding to the second region is subjected to wet etching until the surface of the phosphorus diffusion doped layer corresponding to the second region is exposed.

[0013] Optionally, the first passivation film layer includes a first anti-ultraviolet attenuation film layer and a first anti-reflection layer, and the second passivation film layer includes a second anti-ultraviolet attenuation film layer and a second anti-reflection layer; The process of forming a first passivation film layer on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and forming a second passivation film layer on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer, includes: The first anti-UV degradation film layer is prepared on the side of the boron diffusion doped layer away from the first tunneling oxide layer, and the second anti-UV degradation film layer is prepared on the side of the phosphorus diffusion doped layer away from the second tunneling oxide layer; The first antireflection layer is prepared on the side of the first anti-ultraviolet attenuation film layer away from the boron diffusion doping layer, and the second antireflection layer is prepared on the side of the second anti-ultraviolet attenuation film layer away from the phosphorus diffusion doping layer.

[0014] Optionally, before screen printing and sintering are performed on one side of the first passivation film layer and one side of the second passivation film layer to form an electrode structure, the process further includes: A third passivation film is prepared on the surface of the N-type silicon substrate away from the first tunneling oxide layer and the second tunneling oxide layer.

[0015] Secondly, embodiments of the present invention also provide a TBC battery, which is prepared using the TBC battery preparation method described in any one of the first aspects.

[0016] This invention provides a method for fabricating a TBC battery and the TBC battery itself. First, a central region and an edge region are defined on one side surface of an N-type silicon substrate. The edge region surrounds the central region, and its width at any position ranges from 50 to 200 μm. The central region includes a first region and a second region arranged alternately in an interdigitated pattern. Then, using photolithography and wet etching, a first tunneling oxide layer and a boron diffusion doped layer are sequentially fabricated on the surface of the N-type silicon substrate corresponding to the first region. A second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially fabricated on the surface of the N-type silicon substrate corresponding to the second region. Next, a first passivation film is fabricated on the side of the boron diffusion doped layer away from the first tunneling oxide layer, and a second passivation film is fabricated on the side of the phosphorus diffusion doped layer away from the second tunneling oxide layer. Finally, screen printing and sintering are performed on the side of the first passivation film and the side of the second passivation film to form an electrode structure, thus obtaining the TBC battery. The above method aims to solve the problem of front-side appearance defects and structural anomalies caused by the accumulation and flow of photoresist at the edge regions (i.e., edge overflow) during the photoresist coating process on the back side of an N-type silicon substrate. By implementing photoresist edge blocking technology in a pre-defined edge region on the back side of the N-type silicon substrate, and limiting the width of this edge region to a range of 50-200 μm at any location, radial creep and accumulation of photoresist during coating are effectively restricted. This prevents overflowing photoresist from crossing the back edge or spreading to non-target areas on the front side. In other words, it effectively prevents the flowing photoresist from spreading from the edge on the back side of the N-type silicon substrate to the front side, ensuring the aesthetics of the front-side structure of the N-type silicon substrate and the quality of the fabricated TBC electrode. The overall aesthetics of the cell are improved, and damage to the front side of the N-type silicon substrate caused by photoresist overflow can be avoided. Furthermore, secondary damage to the passivation film and other structures on the front side of the N-type silicon substrate caused by photoresist removal using cleaning solutions can also be prevented. This effectively improves the manufacturing yield and product quality of the prepared TBC cells, significantly enhancing their overall performance. Additionally, preventing photoresist overflow at the edges of the back side of the N-type silicon substrate avoids deformation of the corresponding photolithographic pattern, ensuring the accuracy of the division between the first and second regions. While maintaining the accuracy of the photolithographic pattern on the back side of the N-type silicon substrate, the appearance yield and structural integrity of the front side of the N-type silicon substrate are significantly improved. The isolation or contact performance of the formed electrode structure is unaffected, and the process compatibility is good, making it suitable for large-scale industrial production.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic flowchart of a method for preparing a TBC battery according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of another method for preparing a TBC battery provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a schematic flowchart of a TBC battery preparation method provided by an embodiment of the present invention. This TBC battery preparation method is applicable to the preparation of TBC batteries and can be used to prepare TBC batteries. Figure 1 As shown, the preparation method includes: S110. A middle region and an edge region are divided on one side surface of an N-type silicon substrate; wherein the edge region is arranged around the middle region, and the width of the edge region at any position ranges from 50 to 200 μm, and the middle region includes a first region and a second region arranged alternately in an interdigitated pattern.

[0023] Specifically, an N-type silicon substrate is provided, the N-type silicon substrate including a first surface and a second surface that are opposite to each other. Exemplarily, the first surface can be understood as the back surface of the N-type silicon substrate, and the second surface can be understood as the front surface of the N-type silicon substrate.

[0024] The first surface of the N-type silicon substrate is a polished surface. Exemplarily, the first surface of the N-type silicon substrate can be subjected to alkaline polishing to ensure it is a polished surface, thereby forming a highly reflective polished surface. This improves the flatness of the battery surface and increases the reflection of long-wavelength light, promoting secondary light absorption, increasing short-circuit current, and reducing leakage current. Furthermore, exemplarily, the alkaline polishing treatment achieves a double-sided polishing effect; that is, both the front and back sides of the N-type silicon substrate can be alkaline polished simultaneously.

[0025] The second surface of the N-type silicon substrate is textured. Exemplarily, the second surface of the N-type silicon substrate can be textured to create a textured surface; exemplarily, the textured surface exhibits a pyramidal structure when tested under a microscope. Textured processing can remove organic contaminants and metallic impurities from the surface of the N-type silicon substrate, remove the mechanical damage layer generated during the wire cutting process, reduce recombination centers, and create an uneven textured surface. This facilitates the use of light-trapping effects, increasing the absorption rate of sunlight by the N-type silicon substrate, reducing reflectivity, and simultaneously increasing the surface area of ​​the N-type silicon substrate, thereby also increasing the area of ​​the PN junction formed on the surface.

[0026] Furthermore, it should be noted that this embodiment does not impose specific requirements or limitations on the order of alkaline polishing and texturing. In practice, alkaline polishing can be performed first, followed by texturing, or vice versa. This embodiment is merely an example and is not intended to limit the process. Additionally, after alkaline polishing and texturing, the N-type silicon substrate can be subjected to a chain-like acid pickling process using hydrochloric acid (HCl) solution to further ensure the cleanliness of both sides of the N-type silicon substrate.

[0027] Furthermore, this embodiment pre-divides a central region and an edge region on one side of the back surface of the N-type silicon substrate. The edge region surrounds the central region, which can subsequently be used to form the corresponding film structure. The width of the edge region at any location ranges from 50 to 200 μm. This edge region is spaced between the central region and the edge ridge of the back surface of the N-type silicon substrate. This aims to solve the problem of front-side appearance defects and structural anomalies caused by the accumulation and flow of photoresist at the edge region (i.e., edge overflow) during the photoresist coating process on the back surface of the N-type silicon substrate. The positioning of the edge region and its corresponding width at any location effectively limit the radial creep and accumulation of photoresist during the coating process, thereby preventing the overflowing photoresist liquid from crossing the edge of the back surface or spreading to non-target areas on the front surface. In other words, it effectively prevents the applied flowing photoresist from spreading from the edge of the back surface of the N-type silicon substrate to the front surface of the N-type silicon substrate from the source. It is understandable that if the width of the edge region at any location is less than 50 μm, the liquid photoresist applied near that location can easily flow and cross the back edge of the N-type silicon substrate, even spreading to the front edge. If the width of the edge region at any location is greater than 200 μm, the liquid photoresist applied near that location will not flow and cross the back edge of the N-type silicon substrate, even spreading to the front edge, but this will result in lower utilization of the back area of ​​the N-type silicon substrate, thus affecting the manufacturing cost and product quality of the fabricated TBC battery. Furthermore, exemplarily, the extension direction of the edge region at any location can be a straight line or a curve; this embodiment is not limited thereto. Exemplarily, the surface of the N-type silicon substrate corresponding to the edge region can also be textured, and the edge region may not subsequently form a corresponding film structure.

[0028] S120. Using photolithography and wet etching, a first tunneling oxide layer and a boron diffusion doped layer are sequentially prepared on the surface of the N-type silicon substrate corresponding to the first region, and a second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially prepared on the surface of the N-type silicon substrate corresponding to the second region.

[0029] Specifically, the intermediate region includes a first region and a second region arranged in an interdigitated pattern. In other words, the first region and the second region are located on the same side surface of the N-type silicon substrate, and the first region and the second region are arranged in an interdigitated pattern. Exemplarily, the first region and the second region can both be located on the back side of the N-type silicon substrate. Exemplarily, one of the first region and the second region can be a P-region, and the other can be an N-region. During the fabrication of the TBC battery, doping can be used to make the P-region rich in holes and the N-region rich in electrons. When these two regions come into contact, a PN junction can be formed. When light shines on the PN junction, the energy of the photons is absorbed by the electrons, causing some electrons to jump from the valence band to the conduction band, while simultaneously generating holes. Because the P-region is rich in holes and the N-region is rich in electrons, electrons and holes diffuse in opposite directions, forming a photogenerated potential difference. The photogenerated potential difference causes electrons and holes to move towards the P-region and N-region, respectively. Due to the electric field on the PN junction, electrons are attracted to the N-region, while holes are attracted to the P-region, thus creating a potential gradient that causes electrons to flow from the N-region to the P-region and holes to flow from the P-region to the N-region, thereby generating a photocurrent. An external circuit collects this photocurrent, thus converting light energy into electrical energy. In one specific embodiment, for example, the first region can be a P-region and the second region can be an N-region. More easily understood, the first region can be subsequently used to fabricate a positive gate line, that is, to achieve conduction between the p+ doped region and the positive gate line, thereby achieving good ohmic contact between the positive gate line and the N-type silicon substrate. Similarly, the second region can be subsequently used to fabricate a negative gate line, that is, to achieve conduction between the n+ doped region and the negative gate line, thereby achieving good ohmic contact between the negative gate line and the N-type silicon substrate.

[0030] It should also be noted that this embodiment employs photolithography and wet etching to facilitate the formation of the first tunneling oxide layer and boron diffusion doped layer in the first region, and the formation of the second tunneling oxide layer and phosphorus diffusion doped layer in the second region. In this case, edge overflow caused by photoresist coating will not occur. The edge region design effectively prevents the flowing photoresist from spreading from the back edge of the N-type silicon substrate to the front edge. It is understood that the precision of the photolithography process directly determines the quality of the pattern boundary between the N-region and P-region in the fabricated TBC battery. Higher precision photolithography can achieve finer and more regular pattern transfer, making the outlines of the doped regions corresponding to the N-region and P-region clear, consistent in size, and smooth at the edges, thereby effectively avoiding boundary blurring caused by pattern blurring, offset, or distortion. Precise division of the N-region and P-region can significantly reduce the risk of leakage, punch-through, and other failures in the fabricated TBC battery, improve the consistency and stability of the electrical characteristics of the PN junction, and ensure the controllability of key parameters such as the threshold voltage and on-resistance of the fabricated TBC battery. This not only provides a reliable patterning basis for subsequent processes, but also helps to improve the yield and performance of the prepared TBC cells, meeting the manufacturing requirements of high-density, high-integration semiconductor devices.

[0031] The first region comprises a first tunneling oxide layer and a boron diffusion doped layer sequentially stacked on the surface of an N-type silicon substrate. In other words, the first tunneling oxide layer and the boron diffusion doped layer can be sequentially fabricated on the surface of the N-type silicon substrate corresponding to the first region. The first tunneling oxide layer allows majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thereby achieving selective carrier collection, reducing surface recombination, and improving the open-circuit voltage and fill factor of the TBC cell, thus enhancing the photoelectric conversion efficiency of the TBC cell. The boron diffusion doped layer is a boron-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with boron. The second region comprises a second tunneling oxide layer and a phosphorus diffusion doped layer sequentially stacked on the surface of an N-type silicon substrate. In other words, the second tunneling oxide layer and the phosphorus diffusion doped layer can be sequentially fabricated on the surface of the N-type silicon substrate corresponding to the second region. The second tunneling oxide layer allows majority carriers (electrons) to pass through smoothly via the tunneling effect while preventing the recombination of minority carriers (holes), thus achieving selective carrier collection, reducing surface recombination, and improving the open-circuit voltage and fill factor of the TBC cell, thereby enhancing the photoelectric conversion efficiency of the TBC cell. The phosphorus diffusion-doped layer is a phosphorus-doped polycrystalline silicon layer, a special semiconductor layer with a high doping concentration formed by doping with phosphorus. This embodiment does not specify specific requirements or limitations for the film preparation process of the TBC cell process wafer; details can be found in subsequent embodiments.

[0032] S130. A first passivation film is prepared on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and a second passivation film is prepared on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer.

[0033] Specifically, a first passivation film is formed on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, that is, the first passivation film is formed in the first region. Exemplarily, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or coating processes can be used to form the first passivation film on one side of the first surface of the N-type silicon substrate. The first passivation film may include an aluminum oxide film and / or a silicon nitride film. The first passivation film has passivation and UV-fastness resistance properties, effectively preventing the entire TBC cell from being affected by ultraviolet and infrared radiation, further ensuring the operational reliability of the entire TBC cell. Furthermore, a second passivation film is formed on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer, that is, the second passivation film is formed in the second region. For example, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and coating processes can be used to form a second passivation film on one side of the first surface of the N-type silicon substrate. The second passivation film may include an aluminum oxide film and / or a silicon nitride film. This second passivation film possesses passivation and UV degradation resistance properties, effectively preventing the entire TBC cell from being affected by ultraviolet and infrared radiation, further ensuring the operational reliability of the entire TBC cell.

[0034] It should also be noted that the first passivation layer and the second passivation layer possess passivation and UV degradation resistance properties, effectively preventing the entire TBC cell from being affected by ultraviolet and infrared radiation, further ensuring the operational reliability of the entire solar cell. Furthermore, the first passivation layer and the second passivation layer can essentially be understood as the same passivation layer; the portion of the passivation layer located in the first region is defined as the first passivation layer, and the portion located in the second region is defined as the second passivation layer.

[0035] S140. Screen printing and sintering are performed on one side of the first passivation film layer and the other side of the second passivation film layer to form an electrode structure and obtain a TBC battery.

[0036] Specifically, screen printing is one of the core processes in solar cell manufacturing, primarily used for electrode forming. This process utilizes the basic principle that the paste passes through the mesh openings of the screen in the patterned areas, while the paste does not pass through the non-patterned areas. During printing, the paste is precisely extruded through the mesh openings of the screen onto the N-type silicon substrate. The paste is evenly distributed on the surface of the solar cell in the form of conductive lines, forming the desired electrode pattern. Typically, the paste used for screen printing can include, but is not limited to, silver paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed onto the surface of the cell at high temperatures. This process dries the paste on the N-type silicon substrate, burns off the organic components of the paste, and allows the paste to etch through the passivation film layer, connecting with the PN junction. This ensures good ohmic contact between the metal grid lines and the N-type silicon substrate, achieving the purpose of collecting and discharging current.

[0037] Furthermore, the solar cells after screen printing are sintered at a temperature range of 740-760℃, followed by a light injection process. Laser-induced diffusion after light injection induces silver-silicon interdiffusion, significantly reducing contact resistance, increasing the fill factor, and effectively improving cell efficiency. In addition, efficiency testing and sorting / packaging can be performed to further improve the product quality and manufacturing yield of the prepared TBC cells.

[0038] The technical solution in this invention aims to solve the problem of front-side appearance defects and structural anomalies caused by the accumulation and flow of photoresist in the edge region (i.e., edge overflow) during the photoresist coating process on the back side of an N-type silicon substrate. By implementing photoresist edge blocking technology in a pre-defined edge region on the back side of the N-type silicon substrate, and limiting the width of the edge region at any position to within the range of 50-200 μm, radial creep and accumulation of photoresist during the coating process are effectively restricted. This prevents overflowing photoresist from crossing the edge of the back side or spreading to non-target areas on the front side. In other words, it effectively prevents the flowing photoresist from spreading from the edge of the back side of the N-type silicon substrate to the front side, ensuring the aesthetics of the front-side structure of the N-type silicon substrate and the quality of the fabricated T-type silicon substrate. The improved aesthetics of the BC battery product also prevent damage to the front side of the N-type silicon substrate caused by photoresist overflow, as well as secondary damage to the passivation film and other structures on the front side of the N-type silicon substrate caused by photoresist removal using cleaning solutions. This effectively improves the manufacturing yield and product quality of the fabricated TBC battery, greatly enhancing its overall performance. Furthermore, preventing photoresist overflow at the edges of the N-type silicon substrate avoids deformation of the corresponding photolithographic pattern, ensuring the accuracy of the division between the first and second regions. While maintaining the accuracy of the photolithographic pattern on the back side of the N-type silicon substrate, it significantly improves the appearance yield and structural integrity of the front side of the N-type silicon substrate. The isolation or contact performance of the formed electrode structure is unaffected, and it has good process compatibility, making it suitable for large-scale industrial production.

[0039] Optionally, an adhesive overflow barrier structure is provided in the edge area.

[0040] Specifically, an overflow barrier structure can be pre-formed in the edge region using a patterned approach to effectively limit the radial creep and accumulation of photoresist during the coating process. This prevents the overflowing photoresist liquid from crossing the edge of the back side or spreading to non-target areas on the front side. In other words, it effectively prevents the applied flowing photoresist from spreading from the edge of the back side of the N-type silicon substrate to the front side of the N-type silicon substrate at the source. Exemplarily, the specific height and material of this overflow barrier structure can be reasonably set according to actual needs, and this embodiment does not limit it.

[0041] Optionally, the first passivation film layer includes a first anti-ultraviolet (UV) attenuation film layer and a first anti-reflection layer, and the second passivation film layer includes a second anti-ultraviolet (UV) attenuation film layer and a second anti-reflection layer; the first passivation film layer is formed on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and the second passivation film layer is formed on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer, including: forming a first anti-ultraviolet (UV) attenuation film layer on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and forming a second anti-ultraviolet (UV) attenuation film layer on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer; forming a first anti-reflection layer on the side of the first anti-ultraviolet (UV) attenuation film layer away from the boron diffusion-doped layer, and forming a second anti-reflection layer on the side of the second anti-ultraviolet (UV) attenuation film layer away from the phosphorus diffusion-doped layer.

[0042] Specifically, the first passivation film layer includes a first anti-UV attenuation film layer and a first anti-reflection layer. The first anti-reflection layer is located on the side of the first anti-UV attenuation film layer away from the boron diffusion-doped layer, that is, the first anti-UV attenuation film layer is located between the boron diffusion-doped layer and the first anti-reflection layer. Exemplarily, the material of the first anti-UV attenuation film layer may include aluminum oxide, and the material of the first anti-reflection layer may include silicon nitride. The second passivation film layer includes a second anti-UV attenuation film layer and a second anti-reflection layer. The second anti-reflection layer is located on the side of the second anti-UV attenuation film layer away from the phosphorus diffusion-doped layer, that is, the second anti-UV attenuation film layer is located between the phosphorus diffusion-doped layer and the second anti-reflection layer. Exemplarily, the material of the second anti-UV attenuation film layer may include aluminum oxide, and the material of the second anti-reflection layer may include silicon nitride.

[0043] Optionally, before screen printing and sintering are performed on one side of the first passivation film and the other side of the second passivation film to form an electrode structure and to obtain a TBC cell, the method further includes: preparing a third passivation film on the surface of the N-type silicon substrate away from the first tunneling oxide layer and the second tunneling oxide layer.

[0044] Specifically, a third passivation film is prepared on the surface of the N-type silicon substrate away from the first and second tunneling oxide layers; that is, a third passivation film is formed on the second surface of the N-type silicon substrate. Exemplarily, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or coating processes can be used to form the third passivation film on the second surface of the N-type silicon substrate. It is understood that the third passivation film possesses passivation and UV degradation resistance properties, effectively preventing the entire TBC cell from being affected by ultraviolet and infrared radiation, further ensuring the operational reliability of the entire solar cell. Optionally, the material of the third passivation film includes aluminum oxide and silicon nitride. Exemplarily, the third passivation film includes a third UV degradation resistance layer and a third antireflection layer, with the third antireflection layer located on the side of the third UV degradation resistance layer away from the second surface of the N-type silicon substrate.

[0045] It should also be noted that this embodiment does not impose specific requirements or limitations on the formation order of the first, second, and third passivation layers. In practice, the first and second passivation layers can be formed simultaneously first, followed by the third passivation layer, or the third passivation layer can be formed first, followed by the first and second passivation layers. Furthermore, the alumina and silicon nitride layers in the first, second, and third passivation layers can be understood as being prepared simultaneously, differing only in their positions, while other parameters and preparation methods remain the same.

[0046] Figure 2 This is a schematic flowchart of another TBC battery fabrication method provided by an embodiment of the present invention. This embodiment is an optimization based on the above embodiment. Optionally, a first tunneling oxide layer and a boron diffusion doped layer are sequentially fabricated on the surface of the N-type silicon substrate corresponding to the first region using photolithography and wet etching, and a second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially fabricated on the surface of the N-type silicon substrate corresponding to the second region, including: A first tunneling oxide layer and a first intrinsic silicon layer are prepared on the surface of an N-type silicon substrate; Boron diffusion doping is performed on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form a boron diffusion doped layer; The boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region are removed by photolithography and wet etching, and the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed. A second tunneling oxide layer and a second intrinsic silicon layer are prepared on the surface of an N-type silicon substrate on the side away from the boron diffusion doping layer. Phosphorus diffusion doping is performed on the side of the second intrinsic silicon layer away from the second tunneling oxide layer to form a phosphorus diffusion doped layer; Photolithography and wet etching are used to remove the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region, and to expose the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region.

[0047] For details not covered in this embodiment, please refer to the above embodiments. Figure 2 As shown, the preparation method includes: S210. A middle region and an edge region are defined on one side surface of an N-type silicon substrate; wherein the edge region is arranged around the middle region, and the width of the edge region at any position ranges from 50 to 200 μm, and the middle region includes a first region and a second region arranged alternately in an interdigitated pattern.

[0048] S220. A first tunneling oxide layer and a first intrinsic silicon layer are prepared on the surface of an N-type silicon substrate.

[0049] S230. Boron diffusion doping is performed on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form a boron diffusion doped layer.

[0050] Specifically, for S220 and S230, the LP process (double insertion, low-pressure chemical vapor deposition) can be used to sequentially deposit a first tunneling oxide layer and a first intrinsic silicon layer on the surface (i.e., the back side) of an N-type silicon substrate. After forming the first intrinsic silicon layer, it is necessary to dope the first intrinsic silicon layer with boron to form a boron diffusion doped layer, and simultaneously form a first associated layer. The first intrinsic silicon layer is a silicon material layer with intrinsic semiconductor characteristics. Intrinsic semiconductors are semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs within the material itself. It is understandable that after high-temperature doping forms a boron diffusion doped layer, the boron in the doping process usually does not completely react into the first intrinsic silicon layer, but will generate certain residual organic matter during the reaction. In order to prevent the residual organic matter from affecting the boron diffusion doped layer, the generated residual organic matter can be post-oxidized. By introducing a certain flow rate of oxygen into the post-oxidation reaction chamber, the residual organic matter reacts with oxygen to form a first associated layer. Under normal circumstances, the first associated layer is a borosilicate glass layer (BSG).

[0051] S240. Using photolithography and wet etching, the boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region are removed, and the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed.

[0052] Optionally, photolithography and wet etching are used to remove the boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region, and expose the surface of the N-type silicon substrate corresponding to the second region and the edge region. This includes: forming a first photoresist layer on the side of the boron diffusion doped layer corresponding to the first region away from the first tunneling oxide layer; and performing wet etching on the boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region until the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed.

[0053] Firstly, it can be understood that the surface of the N-type silicon substrate includes an edge region, a first region, and a second region. If the first tunneling oxide layer is deposited as a whole layer, then the first tunneling oxide layer is present in both the edge region, the first region, and the second region. Similarly, if the first intrinsic silicon layer is also deposited as a whole layer, then the first intrinsic silicon layer is present in both the edge region, the first region, and the second region. If the first intrinsic silicon layer is subjected to boron diffusion doping treatment as a whole layer, then the boron diffusion doped layer is present in both the edge region, the first region, and the second region. Specifically, this step essentially involves sequentially removing the first associated layer, the boron diffusion doped layer, and the first tunneling oxide layer corresponding to the second region, and sequentially removing the first associated layer, the boron diffusion doped layer, and the first tunneling oxide layer corresponding to the edge region. If no first associated layer is actually formed during the process, then only the boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region need to be removed sequentially until the surface of the N-type silicon substrate corresponding to the second region and the surface of the N-type silicon substrate corresponding to the edge region are exposed. For example, the back side of the N-type silicon substrate can be patterned using photolithography and wet etching to completely remove the boron diffusion doping layer and the first tunneling oxide layer corresponding to the second region and the edge region, leaving only the boron diffusion doping layer and the first tunneling oxide layer corresponding to the first region. For example, before performing wet etching, a first photoresist layer can be formed on the side of the boron diffusion doping layer corresponding to the first region away from the first tunneling oxide layer. This first photoresist layer can be understood as a mask layer. For example, this first photoresist layer can cover the first region and expose the second region and the edge region, so as to facilitate subsequent precise wet etching in the second region and the edge region, forming the second region and the edge region corresponding to the etched structure and the first region corresponding to the unetched structure, until the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed, thus making the positional difference between the first region and the second region more obvious. Furthermore, it should be noted that the first photoresist layer is disposed in the first region, and the liquid photoresist corresponding to the first photoresist layer is separated by the edge region, so it will not spread from the edge of the back side of the N-type silicon substrate to the front side of the N-type silicon substrate, effectively avoiding the occurrence of edge overflow.

[0054] Optionally, after performing wet etching on the boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region until the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed, the method further includes performing wet etching on the first photoresist layer corresponding to the first region until the surface of the boron diffusion doped layer corresponding to the first region is exposed.

[0055] Specifically, after wet etching of the boron diffusion-doped layer and the first tunneling oxide layer corresponding to the second and edge regions to ensure their complete etching, wet etching of the first photoresist layer corresponding to the first region is also required. This process involves removing the photoresist layer covering the boron diffusion-doped layer in the first region. Furthermore, exemplarily, if a first associated layer exists, wet etching of the first region is further performed to remove this associated layer until the surface of the boron diffusion-doped layer in the first region is exposed. This complete exposure of the surface of the boron diffusion-doped layer in the first region ensures the contact stability and electrode formation reliability of the fabricated TBC battery.

[0056] S250. A second tunneling oxide layer and a second intrinsic silicon layer are prepared on the surface of an N-type silicon substrate on the side away from the boron diffusion doping layer.

[0057] S260. Phosphorus diffusion doping is performed on the side of the second intrinsic silicon layer away from the second tunneling oxide layer to form a phosphorus diffusion doped layer.

[0058] Specifically, for S250 and S260, the LP process (double insertion, low-pressure chemical vapor deposition) can be used to sequentially deposit a second tunneling oxide layer and a second intrinsic silicon layer on the surface of an N-type silicon substrate away from the boron diffusion doping layer. After forming the second intrinsic silicon layer, it is necessary to dope it with phosphorus to form a phosphorus diffusion doped layer, and simultaneously form a second associated layer. The second intrinsic silicon layer is a silicon material layer with intrinsic semiconductor characteristics. Intrinsic semiconductors are semiconductor materials without both donor impurities (n-type dopants) and acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs within the material itself. It is understandable that after the phosphorus diffusion doping layer is formed by high-temperature doping, the phosphorus in the doping process usually does not completely react into the second intrinsic silicon layer, but will generate a certain amount of residual organic matter during the reaction. In order to prevent the residual organic matter from affecting the phosphorus diffusion doping layer, the generated residual organic matter can be post-oxidized. By introducing a certain flow rate of oxygen into the post-oxidation reaction chamber, the residual organic matter reacts with oxygen to form a second associated layer. Under normal circumstances, the second associated layer is a phosphorosilicate glass layer (PSG).

[0059] S270. Photolithography and wet etching are used to remove the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region, and to expose the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region.

[0060] Optionally, photolithography and wet etching are used to remove the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region, and to expose the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region. This includes: forming a second photoresist layer on the side of the phosphorus diffusion doped layer corresponding to the second region away from the second tunneling oxide layer; and performing wet etching on the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region until the surface of the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed.

[0061] Firstly, it can be understood that the surface of the N-type silicon substrate includes an edge region, a first region, and a second region. Since the second tunneling oxide layer is deposited as a whole layer, it corresponds to the second tunneling oxide layer in both the edge region, the first region, and the second region. Similarly, since the second intrinsic silicon layer is also deposited as a whole layer, it corresponds to the second intrinsic silicon layer in both the edge region, the first region, and the second region. If the second intrinsic silicon layer is subjected to phosphorus diffusion doping treatment as a whole layer, it corresponds to the phosphorus diffusion doping layer in both the edge region, the first region, and the second region. Specifically, this step essentially involves sequentially removing the second associated layer, the phosphorus diffusion doping layer, and the second tunneling oxide layer corresponding to the first region, and sequentially removing the second associated layer, the phosphorus diffusion doping layer, and the second tunneling oxide layer corresponding to the edge region. If no second associated layer is actually formed during the process, then only the phosphorus diffusion doping layer and the second tunneling oxide layer corresponding to the first region and the edge region need to be removed sequentially until the surface of the boron diffusion doping layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed. For example, the back side of the N-type silicon substrate can be patterned using photolithography and wet etching to completely remove the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region, leaving only the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the second region. For example, before performing wet etching, a second photoresist layer can be formed on the side of the phosphorus diffusion doped layer corresponding to the second region away from the second tunneling oxide layer. This second photoresist layer can be understood as a mask layer. For example, this second photoresist layer can cover the second region and expose the first region and the edge region, so as to facilitate subsequent precise wet etching in the first region and the edge region, forming the first region, the edge region, and the second region corresponding to the unetched structure, until the surface of the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed, thus exposing the first region and the edge region, making the positional difference between the first region and the second region more obvious. Furthermore, it should be noted that the second photoresist layer is disposed in the second region, and the liquid photoresist corresponding to the second photoresist layer is separated by the edge region, so it will not spread from the edge of the back side of the N-type silicon substrate to the front side of the N-type silicon substrate, effectively avoiding the occurrence of edge overflow.

[0062] Optionally, after performing wet etching on the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region until the surface of the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed, the method further includes performing wet etching on the second photoresist layer corresponding to the second region until the surface of the phosphorus diffusion doped layer corresponding to the second region is exposed.

[0063] Specifically, after wet etching of the phosphorus diffusion-doped layer and the second tunneling oxide layer corresponding to the first and edge regions to ensure their complete etching, wet etching of the second photoresist layer corresponding to the second region is also required. This process involves removing the photoresist layer covering the phosphorus diffusion-doped layer in the second region. Furthermore, exemplarily, if a second associated layer exists, wet etching of the second region is further required to remove this associated layer until the surface of the phosphorus diffusion-doped layer in the second region is exposed. This complete exposure of the surface of the phosphorus diffusion-doped layer in the second region ensures the contact stability and electrode formation reliability of the fabricated TBC battery.

[0064] S280. A first passivation film is prepared on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and a second passivation film is prepared on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer.

[0065] S290. Screen printing and sintering are performed on one side of the first passivation film layer and the other side of the second passivation film layer to form an electrode structure and obtain a TBC battery.

[0066] Based on the same inventive concept, embodiments of the present invention also provide a TBC battery. This TBC battery is prepared using the preparation method of a TBC battery as provided in any of the embodiments of the present invention. Therefore, this TBC battery possesses the functional modules and beneficial effects corresponding to the preparation method of a TBC battery.

[0067] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0068] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing a TBC battery, characterized in that, include: A middle region and an edge region are defined on one side surface of an N-type silicon substrate; wherein the edge region is arranged around the middle region, and the width of the edge region at any position ranges from 50 to 200 μm; the middle region includes a first region and a second region arranged alternately in an interdigitated pattern. A first tunneling oxide layer and a boron diffusion doped layer are sequentially prepared on the surface of the N-type silicon substrate corresponding to the first region using photolithography and wet etching, and a second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially prepared on the surface of the N-type silicon substrate corresponding to the second region. A first passivation film is formed on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and a second passivation film is formed on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer. The TBC battery is fabricated by screen printing and sintering on one side of the first passivation film layer and the other side of the second passivation film layer to form an electrode structure.

2. The preparation method according to claim 1, characterized in that, An adhesive overflow barrier structure is provided in the edge region.

3. The preparation method according to claim 1, characterized in that, A first tunneling oxide layer and a boron diffusion doped layer are sequentially fabricated on the surface of the N-type silicon substrate corresponding to the first region using photolithography and wet etching. A second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially fabricated on the surface of the N-type silicon substrate corresponding to the second region. The first tunneling oxide layer and the first intrinsic silicon layer are prepared on the surface of the N-type silicon substrate; The side of the first intrinsic silicon layer away from the first tunneling oxide layer is subjected to boron diffusion doping to form the boron diffusion doped layer; The boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region are removed by photolithography and wet etching, and the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed. A second tunneling oxide layer and a second intrinsic silicon layer are formed on the surface of the N-type silicon substrate on the side away from the boron diffusion doping layer; The side of the second intrinsic silicon layer away from the second tunneling oxide layer is subjected to phosphorus diffusion doping to form the phosphorus diffusion doped layer; The phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region are removed by photolithography and wet etching, and the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed.

4. The preparation method according to claim 3, characterized in that, The boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region are removed by photolithography and wet etching, exposing the surface of the N-type silicon substrate corresponding to the second region and the edge region, including: A first photoresist layer is formed on the side of the boron diffusion doped layer corresponding to the first region that is away from the first tunneling oxide layer; The boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region are subjected to wet etching until the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed.

5. The preparation method according to claim 4, characterized in that, After performing wet etching on the boron diffusion doped layer and the first tunneling oxide layer corresponding to the second region and the edge region until the surface of the N-type silicon substrate corresponding to the second region and the edge region is exposed, the process further includes: The first photoresist layer corresponding to the first region is subjected to wet etching until the surface of the boron diffusion doped layer corresponding to the first region is exposed.

6. The preparation method according to claim 3, characterized in that, The phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region are removed by photolithography and wet etching, exposing the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region, including: A second photoresist layer is formed on the side of the phosphorus diffusion doped layer corresponding to the second region that is away from the second tunneling oxide layer; The phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region and the edge region are subjected to wet etching until the surface of the boron diffusion doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed.

7. The preparation method according to claim 6, characterized in that, After performing wet etching on the phosphorus diffusion-doped layer and the second tunneling oxide layer corresponding to the first region and the edge region until the surface of the boron diffusion-doped layer corresponding to the first region and the surface of the N-type silicon substrate corresponding to the edge region are exposed, the process further includes: The second photoresist layer corresponding to the second region is subjected to wet etching until the surface of the phosphorus diffusion doped layer corresponding to the second region is exposed.

8. The preparation method according to claim 1, characterized in that, The first passivation film layer includes a first anti-ultraviolet attenuation film layer and a first anti-reflection layer, and the second passivation film layer includes a second anti-ultraviolet attenuation film layer and a second anti-reflection layer; The process of forming a first passivation film layer on the side of the boron diffusion-doped layer away from the first tunneling oxide layer, and forming a second passivation film layer on the side of the phosphorus diffusion-doped layer away from the second tunneling oxide layer, includes: The first anti-UV degradation film layer is prepared on the side of the boron diffusion doped layer away from the first tunneling oxide layer, and the second anti-UV degradation film layer is prepared on the side of the phosphorus diffusion doped layer away from the second tunneling oxide layer; The first antireflection layer is prepared on the side of the first anti-ultraviolet attenuation film layer away from the boron diffusion doping layer, and the second antireflection layer is prepared on the side of the second anti-ultraviolet attenuation film layer away from the phosphorus diffusion doping layer.

9. The preparation method according to claim 1, characterized in that, Before screen printing and sintering on one side of the first passivation film layer and one side of the second passivation film layer to form the electrode structure, and before obtaining the TBC battery, the process further includes: A third passivation film is prepared on the surface of the N-type silicon substrate away from the first tunneling oxide layer and the second tunneling oxide layer.

10. A TBC battery, characterized in that, The TBC battery was prepared using the method described in any one of claims 1-9.

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