A bc battery and its preparation method and application

Abstract

The application provides a BC battery and a preparation method and application thereof. The preparation method of the BC battery comprises the following steps: acquiring a first positioning mark image of a silicon wafer and a second positioning mark image of a functional layer respectively, calculating a first superposition deviation of the silicon wafer and the functional layer according to the first positioning mark image and the second positioning mark image, wherein the first superposition deviation comprises a first rotation deviation and / or a first positioning precision; adjusting the position of the functional layer according to the first superposition deviation, and superimposing the functional layer and the silicon wafer to obtain the BC battery comprising a BC battery precursor; and the functional layer comprises at least one of an electrode layer, a doped layer and a first passivation layer. The electrode misregistration rate of the BC battery prepared by using the method is low, the production yield is high, and the BC battery has excellent electrical performance.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and in particular to a BC cell, its preparation method, and its application. Background Technology

[0002] In the photovoltaic industry, back-contact (BC) cells, with their lack of front-side metal grid shading, high photoelectric conversion efficiency, and excellent resistance to light-induced degradation, have become the core technology route for high-efficiency solar cells, showing broad application prospects in large-scale photovoltaic power plants, distributed power generation systems, and high-end photovoltaic modules. As the industrialization of high-efficiency cells accelerates, the industry is placing higher demands on the consistency of BC cell production, the stability of electrical performance, and manufacturing maturity. In particular, the production yield of BC cells has become a crucial factor affecting their large-scale promotion and application.

[0003] Current BC (Bright Cell) fabrication processes are mostly designed around ultra-thin silicon wafers. In the stacking process of the silicon wafer with functional layers such as passivation layers, doped layers, and electrode layers, manual tooling or single-axis robotic arms are commonly used. Manual tooling stacking is highly dependent on operator experience, has poor positioning accuracy, and is prone to electrode pattern misalignment. This not only significantly reduces the carrier collection efficiency in BC cells, leading to a low fill factor, but also results in low production efficiency and large batch-to-batch yield fluctuations, making it difficult to meet the demands of large-scale production. Single-axis robotic arm stacking relies solely on simple positioning at the silicon wafer edge, also resulting in a high electrode misalignment rate, directly causing a decrease in BC cell production yield.

[0004] Therefore, there is a need to provide a method for preparing BC cells that can improve the production yield of BC cells, so as to meet the actual needs of the photovoltaic industry for large-scale, high-quality production of BC cells. Summary of the Invention

[0005] The first aspect of the present invention provides a method for preparing a BC battery, which can improve the production yield of BC batteries.

[0006] A second aspect of the present invention provides a BC battery prepared by the above-described preparation method, which has excellent production yield.

[0007] A third aspect of the present invention provides a photovoltaic module comprising the above-described BC cell, which has excellent photoelectric conversion efficiency.

[0008] This invention provides a method for preparing a BC battery, comprising:

[0009] A first positioning mark image of the silicon wafer and a second positioning mark image of the functional layer are acquired respectively. A first overlap deviation between the silicon wafer and the functional layer is calculated based on the first positioning mark image and the second positioning mark image. The first overlap deviation includes a first rotational deviation and / or a first positioning accuracy.

[0010] As described above, the first lamination deviation is used to adjust the position of the functional layer, and the functional layer is laminated with the silicon wafer to obtain the BC cell including the BC cell precursor;

[0011] The functional layer includes at least one of an electrode layer, a doped layer, and a first passivation layer.

[0012] The fabrication method described above, wherein the first overlap deviation includes a first positioning accuracy; the step of calculating the first overlap deviation between the silicon wafer and the functional layer based on the first positioning mark image and the second positioning mark image includes:

[0013] Obtain the first center point of the first positioning mark image, with the first center point as the origin, the first direction as the X-axis, and the second direction as the Y-axis, wherein the first direction and the second direction are perpendicular to each other;

[0014] Obtain the second center point of the second positioning mark image, with the second center point as the origin, the first direction as the X-axis, and the second direction as the Y-axis;

[0015] In the first direction, the distance between the X-axis and the X-axis is the first positioning accuracy, and / or, in the second direction, the distance between the Y-axis and the Y-axis is the first positioning accuracy;

[0016] The angle between the X-axis and the Y-axis is the first rotational deviation, and / or the angle between the Y-axis and the Y-axis is the first rotational deviation.

[0017] The fabrication method described above, wherein the first lamination deviation includes a first positioning accuracy; the step of adjusting the position of the functional layer according to the first lamination deviation and laminating the functional layer with the silicon wafer includes:

[0018] If the first positioning accuracy is ≤0.1mm, then the functional layer is stacked with the silicon wafer;

[0019] If the first positioning accuracy is greater than 0.1 mm, then the position of the functional layer and the silicon wafer is adjusted for the first time. The value of the first adjustment is less than or equal to 0.05 mm. The first adjustment includes automatic adjustment by an algorithm.

[0020] The preparation method described above further includes, after stacking the functional layer with the silicon wafer: acquiring a third positioning mark image of the silicon wafer and a fourth positioning mark image of the functional layer respectively, and calculating a second stacking deviation between the silicon wafer and the functional layer based on the third positioning mark image and the fourth positioning mark image, wherein the second stacking deviation includes a second positioning accuracy.

[0021] The position of the functional layer is adjusted according to the second positioning accuracy, wherein the value of the second adjustment is ≤0.02mm, and the second adjustment includes mechanical adjustment.

[0022] In the preparation method described above, at least one of the first positioning marker image, the second positioning marker image, the third positioning marker image, and the fourth positioning marker image is obtained using a high-precision industrial camera; and / or,

[0023] The process of stacking the functional layer with the silicon wafer includes using a vacuum adsorption robotic arm to stack the functional layer with the silicon wafer.

[0024] The fabrication method described above, wherein after the functional layer is laminated with the silicon wafer, further includes: temporarily fixing it using an anti-displacement clamp; and / or,

[0025] After the functional layer is stacked with the silicon wafer, the method further includes: placing the stacked silicon wafer and the functional layer between two buffer layers; the thickness of the buffer layers is 0.5~1.0 mm, the Shore hardness is 30~40 HA, and the temperature resistance is ≥200℃.

[0026] The preparation method described above further includes sequentially performing lamination, annealing, and passivation treatments on the BC battery precursor to form a second passivation layer on the outer surface of the BC battery precursor.

[0027] In the lamination process, the vacuum degree is ≤30Pa, the temperature is 120~140℃, the pressure is 0.2~0.4MPa, the time is 20~25min, the cooling rate is 2~3℃ / min, and the interlayer stress is ≤5MPa; and / or,

[0028] The annealing treatment is carried out in a nitrogen atmosphere, wherein the nitrogen flow rate is 5-10 L / min, the temperature is 800-850℃, and the time is 30-40 min; and / or,

[0029] In the passivation process, the temperature is 300~380℃ and the power is 100~150W.

[0030] This invention provides a BC battery, which is prepared using the above-described preparation method.

[0031] The BC battery described above, wherein the BC battery comprises, in the stacking direction, a second passivation layer, an electrode layer, a doped layer, a first passivation layer, and a silicon wafer.

[0032] The present invention provides a photovoltaic module, wherein the BC cell described above is included.

[0033] This invention improves the production yield and performance stability of BC cells by achieving precise stacking between silicon wafers and functional layers. It also enhances the carrier collection efficiency and photoelectric conversion efficiency of BC cells, and has the advantages of low cost, strong compatibility, and suitability for industrial production. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of the first passivation layer in some embodiments of the present invention;

[0036] Figure 2 This is a schematic diagram of the structure of the doped layer in some embodiments of the present invention;

[0037] Figure 3 This is a schematic diagram of the BC battery structure in some embodiments of the present invention.

[0038] Figure label:

[0039] 1: First passivation layer;

[0040] 11: Silicon nitride layer;

[0041] 12: Alumina layer;

[0042] 2: Doped layer;

[0043] 21: Boron-doped layer;

[0044] 22: Phosphorus-doped layer;

[0045] 3: Second passivation layer;

[0046] 4: Electrode layer;

[0047] 5: Silicon wafers. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In the absence of conflict, the following embodiments and features can be combined with each other.

[0049] In existing technologies, the fabrication of BC batteries typically involves manual assistance or a single-axis robotic arm to stack silicon wafers and functional layers, resulting in high electrode misalignment rates and low production yields. The inventors discovered that by acquiring positioning mark images of the functional layers and silicon wafers separately, and calculating the stacking deviation between the wafers and functional layers, the positioning accuracy between them can be improved, thereby reducing the electrode misalignment rate and increasing the production yield of BC batteries.

[0050] A first aspect of the present invention provides a method for preparing a BC battery, comprising:

[0051] A first positioning mark image of the silicon wafer and a second positioning mark image of the functional layer are acquired respectively. A first overlap deviation between the silicon wafer and the functional layer is calculated based on the first positioning mark image and the second positioning mark image. The first overlap deviation includes a first rotational deviation and / or a first positioning accuracy.

[0052] The position of the functional layer is adjusted according to the first lamination deviation, and the functional layer is laminated with the silicon wafer to obtain a BC cell including the BC cell precursor.

[0053] The functional layer includes at least one of an electrode layer, a doped layer, and a first passivation layer.

[0054] Specifically, a first positioning mark image of the silicon wafer and a second positioning mark image of the functional layer are acquired respectively. By analyzing and calculating the first positioning mark image, a first overlap deviation between the silicon wafer and the functional layer is obtained, thereby confirming the positional deviation state of the silicon wafer and the functional layer before overlap. The first overlap deviation may include a first positioning accuracy, a first rotational deviation, or both. Based on the calculated first overlap deviation, the position of the functional layer is adaptively adjusted so that the first overlap deviation gradually approaches zero. The functional layer, which includes at least one of an electrode doping layer and a first passivation layer, is then overlapped with the silicon wafer to obtain a BC battery including a BC battery precursor.

[0055] The BC cell fabrication method of this invention enables precise stacking of silicon wafers and functional layers, reduces the electrode misalignment rate of BC cells, improves the production yield of BC cells, ensures the stability of BC cell product performance, and makes the fabrication of BC cells more in line with industrial production requirements. At the same time, it improves the carrier collection rate and minority carrier lifetime of BC cells, thereby improving the photoelectric conversion efficiency of BC cells, enabling BC cells to better meet the market demand for high-efficiency photovoltaic cells. In addition, the BC cell fabrication method of this invention has low cost, is compatible with conventional silicon wafers, has excellent compatibility with existing photovoltaic cell production lines, and does not require large-scale equipment modification.

[0056] In some embodiments, the electrode layer includes silver-silver interdigitated electrodes (the positive electrode is silver, and the negative electrode is silver-aluminum). After obtaining the BC battery precursor, the method further includes: welding the welding ribbon to the silver-silver interdigitated electrodes using a pulsed fiber laser welding machine; specifically, the welding ribbon is attached to the outer surface of the electrode layer of the BC battery precursor, making corresponding contact with the interdigitated silver electrode (positive electrode) and the silver-aluminum electrode (negative electrode), and the welding ribbon and the interdigitated electrodes are fixed by the pulsed fiber laser at the preset welding point position.

[0057] The silver-aluminum interdigitated electrodes themselves have an intermittent grid structure, not a complete planar structure. When the solder ribbon is bonded to the electrode layer, only the solder joints and grid contact areas are tightly bonded, and interlayer gaps are naturally formed at the grid gaps. Furthermore, laser welding is a localized welding process, achieving fusion and fixation between the solder ribbon and the silver-aluminum electrode only at the preset solder joints. There is no adhesion between the solder ribbon and the electrode layer in non-solder joint areas. At the same time, due to the rigidity of the solder ribbon itself and the flatness of the electrode layer surface, slight warping and separation are prone to occur in non-solder joint areas, forming gaps. By using a dispensing machine to fill the gaps between the solder ribbon and the electrode layer with conductive silver paste, the originally discontinuous local connection can be transformed into a large-area continuous conductive path, reducing the contact resistance between the electrode layer and the solder ribbon and the series resistance of the BC cell, thereby improving the carrier transport efficiency.

[0058] In some embodiments, after filling with conductive silver paste, the BC battery precursor is cured at 150°C for 30 minutes to make the resistance of the BC battery precursor ≤0.5mΩ / solder joint.

[0059] Figure 1 This is a schematic diagram of the structure of the first passivation layer in some embodiments of the present invention. For example... Figure 1 As shown, in some embodiments, the first passivation layer 1 includes a silicon nitride layer 11 and an aluminum oxide layer 12 in sequence according to the stacked structure.

[0060] Figure 2 This is a schematic diagram of the structure of the doped layer in some embodiments of the present invention. For example... Figure 2 As shown, in some embodiments, the doped layer 2 includes a boron doped layer 21, a phosphorus doped layer 22, and a boron doped layer 21 in sequence in the horizontal direction.

[0061] In some embodiments, the electrode misalignment rate of the BC battery of the present invention is ≤2%, which is more than 85% lower than that of the conventional process, and the carrier collection efficiency of the BC battery is improved by 3~5%;

[0062] In some embodiments, the production yield of the BC battery of the present invention is ≥98%.

[0063] In some embodiments, the photoelectric conversion efficiency of the BC cell prepared by the present invention is ≥26.5%, which is 0.8~1.2% higher than that of the traditional process, meeting the market demand for high-efficiency photovoltaic cells, and is compatible with interdigitated BC cells (IBC), heterojunction BC cells (HBC), and tunnel oxide passivated contact BC cells (TBC).

[0064] In some embodiments, the cost per watt of the present invention is 8-12% lower than that of conventional BC batteries.

[0065] The present invention does not impose any particular limitation on the silicon wafer, and can be any silicon wafer commonly used in the art. For example, the silicon wafer can be an N-type monocrystalline silicon wafer.

[0066] The present invention does not impose any particular limitation on the solder strip, and it can be any solder strip commonly used in the art. For example, the solder strip can be copper-plated tin solder strip.

[0067] In some embodiments of the present invention, the first overlap deviation includes a first positioning accuracy; calculating the first positioning accuracy of the silicon wafer and the functional layer based on the first positioning mark image and the second positioning mark image includes:

[0068] Obtain the first center point of the first positioning mark image, with the first center point as the origin, the first direction as the X1 axis, and the second direction as the Y1 axis, and the first direction and the second direction are perpendicular to each other;

[0069] Obtain the second center point of the second positioning marker image, with the second center point as the origin, the first direction as the X2 axis, and the second direction as the Y2 axis;

[0070] In the first direction, the distance between the X1 axis and the X2 axis is the first positioning accuracy; in the second direction, the distance between the Y1 axis and the Y2 axis is the first positioning accuracy.

[0071] The angle between the X1 axis and the X2 axis is the first rotational deviation, and the angle between the Y1 axis and the Y2 axis is the first rotational deviation.

[0072] This invention aligns and quantifies the first overlap deviation between the silicon wafer and the functional layer using coordinate system alignment, enabling the first positioning accuracy and first rotational deviation between the silicon wafer and the functional layer to be represented by specific distance and angle values, thus reducing the ambiguity in the deviation judgment between the silicon wafer and the functional layer. Simultaneously, it ensures consistent benchmarks and unified dimensions for deviation calculation, further improving the accuracy of the first deviation calculation results. This provides precise and quantifiable data for subsequent adjustments to the functional layer position based on the first overlap deviation, making the adjustment operation more targeted. Furthermore, the calculation method for the first overlap deviation between the silicon wafer and the functional layer in this invention has clear logic and explicit steps, making it easy to standardize and automate in the industrial production of BC batteries without complex calculations or manual intervention, thereby improving the production yield of BC batteries and meeting the needs of large-scale BC battery production.

[0073] The present invention does not particularly limit the first direction. The first direction can be the extension direction of the silicon wafer or the functional layer, or it can be the width direction perpendicular to the extension direction.

[0074] In some embodiments of the present invention, the first lamination deviation includes a first positioning accuracy; adjusting the position of the functional layer according to the first lamination deviation and laminating the functional layer with the silicon wafer includes:

[0075] If the first positioning accuracy is ≤0.1mm, then the functional layer will be stacked with the silicon wafer;

[0076] If the first positioning accuracy is greater than 0.1 mm, the position of the functional layer and the silicon wafer is adjusted first. The value of the first adjustment is less than or equal to 0.05 mm. The first adjustment includes automatic adjustment by the algorithm.

[0077] Specifically, after calculating the first overlap deviation between the silicon wafer and the functional layer, the value of the first positioning accuracy is first determined. If the determination result is that the first positioning accuracy is ≤0.1mm, it means that the positional deviation between the silicon wafer and the functional layer is within the preset overlap range, and the functional layer and the silicon wafer can be directly overlapped. If the determination result is that the first positioning accuracy is greater than 0.1mm, it means that the positional deviation between the silicon wafer and the functional layer exceeds the preset range, and the relative position between the functional layer and the silicon wafer needs to be adjusted first. The value of the first adjustment is controlled within the range of 0.05mm. This first adjustment is achieved by automatic algorithm adjustment. After the algorithm automatic adjustment that meets the value requirements is completed, the functional layer and the silicon wafer are overlapped.

[0078] This invention, by setting a threshold for the first positioning accuracy and performing the stacking operation according to different situations, can strictly control the relative positional deviation between the silicon wafer and the functional layer, ensuring that the alignment error between the functional layer and the silicon wafer is within an acceptable range. This further guarantees the stacking alignment effect between the silicon wafer and the functional layer, improves the accuracy of the BC cell precursor, and ensures that the relative position of the adjusted silicon wafer and the functional layer is closer to the ideal stacking state. At the same time, the position correction is completed by automatic adjustment using an algorithm, eliminating the subjective error caused by manual adjustment, making the position adjustment process more standardized and stable.

[0079] In some embodiments of the present invention, after the functional layer is stacked with the silicon wafer, the method further includes: acquiring a third positioning mark image of the silicon wafer and a fourth positioning mark image of the functional layer respectively, and calculating a second stacking deviation between the silicon wafer and the functional layer based on the third positioning mark image and the fourth positioning mark image, wherein the second stacking deviation includes a second positioning accuracy.

[0080] The position of the functional layer is adjusted a second time according to the second positioning accuracy. The value of the second adjustment is ≤0.02mm. The second adjustment includes mechanical adjustment.

[0081] After lamination, by acquiring the third positioning mark image of the silicon wafer and the fourth positioning mark image of the functional layer and calculating the second lamination deviation, the lamination effect of the silicon wafer and the functional layer can be detected in real time. This allows for timely detection of positional deviations that occur during the lamination process. The visual positioning error is converted into executable mechanical adjustment parameters, thereby achieving coordinated control of automatic algorithm compensation and mechanical clamping. This further improves the lamination accuracy between the silicon wafer and the functional layer, reduces the electrode misalignment rate of the BC battery, and gives the BC battery a higher yield. At the same time, the mechanical adjustment method is adapted to the needs of industrial automated production and can ensure standardization in the second adjustment process.

[0082] In some embodiments of the present invention, at least one of the first positioning mark image, the second positioning mark image, the third positioning mark image, and the fourth positioning mark image is obtained using a high-precision industrial camera. Using a high-precision industrial camera to acquire positioning mark images can improve the clarity and detail recognition of the positioning mark images. Combined with image processing algorithms to extract feature information of the positioning marks, it provides a high-precision image basis for subsequent calculation of superposition deviation, improves the calculation accuracy of the first positioning accuracy, and thus improves the alignment accuracy of the silicon wafer and functional layer superposition. At the same time, the high-precision industrial camera can realize the rapid acquisition of positioning mark images, improve the fabrication efficiency of BC batteries, and adapt to the large-scale and standardized production needs of BC batteries.

[0083] The process of stacking functional layers with silicon wafers includes using a vacuum adsorption robotic arm to stack the functional layers with silicon wafers. The vacuum adsorption robotic arm uses negative pressure to adsorb the functional layers, preventing deformation of the functional layers during the clamping process and ensuring the structural integrity of the functional layers. At the same time, it can also control the functional layers to remain stable during the stacking process, so that the functional layers and silicon wafers have higher alignment accuracy and ensure the accuracy and stability of the stacking process.

[0084] In some implementations, the resolution of the high-precision industrial camera is ≤1μm;

[0085] In some implementations, when using a vacuum adsorption robotic arm to stack the functional layer onto the silicon wafer, the pressure is ≤0.1MPa and the temperature is room temperature.

[0086] In some embodiments of the present invention, after the functional layer and the silicon wafer are stacked, the method further includes: using an anti-displacement clamp for temporary fixation, which can limit the positional movement of the BC battery precursor structure, ensure the stacking accuracy between the silicon wafer 5 and the functional layer, and prevent problems such as loosening or displacement of the silicon wafer and the functional layer.

[0087] In some embodiments of the present invention, the BC battery precursor is further subjected to lamination, annealing, and passivation processes sequentially to form a second passivation layer on the outer surface of the BC battery precursor. The lamination process enables tight bonding between the silicon wafer and the functional layer in the BC battery precursor, eliminating interlayer gaps, enhancing the bonding strength between the silicon wafer and the functional layer, making the BC battery structure more stable, and further ensuring that there is no positional shift between the silicon wafer and the functional layer after lamination, thus improving the production yield of the BC battery. The annealing process can repair lattice defects generated in the BC battery precursor during stacking and lamination, reducing structural defects inside the silicon wafer, reducing carrier losses during transport, improving carrier transport efficiency, and thus improving the electrical performance of the BC battery. Forming a second passivation layer on the outer surface of the BC battery precursor can passivate defects on the outer surface of the BC battery precursor, extend minority carrier lifetime, increase the open-circuit voltage of the BC battery, and simultaneously form a protective layer to reduce the erosion of the BC battery by the external environment, improving the structural stability and operational life of the BC battery.

[0088] In some embodiments of the present invention, after the functional layer is laminated with the silicon wafer, the method further includes: placing the laminated silicon wafer and the functional layer between two buffer layers; the buffer layers have a thickness of 0.5~1.0 mm, a Shore hardness of 30~40 HA, and a temperature tolerance of ≥200°C, which can effectively buffer the hard contact force during subsequent lamination processing, disperse the stress generated by lamination processing, prevent the silicon wafer from developing microcracks and the functional layer from being damaged, and further improve the production yield of BC cells.

[0089] In some embodiments of the present invention, during the lamination process, when the vacuum degree is ≤30Pa, the temperature is 120~140℃, the pressure is 0.2~0.4MPa, the time is 20~25min, the cooling rate is 2~3℃ / min, and the interlayer stress is ≤5MPa, the probability of microcracks in the silicon wafer can be reduced, thereby reducing the breakage rate of BC cells and improving the production yield of BC cells. At the same time, it can fully remove air bubbles between the silicon wafer and the functional layer, making the silicon wafer and the functional layer tightly bonded, further enhancing the bonding strength between the silicon wafer and the functional layer, and maintaining the precise alignment effect formed by the previous stacking. Furthermore, it can also reduce the accumulation of thermal stress during the lamination process, ensuring the integrity and stability of the BC cell precursor stacked structure. The lamination processing conditions of the present invention can be adapted to the characteristics of N-type silicon wafers of conventional thickness, solving the problem of poor compatibility between traditional high-temperature and high-pressure lamination processes and silicon wafers. It does not require large-scale modification of existing production lines, and takes into account both the structural stability improvement of BC cells and the needs of industrial production.

[0090] In some embodiments of the present invention, the annealing treatment is carried out in a nitrogen atmosphere. During the annealing treatment, the nitrogen flow rate is 5~10L / min, the temperature is 800~850℃, and the time is 30~40min. This can protect the BC cell precursor from oxidation during the high-temperature annealing process, and at the same time, it can fully repair the lattice defects generated in the BC cell precursor during the stacking and lamination process, improve the carrier transport efficiency in the BC cell, and enable more carriers to be collected by the electrodes and converted into electrical energy, thereby improving the photoelectric conversion efficiency in the photovoltaic module.

[0091] During passivation treatment, when the temperature is 300~380℃ and the power is 100~150W, a second passivation layer of suitable thickness can be formed on the outer surface of the front body of the BC battery, which prolongs the minority carrier lifetime in the BC battery and makes the BC battery have better conductivity; furthermore, the passivation treatment temperature is 350℃ and the power is 125W.

[0092] In some implementations, the interlayer stress of the BC battery precursor is ≤5MPa during lamination.

[0093] In some implementations, the buffer layer is made of silicone.

[0094] In some implementations, the second passivation layer comprises silicon nitride.

[0095] In some implementations, after passivation treatment, the interfacial recombination rate of the BC battery can be ≤8cm / s, the minority carrier lifetime can be ≥1500μs, and the open-circuit voltage can be ≥720mV, which is 10~15mV higher than that of the traditional BC battery.

[0096] In some embodiments, the BC battery of the present invention can be prepared by including the following steps:

[0097] N-type monocrystalline silicon wafers were selected, and the standard RCA cleaning process was used to remove organic matter, metallic impurities, and particles from the surface of the N-type monocrystalline silicon wafers. Specifically, the N-type monocrystalline silicon wafers were first cleaned with SC-1 cleaning solution, and then rinsed with pure water three times. Then, the N-type monocrystalline silicon wafers were second cleaned with SC-2 cleaning solution, rinsed with pure water, and then spin-dried to obtain clean monocrystalline silicon wafers.

[0098] A texturing process is performed on a clean monocrystalline silicon wafer using an alkaline solution to form a uniform nano-pyramid texture on the surface of the clean monocrystalline silicon wafer, resulting in a rough monocrystalline silicon wafer.

[0099] A rough single-crystal silicon wafer is placed in an oven for a first drying process to obtain a silicon wafer.

[0100] A first passivation layer 1 comprising aluminum oxide and silicon nitride was prepared using atomic layer deposition (ALD), wherein the aluminum oxide was prepared by deposition of trimethylaluminum and water, and the silicon nitride was prepared by deposition of SiH4 and ammonia.

[0101] Boron and phosphorus co-doped layer 2 was prepared using a low-pressure chemical vapor deposition furnace;

[0102] Silver-silver interdigitated electrodes were prepared using a screen printing machine to obtain an electrode layer.

[0103] Using a laser, markings are made at the four corners of silicon wafer 5, first passivation layer 1, doped layer 2, and electrode layer to obtain positioning marks. The positioning marks are four squares of 50×50μm in size. One vertex of the square coincides with the vertex of silicon wafer, first passivation layer 1, doped layer 2, and electrode layer, and two adjacent sides of the square coincide with two adjacent edges of silicon wafer, first passivation layer 1, doped layer 2, and electrode layer.

[0104] A high-precision industrial camera is used to acquire the first positioning mark image of the silicon wafer and the second positioning mark image of the functional layer. The first positioning accuracy and the first rotational deviation of the silicon wafer and the functional layer are calculated based on the first positioning mark image and the second positioning mark image.

[0105] The position of the functional layer is adjusted according to the first positioning accuracy and the first rotational deviation, and the functional layer is stacked with the silicon wafer using a vacuum adsorption robotic arm so that the first rotational deviation is 0.

[0106] If the first positioning accuracy is ≤0.1mm, then the functional layer will be stacked with the silicon wafer;

[0107] If the first positioning accuracy is >0.1mm, then the position of the functional layer and the silicon wafer is adjusted for the first time, and the value of the first adjustment is ≤0.05mm.

[0108] Then, the third positioning mark image of the silicon wafer and the fourth positioning mark image of the functional layer are obtained respectively. The second positioning accuracy of the silicon wafer and the functional layer is calculated based on the third positioning mark image and the fourth positioning mark image. The position of the functional layer is adjusted according to the second positioning accuracy. The value of the second adjustment is ≤0.02mm, and the BC cell precursor is obtained.

[0109] Use anti-displacement clamps to temporarily secure the BC battery front body;

[0110] A buffer layer made of silicone is placed on the upper and lower surfaces of the BC battery precursor. Then, the BC battery precursor including the buffer layer is placed in a laminator for lamination.

[0111] The BC battery precursor was then cooled to ensure that the interlayer stress of the BC battery precursor was ≤5MPa.

[0112] The BC battery precursor is annealed and then passivated using plasma-enhanced chemical vapor deposition equipment to deposit a second passivation layer on the surface of the BC battery precursor. The second passivation layer is silicon nitride and is located on the surface of the electrode layer.

[0113] A pulsed fiber laser welding machine was used to weld the copper-plated tin solder strip to the electrode layer. Then, a dispensing machine was used to fill the gap between the copper-plated tin solder strip and the electrode layer with conductive silver paste. Next, the BC battery precursor was rinsed twice with deionized water and then spun dry for a second drying process to obtain the BC battery.

[0114] Among them, the thickness of the N-type single crystal silicon wafer is 150~180μm, the resistivity is 1.5~3.0Ω·cm, and the minority carrier lifetime is ≥3000μs;

[0115] The SC-1 cleaning solution includes ammonia, hydrogen peroxide, and water, with a mass ratio of 1:1:5; the SC-2 cleaning solution includes hydrogen chloride, hydrogen peroxide, and water, with a mass ratio of 1:1:6.

[0116] The first cleaning temperature is 70~80℃ and the time is 10 minutes; the second cleaning temperature is 70~80℃ and the time is 10 minutes.

[0117] In the spin-drying process, the rotation speed is 500 rpm and the time is 30 seconds.

[0118] The alkaline solution is formulated with 1-2% sodium hydroxide by mass, 0.5-1% isopropanol by mass, and deionized water.

[0119] In the flocking process, the temperature is 75~85℃ and the time is 15~20min;

[0120] Among them, in the rough single-crystal silicon wafer, the height of the nano pyramid textured surface is 2~3μm, and the surface roughness Ra≤0.3μm;

[0121] In the first drying process, the temperature is 110~130℃ and the time is 30min;

[0122] In the first passivation layer 1, the aluminum oxide layer 12 has a thickness of 10~15nm, and the silicon nitride layer 11 has a thickness of 70~105nm; the total thickness of the first passivation layer 1 is 80~120nm, and the refractive index is 2.0~2.2.

[0123] The deposition temperature of alumina is 300℃, and the deposition temperature of silicon nitride is 400℃.

[0124] The thickness of boron doped layer 21 is 500~600nm, the thickness of phosphorus doped layer 22 is 500~600nm, and the temperature for preparing doped layer 2 is 600℃.

[0125] In the screen printing machine, the screen line width is 20~30μm, the line spacing is 50~80μm, the printing pressure is 0.1~0.3MPa, and the squeegee speed is 50~80mm / s;

[0126] Among them, when preparing silver-silver interdigitated electrodes, the sintering temperature is 750~800℃, the time is 15~20min, and the electrode adhesion is ≥5N / mm;

[0127] The laser has a wavelength of 532nm and a power of 10~15W.

[0128] The positioning mark has a depth of 1~2μm in the boron doped layer 21;

[0129] The thickness of the buffer layer is 0.5~1.0mm, the Shore hardness is 30~40HA, and the temperature resistance is ≥200℃.

[0130] In the lamination process, the vacuum degree is ≤30Pa, the temperature is 120~140℃, and the pressure is 0.2~0.4MPa;

[0131] The thickness of the second passivation layer is 10~15nm;

[0132] The deposition temperature of the second passivation layer is 350℃, and the power is 100~150W.

[0133] The laser welding machine has a wavelength of 1064nm, a power of 60~80W, a pulse width of 50~100ns, and a scanning speed of 50mm / s.

[0134] The thickness of the copper-plated tin solder strip is 0.15~0.2mm, and the solder joint spacing is 100~150μm;

[0135] Among them, the conductivity of conductive silver paste is ≥10. 4 S / m, viscosity of 5000~10000 cP, and filling thickness of 10~20 μm;

[0136] The second drying process was carried out at a temperature of 120°C for 20 minutes.

[0137] A second aspect of the present invention provides a BC battery prepared by the above-described preparation method. The BC battery of the present invention exhibits low electrode misalignment rate, high carrier collection efficiency, and long minority carrier lifetime, possessing excellent electrical performance and meeting the application requirements of high-efficiency photovoltaic modules.

[0138] Figure 3 This is a schematic diagram of the BC battery structure in some embodiments of the present invention. For example... Figure 3 As shown, in some embodiments of the present invention, the BC cell sequentially includes, in the stacking direction: a second passivation layer 3, an electrode layer 4, a doped layer 2, a first passivation layer 1, and a silicon wafer 5. The sequential stacking of the second passivation layer 3, electrode layer 4, doped layer 2, first passivation layer 1, and silicon wafer 5 ensures precise matching between the functional layers and the silicon wafer 5, guaranteeing efficient carrier transport and collection in the BC cell, and significantly improving carrier collection efficiency. Furthermore, the synergistic effect of each layer reduces the series resistance within the BC cell, improves the electrical performance of the BC cell, and consequently enhances the photoelectric conversion efficiency of the photovoltaic module including the BC cell.

[0139] In some embodiments, the series resistance of the BC battery of the present invention is ≤2.2mΩ·cm. 2 It reduces energy consumption by more than 20% compared to traditional BC batteries, has an electrode connection desoldering rate of ≤0.5%, and is resistant to thermal cycling (-40℃~85℃, 1000 cycles) without failure.

[0140] A third aspect of the present invention provides a photovoltaic module including the aforementioned BC cell. Since the BC cell of the present invention has a low electrode misalignment rate and a high production yield, the overall production yield of the photovoltaic module is improved. Furthermore, the BC cell of the present invention has a long minority carrier lifetime and excellent electrical performance, thus enabling the photovoltaic module to have a better photoelectric conversion efficiency.

[0141] The technical solution of the present invention will be further described below with reference to specific embodiments.

[0142] Example 1

[0143] The method for preparing the BC battery in this embodiment includes the following steps:

[0144] (a) Select an N-type monocrystalline silicon wafer with a length of 160 μm, a resistivity of 1.8 Ω·cm, and a minority carrier lifetime of 3000 μs. Clean the N-type monocrystalline silicon wafer with SC-1 cleaning solution at a temperature of 75°C for 10 min. Then rinse it with pure water three times, each time for 5 min. Then clean the N-type monocrystalline silicon wafer with SC-2 cleaning solution at a temperature of 75°C for 10 min. After rinsing with pure water, spin dry at 500 rpm for 30 s to obtain a clean monocrystalline silicon wafer. Among them, SC-1 cleaning solution includes ammonium hydroxide, hydrogen peroxide, and water, with a mass ratio of ammonium hydroxide, hydrogen peroxide, and water of 1:1:5. SC-2 cleaning solution includes hydrogen chloride, hydrogen peroxide, and water, with a mass ratio of hydrogen chloride, hydrogen peroxide, and water of 1:1:6.

[0145] (b) A clean monocrystalline silicon wafer was texturized using an alkaline solution at a temperature of 75°C for 15 minutes to form a uniform nano-pyramid texture on the surface of the clean monocrystalline silicon wafer, resulting in a rough monocrystalline silicon wafer with a pyramid texture height of 1.0 μm and a surface roughness of 0.8 μm; wherein the alkaline solution was formulated with 3% sodium hydroxide by mass, 2% isopropanol by mass, and deionized water;

[0146] (c) The rough single-crystal silicon wafer is placed in an oven for the first drying treatment at a temperature of 105°C for 30 minutes to obtain silicon wafer 5;

[0147] (d) An atomic layer deposition method was used to prepare a first passivation layer 1 comprising aluminum oxide and silicon nitride, wherein the aluminum oxide was prepared by deposition of trimethylaluminum and water at 300°C, and the silicon nitride was prepared by deposition of SiH4 and ammonia at 400°C; in the first passivation layer 1, the aluminum oxide layer 12 has a thickness of 30 nm, and the silicon nitride layer 11 has a thickness of 70 nm; the total thickness of the first passivation layer 1 is 100 nm, and the refractive index is 2.1;

[0148] (e) A boron-phosphorus co-doped layer 2 was prepared at 600 °C using a low-pressure chemical vapor deposition furnace, wherein the thickness of the boron doped layer 21 was 500 nm and the thickness of the phosphorus doped layer 22 was 500 nm.

[0149] (f) Silver-silver interdigitated electrodes were prepared using a screen printing machine to obtain electrode layer 4; wherein, in the screen printing machine, the screen line width was 25μm, the line spacing was 65μm, the printing pressure was 0.2MPa, and the squeegee speed was 40mm / s; when preparing the silver-silver interdigitated electrodes, the sintering temperature was 780℃, the time was 12min, and the electrode adhesion was 1.8N / mm;

[0150] (g) Using a laser with a wavelength of 532nm and a power of 12W, mark the four corners of the silicon wafer 5, the first passivation layer 1, the doped layer 2, and the electrode layer 4 to obtain positioning marks. The positioning marks are four squares with a size of 50×50μm and a depth of 1.5μm. One vertex of the square coincides with the vertex of the silicon wafer 5, the first passivation layer 1, the doped layer 2, and the electrode layer 4, and two adjacent sides of the square coincide with two adjacent edges of the silicon wafer 5, the first passivation layer 1, the doped layer 2, and the electrode layer 4.

[0151] (h) Use a high-precision industrial camera with a resolution of 1μm to acquire the first positioning mark image of silicon wafer 5 and the second positioning mark image of the functional layer respectively, and calculate the first positioning accuracy and the first rotation deviation of silicon wafer 5 and functional layer based on the first positioning mark image and the second positioning mark image;

[0152] The position of the functional layer is adjusted according to the first positioning accuracy and the first rotational deviation, and the functional layer is stacked with the silicon wafer 5 using a vacuum adsorption robotic arm so that the first rotational deviation is 0.

[0153] If the first positioning accuracy is ≤0.1mm, then the functional layer will be laminated with silicon wafer 5;

[0154] If the first positioning accuracy is >0.1mm, then the position of the functional layer and the silicon wafer 5 is adjusted for the first time, and the value of the first adjustment is ≤0.05mm.

[0155] (i) Then, the third positioning mark image of silicon wafer 5 and the fourth positioning mark image of the functional layer are obtained respectively. The second positioning accuracy of silicon wafer 5 and functional layer is calculated based on the third positioning mark image and the fourth positioning mark image. The position of functional layer is adjusted according to the second positioning accuracy. The value of the second adjustment is ≤0.02mm, and the BC cell precursor is obtained.

[0156] (j) Temporarily secure the BC battery front body using an anti-displacement clamp;

[0157] (k) A buffer layer is placed on the upper and lower surfaces of the BC battery precursor. The buffer layer is made of silicone with a thickness of 0.5 mm and a Shore hardness of 35 HA. Then, the BC battery precursor including the buffer layer is placed in a laminator for lamination. During the lamination process, the vacuum degree is 0.08 Pa, the temperature is 140 °C, and the pressure is 0.3 MPa.

[0158] (l) Cool the BC battery precursor to room temperature at a rate of 2℃ / min, so that the interlayer stress of the BC battery precursor is ≤5MPa;

[0159] (m) The BC battery precursor was annealed in a nitrogen atmosphere at a flow rate of 5 L / min, a temperature of 820 °C, and a time of 30 min.

[0160] (n) The BC battery precursor is passivated using a plasma-enhanced chemical vapor deposition (PECVD) device to deposit a second passivation layer 3 on the surface of the BC battery precursor. The deposition temperature is 350°C and the power is 125W. The second passivation layer 3 is silicon nitride with a thickness of 15nm. The second passivation layer 3 is located on the surface of the electrode layer 4.

[0161] (o) A pulsed fiber laser welding machine was used to weld a 0.15mm copper-plated tin solder strip to electrode layer 4 under the conditions of wavelength of 1064nm, power of 70W, pulse width of 35ns, and scanning speed of 50mm / s, with a solder joint spacing of 120μm.

[0162] (p) Conductive silver paste is filled into the gap between the copper-plated tin solder strip and electrode layer 4 using a dispensing machine. The conductivity of the conductive silver paste is 10. 4 The S / m value is 8000 cP, and the filling thickness is 20 μm. After filling, the BC battery precursor is cured at 150 °C for 30 min.

[0163] (q) Rinse the BC battery precursor twice with deionized water and spin dry. Then perform a second drying treatment at 120°C for 20 minutes to obtain the BC battery.

[0164] Comparative Example 1

[0165] The preparation method of the BC battery in this comparative example is basically the same as that in Example 1, except that:

[0166] (g) The silicon wafer 5, the first passivation layer 1, the doped layer 2 and the electrode layer 4 are stacked and bonded by manual assistance with auxiliary tooling. The stacking accuracy is controlled within ±50μm. Then, a single-axis robotic arm is used to complete the final stacking process of the BC cell. The stacking speed is 50mm / s and the stacking pressure is 0.1MPa to obtain the BC cell precursor.

[0167] The (h)-(m) step is omitted; the remaining steps are the same as in Example 1.

[0168] Performance testing

[0169] The following performance tests were performed on the examples and comparative examples respectively:

[0170] (1) Integrity

[0171] The integrity of silicon wafer 5 in the BC cells of the examples and comparative examples was tested using an electroluminescence tester (model: EL-1000).

[0172] Test parameters: Near-infrared light with a wavelength of 850nm, test voltage of 0.8V, test temperature of 25℃, and test area of ​​156.75mm×156.75mm.

[0173] Test procedure: Place the BC battery on the test platform, fix the electrodes, and apply the test voltage; turn on the electroluminescence tester and acquire the light emission image of silicon wafer 5 with a resolution of 1920×1080; observe defects such as microcracks, cracks, and holes in the image, and calculate the defect rate.

[0174] (2) Electrical properties

[0175] The electrical performance of the BC cells in the examples and comparative examples was tested using an IV test system (AM1.5G, 1000W / m²). The electrical performance included open-circuit voltage (Voc), short-circuit current (Isc), fill factor (FF), and conversion efficiency (η).

[0176] Test equipment: Solar cell IV test system (model: IV-300).

[0177] Test conditions: AM1.5G, irradiance of 1000W / m², test temperature of 25℃, spectral matching degree ±5%.

[0178] Test procedure: Fix the BC battery on the test fixture and calibrate the test system; apply a standard test light source, scan the current-voltage curve, and calculate the electrical performance parameters; test each BC battery 5 times and take the average value.

[0179] (3) Low birth rate life expectancy

[0180] The minority carrier lifetime of the BC cells in the examples and comparative examples was detected using a microwave photoconductivity attenuator (model: μ-PCD 3000).

[0181] Test parameters: test wavelength is 904nm, test temperature is 25℃, and test spot diameter is 5mm.

[0182] Test procedure: The carriers in silicon wafer 5 of the BC cell are excited by laser pulse, and the photoconductivity decay signal is detected; the minority carrier lifetime (τ) is calculated. Five points are tested for each group of BC cells, and the average value is taken.

[0183] (4) Production yield of BC batteries

[0184] According to the conversion efficiency measured in (2), BC batteries with a conversion efficiency ≥26.5% are classified as qualified finished products, and BC batteries with a conversion efficiency less than 26.5% are classified as unqualified products.

[0185] Testing process: Batch testing (100 cells each) was conducted on the BC batteries of the example and comparative examples; the number of qualified finished products was counted, and the production yield was calculated;

[0186] Test environment: temperature 25℃, humidity 50%RH, no light interference.

[0187] The results of the above performance tests are shown in Table 1.

[0188] Table 1

[0189]

[0190] As can be seen from Table 1, the integrity, electrical performance, minority carrier lifetime, and production yield of the BC battery of the present invention are all superior to those of the comparative example. The reason is that the present invention obtains the positioning mark images of silicon wafer 5 and functional layer through visual positioning and calculates the stacking deviation, thereby achieving high-precision alignment and stacking of silicon wafer 5 and functional layer, reducing the electrode misalignment rate and silicon wafer defect rate of the BC battery, resulting in a higher production yield of the BC battery. At the same time, it also improves the carrier collection efficiency and transport efficiency of the BC battery, thereby improving the electrical performance of the BC battery.

[0191] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for preparing a BC battery, characterized in that, include: A first positioning mark image of the silicon wafer and a second positioning mark image of the functional layer are acquired respectively. A first overlap deviation between the silicon wafer and the functional layer is calculated based on the first positioning mark image and the second positioning mark image. The first overlap deviation includes a first rotational deviation and / or a first positioning accuracy. The position of the functional layer is adjusted according to the first lamination deviation, and the functional layer is laminated with the silicon wafer to obtain the BC battery including the BC battery precursor; The functional layer includes at least one of an electrode layer, a doped layer, and a first passivation layer.

2. The preparation method according to claim 1, characterized in that, The first overlap deviation includes a first positioning accuracy; the step of calculating the first overlap deviation between the silicon wafer and the functional layer based on the first positioning mark image and the second positioning mark image includes: Obtain the first center point of the first positioning mark image, with the first center point as the origin, the first direction as the X-axis, and the second direction as the Y-axis, wherein the first direction and the second direction are perpendicular to each other; Obtain the second center point of the second positioning mark image, with the second center point as the origin, the first direction as the X-axis, and the second direction as the Y-axis; In the first direction, the distance between the X-axis and the X-axis is the first positioning accuracy, and / or, in the second direction, the distance between the Y-axis and the Y-axis is the first positioning accuracy; The angle between the X-axis and the Y-axis is the first rotational deviation, and / or the angle between the Y-axis and the Y-axis is the first rotational deviation.

3. The preparation method according to claim 1 or 2, characterized in that, The first lamination deviation includes a first positioning accuracy; the step of adjusting the position of the functional layer according to the first lamination deviation and laminating the functional layer with the silicon wafer includes: If the first positioning accuracy is ≤0.1mm, then the functional layer is stacked with the silicon wafer; If the first positioning accuracy is greater than 0.1 mm, then the position of the functional layer and the silicon wafer is adjusted for the first time. The value of the first adjustment is less than or equal to 0.05 mm. The first adjustment includes automatic adjustment by an algorithm.

4. The preparation method according to claim 3, characterized in that, The process of stacking the functional layer with the silicon wafer further includes: acquiring a third positioning mark image of the silicon wafer and a fourth positioning mark image of the functional layer, respectively, and calculating a second stacking deviation between the silicon wafer and the functional layer based on the third positioning mark image and the fourth positioning mark image, wherein the second stacking deviation includes a second positioning accuracy. The position of the functional layer is adjusted according to the second positioning accuracy, wherein the value of the second adjustment is ≤0.02mm, and the second adjustment includes mechanical adjustment.

5. The preparation method according to claim 4, characterized in that, At least one of the first positioning marker image, the second positioning marker image, the third positioning marker image, and the fourth positioning marker image was obtained using a high-precision industrial camera; and / or, The process of stacking the functional layer with the silicon wafer includes using a vacuum adsorption robotic arm to stack the functional layer with the silicon wafer.

6. The preparation method according to any one of claims 1-5, characterized in that, After the functional layer is laminated with the silicon wafer, the method further includes: temporarily fixing it using an anti-displacement clamp; and / or, After the functional layer is stacked with the silicon wafer, the method further includes: placing the stacked silicon wafer and the functional layer between two buffer layers; the thickness of the buffer layers is 0.5~1.0 mm, the Shore hardness is 30~40 HA, and the temperature resistance is ≥200℃.

7. The preparation method according to claim 6, characterized in that, It also includes sequentially performing lamination, annealing and passivation on the BC battery precursor to form a second passivation layer on the outer surface of the BC battery precursor; In the lamination process, the vacuum degree is ≤30Pa, the temperature is 120~140℃, the pressure is 0.2~0.4MPa, the time is 20~25min, the cooling rate is 2~3℃ / min, and the interlayer stress is ≤5MPa; and / or, The annealing treatment is carried out in a nitrogen atmosphere, wherein the nitrogen flow rate is 5-10 L / min, the temperature is 800-850℃, and the time is 30-40 min; and / or, In the passivation process, the temperature is 300~380℃ and the power is 100~150W.

8. A BC battery, characterized in that, It was prepared using the preparation method described in any one of claims 1-7.

9. The BC battery according to claim 8, characterized in that, The BC battery comprises, in the stacking direction, a second passivation layer, an electrode layer, a doped layer, a first passivation layer, and a silicon wafer.

10. A photovoltaic module, characterized in that, Includes the BC battery as described in claim 8 or 9.

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