A method for manufacturing a stacked battery, a stacked battery, a photovoltaic module, and a photovoltaic system

Abstract

The application discloses a laminated battery preparation method, a laminated battery, a photovoltaic module and a photovoltaic system, and belongs to the technical field of batteries. The method comprises the following steps: forming a first rough surface on a first surface of a substrate, and preparing a first transmission structure on the first rough surface; forming a second rough surface on a second surface of the substrate, and sequentially preparing a second transmission structure and a first mask layer on the second rough surface; the second surface and the first surface are oppositely arranged, and the size of pyramids of the second rough surface is smaller than that of the first rough surface; after the first mask layer is formed, a first functional layer is prepared on the surface of the first transmission structure; a first electrode is prepared on the surface of the first functional layer; after the first electrode is formed, the first mask layer is removed, and a first battery is obtained; a second battery is prepared on the second surface of the first battery, and a laminated battery is obtained. The application can improve the problems of belt marks and furnace belt marks caused by the introduction of the rough surface, so that the yield of mass production can be improved.

Description

Technical Field

[0001] This application relates to the field of battery technology, and in particular to a method for preparing a tandem battery, a tandem battery, a photovoltaic module, and a photovoltaic system. Background Technology

[0002] Perovskite and crystalline silicon tandem solar cells are a type of solar cell, typically stacked in series to form a tandem structure with the perovskite cell at the top and the crystalline silicon cell at the bottom. Due to the limited transmittance of the perovskite top cell to long-wavelength light and the optical and parasitic absorption losses in the crystalline silicon bottom cell, the current of the crystalline silicon bottom cell is relatively low, thus affecting the cell efficiency. Currently, the main approach is to improve the current by fabricating a textured surface on the light-receiving surface of the crystalline silicon bottom cell. However, this textured surface easily produces belt marks and furnace marks when it comes into contact with the transmission structure in subsequent processes, leading to a decrease in the yield of the crystalline silicon bottom cell and increasing the difficulty of large-area mass production. Therefore, improving the belt marks and furnace marks caused by the introduction of textured surfaces is of great significance for the technological upgrade of existing crystalline silicon bottom cell production lines. Summary of the Invention

[0003] This application provides a method for preparing tandem solar cells, tandem solar cells, photovoltaic modules, and photovoltaic systems, which can solve the technical problem of belt marks and furnace marks caused by contact between the textured surface and transmission structures such as belts and furnace belts.

[0004] In a first aspect, a method for fabricating a tandem solar cell is provided, comprising:

[0005] A first textured surface is formed on a first surface of a substrate, and a first transport structure is fabricated on the first textured surface;

[0006] A second textured surface is formed on the second surface of the substrate, and a second transport structure and a first mask layer are sequentially fabricated on the second textured surface; the second surface and the first surface are disposed opposite to each other, and the pyramid size of the second textured surface is smaller than the pyramid size of the first textured surface;

[0007] After forming the first mask layer, a first functional layer is prepared on the surface of the first transport structure;

[0008] A first electrode is fabricated on the surface of the first functional layer;

[0009] After forming the first electrode, the first mask layer is removed to obtain the first battery;

[0010] A second battery is prepared on the second surface of the first battery to obtain the stacked battery.

[0011] This application provides a method for fabricating a tandem solar cell. A micro-textured surface is prepared on the first surface, which reduces the optical loss of the bottom first cell, thereby increasing the output current of the first cell and thus improving the conversion efficiency of the tandem solar cell. Simultaneously, before preparing the functional layer and electrodes on the second surface, a mask layer is prepared on the first surface. The mask layer protects the textured surface of the first surface, mitigating belt marks and furnace marks caused by the textured surface. This addresses the pain points in mass production of high-efficiency, large-area first cells, thereby improving mass production yield. Furthermore, the process and procedures for preparing the mask layer on the first surface are compatible with existing first cell production line equipment and processes, thus reducing technology upgrade costs.

[0012] In some embodiments, the preparation of the second transmission structure includes:

[0013] A second tunneling layer is formed on the second textured surface by thermal growth at a preset temperature using an LPCVD device.

[0014] A second intrinsic amorphous silicon is deposited on the surface of the second tunneling layer by thermal decomposition of silane.

[0015] A second impurity diffusion is performed on the surface of the second intrinsic amorphous silicon to form a second doped polysilicon layer, and a second impurity mask layer is formed on the surface of the second doped polysilicon layer; the second tunneling layer and the second doped polysilicon layer constitute the second transport structure.

[0016] In some embodiments, the preparation of the second transport structure includes: sequentially performing the following steps using a PECVD device:

[0017] Ionized N2O forms a second tunneling layer on the second textured surface;

[0018] In-situ doping with ionized PH3 and SiH4 forms a second doped polycrystalline silicon layer on the surface of the second tunneling layer.

[0019] Ionized N₂O and SiH₄ form a second mask layer on the surface of the second doped polycrystalline silicon layer;

[0020] Annealing activation is performed at a preset temperature to obtain the final second doped polysilicon layer; the second tunneling layer and the second doped polysilicon layer constitute the second transport structure.

[0021] In some embodiments, removing the first mask layer includes:

[0022] The first mask layer is removed using an acid solution in a chain-type device.

[0023] In some embodiments, the preparation of the first mask layer includes:

[0024] The first mask layer is formed on the surface of the second transport structure by ionizing SiH4 and N2O using a PECVD device.

[0025] In some embodiments, the first mask layer includes a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0026] In a first aspect, a stacked battery is provided, comprising: a first battery and a second battery stacked together;

[0027] The first battery includes: a substrate having a first surface and a second surface disposed opposite to each other, the first surface having a first textured surface, the second surface having a second textured surface, the pyramid size of the second textured surface being smaller than the pyramid size of the first textured surface; a first transport structure, a first functional layer, and a first electrode are sequentially stacked on the first textured surface in a direction away from the substrate; and a second transport structure is disposed on the second textured surface.

[0028] The second battery is disposed on the surface of the second transmission structure.

[0029] This application provides a tandem solar cell in which the pyramid size of the second textured surface in the crystalline silicon solar cell is smaller, while the pyramid size of the first textured surface is larger, making it compatible with the current crystalline silicon solar cell production line in terms of manufacturing process and reducing the cost of subsequent technology upgrades; the smaller pyramid size of the second textured surface can take into account both optical loss and the matching of the crystalline silicon solar cell and the perovskite solar cell structure, and since it can be prepared by the above-mentioned tandem solar cell manufacturing method, it also has the above-mentioned beneficial effects.

[0030] In some embodiments, the linear average height of the pyramid in the second velvet surface is 400nm-800nm, including the values ​​at both ends; the linear average width of the pyramid in the second velvet surface is 12μm-30μm, including the values ​​at both ends.

[0031] In some embodiments, the linear average height of the pyramid in the first velvet surface is 1.1 μm-1.8 μm, including the values ​​at both ends; the linear average width of the pyramid in the first velvet surface is 1.2 μm-2 μm, including the values ​​at both ends.

[0032] In some embodiments, a second functional layer is provided on the surface of the first transmission structure and the surface of the second transmission structure; the second functional layer includes a passivation layer.

[0033] Thirdly, a photovoltaic module is provided, comprising: the aforementioned tandem cell.

[0034] This application provides a photovoltaic module, including the aforementioned tandem cells.

[0035] Fourthly, a photovoltaic system is provided, comprising: the aforementioned photovoltaic module.

[0036] This application provides a photovoltaic system including the aforementioned photovoltaic modules. Attached Figure Description

[0037] Figure 1 This is a flowchart of the method for preparing a stacked battery provided in this application;

[0038] Figure 2 This is a schematic diagram of the stacked battery provided in this application;

[0039] Figure 3 This is a schematic diagram of the photovoltaic module provided in this application;

[0040] Figure 4 This is an exploded view of the photovoltaic module provided in this application;

[0041] Figure 5 This is a schematic diagram of the photovoltaic system provided in this application. The accompanying drawings are not drawn to scale.

[0042] Figure label:

[0043] 01-Photovoltaic system;

[0044] 1- Photovoltaic modules;

[0045] 11-Rear cover; 12-Rear encapsulation layer; 13-Stacked battery string layer; 14-Front encapsulation layer; 15-Front cover; 16-Gateway box; 17-Frame;

[0046] 130-Stacked battery;

[0047] 1311 - Substrate; 1312 - Heavily doped first impurity diffusion layer; 1313 - Lightly doped first impurity diffusion layer; 1314 - Second tunneling layer; 1315 - Second doped polysilicon layer; 1316 - Passivation layer; 1317 - First antireflection layer; 1318 - First electrode;

[0048] 132 - Connector Layer;

[0049] 1331 - Hole transport layer; 1332 - Perovskite layer; 1333 - Electron transport layer; 1334 - Second antireflection layer; 1335 - Second electrode. Detailed Implementation

[0050] The descriptions of specific structures or functions implemented according to the concept of this application disclosed in this specification are merely illustrative examples for explaining embodiments based on the concept of this application. Those skilled in the art will understand that embodiments based on the concept of this application can have various variations and forms, and are not limited to the embodiments described in this specification, but also include various modifications, equivalents, or substitutions made within the scope of the purpose, concept, and technology of this application.

[0051] In the description of this application, it should be understood that the use of terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicates the relative orientation or positional relationship between different components, and is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0052] Although the terms "first" or "second" may be used to describe various components or components, the components or components should not be limited by the terms. The terms above are used only for the purpose of distinguishing one component or component from another. For example, without departing from the scope of the claims according to the concept of this application, a first battery cell may be referred to as a second battery cell, and similarly, a second battery cell may be referred to as a first battery cell.

[0053] In this application, unless otherwise expressly specified and limited, the terms "connected," "fixed," "set," etc., should be interpreted broadly. For example, when one component is said to "connect" another component, it should be understood that it can be directly or indirectly connected to the other component, meaning that other components may also be present in between. Similarly, the terms "fixed" and "set" should be interpreted broadly in a similar way. Furthermore, the term "connected" can refer to a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. In this application, unless otherwise expressly specified and limited, the description of "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. The first feature being "below", "under", or "below" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0054] The researchers who developed this application discovered that, due to the "weakest link" effect, the output current of a perovskite-silicon tandem solar cell is determined by the lower of the two. Therefore, to maximize the theoretical output current of the tandem solar cell, the theoretically optimal bandgap (1.68 eV) of the perovskite top cell should allow the absorption spectra of both cells to be roughly evenly distributed, thus ensuring that the output currents of the perovskite top cell and the crystalline silicon bottom cell are consistent.

[0055] However, in practical applications, due to the fact that the functional layers in perovskite top cells are not 100% transparent to long-wavelength light, and due to optical losses and parasitic absorption losses in some film layers of crystalline silicon bottom cells, the output current of crystalline silicon bottom cells is lower than that of perovskite top cells. The low current of crystalline silicon bottom cells is a major bottleneck for further improving the efficiency of tandem cells. The existing solution is to create a textured surface on the light-incident surface of the crystalline silicon bottom cell, which can significantly increase the current. However, after forming the textured surface on the light-incident surface, subsequent processes such as fabricating functional layers and electrodes on the backlight surface are required. During these processes, the textured surface comes into contact with conveyor belts, furnace belts, and other transmission structures. Without proper protection, this easily leads to belt marks and furnace belt marks, resulting in a decrease in the yield of crystalline silicon bottom cells and becoming a challenge in the mass production of large-area crystalline silicon bottom cells. Therefore, improving the belt marks and furnace belt marks caused by the introduction of textured surfaces is of great significance for upgrading existing crystalline silicon bottom cell production line technology. Based on this, this application provides a method for fabricating a stacked battery. By preparing a textured surface on the first surface and before preparing the functional layer and electrodes on the second surface, a step of preparing a mask layer on the first surface is added. The textured surface on the first surface is protected by the mask layer, which can solve the technical problem of belt marks and furnace marks caused by the textured surface coming into contact with transmission structures such as belts and furnace belts.

[0056] In the description of this application, the first transport structure refers to a structure capable of transporting a first charge carrier; the second transport structure refers to a structure capable of transporting a second charge carrier; the first charge carrier and the second charge carrier are two different types of charge carriers, wherein when the first charge carrier is an electron, the second charge carrier is a hole; and when the first charge carrier is a hole, the second charge carrier is an electron.

[0057] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. Please refer to... Figure 1 and Figure 2 , Figure 1 This is a flowchart of the method for preparing the tandem solar cell 130 provided in this application; Figure 2 This is a schematic diagram of the stacked battery provided in this application.

[0058] This application provides a method for fabricating a tandem solar cell 130, which may include:

[0059] S101: A first textured surface is formed on the first surface of the substrate, and a first transport structure is prepared on the first textured surface.

[0060] This embodiment does not limit the specific type of substrate 1311, which can be determined according to actual conditions. For example, substrate 1311 may include a single-crystal silicon wafer. This embodiment does not limit the specific type of substrate 1311, which can be determined according to actual conditions. For example, substrate 1311 may include an N-type substrate 1311 or a P-type substrate 1311. This embodiment does not limit the specific structure or performance parameters of substrate 1311. For example, the resistivity of substrate 1311 may be 0.5 Ω·cm-25 Ω·cm, including the values ​​at both ends; and / or, the thickness of substrate 1311 may be 120 μm-200 μm, including the values ​​at both ends.

[0061] It should be noted that in this embodiment, the first surface and the second surface are two sides that are arranged opposite to each other. For example, when the first surface is the back side, the corresponding second surface can be the front side.

[0062] This embodiment does not limit the specific type of the first battery. It can be any battery that can be stacked with other batteries. For example, the first battery may include a TOPcon (Tunnel Oxide Passivated Contact) battery.

[0063] This embodiment does not limit the specific type of the first transmission structure, and can be determined according to the specific type of the first battery. For example, when the first battery includes a TOPcon battery, the first transmission structure may include a first emitter layer, or include a first tunneling layer and a first doped polysilicon layer sequentially disposed along the direction away from the substrate 1311.

[0064] This embodiment does not limit the specific method of fabricating the first transport structure. It can be determined according to the specific type of the first transport structure. For example, when the first transport structure includes a first emitter layer, the first impurity diffusion can be performed on the first textured surface to form a first impurity diffusion layer and a first impurity mask layer; the first impurity diffusion layer serves as the first emitter layer. Specifically, a tubular device can be used to perform the first impurity diffusion on the first surface of the substrate 1311.

[0065] This embodiment does not limit the specific type of the first impurity, and it can be determined according to the specific type of the substrate 1311. For example, when the substrate 1311 includes an N-type substrate 1311, the first impurity can include a P-type impurity, and the P-type impurity includes boron. Accordingly, the first impurity diffusion layer can be a boron diffusion layer; the first impurity mask layer can be a borosilicate glass layer; and the first surface can be referred to as the P-plane.

[0066] This embodiment does not limit the specific structure or performance parameters of the first impurity diffusion layer. For example, the sheet resistance of the first impurity diffusion layer can be 120 ohm / sp-450 ohm / sp, including the values ​​at both ends; and / or, the first impurity doping concentration in the first impurity diffusion layer can be 2E18-5E19, including the values ​​at both ends; and / or, the junction depth of the first impurity diffusion layer can be 0.5 μm-1.5 μm, including the values ​​at both ends.

[0067] In one possible implementation, after performing a first impurity diffusion on the first textured surface to form a first impurity diffusion layer and a first impurity mask layer, the process may further include:

[0068] The electrode contact area of ​​the first textured surface is treated with continuous infrared laser to form a heavily doped first impurity diffusion layer 1312 in the first impurity diffusion layer of the electrode contact area.

[0069] The non-electrode contact area of ​​the first textured surface is subjected to high-temperature oxidation to form a lightly doped first impurity diffusion layer 1313 in the non-electrode contact area; the heavily doped first impurity diffusion layer 1312 and the lightly doped first impurity diffusion layer 1313 constitute the first emitter layer.

[0070] It should be noted that, in this embodiment, by forming a heavily doped first impurity diffusion layer 1312 with a high doping concentration in the first impurity diffusion layer of the electrode contact area, the contact effect with the electrode can be further improved.

[0071] This embodiment does not limit the specific process parameters of laser treatment. For example, the width of laser treatment can be 50μm-200μm, including the values ​​at both ends. This embodiment does not limit the specific process parameters of high-temperature oxidation, which can be determined according to the actual situation. For example, the temperature of high-temperature oxidation can be 1040℃.

[0072] In this embodiment, the first impurity doping concentration of the heavily doped first impurity diffusion layer 1312 is greater than the first impurity doping concentration of the lightly doped first impurity diffusion layer 1313.

[0073] This embodiment does not limit the specific structure or performance parameters of the heavily doped first impurity diffusion layer 1312. For example, the sheet resistance of the heavily doped first impurity diffusion layer 1312 can be 80 ohm / sp-120 ohm / sp, including the values ​​at both ends; and / or, the first impurity doping concentration of the heavily doped first impurity diffusion layer 1312 can be 8E18-5E19, including the values ​​at both ends; and / or, the junction depth of the heavily doped first impurity diffusion layer 1312 can be 1 μm-2 μm, including the values ​​at both ends.

[0074] This embodiment does not limit the specific structure or performance parameters of the lightly doped first impurity diffusion layer 1313. For example, the sheet resistance of the lightly doped first impurity diffusion layer 1313 can be 400 ohm / sp-600 ohm / sp, including the values ​​at both ends; and / or, the first impurity doping concentration of the lightly doped first impurity diffusion layer 1313 can be 1E18-5E18, including the values ​​at both ends; and / or, the junction depth of the lightly doped first impurity diffusion layer 1313 can be 0.4 μm-1.5 μm, including the values ​​at both ends.

[0075] It should be noted that when the first transport structure in this embodiment includes a first tunneling layer and a first doped polysilicon layer sequentially disposed along a direction away from the substrate 1311, the specific fabrication method can refer to the method for fabricating the second transport structure described below, and will not be repeated here.

[0076] S102: A second textured surface is formed on the second surface of the substrate, and a second transport structure and a first mask layer are sequentially prepared on the second textured surface.

[0077] This embodiment does not limit the specific method of forming the second velvet surface, as long as it ensures that a velvet surface can be formed on the second surface. For example, the following methods can be used:

[0078] Step 11: Perform a first texturing process on the second surface of the substrate 1311 to form a first texturing surface.

[0079] In one possible implementation, step 11 can be performed simultaneously with the step of forming a first textured surface on the first surface of the substrate, that is, the first and second surfaces of the substrate 1311 are first textured to form a first textured surface.

[0080] It should be noted that in this embodiment, texturing is performed on both sides of the substrate 1311 before preparing the film layer, which can remove cutting damage and surface dirt from the substrate 1311, thereby improving the quality of the film layer prepared subsequently.

[0081] This embodiment does not limit the specific method of the first texturing process, as long as it ensures that a first texturized surface can be formed. For example, an alkaline solution can be used to perform the first texturing on the first and second surfaces of the substrate 1311 to form the first texturized surface. It should be noted that the first texturized surface formed by the alkaline texturing process in this embodiment is a pyramidal texturized surface.

[0082] This embodiment does not limit the specific structural parameters of the first velvet surface. For example, the linear average height of the pyramids in the first velvet surface can be 1.1μm-1.8μm, including the values ​​at both ends; the linear average width of the pyramids in the first velvet surface can be 1.2μm-2μm, including the values ​​at both ends. It should be noted that the linear average height of the pyramids refers to the arithmetic mean of the vertical heights from the vertices of all pyramids to the base within the same velvet surface; the linear average width of the pyramids refers to the arithmetic mean of the maximum linear dimensions of the projected outlines of the bases of all pyramids within the same velvet surface.

[0083] Step 12: After forming the first transport structure, the second surface of the substrate 1311 is polished.

[0084] It should be noted that during the preparation of the first transport structure on the first surface in this embodiment, the film layer formed (such as the first impurity mask layer and the first impurity diffusion layer) may be deposited around the second surface. By polishing the second surface of the substrate 1311, the film layer deposited around the second surface can be removed, thereby improving the quality of the film layer prepared subsequently.

[0085] This embodiment does not limit the specific polishing method, as long as the coated film layer can be removed. For example, an alkaline solution can be used to polish the second surface of the substrate 1311. Specifically, the alkaline solution can be used to polish the second surface of the substrate 1311 in a chain-type device.

[0086] It should be noted that polishing the second surface of the substrate 1311 in this embodiment is actually thinning the substrate 1311. This embodiment does not limit the specific thickness of the thinning; for example, the thickness of the substrate 1311 thinned can be 2μm-5μm, including the values ​​at both ends.

[0087] It should be noted that polishing the second surface of the substrate 1311 in this embodiment will change the structure of the first textured surface. This embodiment does not limit the specific structural parameters of the polished first textured surface. For example, the linear average width of the pyramids in the polished first textured surface can be 12μm-30μm, including the values ​​at both ends.

[0088] Step 13: Perform a second texturing process on the second surface of the polished substrate 1311 to form a second texturing surface; the pyramid size of the second texturing surface is smaller than the pyramid size of the first texturing surface.

[0089] It should be noted that the first textured surface in this embodiment is a large textured surface, meaning the pyramid size is relatively large. The purpose of the second texturing after polishing is to form a micro-textured surface on the second surface, meaning the pyramid size is smaller. This means the size of the second textured surface is smaller than the size of the first textured surface, including the fact that the linear average height of the pyramid in the second textured surface is smaller than the linear average height of the pyramid in the first textured surface. This embodiment, by forming a micro-textured surface on the second surface of the substrate 1311, can simultaneously reduce optical losses and achieve structural matching between the first and second cells. The pyramid size includes the linear average width and linear average height of the pyramid.

[0090] This embodiment does not limit the specific method of the second texturing process, as long as the linear average height of the pyramids in the second texturing surface is less than the linear average height of the pyramids in the first texturing surface. For example, an alkaline solution can be used to perform the second texturing on the second surface of the polished substrate 1311. Specifically, the second texturing on the second surface of the polished substrate 1311 can be performed using an alkaline solution in a chain-type device.

[0091] This embodiment does not limit the specific structural parameters of the second textured surface. For example, the linear average height of the pyramid in the second textured surface can be 400nm-800nm, including the values ​​at both ends; the linear average width of the pyramid in the second textured surface can be 12μm-30μm, including the values ​​at both ends.

[0092] This embodiment does not limit the specific type of the second transmission structure. It can be determined according to the specific type of the first battery. For example, when the first battery includes a TOPcon battery, the second transmission structure may include a second emitter layer, or a second tunneling layer 1314 and a second doped polysilicon layer 1315 arranged sequentially along the direction away from the substrate 1311.

[0093] This embodiment does not limit the specific method of preparing the second transport structure. It can be determined according to the specific type of the second transport structure. For example, when the second transport structure includes a second tunneling layer 1314 and a second doped polysilicon layer 1315 arranged sequentially along the direction away from the substrate 1311, the following two methods can be used:

[0094] Method (1) includes:

[0095] Step 21: Prepare the second tunneling layer 1314 on the second textured surface.

[0096] This embodiment does not limit the specific type of the second tunneling layer 1314, as long as it ensures that chemical passivation can be formed on the second surface of the substrate 1311. For example, the second tunneling layer 1314 may include a silicon dioxide layer. This embodiment does not limit the specific structural parameters of the second tunneling layer 1314. For example, the thickness of the second tunneling layer 1314 may be 1nm-2nm, including the values ​​at both ends.

[0097] This embodiment does not limit the specific method of preparing the second tunneling layer 1314. It can be determined according to the specific type of the second tunneling layer 1314. For example, when the second tunneling layer 1314 includes a silicon dioxide layer, it can be thermally grown using an LPCVD (Low Pressure Chemical Vapor Deposition) device at a preset temperature to form the second tunneling layer 1314 on the second textured surface. The preset temperature can be 580℃-630℃, including both extreme values.

[0098] Step 22: Prepare a second intrinsic amorphous silicon on the surface of the second tunneling layer 1314.

[0099] This embodiment does not limit the specific structural parameters of the second intrinsic amorphous silicon. For example, the thickness of the second intrinsic amorphous silicon can be 10nm-80nm, including the values ​​at both ends.

[0100] This embodiment does not limit the specific method of preparing the second intrinsic amorphous silicon, as long as it can be formed. For example, silane can be thermally decomposed to deposit the second intrinsic amorphous silicon on the surface of the second tunneling layer 1314.

[0101] Step 23: Perform second impurity diffusion on the surface of the second intrinsic amorphous silicon to form a second doped polysilicon layer 1315, and form a second impurity mask layer on the surface of the second doped polysilicon layer 1315; the second tunneling layer 1314 and the second doped polysilicon layer 1315 constitute the second transport structure.

[0102] This embodiment does not limit the specific type of the second impurity, and it can be determined according to the specific type of the substrate 1311. For example, when the substrate 1311 includes an N-type substrate 1311, the second impurity can include an N-type impurity, which includes phosphorus. Accordingly, a phosphorus diffusion apparatus can be used to diffuse the second impurity onto the surface of the second intrinsic amorphous silicon; the second doped polycrystalline silicon layer 1315 can be a phosphorus-doped polycrystalline silicon layer; the second impurity mask layer can be a phosphorus-silicon glass layer; and the second surface can be referred to as the N-plane.

[0103] This embodiment does not limit the specific performance parameters of the second doped polysilicon layer 1315. For example, the doping concentration of the second impurity in the second doped polysilicon layer 1315 can be 3E20-6E20, including the values ​​at both ends.

[0104] Method (2) includes:

[0105] Step 31: Prepare the second tunneling layer 1314 on the second textured surface.

[0106] In one possible implementation, when the second tunneling layer 1314 includes a silicon dioxide layer, the second tunneling layer 1314 can be formed on the second textured surface by ionizing N2O using a PECVD device.

[0107] Step 32: Prepare a second doped polycrystalline silicon layer 1315 on the surface of the second tunneling layer 1314.

[0108] In one possible implementation, PECVD equipment can be used to ionize PH3 and SiH4 for in-situ doping, forming a second doped polysilicon layer 1315 on the surface of the second tunneling layer 1314.

[0109] Step 33: Prepare a second mask layer on the surface of the second doped polysilicon layer 1315.

[0110] In one possible implementation, the second mask layer may include a silicon oxide layer; the second mask layer may be formed on the surface of the second doped polysilicon layer 1315 by ionizing N2O and SiH4 using a PECVD device.

[0111] Step 34: Annealing activation is performed at a preset temperature to obtain the final second doped polysilicon layer 1315; the second tunneling layer 1314 and the second doped polysilicon layer 1315 constitute the second transport structure.

[0112] The preset temperature can be 850℃-950℃, including both values.

[0113] It should be noted that when the second transmission structure in this embodiment includes a second emitter layer, the specific preparation method can refer to the preparation method of the first transmission structure described above, and will not be repeated here.

[0114] It should be noted that, in the process of fabricating the second transport structure in this embodiment, the film layer formed (such as the second doped polysilicon layer 1315 and the second impurity mask layer, or the second doped polysilicon layer 1315 and the second mask layer) may be deposited around the first surface. In order to improve the quality of the subsequently fabricated film layer, in one possible implementation, the film layer deposited around the first surface can be removed after the second transport structure is formed.

[0115] This embodiment does not limit the specific method of removing the film layer coated around the first surface. It can be determined according to the specific type of film layer. For example, the following methods can be used:

[0116] In the chain equipment, acid solution is used for single-sided cleaning to remove the second impurity mask layer or the second mask layer that is coated around the first surface;

[0117] An alkaline solution is used in a tank etching apparatus to remove the second doped polysilicon layer 1315 deposited around the first surface.

[0118] It should be noted that in this embodiment, the first impurity mask layer on the first surface and the second impurity mask layer or the second mask layer on the second surface are only temporary masks and need to be removed after the film layer deposited around the first surface is removed. In one possible implementation, an acid solution can be used in a tank etching apparatus to remove the first impurity mask layer on the first surface and the second impurity mask layer or the second mask layer on the second surface.

[0119] This embodiment does not limit the specific type of the first mask layer, as long as it can protect the second surface. For example, the first mask layer may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. This embodiment does not limit the specific thickness of the first mask layer. For example, the thickness of the first mask layer can be 5nm-50nm, including both ends.

[0120] This embodiment does not limit the specific method of preparing the first mask layer. It can be determined based on the specific type of the first mask layer. For example, when the first mask layer includes a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, PECVD (Plasma-Enhanced Chemical Vapor Deposition) equipment can be used to ionize SiH4 and N2O to form the first mask layer on the surface of the second transport structure. It should be noted that in this embodiment, the first mask layer is formed by ionizing SiH4 and N2O. During the ionization process, hydrogen passivation is performed on the film layer on the second surface, which can further saturate the dangling bonds in the film layer on the second surface (such as the second doped polycrystalline silicon layer 1315), thereby increasing the open-circuit voltage Voc of the first cell.

[0121] In one possible implementation, this embodiment may further include the following steps after fabricating the second transport structure and before fabricating the first mask layer:

[0122] A second functional layer is prepared on the surface of the first transport structure and the surface of the second transport structure; the second functional layer includes a passivation layer 1316. It should be noted that, in this embodiment, by preparing the passivation layer 1316 on the surface of the first transport structure and the surface of the second transport structure, a passivation effect is provided on the film layers in the first transport structure and the film layers in the second transport structure, which can further saturate the dangling bonds in the film layers in the first transport structure (such as the first emitter layer) and the film layers in the second transport structure (such as the second doped polycrystalline silicon layer 1315), thereby improving the Voc of the first battery.

[0123] This embodiment does not limit the specific type of passivation layer 1316, as long as it can provide passivation. For example, passivation layer 1316 may include an aluminum oxide layer. It should be noted that the aluminum oxide layer can provide hydrogen passivation. This embodiment does not limit the specific structural parameters of passivation layer 1316. For example, the thickness of passivation layer 1316 can be 2nm-6nm, including the values ​​at both ends.

[0124] This embodiment does not limit the specific method of preparing the passivation layer 1316. It can be determined according to the specific type of passivation layer 1316. For example, when the passivation layer 1316 includes an aluminum oxide layer, the second functional layer can be formed on the surface of the first transport structure and the surface of the second transport structure using ALD (Atomic Layer Deposition). In particular, the second functional layer can be formed on the surface of the first transport structure and the surface of the second transport structure using ALD in a tubular device.

[0125] It should be noted that, in order to avoid the passivation layer 1316 affecting the electrical connection between the first and second batteries, the passivation layer 1316 on the second surface of the substrate 1311 can be removed before step S106 in this embodiment. This embodiment does not limit the specific method of removing the passivation layer 1316, as long as it can be removed. For example, the passivation layer 1316 on the second surface of the substrate 1311 can be removed using an acid solution in a chain-type device.

[0126] This embodiment does not limit the specific type of acid solution, but can be determined according to the specific type of passivation layer 1316. For example, when the first mask layer includes aluminum oxide, the acid solution may include HF.

[0127] In one possible implementation, the steps of removing the passivation layer 1316 from the second surface of the substrate 1311 and removing the first mask layer can be performed simultaneously.

[0128] S103: After forming the first mask layer, a first functional layer is prepared on the surface of the first transport structure.

[0129] This embodiment does not limit the specific type of the first functional layer, and it can be determined according to the specific type of the first battery. For example, when the first battery includes a TOPcon battery, the first functional layer may include a first antireflection layer 1317. It should be noted that in this embodiment, light reflection can be reduced by preparing the first antireflection layer 1317 on the first surface of the substrate 1311.

[0130] This embodiment does not limit the specific type of the first antireflection layer 1317, as long as it can reduce light reflection. For example, the first antireflection layer 1317 may include a silicon nitride layer. This embodiment does not limit the specific structural parameters of the first antireflection layer 1317. For example, the thickness of the first antireflection layer 1317 may be 50nm-100nm, including the values ​​at both ends.

[0131] This embodiment does not limit the specific method of preparing the first antireflection layer 1317. It can be determined according to the specific type of the first antireflection layer 1317. For example, when the first antireflection layer 1317 includes a silicon nitride layer, the first antireflection layer 1317 can be formed on the surface of the first transmission structure using a PECVD device.

[0132] It should be noted that, in this embodiment, before the first functional layer is prepared on the first surface of the substrate 1311, the first battery semi-finished product that has completed the front-end process is usually transported to the equipment for preparing the first functional layer via a belt. During the transport process, the second surface will face the belt. In this embodiment, by preparing the first mask layer on the second surface in advance, the texture of the second surface is protected, which can avoid the generation of belt marks.

[0133] S104: Prepare the first electrode on the surface of the first functional layer.

[0134] This embodiment does not limit the specific type of the first electrode 1318, as long as it can conduct electricity. For example, the first electrode 1318 may include silver grid lines. This embodiment does not limit the structural parameters of the first electrode 1318. For example, the height of the first electrode 1318 may be 5μm-12μm, including the values ​​at both ends; and / or, the width of the first electrode 1318 may be 10μm-30μm, including the values ​​at both ends.

[0135] This embodiment does not limit the specific method of preparing the first electrode 1318. It can be determined according to the specific type of the first electrode 1318. For example, when the first electrode 1318 includes silver grid lines, silver grid lines can be printed on the surface of the first functional layer by screen printing and then sintered to obtain the first electrode 1318.

[0136] It should be noted that, in this embodiment, before the first electrode 1318 is prepared on the surface of the first functional layer, the first battery semi-finished product that has completed the previous process is usually transferred to the equipment for preparing the first electrode 1318 via a furnace belt. During the transfer, the second surface will face the furnace belt. In this embodiment, by preparing a first mask layer on the second surface in advance, the textured surface of the second surface is protected, which can avoid the generation of furnace belt marks.

[0137] S105: After forming the first electrode, remove the first mask layer to obtain the first cell.

[0138] This embodiment does not limit the specific method of removing the first mask layer, as long as the first mask layer can be removed. For example, the first mask layer can be removed by using an acid solution in a chain device.

[0139] This embodiment does not limit the specific type of acid solution, but can be determined according to the specific type of the first mask layer. For example, when the first mask layer includes a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, the acid solution may include HF.

[0140] S106: Prepare a second cell on the second surface of the first cell to obtain a stacked cell.

[0141] This embodiment does not limit the specific type of the second battery; it can be any battery that can be stacked with other batteries. For example, the second battery can include a perovskite battery. The perovskite battery can include a hole transport layer 1331, a perovskite layer 1332, an electron transport layer 1333, and a second antireflective layer 1334 sequentially disposed along a direction away from the substrate 1311, and a second electrode 1335 connecting the second antireflective layer 1334 and the electron transport layer 1333; the second electrode 1335 can include silver grid lines.

[0142] This embodiment does not limit the specific method of preparing the second battery, and can be determined according to the specific type of the second battery. For example, the following methods can be used:

[0143] Step 41: Prepare a bonding layer 132 on the second surface of the first battery.

[0144] It should be noted that in this embodiment, the second battery can be electrically connected to the first battery through the connecting layer 132. This embodiment does not limit the specific type of the connecting layer 132, as long as it is conductive. For example, the connecting layer 132 may include a TCO (Transparent Conductive Oxide) layer. This embodiment does not limit the specific structural parameters of the connecting layer 132; for example, the thickness of the connecting layer 132 can be 5nm-50nm, including the values ​​at both ends.

[0145] This embodiment does not limit the specific method of preparing the connection layer 132. It can be determined according to the specific type of the connection layer 132. For example, when the connection layer 132 includes a TCO layer, the connection layer 132 can be formed on the second surface of the first battery by PVD (Physical Vapor Deposition) or RPD (Reactive Plasma Deposition).

[0146] Step 42: On the surface of the connecting layer 132, a hole transport layer 1331, a perovskite layer 1332, an electron transport layer 1333, and a second antireflection layer 1334 are sequentially prepared in a direction away from the substrate 1311 to form a second battery.

[0147] The perovskite layer 1332 can be prepared using either a solution method or a vapor deposition method.

[0148] Based on the above embodiments, this application prepares a micro-textured surface on the first surface, which can reduce the optical loss of the bottom first cell, thereby increasing the output current of the first cell and thus improving the conversion efficiency of the stacked cell 130. At the same time, before preparing the functional layer and electrodes on the second surface, a step of preparing a mask layer on the first surface is added. By protecting the textured surface of the first surface with the mask layer, the problems of belt marks and furnace marks caused by the introduction of textured surface can be improved, thereby solving the pain point of mass production of high-efficiency large-area first cells and thus improving the mass production yield. In addition, the process and procedures for preparing the mask layer on the first surface are compatible with existing first cell production line equipment and procedures, thereby reducing the cost of technology upgrades.

[0149] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of the stacked battery provided in this application.

[0150] This application provides a stacked battery 130, comprising: a first battery and a second battery stacked together;

[0151] The first battery includes: a substrate 1311, the substrate 1311 having a first surface and a second surface disposed opposite to each other, the first surface having a first textured surface, the second surface having a second textured surface, the pyramid size of the second textured surface being smaller than the pyramid size of the first textured surface; the first textured surface having a first transport structure, a first functional layer and a first electrode 1318 sequentially stacked along a direction away from the substrate; the second textured surface having a second transport structure.

[0152] The second battery is disposed on the surface of the second transmission structure.

[0153] The specific types, structures, and parameters of the substrate 1311, the first transmission structure, and the second transmission structure in this embodiment can be found in the embodiments described above.

[0154] In one possible implementation, the linear average height of the pyramid in the second textured surface can be 400nm-800nm, including the values ​​at both ends; the linear average width of the pyramid in the second textured surface can be 12μm-30μm, including the values ​​at both ends.

[0155] In one possible implementation, the linear average height of the pyramid in the first velvet surface can be 1.1 μm-1.8 μm, including the values ​​at both ends; the linear average width of the pyramid in the first velvet surface can be 1.2 μm-2 μm, including the values ​​at both ends.

[0156] In one possible implementation, the first transmission structure may include a first emitter layer; the first emitter layer includes a heavily doped first impurity diffusion layer 1312 corresponding to the electrode contact region and a lightly doped first impurity diffusion layer 1313 corresponding to the non-electrode contact region.

[0157] In one possible implementation, the second transport structure may include a second tunneling layer 1314 and a second doped polysilicon layer 1315 disposed sequentially along a direction away from the substrate 1311.

[0158] In one possible implementation, the surface of the first transmission structure may be provided with a first functional layer; the first functional layer may include a first antireflection layer 1317.

[0159] In one possible implementation, the surfaces of the first transmission structure and the second transmission structure may be provided with a second functional layer; the second functional layer may include a passivation layer 1316.

[0160] In one possible implementation, a connecting layer 132 may be provided on the second surface of the first battery; the second battery may be electrically connected to the first battery through the connecting layer 132.

[0161] In one possible implementation, the second battery may include a hole transport layer 1331, a perovskite layer 1332, an electron transport layer 1333, and a second antireflection layer 1334 disposed sequentially along a direction away from the substrate 1311, and a second electrode 1335 connecting the second antireflection layer 1334 and the electron transport layer 1333.

[0162] Based on the above embodiments, the pyramid size of the second textured surface in the crystalline silicon cell of this application is smaller, while the pyramid size of the first textured surface is larger, making it compatible with the current crystalline silicon cell production line in terms of manufacturing process and reducing the cost of subsequent technology upgrades; the smaller pyramid size of the second textured surface can take into account both optical loss and the matching of the crystalline silicon cell and the perovskite cell structure; at the same time, since it can be prepared by the above-mentioned stacked cell manufacturing method, it also has the above-mentioned beneficial effects.

[0163] Please refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the photovoltaic module provided in this application; Figure 4 This is an exploded view of the photovoltaic module provided in this application. An embodiment of this application also provides a photovoltaic module 1, including: the aforementioned tandem solar cells.

[0164] In one possible implementation, the photovoltaic module 1 may include a stacked cell string layer 13, which includes at least two stacked cells connected in series.

[0165] In one possible implementation, the photovoltaic module 1 may include: a back cover plate 11, a back encapsulation layer 12, a stacked cell string layer 13, a front encapsulation layer 14, and a front cover plate 15 arranged in sequence.

[0166] In one possible implementation, a junction box 16 may be provided on the surface of the back cover 11 opposite to the back encapsulation layer 12.

[0167] In one possible implementation, the photovoltaic module 1 may be surrounded by a frame 17.

[0168] Based on the above embodiments, this application includes the above-described stacked battery, which also has the above-described beneficial effects.

[0169] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the photovoltaic system 01 provided in this application. This application also provides a photovoltaic system 01, including the aforementioned photovoltaic module 1.

[0170] Based on the above embodiments, this application includes the aforementioned photovoltaic module, which also has the aforementioned beneficial effects.

[0171] This application provides a photovoltaic system that can be used in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and water-based power plants, as well as in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings.

[0172] It is understandable that the application scenarios of photovoltaic (PV) systems are not limited to this; that is to say, PV systems can be applied in all fields that require solar energy for power generation. Taking a PV power generation system as an example, a PV system can include a PV array, a combiner box, and an inverter. The PV array can be an array combination of multiple PV modules; for example, multiple PV modules can form multiple PV arrays. The PV array is connected to the combiner box, which can collect the current generated by the PV array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to realize solar power supply.

[0173] A photovoltaic module is a device that directly converts light energy into electrical energy through the photoelectric effect or photochemical effect.

[0174] The front cover 15 may be made of a material with excellent light transmittance, impact resistance, corrosion resistance, and weather resistance, and may optionally include at least one of the following materials: tempered glass, plexiglass, transparent ceramics, organic fibers, or polymers. In some embodiments, the front cover 15 may include at least one of an insulating barrier layer, a fluorinated weather-resistant layer, and a transition adhesive layer.

[0175] The back cover 11 typically needs to possess insulation, water resistance, aging resistance, weather resistance, and corrosion resistance, and may optionally include at least one of the following composite back covers with tempered glass, plexiglass, metal back cover, or PET film as the substrate. The PET-based composite back cover may, depending on the needs of different scenarios, include various types such as composite (e.g., TPT / KPK, TPE / KPE), coated (e.g., TPC, KPC, CPC), and co-extruded (e.g., PO).

[0176] It is understandable that the material selection of the front cover plate 15 and the back cover plate 11 does not affect each other, and the same or different materials can be selected according to different application scenarios of the components (such as residential photovoltaics and building-integrated photovoltaics).

[0177] The first and second encapsulating films can be selected from at least one of ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, EVA-POE-EVA co-extruded film (EPE), PVB (polyvinyl butyral), polyethylene terephthalate (PET) film, or liquid silicone. In some embodiments, the first and second encapsulating films may further include one or more functional additives selected from the group consisting of crosslinking agents, coupling agents, antioxidants, and ultraviolet absorbers to improve the degree of crosslinking, weather resistance, adhesive strength, and anti-aging properties of the films. It is understood that the first and second encapsulating films can be made of the same or different materials.

[0178] The stacked battery string layer 13 includes multiple battery strings, which can be combined in series, parallel, or series-parallel configurations to achieve current collection and output. Further, each battery string is formed by sequentially connecting multiple battery cells via connectors. In some embodiments, at least a portion of the connector is electrically connected to the back electrode of one battery cell, and at least another portion of the connector is electrically connected to the front or back electrode of another battery cell to form a battery string. The connector may optionally include conductive elements such as solder strips, busbars, or metal clips. In some embodiments, to improve welding performance, oxidation resistance, and weather resistance, the connector material may preferably be a highly conductive metal material, such as at least one of silver, copper, tin, and nickel, or an alloy thereof. In some embodiments, to balance conductivity and cost control, the connector material may also be at least one of metal-clad composite materials such as silver-coated copper, copper-coated silver, copper-coated aluminum, aluminum-coated copper, tin-plated copper, or nickel-plated copper. The electrical connection may be selected from one of the following methods: laser welding, spot welding, bonding, ultrasonic welding, resistance welding, or brazing.

[0179] The solar cell may include a substrate of a crystalline silicon cell, a first emitter of a first conductivity type, and a second emitter of a second conductivity type. It is understood that one of the first and second conductivity types is P-type, and the other is N-type. The substrate of the crystalline silicon cell may include an N-type silicon substrate or a P-type silicon substrate. N-type silicon substrates are typically formed by doping with Group V elements such as phosphorus, arsenic, or antimony, and have the characteristic that the majority charge carriers are electrons; P-type silicon substrates are typically formed by doping with Group III elements such as boron, gallium, or aluminum, and have the characteristic that the majority charge carriers are holes.

[0180] The solar cell can employ a grid line design with no main grid (OBB), multiple main grid (MBB), or super-multiple main grid (SMBB). In some embodiments, the grid line material can be selected as at least one of silver-based conductive paste or silver-coated copper composite paste. The paste uses highly conductive metal powder as the conductive substrate, and the substrate can be at least one of silver powder, copper powder, or silver-coated copper composite powder. To improve the ohmic contact performance, conductivity, and long-term weather resistance of the electrodes, a composite functional layer can be formed on the surface of the substrate or in the grid line structure. The functional layer material includes at least one of glass powder, organic carrier, nickel-based barrier layer, tin-based alloy layer, or anti-oxidation and corrosion-resistant coating.

[0181] Understandably, the solar cells are perovskite / tandem solar cells.

[0182] The frame surrounds the periphery of the stacked structure and is mostly made of aluminum alloy or steel alloy. In some embodiments, the frame may also be a fiberglass frame or a plastic frame. The inner side of the frame usually has grooves for filling with sealant to achieve a sealed bond with the stacked components formed by the front cover plate 15, the first encapsulation film, the stacked battery string layer 13, the second encapsulation film, and the back cover plate 11, thereby blocking moisture and buffering external impacts. In some embodiments, the frame can be connected and assembled using corner brackets.

[0183] Junction box 16 is located on one side of the back cover 11 and is electrically connected to the terminals of the bus electrodes in the stacked battery string layer 13 via a lead-out busbar for energy extraction. The junction box typically includes a housing and cover made of weather-resistant insulating material, conductive connecting pieces disposed within the housing, and one or more bypass diodes. The bypass diodes are connected in parallel with sub-units of the battery string. The electrical lead-out portion of the junction box 16 includes photovoltaic-specific connectors and cables. The cables preferably use cross-linked polyethylene insulating sheaths and tinned copper core wires. In some embodiments, the interior of the junction box may also be filled and encapsulated with potting compound to achieve insulation, thermal conductivity, moisture protection, and fixation.

[0184] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific implementation methods of this application will be described in detail below with reference to specific embodiments and comparative examples.

[0185] Example 1:

[0186] 1. Select an N-type single-crystal silicon wafer with a resistivity of 1 Ω·cm and a thickness of 130 μm;

[0187] An alkaline texturing process was used to perform the first texturing on the front and back sides of the N-type monocrystalline silicon wafer to remove cutting damage and surface contaminants. The resulting large texturing surface has a linear average pyramid height of 1.5 μm and a linear average pyramid width of 1.8 μm.

[0188] 2. Boron diffusion is performed on the texturized N-type single crystal silicon wafer to form a boron diffusion layer (hereinafter referred to as P+ layer) and a borosilicate glass (BSG) mask. At this time, the sheet resistance of the P+ layer is 150 ohm / sp, the boron doping concentration is 5E19, and the junction depth is 1.5μm.

[0189] 3. The front side of the N-type monocrystalline silicon wafer is subjected to alkaline polishing to remove the BSG mask and P+ layer. After polishing, the linear average width of the pyramid is 15μm, and the thickness of the N-type monocrystalline silicon wafer is reduced to 2μm.

[0190] Subsequently, alkali texturing was performed to prepare microtextured surfaces, and the linear average height of the pyramids in the microtextured surfaces was controlled at 450 nm.

[0191] 4. A 1.8 nm thick silicon dioxide layer was formed on the microtextured surface by thermal growth at 600℃ using an LPCVD device as a tunneling layer.

[0192] Subsequently, silane was used for thermal decomposition to deposit a 50 nm thick intrinsic amorphous silicon layer on the surface of the tunneling layer;

[0193] Phosphorus diffusion was then performed using a phosphorus diffusion apparatus to form a phosphorus-doped polycrystalline silicon layer (hereinafter referred to as N-poly) and a phosphorus-silicon glass (PSG) mask, forming the transport structure on the front side; wherein, the phosphorus doping concentration of N-poly is 3.5E20.

[0194] 5. Use HF for single-sided cleaning in the chain equipment to remove the PSG mask on the back side;

[0195] Subsequently, an alkaline solution was used in a tank etching process to remove the N-poly coated on the back side.

[0196] At the same time, acid solution is used for etching in the tank equipment to remove the BSG mask on the back and the PSG mask on the front.

[0197] 6. In tubular equipment, an aluminum oxide layer with a thickness of 3 nm is simultaneously prepared on the back and front sides as a passivation layer using the ALD method.

[0198] 7. A 10 nm silicon oxide layer was prepared on the N-side using PECVD equipment by ionizing SiH4 and N2O as a mask;

[0199] 8. An 80nm thick silicon nitride layer was prepared on the back side using a PECVD device as the first antireflection layer;

[0200] 9. Silver grid lines are prepared on the back side using screen printing. The height of the silver grid lines is 10 μm and the width is 20 μm.

[0201] 10. In chain equipment, HF is used to remove the front alumina and silicon oxide layer mask;

[0202] 11. A 30nm thick TCO layer is prepared on the front side as a bonding layer using PVD or RPD methods;

[0203] 12. Hole transport layer, perovskite layer, electron transport layer, antireflection layer and silver grid line are sequentially prepared on the surface of TCO layer to form a stacked cell.

[0204] Example 2:

[0205] The difference between this embodiment and embodiment 1 is that in this embodiment, step 7 involves preparing a 30nm silicon oxide layer on the N-side as a mask, while the remaining steps are the same as in embodiment 1.

[0206] Example 3:

[0207] The difference between this embodiment and embodiment 1 is that in this embodiment, step 7 involves preparing a 30nm silicon nitride layer as a mask on the N-side, while the remaining steps are the same as in embodiment 1.

[0208] Comparative Example 1:

[0209] The difference between this comparative example and Example 1 is that steps 7 and 10 are omitted in this comparative example, while the remaining steps are the same as in Example 1.

[0210] Comparative Example 2:

[0211] The difference between this comparative example and Comparative Example 1 is that the linear average height of the pyramid in the microtextured surface in step 3 of this comparative example is controlled at 600 nm, while the other steps are the same as those in Comparative Example 1.

[0212] Comparative Example 3:

[0213] The difference between this comparative example and Comparative Example 1 is that step 3 in this comparative example omits the step of preparing micro-textured surface by alkali texturing, while the remaining steps are the same as those in Comparative Example 1.

[0214] The battery performance data for the examples and comparative examples were obtained using the following methods:

[0215] The prepared tandem solar cells were subjected to EL (Electroluminescence) testing using a Weixin VS-6831S Double-type testing instrument to obtain EL imaging images. At the same time, the appearance was judged by a camera AOI (Automated Optical Inspection) system. The EL imaging results and AOI appearance inspection results were compared together to comprehensively determine whether the tandem solar cells were normal, thereby obtaining the yield of the tandem solar cells.

[0216] The test results of the obtained embodiments and comparative examples are shown in Table 1.

[0217] Table 1 Test Results

[0218]

[0219] As shown in Table 1, in order to improve battery efficiency, Comparative Examples 1 and 2 introduced microtextured surfaces on the N-side. However, the introduction of microtextured surfaces also introduces belt marks and furnace marks, so the yield of the stacked batteries in Comparative Examples 1 and 2 is significantly reduced compared to Comparative Example 3. The embodiments provided in this application, by introducing a step of preparing a mask on the N-side before the step of preparing the first antireflection layer, can effectively improve the belt marks and furnace marks caused by the introduction of microtextured surfaces, thereby significantly improving the yield while ensuring high battery efficiency.

Claims

1. A method for preparing a tandem battery, characterized in that, include: A first textured surface is formed on a first surface of a substrate, and a first transport structure is fabricated on the first textured surface; A second textured surface is formed on the second surface of the substrate, and a second transport structure and a first mask layer are sequentially fabricated on the second textured surface; the second surface and the first surface are disposed opposite to each other, and the pyramid size of the second textured surface is smaller than the pyramid size of the first textured surface; After forming the first mask layer, a first functional layer is prepared on the surface of the first transport structure; A first electrode is fabricated on the surface of the first functional layer; After forming the first electrode, the first mask layer is removed to obtain the first battery; A second battery is prepared on the second surface of the first battery to obtain the stacked battery.

2. The method for preparing a stacked battery according to claim 1, characterized in that, The preparation of the second transmission structure includes: A second tunneling layer is formed on the second textured surface by thermal growth at a preset temperature using an LPCVD device. A second intrinsic amorphous silicon is deposited on the surface of the second tunneling layer by thermal decomposition of silane. A second impurity diffusion is performed on the surface of the second intrinsic amorphous silicon to form a second doped polysilicon layer, and a second impurity mask layer is formed on the surface of the second doped polysilicon layer; the second tunneling layer and the second doped polysilicon layer constitute the second transport structure.

3. The method for preparing a stacked battery according to claim 1, characterized in that, The preparation of the second transport structure includes: performing the following sequentially using a PECVD device: Ionized N2O forms a second tunneling layer on the second textured surface; In-situ doping with ionized PH3 and SiH4 forms a second doped polycrystalline silicon layer on the surface of the second tunneling layer. Ionized N₂O and SiH₄ form a second mask layer on the surface of the second doped polycrystalline silicon layer; Annealing activation is performed at a preset temperature to obtain the final second doped polysilicon layer; the second tunneling layer and the second doped polysilicon layer constitute the second transport structure.

4. The method for preparing a stacked battery according to claim 1, characterized in that, The removal of the first mask layer includes: The first mask layer is removed using an acid solution in a chain-type device.

5. The method for preparing a tandem battery according to any one of claims 1 to 4, characterized in that, The preparation of the first mask layer includes: The first mask layer is formed on the surface of the second transport structure by ionizing SiH4 and N2O using a PECVD device.

6. The method for preparing a stacked battery according to claim 5, characterized in that, The first mask layer includes a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

7. A stacked battery, characterized in that, include: A first and second battery stacked together; The first battery includes: a substrate having a first surface and a second surface disposed opposite to each other, the first surface having a first textured surface, the second surface having a second textured surface, and the pyramid size of the second textured surface being smaller than the pyramid size of the first textured surface; The first textured surface is provided with a first transmission structure, a first functional layer and a first electrode stacked sequentially along the direction away from the substrate; the second textured surface is provided with a second transmission structure; The second battery is disposed on the surface of the second transmission structure.

8. The stacked battery according to claim 7, characterized in that, The linear average height of the pyramid in the second velvet surface is 400nm-800nm, including the values ​​at both ends; the linear average width of the pyramid in the second velvet surface is 12μm-30μm, including the values ​​at both ends.

9. The stacked battery according to claim 7, characterized in that, The linear average height of the pyramid in the first velvet surface is 1.1μm-1.8μm, including the values ​​at both ends; the linear average width of the pyramid in the first velvet surface is 1.2μm-2μm, including the values ​​at both ends.

10. The stacked battery according to claim 7, characterized in that, A second functional layer is provided on the surface of the first transmission structure and the surface of the second transmission structure; the second functional layer includes a passivation layer.

11. A photovoltaic module, characterized in that, include: The stacked battery according to any one of claims 7-10.

12. A photovoltaic system, characterized in that, include: The photovoltaic module according to claim 11.

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