A BC battery with a laminated passivation structure, a preparation method thereof and a photovoltaic module

Abstract

The application provides a BC battery with a laminated passivation structure, a preparation method thereof and a photovoltaic module, and relates to the field of solar cell manufacturing. The BC battery comprises a P+ diffusion region, an N+ diffusion region and a surface base region arranged horizontally on the surface of a crystalline silicon substrate. The P+ diffusion region comprises, in sequence and from the direction away from the surface of the crystalline silicon substrate, a first tunneling oxide layer, a boron-doped polysilicon layer, a first surface silicon oxide layer, a first aluminum oxide layer, a first hafnium oxide layer and a first silicon nitride layer. The N+ diffusion region comprises, in sequence and from the direction away from the surface of the crystalline silicon substrate, a second tunneling oxide layer, a phosphorus-doped polysilicon layer, a second surface silicon oxide layer, a second aluminum oxide layer, a second hafnium oxide layer and a second silicon nitride layer. The surface base region comprises, in sequence and from the direction away from the surface of the crystalline silicon substrate, a third surface silicon oxide layer, a third aluminum oxide layer, a third hafnium oxide layer and a third silicon nitride layer.

Description

Technical Field

[0001] This application relates to the field of solar cell manufacturing, and more particularly to a BC cell with a stacked passivation structure, its preparation method, and a photovoltaic module. Background Technology

[0002] BC batteries significantly improve photoelectric conversion efficiency by placing all electrodes on the back side, but their back passivation and metallization processes face the following technical bottlenecks: Traditional passivation layer processes use ALD to deposit AlO2. x / SiN x Stacked passivation films require patterning via wet etching, a complex and costly process. Existing metallization processes utilize burn-through pastes primarily designed for TOPCon cells, failing to adapt to the back-side passivation layer structure of BC cells, resulting in insufficient penetration or damage to the passivation layer. Full-back-side etching processes can disrupt the integrity of the passivation layer, reducing open-circuit voltage and fill factor. These issues severely restrict the performance improvement and industrial application of BC cells.

[0003] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0004] The purpose of this application is to provide a BC cell with a stacked passivation structure, a method for its fabrication, and a photovoltaic module, in order to solve the above-mentioned problems.

[0005] To achieve the above objectives, this application adopts the following technical solution: This application provides a BC cell with a stacked passivation structure, including a P+ diffusion region, an N+ diffusion region and a surface base region horizontally disposed on the surface of a crystalline silicon substrate; The P+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a first tunneling oxide layer, a boron-doped polycrystalline silicon layer, a first surface silicon oxide layer, a first aluminum oxide layer, a first hafnium oxide layer, and a first silicon nitride layer stacked sequentially. The N+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a second tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a second surface silicon oxide layer, a second aluminum oxide layer, a second hafnium oxide layer, and a second silicon nitride layer stacked sequentially. The surface base region includes a third surface silicon oxide layer, a third aluminum oxide layer, a third hafnium oxide layer, and a third silicon nitride layer stacked sequentially in the direction away from the surface of the crystalline silicon substrate.

[0006] Optionally, the thickness of the first tunneling oxide layer and the second tunneling oxide layer are each independently 1.5-2.5 nm.

[0007] Optionally, the thickness of the boron-doped polycrystalline silicon layer and the phosphorus-doped polycrystalline silicon layer are each independently 60-100 nm.

[0008] Optionally, the thicknesses of the first surface silicon oxide layer, the second surface silicon oxide layer, and the third surface silicon oxide layer are each independently 1.5-2 nm.

[0009] Optionally, the thicknesses of the first alumina layer, the second alumina layer, and the third alumina layer are each independently 30-40 nm.

[0010] Optionally, the thicknesses of the first hafnium oxide layer, the second hafnium oxide layer, and the third hafnium oxide layer are each independently 10-15 nm.

[0011] Optionally, the thicknesses of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are each independently 65-85 nm.

[0012] Optionally, the P+ diffusion region further includes a first electrode, and the N+ diffusion region further includes a second electrode.

[0013] Optionally, the first electrode and the second electrode are each independently made from burn-through slurry; The burn-through slurry, calculated based on 100% of its total raw material mass, includes: 65-75% silver powder, 3-8% aluminum powder, 6.5-8.5% glass powder, 1-3% TiO2, 0.5-1.5% B4C, 0.2-1.5% organic binder, and 1-2.5% dispersant.

[0014] Optionally, the particle size of the silver powder and the aluminum powder is independently D50 = 2-4 nm.

[0015] Optionally, the glass powder is a B2O3-SiO2-Al2O3 system, and the softening point of the glass powder is 480-530℃.

[0016] Optionally, the organic binder includes ethyl cellulose.

[0017] Optionally, the dispersant includes BYK-163.

[0018] This application also provides a method for preparing a BC battery with a stacked passivation structure, including: A first tunneling oxide layer and an amorphous silicon layer are prepared on the surface of the crystalline silicon substrate, and a first silicon wafer is obtained after boron diffusion treatment. Boron doping is removed from the first silicon wafer by first laser patterning to obtain a first silicon wafer having the N+ diffusion region and the blank area of ​​the surface base region. A second tunneling oxide layer and an amorphous silicon layer are prepared on the surface of the first silicon wafer having the blank area, and a second silicon wafer is obtained after phosphorus doping treatment. The surface base region is exposed by second laser patterning on the second silicon wafer to obtain a third silicon wafer. A surface silicon oxide layer, an aluminum oxide layer, a hafnium oxide layer, and a silicon nitride layer are sequentially deposited on the third silicon wafer. The first surface silicon oxide layer, the first aluminum oxide layer, the first hafnium oxide layer, and the first silicon nitride layer are sequentially prepared in the P+ diffusion region. The second silicon oxide layer, the second aluminum oxide layer, the second hafnium oxide layer, and the second silicon nitride layer are sequentially prepared in the N+ diffusion region. The third silicon oxide layer, the third aluminum oxide layer, the third hafnium oxide layer, and the third silicon nitride layer are sequentially prepared in the surface base region.

[0019] Optionally, the boron diffusion treatment includes: introducing BCl3 gas at 820-840°C at a flow rate of 100-150 sccm for 1-1.5 min.

[0020] Optionally, the phosphorus diffusion treatment includes: introducing POCl3 gas at 790-810°C at a flow rate of 1300-1500 sccm for 15-18 min.

[0021] Optionally, the method for preparing the silicon oxide layer includes: a deposition temperature of 250-300℃, a precursor pulse time of 2-3s for ozone and 1-2s for H2O, a purging time of 2-5s, and 50-100 cycles.

[0022] Optionally, the method for preparing the alumina layer includes: a deposition temperature of 250-300℃, a precursor pulse time of 1-3s for TMA, 1-2s for H2O, a purging time of 2-5s, and 300-550 cycles.

[0023] Optionally, the preparation method of the hafnium oxide layer is as follows: the precursor pulse time is HfCl4 3-5s, H2O 1-2s, the purging time is 2-5s, and the number of cycles is 250-350.

[0024] Optionally, the preparation method further includes coating the burn-through slurry onto the surface of the first hafnium oxide layer and the surface of the second hafnium oxide layer after depositing the hafnium oxide layer, and then sintering.

[0025] Optionally, the sintering is a laser-assisted three-stage sintering, comprising: A femtosecond laser is used to create grooves on the surfaces of the first and second hafnium oxide layers, respectively; the wavelength of the femtosecond laser is 532 nm, the pulse energy is 3-5 μJ, and the groove depth is 75-85% of the total thickness of the surface silicon oxide layer, aluminum oxide layer, and hafnium oxide layer; Heat to 380-420℃ and hold for 1.5-2.5 minutes; Heat to 780-820℃ and hold for 4-6 minutes; Cool down to 500-550℃ and keep warm for 2-3 minutes.

[0026] This application also provides a photovoltaic module, including the BC cell.

[0027] Compared with the prior art, the beneficial effects of this application include: This application provides a BC solar cell with a stacked passivation structure. A P+ diffusion region, an N+ diffusion region, and a surface base region are defined on the surface of a crystalline silicon substrate using photolithography. In the P+ diffusion region, a tunneling oxide layer and a boron-doped polycrystalline silicon layer form a hole transport path. The surface silicon oxide layer provides interface passivation, the aluminum oxide layer generates field-effect passivation, the hafnium oxide layer enhances chemical passivation, and the silicon nitride layer achieves optical matching. In the N+ diffusion region, a phosphorus-doped polycrystalline silicon layer constructs an electron transport channel. The materials and thicknesses of each passivation layer are adapted to the electron transport characteristics. In the surface base region, a recombination suppression structure is formed in the undoped area through a combination of multiple passivation films. The passivation layers in each region optimize the interface band structure through material combinations, reducing the carrier recombination rate. Compared with existing technologies, traditional processes use a single passivation layer structure, which cannot adapt to the interface characteristic requirements of different doped regions. This application designs separate passivation stacks for the P+ and N+ regions, optimizing interface band matching, reducing contact resistance, suppressing hole recombination, and improving open-circuit voltage.

[0028] This application also provides a method for preparing the BC battery. After coating a burn-through slurry onto the surface of a hafnium oxide layer, a sintering process is used to allow the metal components in the slurry to penetrate the surface silicon oxide layer, aluminum oxide layer, and hafnium oxide layer, forming an electrical connection with the underlying doped polycrystalline silicon layer. During this process, glass powder softens at high temperature and assists silver and aluminum particles in penetrating the passivation layer. Simultaneously, the high dielectric constant of the hafnium oxide layer suppresses carrier recombination during sintering. This solves the problem of insufficient penetration depth in traditional metallization slurries. The passivation layer thickness and material combination in this application's technical solution can be adapted to the burn-through process requirements, thereby achieving a synergistic efficiency improvement. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.

[0030] Figure 1 A schematic diagram of a BC battery with a stacked passivation structure is provided for an embodiment. Figure 2 The image shows the SEM spectrum of the stacked passivation layer of the BC battery provided in Example 1.

[0031] The main labeling information is as follows: 100 - Crystalline silicon substrate; 110 - P+ diffusion region; 1101 - First tunneling oxide layer; 1102 - Boron-doped polycrystalline silicon layer; 1103 - First surface silicon oxide layer; 1104 - First aluminum oxide layer; 1105 - First hafnium oxide layer; 1105 - First silicon nitride layer; 1106 - First silicon nitride layer; 120 - N+ diffusion region; 1201 - Second tunneling oxide layer; 1202 - Phosphorus-doped polycrystalline silicon layer; 1203 - Second surface silicon oxide layer; 1204 - Second aluminum oxide layer; 1205 - Second hafnium oxide layer; 1206 - Second silicon nitride layer; 130 - Surface base region; 1301 - Third surface silicon oxide layer; 1302 - Third aluminum oxide layer; 1303 - Third hafnium oxide layer; 1304 - Third silicon nitride layer. Detailed Implementation

[0032] As used in this article: "Prepared from" is synonymous with "comprising". The terms "comprising", "including", "having", "containing", or any other variations thereof as used herein are intended to cover non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not necessarily limited to those elements, but may include other elements not expressly listed or elements inherent to such composition, step, method, article, or apparatus.

[0033] The conjunction "composed of..." excludes any unspecified elements, steps, or components. If used in a claim, this phrase makes the claim closed, excluding materials other than those described, except for associated conventional impurities. When the phrase "composed of..." appears in a clause of the body of a claim rather than immediately following it, it limits only the elements described in that clause; other elements are not excluded from the claim as a whole.

[0034] When a quantity, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pair of any upper or preferred value with any lower or preferred value, regardless of whether the range is disclosed individually. For example, when the range “1–5” is disclosed, the described range should be interpreted as including ranges “1–4”, “1–3”, “1–2”, “1–2 and 4–5”, “1–3 and 5”, etc. When numerical ranges are described herein, unless otherwise stated, the range is intended to include its endpoints and all integers and fractions within that range.

[0035] In these embodiments, unless otherwise specified, the portions and percentages are all by weight.

[0036] "Parts by mass" refers to the basic unit of measurement that expresses the mass ratio of multiple components. One part can represent any unit mass, such as 1g or 2.689g. If we say that component A has "a" parts by mass and component B has "b" parts by mass, it means the ratio of the mass of component A to the mass of component B is a:b. Alternatively, it can mean that the mass of component A is aK and the mass of component B is bK (where K is any number representing a multiplier). It is important to understand that, unlike parts by mass, the sum of the mass parts of all components is not limited to 100 parts.

[0037] "And / or" is used to indicate that one or both of the described situations may occur, for example, A and / or B includes (A and B) and (A or B).

[0038] To better explain the technical solution provided in this application, the technical solution provided in this application will be described in general before the specific implementation.

[0039] In existing technologies, back-contact batteries improve photoelectric conversion efficiency by placing electrodes on the back side; however, the back passivation and metallization processes face technical bottlenecks. Traditional passivation layers use a stack of aluminum oxide and silicon nitride, requiring wet etching for patterning, resulting in high process complexity and increased cost. Existing metallization pastes are designed for other battery structures and cannot be adapted to the passivation layer structure of back-contact batteries, leading to insufficient penetration or damage to the passivation layer. Full back-side etching processes disrupt the integrity of the passivation layer, causing a decrease in open-circuit voltage and fill factor, affecting battery performance.

[0040] To address the aforementioned issues, it is necessary to optimize the passivation layer structure to simplify the fabrication process, while simultaneously developing suitable metallization pastes. Analysis of the interface characteristics between the passivation layer and the electrode reveals that different doping regions have varying interface matching requirements for the passivation material. Designing multilayer passivation structures for both P-type and N-type diffusion regions improves the interface passivation effect. A specific stacked combination is used in the surface base region to balance surface recombination suppression and optical performance. The selection of the passivation layer material must consider both the quality of interface passivation and compatibility with subsequent metallization processes.

[0041] Therefore, in a first aspect, this application provides a BC cell with a stacked passivation structure, including a P+ diffusion region, an N+ diffusion region and a surface base region horizontally disposed on the surface of a crystalline silicon substrate; The P+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a first tunneling oxide layer, a boron-doped polycrystalline silicon layer, a first surface silicon oxide layer, a first aluminum oxide layer, a first hafnium oxide layer, and a first silicon nitride layer stacked sequentially. The N+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a second tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a second surface silicon oxide layer, a second aluminum oxide layer, a second hafnium oxide layer, and a second silicon nitride layer stacked sequentially. The surface base region includes a third surface silicon oxide layer, a third aluminum oxide layer, a third hafnium oxide layer, and a third silicon nitride layer stacked sequentially in the direction away from the surface of the crystalline silicon substrate.

[0042] In one optional embodiment, the thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are each independently 1.5-2.5 nm.

[0043] In one optional embodiment, the thickness of the boron-doped polycrystalline silicon layer and the phosphorus-doped polycrystalline silicon layer are each independently 60-100 nm.

[0044] In one optional embodiment, the thicknesses of the first surface silicon oxide layer, the second surface silicon oxide layer, and the third surface silicon oxide layer are each independently 1.5-2 nm.

[0045] Optionally, the thicknesses of the first surface silicon oxide layer, the second surface silicon oxide layer, and the third surface silicon oxide layer can each be independently 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, or any value between 1.5 and 2 nm.

[0046] In one optional embodiment, the thicknesses of the first alumina layer, the second alumina layer, and the third alumina layer are each independently 30-40 nm.

[0047] Optionally, the thicknesses of the first alumina layer, the second alumina layer, and the third alumina layer can each be independently 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 39 nm, 30 nm, 40 nm, or any value between 30 and 40 nm.

[0048] In one optional embodiment, the thicknesses of the first hafnium oxide layer, the second hafnium oxide layer, and the third hafnium oxide layer are each independently 10-15 nm.

[0049] Optionally, the thicknesses of the first hafnium oxide layer, the second hafnium oxide layer, and the third hafnium oxide layer can each be independently 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, or any value between 10 and 15 nm.

[0050] In one optional embodiment, the thicknesses of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are each independently 65-85 nm.

[0051] In an optional implementation, the P+ diffusion region further includes a first electrode, and the N+ diffusion region further includes a second electrode.

[0052] In one alternative embodiment, the first electrode and the second electrode are each independently made from a burn-through slurry; The burn-through slurry, calculated based on 100% of its total raw material mass, includes: 65-75% silver powder, 3-8% aluminum powder, 6.5-8.5% glass powder, 1-3% TiO2, 0.5-1.5% B4C, 0.2-1.5% organic binder, and 1-2.5% dispersant.

[0053] Optionally, the burn-through slurry, calculated based on the total mass of raw materials (100%), may contain silver powder at amounts of 65%, 66%, 67%, 68%, 69%, 70%, 71%, 72%, 73%, 74%, 75%, or any value between 65% and 75%; aluminum powder at amounts of 3%, 4%, 5%, 6%, 7%, 8%, or any value between 3% and 8%; glass powder at amounts of 6.5%, 6.6%, 6.7%, 6.8%, 6.9%, 7%, 7.1%, 7.2%, 7.3%, 7.4%, 7.5%, 7.6%, 7.7%, 7.8%, 7.9%, 8%, 8.1%, 8.2%, 8.3%, 8.4%, 8.5%, or any value between 6.5% and 8.5%; and TiO2 at amounts of 1%, 2%, 3%, or 1-3%. The dosage of B4C can be any value between % and %; the dosage of B4C can be 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, or any value between 0.5% and 1.5%; the dosage of organic binder can be 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, or any value between 0.2% and 1.5%; the dosage of dispersant can be 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, or any value between 1% and 2.5%.

[0054] In one optional embodiment, the particle size of the silver powder and the aluminum powder are each independently D50 = 2-4 nm.

[0055] Optionally, the particle size of the silver powder and the aluminum powder can be independently 2nm, 3nm, 4nm, or any value between 2-4nm.

[0056] In one optional embodiment, the glass powder is a B2O3-SiO2-Al2O3 system, and the softening point of the glass powder is 480-530℃.

[0057] Optionally, the softening point of the glass powder can be 480℃, 485℃, 490℃, 495℃, 500℃, 505℃, 510℃, 515℃, 520℃, 525℃, 530℃, or any value between 480℃ and 530℃.

[0058] In an alternative embodiment, the organic binder comprises ethyl cellulose.

[0059] In one alternative embodiment, the dispersant comprises BYK-163.

[0060] It is understandable that a passivation layer consisting of silicon dioxide, aluminum oxide, and hafnium oxide is deposited sequentially: silicon dioxide provides interface passivation, aluminum oxide provides field passivation, and the high refractive index and anti-reflection properties of hafnium oxide improve the overall passivation effect.

[0061] Specifically, the silicon oxide layer (bottom layer) is tightly bonded to the silicon substrate and forms a dense interface layer through thermal oxidation, reducing surface dangling bonds and defect state density (Dit < 1 × 10⁻⁶). 10 cm -2 ·eV -1 The positive charge characteristic can compensate for the negative charge on the silicon surface and suppress minority carrier recombination. Alumina layer (intermediate layer): high negative charge density (>1×10⁻⁶). 11 cm -2 The passivation layer further passivates the interface through the potential shielding effect, reducing defects introduced by processes such as laser cutting. It exhibits high chemical stability, preventing water and oxygen penetration and extending the passivation layer's lifespan. The hafnium oxide layer (top layer) has a high refractive index (2.0-2.1), optimizing light reflection and improving the cell's absorption efficiency for long-wavelength light. It also boasts high mechanical strength, alleviating thermal stress and reducing crack formation during sintering or laser processing. The combination of silicon oxide (low refractive index) and hafnium oxide (high refractive index) forms a gradient refractive index structure, broadening the anti-reflection spectral range (300-1100 nm), and reducing the average reflectivity to below 3.5%. Compared to traditional SiN… x Single-layer passivation and stacked structure reduce short-wavelength (300-500nm) light loss and improve quantum efficiency.

[0062] Secondly, this application also provides a method for preparing a BC battery with a stacked passivation structure, comprising: A first tunneling oxide layer and an amorphous silicon layer are prepared on the surface of the crystalline silicon substrate, and a first silicon wafer is obtained after boron diffusion treatment. Boron doping is removed from the first silicon wafer by first laser patterning to obtain a first silicon wafer having the N+ diffusion region and the blank area of ​​the surface base region. A second tunneling oxide layer and an amorphous silicon layer are prepared on the surface of the first silicon wafer having the blank area, and a second silicon wafer is obtained after phosphorus doping treatment. The surface base region is exposed by second laser patterning on the second silicon wafer to obtain a third silicon wafer. A surface silicon oxide layer, an aluminum oxide layer, a hafnium oxide layer, and a silicon nitride layer are sequentially deposited on the third silicon wafer. The first surface silicon oxide layer, the first aluminum oxide layer, the first hafnium oxide layer, and the first silicon nitride layer are sequentially prepared in the P+ diffusion region. The second silicon oxide layer, the second aluminum oxide layer, the second hafnium oxide layer, and the second silicon nitride layer are sequentially prepared in the N+ diffusion region. The third silicon oxide layer, the third aluminum oxide layer, the third hafnium oxide layer, and the third silicon nitride layer are sequentially prepared in the surface base region.

[0063] In an optional embodiment, the boron diffusion treatment includes: introducing BCl3 gas at 820-840°C at a flow rate of 100-150 sccm for 1-1.5 min.

[0064] Optionally, the temperature for boron diffusion treatment can be 820℃, 825℃, 830℃, 835℃, 840℃, or any value between 820℃ and 840℃.

[0065] In an optional embodiment, the phosphorus diffusion treatment includes: introducing POCl3 gas at 790-810°C at a flow rate of 1300-1500 sccm for 15-18 min.

[0066] Optionally, the phosphorus diffusion treatment time can be 790℃, 795℃, 800℃, 805℃, 810℃, or any value between 790℃ and 800℃.

[0067] In one optional embodiment, the method for preparing the silicon oxide layer includes: a deposition temperature of 250-300°C, a precursor pulse duration of 2-3 seconds for ozone and 1-2 seconds for H2O, a purging time of 2-5 seconds, and 50-100 cycles.

[0068] Optionally, during the preparation of the silicon oxide layer, the deposition temperature can be 250℃, 255℃, 260℃, 265℃, 270℃, 275℃, 280℃, 285℃, 290℃, 295℃, 300℃, or any value between 250℃ and 300℃; the ozone pulse time can be 2s, 2.2s, 2.4s, 2.6s, 2.8s, 3s, or any value between 2 and 3s; the water pulse time can be 1s, 1.2s, 1.4s, 1.6s, 1.8s, 2s, or any value between 1 and 2s; the purging time can be 2s, 3s, 4s, 5s, or any value between 2 and 5s. Any value between s; the number of iterations can be 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100, or any value between 50 and 100.

[0069] In one optional embodiment, the method for preparing the alumina layer includes: a deposition temperature of 250-300℃, a precursor pulse time of 1-3s for TMA, 1-2s for H2O, a purging time of 2-5s, and 300-550 cycles.

[0070] Optionally, during the preparation of the alumina layer, the deposition temperature can be 250℃, 255℃, 260℃, 265℃, 270℃, 275℃, 280℃, 285℃, 290℃, 295℃, 300℃, or any value between 250℃ and 300℃; the pulse time of the TMA can be 1s, 2s, 3s, or any value between 1s and 3s; the pulse time of the water can be 1s, 1.2s, 1.4s, 1.6s, 1.8s, 2s, or any value between 1s and 2s; the purging time can be 2s, 3s, 4s, 5s, or any value between 2s and 5s; the number of cycles can be 300, 350, 400, 450, 500, 550, or any value between 300 and 500.

[0071] In one optional embodiment, the hafnium oxide layer is prepared by: a precursor pulse time of 3-5 s for HfCl4, 1-2 s for H2O, a purging time of 2-5 s, and 250-350 cycles.

[0072] Optionally, during the preparation of hafnium oxide, the pulse time of HfCl4 can be 3 s, 4 s, 5 s, or any value between 3 and 5 s; the pulse time of water can be 1 s, 1.2 s, 1.4 s, 1.6 s, 1.8 s, 2 s, or any value between 1 and 2 s; the purging time can be 2 s, 3 s, 4 s, 5 s, or any value between 2 and 5 s; and the number of cycles can be 300, 350, 400, 450, 500, or any value between 300 and 500.

[0073] In an optional embodiment, the preparation method further includes coating the burn-through slurry onto the surfaces of the first hafnium oxide layer and the second hafnium oxide layer after depositing the hafnium oxide layer, and then sintering.

[0074] In one optional implementation, the sintering is a laser-assisted three-stage sintering, comprising: A femtosecond laser is used to create grooves on the surfaces of the first and second hafnium oxide layers, respectively; the wavelength of the femtosecond laser is 532 nm, the pulse energy is 3-5 μJ, and the groove depth is 75-85% of the total thickness of the surface silicon oxide layer, aluminum oxide layer, and hafnium oxide layer; Heat to 380-420℃ and hold for 1.5-2.5 minutes; Heat to 780-820℃ and hold for 4-6 minutes; Cool down to 500-550℃ and keep warm for 2-3 minutes.

[0075] Optionally, the pulse energy of the femtosecond laser can be 3μJ, 4μJ, 5μJ, or any value between 3 and 5μJ; the groove depth can be 75%, 76%, 77%, 78%, 79%, 80%, 81%, 82%, 83%, 84%, 85% of the total passivation layer thickness, or any value between 75 and 85%; during the sintering process, the final temperature of the first stage can be 380℃, 385℃, 390℃, 395℃, 400℃, 405℃, 410℃, 415℃, 420℃, or any value between 380 and 420℃; the holding time of the first stage can be 1.5 min, 2 min, 2.5 min, or 1.5-2.5 min. The end temperature of the second stage can be any value between 780℃, 785℃, 790℃, 795℃, 800℃, 805℃, 810℃, 815℃, 820℃, or any value between 780℃ and 820℃; the holding time of the second stage can be 4 min, 5 min, 6 min, or any value between 4 min and 6 min; the end temperature of the third stage can be 500℃, 505℃, 510℃, 515℃, 520℃, 525℃, 530℃, 535℃, 540℃, 545℃, 550℃, or any value between 500℃ and 550℃, and the holding time can be 2 min, 2.5 min, 3 min, or any value between 2 min and 3 min.

[0076] It is understandable that the coefficient of thermal expansion of borosilicate glass (CTE≈3.2×10⁻⁶) is... -6 / ℃) and silicon (CTE≈2.6×10 -6 The CTE (temperature range) of Al2O3 is close to that of Al2O3 (5.6 × 10⁻⁶ °C), which reduces interfacial thermal stress after sintering and avoids crack propagation. -6 / ℃) and HfO2 (5.7×10 -6 ( / ℃) matching enhances the overall stability of the laminated structure.

[0077] Low contact resistance: The Ag-Al alloy forms a continuous conductive network during sintering, resulting in a contact resistance of <8 mΩ·cm. 2 It is lower than that of traditional Ag plasma.

[0078] Carrier transport: High negative charge density of the alumina layer (>1×10⁻⁶) 11 cm -2 This forms a potential barrier, inhibits hole recombination, and increases the open-circuit voltage.

[0079] Thirdly, this application also provides a photovoltaic module, including the BC cell.

[0080] The implementation schemes of this application will be described in detail below with reference to specific embodiments. However, those skilled in the art will understand that the following embodiments are only for illustrating this application and should not be regarded as limiting the scope of this application. Unless otherwise specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments used without specified manufacturers are all conventional products that can be purchased commercially.

[0081] The burn-through slurry used in the examples and comparative examples is calculated based on the total mass of its raw materials as 100%, including 77% silver powder, 8% aluminum powder, 8% glass powder, 2.5% TiO2, 1.5% B4C, 1% ethyl cellulose, and 2% BYK-163.

[0082] The silver powder has a particle size D50 of 3.5 nm; the aluminum powder has a particle size D50 of 3.6 nm; and the glass powder is borosilicate glass powder with a softening point of 506℃ (purchased from Nichigo Photovoltaic).

[0083] Example 1 This embodiment provides a BC battery with a stacked passivation structure, the structural schematic of which is shown below. Figure 1 As shown: It includes a P+ diffusion region 110, an N+ diffusion region 120 and a surface base region 130 horizontally disposed on the surface of a crystalline silicon substrate 100.

[0084] The P+ diffusion region 110, in the direction away from the surface of the crystalline silicon substrate 100, includes a first tunneling oxide layer 1101, a boron-doped polycrystalline silicon layer 1102, a first surface silicon oxide layer 1103, a first aluminum oxide layer 1104, a first hafnium oxide layer 1105, and a first silicon nitride layer 1106, which are sequentially stacked.

[0085] The N+ diffusion region 120, in the direction away from the surface of the crystalline silicon substrate 100, includes a second tunneling oxide layer 1201, a phosphorus-doped polycrystalline silicon layer 1202, a second surface silicon oxide layer 1203, a second aluminum oxide layer 1204, a second hafnium oxide layer 1205, and a second silicon nitride layer 1206, which are sequentially stacked.

[0086] The surface base region 130 includes a third surface silicon oxide layer 1301, a third aluminum oxide layer 1302, a third hafnium oxide layer 1303, and a third silicon nitride layer 1304, which are sequentially stacked in the direction away from the surface of the crystalline silicon substrate 100.

[0087] in: The thickness of the first tunneling oxide layer 1101 is 2 nm; the thickness of the second tunneling oxide layer 1201 is 2 nm.

[0088] The thickness of the boron-doped polycrystalline silicon layer 1102 is 70 nm; the thickness of the phosphorus-doped polycrystalline silicon layer 1202 is 95 nm.

[0089] The thicknesses of the first surface silicon oxide layer 1103, the second surface silicon oxide layer 1203, and the third surface silicon oxide layer 1301 are each 1.75 nm.

[0090] The thicknesses of the first alumina layer 1104, the second alumina layer 1204, and the third alumina layer 1302 are each 35 nm.

[0091] The thicknesses of the first hafnium oxide layer 1105, the second hafnium oxide layer 1205, and the third hafnium oxide layer 1303 are each 12.4 nm.

[0092] The thicknesses of the first silicon nitride layer 1106, the second silicon nitride layer 1206, and the third silicon nitride layer 1304 are each 55 nm.

[0093] This embodiment also provides a method for preparing the BC battery, the specific steps of which are as follows: Silicon wafer pretreatment: Using 182mm×210mm N-type monocrystalline silicon wafers (resistivity 0.8Ω·cm), surface impurities are removed by chemical cleaning, and the reflectivity after texturing is 35%.

[0094] The first tunneling oxide layer of 2 nm was prepared by introducing oxygen at 600 °C using an LPCVD machine, followed by the deposition of 100 nm of amorphous silicon by introducing silane.

[0095] Boron diffusion forms a P+ emitter using BCl3 tubular diffusion, with BCl3 gas introduced at 830℃ to form a boron-doped layer (sheet resistance of 350Ω).

[0096] Laser patterning to remove boron doping: A green laser (pulse width 15ps, wavelength 1064nm), power 55W, and marking speed 25000mm / s is used to penetrate and modify the BSG layer.

[0097] Alkaline cleaning: Use 5% NaOH solution to clean for 110s to remove modified BSG, exposing the silicon substrate to facilitate the next step of N+ emitter preparation; The first tunneling oxide layer of 2 nm was prepared by introducing oxygen at 600 °C using an LPCVD machine, followed by the deposition of 100 nm of amorphous silicon by introducing silane.

[0098] The N+ back field was prepared by high-temperature phosphorus diffusion. POCl3 gas was introduced at 800℃ to form an N+ emitter with a sheet resistance of 50Ω.

[0099] A silicon oxide layer, an aluminum oxide layer, and a hafnium oxide layer were deposited sequentially using atomic layer deposition (ALD) technology: Silicon oxide layer preparation: ALD deposition temperature 280℃, precursor pulse time (ozone / H2O) 2.5s / 1.5s, purge time 3.5s, cycle number 75, thickness 1.75nm.

[0100] Alumina layer preparation: ALD deposition temperature 280℃, precursor pulse time (TMA / H2O) 2s / 1.5s, purging time 3.5s, cycle number 450 times, thickness 35nm; aluminum trichloride (AlCl3) was used to assist TMA deposition in the preparation of the alumina layer, which improved the density of the Al2O3 layer and reduced residue.

[0101] Hafnium oxide layer preparation: precursor pulse time (HfCl4 / H2O) was 4s / 1.5s, purge time was 3.5s, number of cycles was 300, and thickness was 12.4 nm.

[0102] A 55 nm silicon nitride layer was prepared using PECVD.

[0103] A femtosecond laser with a wavelength of 532 nm and a pulse energy of 4 μJ is used to create grooves in the passivation layer. The groove depth is controlled to be 80% of the total thickness of the passivation layer to ensure precise penetration of the slurry.

[0104] Burn-through slurry printing, three-stage printing sintering: First stage: Rapidly heat up to 400℃, hold for 2 minutes to activate the fluidity of the glass phase and initially burn through the passivation layer; Second stage: Stepwise heating to 800℃, holding for 5 minutes to promote Ag-Al alloy formation and reduce contact resistance; Third stage: Cool down to 525℃, keep warm for 2.5 minutes to relieve thermal stress.

[0105] The SEM image of its stacked passivation layer is as follows Figure 2 As shown.

[0106] Example 2 This embodiment provides a BC battery with a stacked passivation structure: It includes a P+ diffusion region 110, an N+ diffusion region 120 and a surface base region 130 horizontally disposed on the surface of a crystalline silicon substrate 100.

[0107] The P+ diffusion region 110, in the direction away from the surface of the crystalline silicon substrate 100, includes a first tunneling oxide layer 1101, a boron-doped polycrystalline silicon layer 1102, a first surface silicon oxide layer 1103, a first aluminum oxide layer 1104, a first hafnium oxide layer 1105, and a first silicon nitride layer 1106, which are sequentially stacked.

[0108] The N+ diffusion region 120, in the direction away from the surface of the crystalline silicon substrate 100, includes a second tunneling oxide layer 1201, a phosphorus-doped polycrystalline silicon layer 1202, a second surface silicon oxide layer 1203, a second aluminum oxide layer 1204, a second hafnium oxide layer 1205, and a second silicon nitride layer 1206, which are sequentially stacked.

[0109] The surface base region 130 includes a third surface silicon oxide layer 1301, a third aluminum oxide layer 1302, a third hafnium oxide layer 1303, and a third silicon nitride layer 1304, which are sequentially stacked in the direction away from the surface of the crystalline silicon substrate 100.

[0110] in: The thickness of the first tunneling oxide layer 1101 is 2 nm; the thickness of the second tunneling oxide layer 1201 is 2 nm.

[0111] The thickness of the boron-doped polycrystalline silicon layer 1102 is 60 nm; the thickness of the phosphorus-doped polycrystalline silicon layer 1202 is 90 nm.

[0112] The thicknesses of the first surface silicon oxide layer 1103, the second surface silicon oxide layer 1203, and the third surface silicon oxide layer 1301 are each 1.5 nm.

[0113] The thicknesses of the first alumina layer 1104, the second alumina layer 1204, and the third alumina layer 1302 are each 30 nm.

[0114] The thicknesses of the first hafnium oxide layer 1105, the second hafnium oxide layer 1205, and the third hafnium oxide layer 1303 are each 10 nm.

[0115] The thickness of each of the first silicon nitride layer 1106, the second silicon nitride layer 1206, and the third silicon nitride layer 1304 is 50 nm.

[0116] This embodiment also provides a method for preparing the BC battery, the specific steps of which are as follows: Silicon wafer pretreatment: Using 182mm×210mm N-type monocrystalline silicon wafers (resistivity 0.8Ω·cm), surface impurities are removed by chemical cleaning, and the reflectivity after texturing is 35%.

[0117] The first tunneling oxide layer of 2 nm was prepared by introducing oxygen at 600 °C using an LPCVD machine, followed by the deposition of 100 nm of amorphous silicon by introducing silane.

[0118] Boron diffusion forms a P+ emitter using BCl3 tubular diffusion, with BCl3 gas introduced at 820℃ to form a boron-doped layer (sheet resistance of 300Ω).

[0119] Laser patterning to remove boron doping: A green laser (pulse width 15ps, wavelength 1064nm), power 55W, and marking speed 25000mm / s is used to penetrate and modify the BSG layer.

[0120] Alkaline cleaning: Use 5% NaOH solution to clean for 110s to remove modified BSG, exposing the silicon substrate to facilitate the next step of N+ emitter preparation; The first tunneling oxide layer of 2 nm was prepared by introducing oxygen at 600 °C using an LPCVD machine, followed by the deposition of 100 nm of amorphous silicon by introducing silane.

[0121] The N+ back field was prepared by high-temperature phosphorus diffusion. POCl3 gas was introduced at 800℃ to form an N+ emitter with a sheet resistance of 50Ω.

[0122] A silicon oxide layer, an aluminum oxide layer, and a hafnium oxide layer were deposited sequentially using atomic layer deposition (ALD) technology: Silicon oxide layer preparation: ALD deposition temperature 250℃, precursor pulse time (ozone / H2O) 2s / 1s, purge time 2s, cycle number 50, thickness 1.5nm.

[0123] Alumina layer preparation: ALD deposition temperature 250℃, precursor pulse time (TMA / H2O) 1s / 1.5s, purging time 2s, cycle number 300 times, thickness 30nm; aluminum trichloride (AlCl3) was used to assist TMA deposition in the preparation of the alumina layer, which improved the density of the Al2O3 layer and reduced residue.

[0124] Hafnium oxide layer preparation: precursor pulse time (HfCl4 / H2O) is 3s / 1s, purge time is 2s, cycle number is 250, and thickness is 10nm.

[0125] A 50 nm silicon nitride layer was prepared using PECVD.

[0126] A femtosecond laser with a wavelength of 532 nm and a pulse energy of 3 μJ is used to create grooves in the passivation layer. The groove depth is controlled to be 75% of the total thickness of the passivation layer to ensure precise penetration of the slurry.

[0127] Burn-through slurry printing, three-stage printing sintering: First stage: Rapidly heat to 380℃ and hold for 1.5 minutes to activate the fluidity of the glass phase and initially burn through the passivation layer; Second stage: Stepwise heating to 780℃, holding for 4 minutes to promote Ag-Al alloy formation and reduce contact resistance; Third stage: Cool down to 500℃, keep warm for 2 minutes to relieve thermal stress.

[0128] Example 3 This embodiment provides a BC battery with a stacked passivation structure: It includes a P+ diffusion region 110, an N+ diffusion region 120 and a surface base region 130 horizontally disposed on the surface of a crystalline silicon substrate 100.

[0129] The P+ diffusion region 110, in the direction away from the surface of the crystalline silicon substrate 100, includes a first tunneling oxide layer 1101, a boron-doped polycrystalline silicon layer 1102, a first surface silicon oxide layer 1103, a first aluminum oxide layer 1104, a first hafnium oxide layer 1105, and a first silicon nitride layer 1106, which are sequentially stacked.

[0130] The N+ diffusion region 120, in the direction away from the surface of the crystalline silicon substrate 100, includes a second tunneling oxide layer 1201, a phosphorus-doped polycrystalline silicon layer 1202, a second surface silicon oxide layer 1203, a second aluminum oxide layer 1204, a second hafnium oxide layer 1205, and a second silicon nitride layer 1206, which are sequentially stacked.

[0131] The surface base region 130 includes a third surface silicon oxide layer 1301, a third aluminum oxide layer 1302, a third hafnium oxide layer 1303, and a third silicon nitride layer 1304, which are sequentially stacked in the direction away from the surface of the crystalline silicon substrate 100.

[0132] in: The thickness of the first tunneling oxide layer 1101 is 2 nm; the thickness of the second tunneling oxide layer 1201 is 2 nm.

[0133] The thickness of the boron-doped polycrystalline silicon layer 1102 is 90 nm; the thickness of the phosphorus-doped polycrystalline silicon layer 1202 is 100 nm.

[0134] The thicknesses of the first surface silicon oxide layer 1103, the second surface silicon oxide layer 1203, and the third surface silicon oxide layer 1301 are each 2 nm.

[0135] The thicknesses of the first alumina layer 1104, the second alumina layer 1204, and the third alumina layer 1302 are each 40 nm.

[0136] The thicknesses of the first hafnium oxide layer 1105, the second hafnium oxide layer 1205, and the third hafnium oxide layer 1303 are each 15 nm.

[0137] The thickness of the first silicon nitride layer 1106, the second silicon nitride layer 1206, and the third silicon nitride layer 1304 is 60 nm each.

[0138] This embodiment also provides a method for preparing the BC battery, the specific steps of which are as follows: Silicon wafer pretreatment: Using 182mm×210mm N-type monocrystalline silicon wafers (resistivity 0.8Ω·cm), surface impurities are removed by chemical cleaning, and the reflectivity after texturing is 35%.

[0139] The first tunneling oxide layer of 2 nm was prepared by introducing oxygen at 600 °C using an LPCVD machine, followed by the deposition of 100 nm of amorphous silicon by introducing silane.

[0140] Boron diffusion forms a P+ emitter using BCl3 tubular diffusion, with BCl3 gas introduced at 840℃ to form a boron-doped layer (sheet resistance of 400Ω).

[0141] Laser patterning to remove boron doping: A green laser (pulse width 15ps, wavelength 1064nm), power 55W, and marking speed 25000mm / s is used to penetrate and modify the BSG layer.

[0142] Alkaline cleaning: Use 5% NaOH solution to clean for 110s to remove modified BSG, exposing the silicon substrate to facilitate the next step of N+ emitter preparation; The first tunneling oxide layer of 2 nm was prepared by introducing oxygen at 600 °C using an LPCVD machine, followed by the deposition of 100 nm of amorphous silicon by introducing silane.

[0143] The N+ back field was prepared by high-temperature phosphorus diffusion. POCl3 gas was introduced at 800℃ to form an N+ emitter with a sheet resistance of 50Ω.

[0144] A silicon oxide layer, an aluminum oxide layer, and a hafnium oxide layer were deposited sequentially using atomic layer deposition (ALD) technology: Silicon oxide layer preparation: ALD deposition temperature 300℃, precursor pulse time (ozone / H2O) 3s / 2s, purging time 5s, cycle number 100 times, thickness 2nm.

[0145] Alumina layer preparation: ALD deposition temperature 300℃, precursor pulse time (TMA / H2O) 3s / 2s, purging time 5s, cycle number 550, thickness 40nm; aluminum trichloride (AlCl3) was used to assist TMA deposition in the preparation of the alumina layer, which improved the density of the Al2O3 layer and reduced residue.

[0146] Hafnium oxide layer preparation: precursor pulse time (HfCl4 / H2O) is 5s / 2s, purging time is 5s, cycle number is 350, and thickness is 15nm.

[0147] A 60 nm silicon nitride layer was prepared using PECVD.

[0148] A femtosecond laser with a wavelength of 532 nm and a pulse energy of 5 μJ is used to create grooves in the passivation layer. The groove depth is controlled to be 85% of the total thickness of the passivation layer to ensure precise penetration of the slurry.

[0149] Burn-through slurry printing, three-stage printing sintering: First stage: Rapidly heat to 420℃ and hold for 2.5 minutes to activate the fluidity of the glass phase and initially burn through the passivation layer; Second stage: Stepwise heating to 820℃, holding for 6 minutes to promote Ag-Al alloy formation and reduce contact resistance; Third stage: Cool down to 550℃, keep warm for 3 minutes to relieve thermal stress.

[0150] Comparative Example 1 This comparative example provides a BC battery with a stacked passivation structure: This includes P+ diffusion regions, N+ diffusion regions, and surface base regions horizontally disposed on the surface of a crystalline silicon substrate.

[0151] The P+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a first tunneling oxide layer, a boron-doped polycrystalline silicon layer, a first surface silicon oxide layer, a first aluminum oxide layer, and a first silicon nitride layer, which are stacked sequentially.

[0152] The N+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a second tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a second surface silicon oxide layer, a second aluminum oxide layer, and a second silicon nitride layer stacked sequentially.

[0153] The surface base region includes a third surface silicon oxide layer, a third aluminum oxide layer, and a third silicon nitride layer stacked sequentially in the direction away from the surface of the crystalline silicon substrate.

[0154] in: The thickness of the first tunneling oxide layer is 2 nm; the thickness of the second tunneling oxide layer is 2 nm.

[0155] The thickness of the boron-doped polycrystalline silicon layer is 70 nm; the thickness of the phosphorus-doped polycrystalline silicon layer is 95 nm.

[0156] The thicknesses of the first, second, and third surface silicon oxide layers are each 1.75 nm.

[0157] The thicknesses of the first, second, and third alumina layers are each 35 nm.

[0158] The thicknesses of the first, second, and third silicon nitride layers are each 55 nm.

[0159] This comparative example also provides a method for preparing the BC battery, the specific steps of which are as follows: Silicon wafer pretreatment: Using 182mm×210mm N-type monocrystalline silicon wafers (resistivity 0.8Ω·cm), surface impurities are removed by chemical cleaning, and the reflectivity after texturing is 35%.

[0160] The first tunneling oxide layer of 2 nm was prepared by introducing oxygen at 600 °C using an LPCVD machine, followed by the deposition of 100 nm of amorphous silicon by introducing silane.

[0161] Boron diffusion forms a P+ emitter using BCl3 tubular diffusion, with BCl3 gas introduced at 830℃ to form a boron-doped layer (sheet resistance of 350Ω).

[0162] Laser patterning to remove boron doping: A green laser (pulse width 15ps, wavelength 1064nm), power 55W, and marking speed 25000mm / s was used to penetrate and modify the BSG layer.

[0163] Alkaline cleaning: Use 5% NaOH solution to clean for 110s to remove modified BSG, exposing the silicon substrate to facilitate the next step of N+ emitter preparation; The first tunneling oxide layer of 2 nm was prepared by introducing oxygen at 600 °C using an LPCVD machine, followed by the deposition of 100 nm of amorphous silicon by introducing silane.

[0164] The N+ back field was prepared by high-temperature phosphorus diffusion. POCl3 gas was introduced at 800℃ to form an N+ emitter with a sheet resistance of 50Ω.

[0165] A silicon oxide layer, an aluminum oxide layer, and a hafnium oxide layer were deposited sequentially using atomic layer deposition (ALD) technology: Silicon oxide layer preparation: ALD deposition temperature 280℃, precursor pulse time (ozone / H2O) 2.5s / 1.5s, purge time 3.5s, cycle number 75, thickness 1.75nm.

[0166] Alumina layer preparation: ALD deposition temperature 280℃, precursor pulse time (TMA / H2O) 2s / 1.5s, purging time 3.5s, cycle number 450 times, thickness 35nm; aluminum trichloride (AlCl3) was used to assist TMA deposition in the preparation of the alumina layer, which improved the density of the Al2O3 layer and reduced residue.

[0167] A 55 nm silicon nitride layer was prepared using PECVD.

[0168] A femtosecond laser with a wavelength of 532 nm and a pulse energy of 4 μJ is used to create grooves in the passivation layer. The groove depth is controlled to be 80% of the total thickness of the passivation layer to ensure precise penetration of the slurry.

[0169] Burn-through slurry printing, three-stage printing sintering: First stage: Rapidly heat up to 400℃, hold for 2 minutes to activate the fluidity of the glass phase and initially burn through the passivation layer; Second stage: Stepwise heating to 800℃, holding for 5 minutes to promote Ag-Al alloy formation and reduce contact resistance; Third stage: Cool down to 525℃, keep warm for 2.5 minutes to relieve thermal stress.

[0170] Comparative Example 2 This comparative example provides a BC battery, with each layer identical to that of Example 1; the difference from Example 1 is that a conventional sintering process is used: Print the burn-through paste, sinter at a constant temperature of 850℃, and hold for 1 minute.

[0171] Comparative Example 3 This comparative example provides a BC battery, with each layer being the same as in Example 1; however, unlike Example 1, laser co-sintering is not used.

[0172] Comparative Example 4 This comparative example provides a BC battery, which differs from Example 1 in that no aluminum oxide layer is provided in the P+ diffusion region, N+ diffusion region, and surface base region; that is: The P+ diffusion region includes, in the direction away from the surface of the crystalline silicon substrate, a first tunneling oxide layer, a boron-doped polycrystalline silicon layer, a first surface silicon oxide layer, a first hafnium oxide layer, and a first silicon nitride layer, which are sequentially stacked.

[0173] The N+ diffusion region includes, in the direction away from the surface of the crystalline silicon substrate, a second tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a second surface silicon oxide layer, a second hafnium oxide layer, and a second silicon nitride layer, which are stacked sequentially.

[0174] The surface base region, in the direction away from the surface of the crystalline silicon substrate, includes a third surface silicon oxide layer, a third hafnium oxide layer, and a third silicon nitride layer stacked sequentially.

[0175] Comparative Example 5 This comparative example provides a BC battery, which differs from Example 1 in that no surface silicon oxide layer is provided in the P+ diffusion region, N+ diffusion region, and surface base region; that is: The P+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a first tunneling oxide layer, a boron-doped polycrystalline silicon layer, a first aluminum oxide layer, a first hafnium oxide layer, and a first silicon nitride layer, which are stacked sequentially.

[0176] The N+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a second tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a second alumina layer, a second urethane oxide layer, and a second silicon nitride layer, which are stacked sequentially.

[0177] The surface base region includes a third aluminum oxide layer, a third hafnium oxide layer, and a third silicon nitride layer stacked sequentially in the direction away from the surface of the crystalline silicon substrate.

[0178] The IV test results of the BC batteries provided in each embodiment and comparative example are shown in Table 1: Table 1 IV Test Results

[0179] As shown in Table 1, the open pressure (UOC) and fill factor (FF) of the examples are higher than those of the comparative examples, and the passivation effect is significantly improved. The increase in FF is due to the better contact effect of the new slurry. The increase in UOC indicates that the passivation effect of the alumina plus hafnium oxide stacked passivation layer is better than that of single-layer alumina passivation.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0181] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the foregoing claims, any of the claimed embodiments can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

Claims

1. A BC battery having a stacked passivation structure, characterized by, This includes P+ diffusion regions, N+ diffusion regions, and surface base regions horizontally disposed on the surface of a crystalline silicon substrate; The P+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a first tunneling oxide layer, a boron-doped polycrystalline silicon layer, a first surface silicon oxide layer, a first aluminum oxide layer, a first hafnium oxide layer, and a first silicon nitride layer stacked sequentially. The N+ diffusion region, in the direction away from the surface of the crystalline silicon substrate, includes a second tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a second surface silicon oxide layer, a second aluminum oxide layer, a second hafnium oxide layer, and a second silicon nitride layer stacked sequentially. The surface base region includes a third surface silicon oxide layer, a third aluminum oxide layer, a third hafnium oxide layer, and a third silicon nitride layer stacked sequentially in the direction away from the surface of the crystalline silicon substrate.

2. The BC battery with a stacked passivation structure of claim 1, wherein, At least one of the following conditions must be met: a. The thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are each independently 1.5-2.5 nm; b. The thickness of the boron-doped polycrystalline silicon layer and the phosphorus-doped polycrystalline silicon layer are each independently 60-100 nm; c. The thicknesses of the first surface silicon oxide layer, the second surface silicon oxide layer, and the third surface silicon oxide layer are each independently 1.5-2 nm; d. The thicknesses of the first alumina layer, the second alumina layer, and the third alumina layer are each 30-40 nm. e. The thicknesses of the first hafnium oxide layer, the second hafnium oxide layer, and the third hafnium oxide layer are each independently 10-15 nm; f. The thicknesses of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are each 65-85 nm.

3. The BC battery with a stacked passivation structure of claim 1, wherein, The P+ diffusion region further includes a first electrode, and the N+ diffusion region further includes a second electrode.

4. The BC battery of claim 3, wherein, The first electrode and the second electrode are each independently made from burn-through slurry; The burn-through slurry, calculated based on 100% of its total raw material mass, includes: 65-75% silver powder, 3-8% aluminum powder, 6.5-8.5% glass powder, 1-3% TiO2, 0.5-1.5% B4C, 0.2-1.5% organic binder, and 1-2.5% dispersant.

5. The BC battery with a stacked passivation structure according to claim 4, characterized in that, At least one of the following conditions must be met: g. The particle size of the silver powder and the aluminum powder is independently D50 = 2-4 nm; h. The glass powder is a B2O3-SiO2-Al2O3 system, and the softening point of the glass powder is 480-530℃; i. The organic binder includes ethyl cellulose; j. The dispersant includes BYK-163.

6. A method for preparing a BC battery with a stacked passivation structure as described in any one of claims 1-5, characterized in that, include: The first tunneling oxide layer and amorphous silicon layer are prepared on the surface of the crystalline silicon substrate, and a first silicon wafer is obtained after boron diffusion treatment. A first silicon wafer is obtained by performing a first laser patterning to remove boron doping on the first silicon wafer, resulting in a first silicon wafer having the N+ diffusion region and the blank area of ​​the surface base region; a second tunneling oxide layer and an amorphous silicon layer are prepared on the surface of the first silicon wafer having the blank area, and then phosphorus doping is performed to obtain a second silicon wafer; a second laser patterning is performed on the second silicon wafer to expose the surface base region, resulting in a third silicon wafer; a surface silicon oxide layer, an aluminum oxide layer, a hafnium oxide layer, and a silicon nitride layer are sequentially deposited on the third silicon wafer; the first surface silicon oxide layer, the first aluminum oxide layer, the first hafnium oxide layer, and the first silicon nitride layer are sequentially formed in the P+ diffusion region; the second silicon oxide layer, the second aluminum oxide layer, the second hafnium oxide layer, and the second silicon nitride layer are sequentially formed in the N+ diffusion region; and the third silicon oxide layer, the third aluminum oxide layer, the third hafnium oxide layer, and the third silicon nitride layer are sequentially formed in the surface base region.

7. The preparation method according to claim 6, characterized in that, At least one of the following conditions must be met: A. The boron diffusion treatment includes: introducing BCl3 gas at 820-840℃, with a flow rate of 150-200 sccm and a time of 1-1.5 min; B. The phosphorus diffusion treatment includes: introducing POCl3 gas at 790-810℃, with a flow rate of 1300-1500 sccm, for 15-18 min; C. The method for preparing the silicon oxide layer includes: deposition temperature of 250-300℃, precursor pulse time of ozone 2-3s, H2O 1-2s, purging time of 2-5s, and number of cycles of 50-100. D. The method for preparing the alumina layer includes: deposition temperature of 250-300℃, precursor pulse time of TMA 1-3s, H2O 1-2s, purging time of 2-5s, and number of cycles of 300-550. E. The preparation method of the hafnium oxide layer is as follows: the precursor pulse time is 3-5s for HfCl4, 1-2s for H2O, the purging time is 2-5s, and the number of cycles is 250-350.

8. The preparation method according to claim 6, characterized in that, The preparation method further includes coating the burn-through slurry onto the surface of the first hafnium oxide layer and the surface of the second hafnium oxide layer after depositing the hafnium oxide layer, and then sintering.

9. The preparation method according to any one of claims 6-8, characterized in that, The sintering is a laser-assisted three-stage sintering process, including: A femtosecond laser is used to create grooves on the surfaces of the first and second hafnium oxide layers, respectively; the wavelength of the femtosecond laser is 532 nm, the pulse energy is 3-5 μJ, and the groove depth is 75-85% of the total thickness of the surface silicon oxide layer, aluminum oxide layer, and hafnium oxide layer; Heat to 380-420℃ and hold for 1.5-2.5 minutes; Heat to 780-820℃ and hold for 4-6 minutes; Cool down to 500-550℃ and keep warm for 2-3 minutes.

10. A photovoltaic module, characterized in that, Includes the BC battery as described in any one of claims 1-5.

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