A bc battery and a method of manufacturing the same

Abstract

This invention discloses a BC battery and its fabrication method. The method includes: providing an N-type silicon substrate; forming a first tunneling oxide layer and a first doped layer in a first region on the back side, and forming a second tunneling oxide layer and a second doped layer in a second region; forming a textured structure in the spacer region between the front side of the N-type silicon substrate and the first and second regions, and forming a composite passivation layer on the surface of the textured structure on the front side facing away from the N-type silicon substrate; the composite passivation layer includes a thermally deposited silicon oxide layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer, and a silicon oxynitride layer stacked sequentially; forming a first electrode in contact with the first doped layer on the surface of the first region facing away from the N-type silicon substrate, and forming a second electrode in contact with the second doped layer on the surface of the second region facing away from the N-type silicon substrate; and performing low-temperature annealing on the N-type silicon substrate on which the first and second electrodes are formed. Using the above method, the open-circuit voltage and battery conversion efficiency are improved.

Description

Technical Field

[0001] This invention relates to the technical field of solar cells, and more particularly to a BC cell and its preparation method. Background Technology

[0002] Back-contact (BC) cells, due to the absence of metal grid lines obstructing the front side, can effectively improve incident light utilization efficiency, making them an important technological direction for high-efficiency crystalline silicon solar cells. Among them, N-type BC cells, combined with a tunneling oxide layer / doped polycrystalline silicon passivated contact structure, can further reduce back-side carrier recombination losses, exhibiting excellent photoelectric conversion potential.

[0003] Existing BC cells will deposit a double passivation structure (such as silicon oxide and silicon nitride or aluminum oxide and silicon nitride) on the front side during the fabrication process, or in some schemes, a thicker intrinsic hydrogenated amorphous silicon layer combined with silicon nitride will be used as a passivation and antireflection layer.

[0004] However, the interfacial chemical passivation capability of this double-layer passivation structure is limited. After high-temperature annealing of the polycrystalline silicon structure on the back side, the interfacial defects of the passivation structure will regenerate and a large amount of hydrogen will be lost, making it difficult to increase the open-circuit voltage of the battery. In addition, although the thicker intrinsic hydrogenated amorphous silicon layer can provide a certain passivation effect, its parasitic light absorption is severe, which will reduce the short-circuit current of the battery. At the same time, its high-temperature stability is poor, and it is prone to crystallization and failure in subsequent processes. Summary of the Invention

[0005] This invention provides a BC battery and its preparation method, which uses a four-layer composite passivation structure formed sequentially on the front side by a thermally oxidized silicon layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer and a silicon oxynitride layer. By utilizing the synergistic effect of each functional layer, interface recombination is suppressed, short-circuit current is guaranteed, and open-circuit voltage is increased, thereby comprehensively improving the battery conversion efficiency.

[0006] In a first aspect, the present invention provides a method for preparing a BC battery, comprising: An N-type silicon substrate is provided; the N-type silicon substrate includes an opposing front side and a back side, the back side including a first region and a second region arranged in an interdigitated space; A first tunneling oxide layer and a first doped layer are formed in the first region on the back side, and a second tunneling oxide layer and a second doped layer are formed in the second region, respectively. A textured structure is formed on the front side of the N-type silicon substrate and in the spacer between the first and second regions, and a composite passivation layer is formed on the side of the textured structure on the front side facing away from the N-type silicon substrate; the composite passivation layer includes a thermally oxidized silicon layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer and a silicon oxynitride layer stacked sequentially. A first electrode is formed on the surface of the first region away from the N-type silicon substrate, in contact with the first doped layer; and a second electrode is formed on the surface of the second region away from the N-type silicon substrate, in contact with the second doped layer. The N-type silicon substrate forming the first and second electrodes is subjected to low-temperature annealing.

[0007] Optionally, a first tunneling oxide layer and a first doped layer are formed in a first region on the back side, and a second tunneling oxide layer and a second doped layer are formed in a second region, respectively, including: Using a first deposition process, under first preset conditions, a tunneling oxide layer is formed on the back side; Using a second deposition process, under second preset conditions, an intrinsic silicon layer is formed on the side of the tunnel oxide layer facing away from the N-type silicon substrate; The intrinsic silicon layer is patterned to remove the tunneling oxide layer and intrinsic silicon layer in the spacer region between the first region and the second region, so as to form a first tunneling oxide layer and intrinsic silicon layer in the first region and a second tunneling oxide layer and intrinsic silicon layer in the second region. The intrinsic silicon layer formed in the first region and the intrinsic silicon layer formed in the second region are respectively doped with elements to form a first doped layer on the side of the first tunneling oxide layer facing away from the N-type silicon substrate, and a second doped layer on the side of the second tunneling oxide layer facing away from the N-type silicon substrate.

[0008] Optionally, the first preset condition is to introduce oxygen into the reaction chamber of the first deposition process, with an oxidation time of 15 min-25 min and an oxidation temperature of 540℃-560℃; the second preset condition is to introduce silane gas with a flow rate of 1240 sccm / min-1550 sccm / min into the reaction chamber of the second deposition process, with a deposition temperature of 610℃-630℃, a pressure of 140 mTorr-160 mTorr, and a deposition time of 35 min-45 min.

[0009] Optionally, a composite passivation layer is formed on the surface of the textured structure on the front side facing away from the N-type silicon substrate, including: Using the first passivation process, under the first passivation conditions, a thermally oxidized silicon layer is formed on the side of the textured structure facing away from the N-type silicon substrate. Using a second passivation process, under the second passivation conditions, an intrinsic hydrogenated amorphous silicon layer is formed on the surface of the thermally oxidized silicon layer on the side facing away from the N-type silicon substrate; Using the third passivation process, under the third passivation conditions, a silicon nitride layer is formed on the side of the intrinsic hydrogenated amorphous silicon layer that is away from the N-type silicon substrate. Using the fourth passivation process, under the fourth passivation conditions, a silicon oxynitride layer is formed on the side of the silicon nitride layer facing away from the N-type silicon substrate.

[0010] Optionally, the first passivation condition involves introducing oxygen into the reaction chamber of the first passivation process, with a passivation temperature of 520℃-550℃ and a holding time of 10min-20min; the second passivation condition involves introducing a mixed gas of silane and hydrogen at a gas flow ratio of 1:4-1:5 into the reaction chamber of the second passivation process, with a passivation temperature of 210℃-230℃, a pressure of 1.7mbar-2.1mbar, and a radio frequency power of 13000W-16000W; the third passivation condition involves introducing a gas at a gas flow ratio of 1:1.0-1... The first passivation condition involves introducing a mixture of silane, ammonia, and nitrous oxide into the reaction chamber of the fourth passivation process. The passivation temperature is 400℃-500℃, the pressure is 1.8mbar-2.0mbar, and the RF power is 14000W-16000W. The second passivation condition involves introducing a mixture of silane, ammonia, and nitrous oxide into the reaction chamber of the fourth passivation process. The flow rate of silane is 1200sccm-1500sccm, the flow rate of ammonia is 4000sccm-6000sccm, the flow rate of nitrous oxide is 3000sccm-5000sccm, and the passivation temperature is 400℃-500℃.

[0011] Optionally, the N-type silicon substrate forming the first and second electrodes undergoes low-temperature annealing, including: Under preset annealing conditions, the N-type silicon substrate forming the first and second electrodes is subjected to low-temperature annealing. The preset annealing conditions are: a mixture of nitrogen and hydrogen is introduced into the reaction chamber of the annealing process, with the hydrogen gas accounting for 10%-15%, the annealing temperature is 220℃-250℃, and the holding time is 35min-45min.

[0012] Optionally, after the velvet structure is formed in the spacer area between the first and second regions, the following steps are also included: A composite dielectric insulating layer is formed on the back side.

[0013] In a second aspect, the present invention provides a BC battery, comprising: an N-type silicon substrate, the N-type silicon substrate comprising a front side and a back side opposite to each other, the back side comprising a first region and a second region arranged in an interdigitated space; The front side includes a textured structure and a composite passivation layer located on the surface of the textured structure facing away from the N-type silicon substrate; the composite passivation layer includes a thermally oxidized silicon layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer and a silicon oxynitride layer stacked sequentially; the first region includes a first tunneling oxide layer, a first doped layer and a first electrode in contact with the first doped layer stacked sequentially, and the second region includes a second tunneling oxide layer, a second doped layer and a second electrode in contact with the second doped layer stacked sequentially; a textured structure is provided in the spacer region between the first region and the second region.

[0014] Optionally, the resistivity of the N-type silicon substrate is 4Ω·cm-16.0Ω·cm, the thickness is 120μm-135μm, and the original minority carrier lifetime is ≥1000μs; and / or, the thickness of the first doped layer or the second doped layer is 50nm-60nm, and the thickness of the first tunneling oxide layer is 1nm-3nm.

[0015] Optionally, the thickness of the thermally oxidized silicon layer is 2nm-4nm; the thickness of the intrinsic hydrogenated amorphous silicon layer is 10nm-15nm; the thickness of the silicon nitride layer is 20nm-30nm and the refractive index is 2.15-2.30; and the thickness of the silicon oxynitride layer is 40nm-50nm and the refractive index is 1.6-1.8.

[0016] Optionally, the total thickness of the silicon nitride layer and the silicon oxynitride layer is 70nm-82nm.

[0017] The technical solution of this invention provides an N-type silicon substrate. The N-type silicon substrate includes a front side and a back side, the back side including a first region and a second region arranged in an interdigitated pattern. A first tunneling oxide layer and a first doped layer are formed in the first region of the back side, and a second tunneling oxide layer and a second doped layer are formed in the second region. A textured structure is formed in the spacer region between the front side and the first and second regions of the N-type silicon substrate, and a composite passivation layer is formed on the surface of the textured structure on the front side facing away from the N-type silicon substrate. The composite passivation layer includes a thermally heated silicon oxide layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer, and a silicon oxynitride layer stacked sequentially. A first electrode in contact with the first doped layer is formed on the surface of the first region facing away from the N-type silicon substrate, and a second electrode in contact with the second doped layer is formed on the surface of the second region facing away from the N-type silicon substrate. The N-type silicon substrate with the first and second electrodes is subjected to low-temperature annealing. Using the above method, by sequentially forming a four-layer composite passivation structure on the front side, the synergistic effect of each functional layer is utilized to suppress interface recombination, ensure short-circuit current, and simultaneously improve open-circuit voltage, thereby comprehensively improving the battery conversion efficiency.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1This is a flowchart of a method for preparing a BC battery according to an embodiment of the present invention; Figure 2 A flowchart illustrating another method for preparing a BC battery according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a BC battery provided in an embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] In one embodiment, Figure 1 This is a flowchart illustrating a method for preparing a BC battery according to an embodiment of the present invention. This embodiment is applicable to situations where a composite passivation structure is set to suppress interface recombination, ensure short-circuit current, and simultaneously improve open-circuit voltage and battery conversion efficiency. Figure 1 As shown, the method includes: S110, Provides an N-type silicon substrate; the N-type silicon substrate includes an opposing front side and a back side, the back side including a first region and a second region arranged in an interdigitated space.

[0024] Among them, N-type silicon substrate refers to single-crystal silicon wafers with electrons as the majority carriers. Its minority carrier (hole) lifetime is relatively long, making it suitable for making high-efficiency batteries.

[0025] Specifically, by setting interdigitated first and second regions on the back side of the N-type silicon substrate, the PN junction, originally located on the front side, is moved to the back side, ensuring that all subsequently fabricated metal electrodes are located on the back side, thus completely eliminating light-blocking losses from the front-side gate lines. The front side then serves as a purely light-receiving surface, focusing on light trapping and passivation. This structural premise ensures that incident light is absorbed and utilized to the maximum extent, laying the foundation for achieving high short-circuit current and high open-circuit voltage.

[0026] S120. A first tunneling oxide layer and a first doped layer are formed in the first region on the back side, and a second tunneling oxide layer and a second doped layer are formed in the second region, respectively.

[0027] In this embodiment, both the first and second tunneling oxide layers are ultrathin silicon dioxide films, thick enough to allow charge carriers to pass through via quantum tunneling while physically isolating the silicon substrate from the doped layers. The first and second doped layers are heavily doped polycrystalline silicon layers of P-type (e.g., boron-doped) and N-type (e.g., phosphorus-doped), respectively, each forming a passivation contact structure with the overlying tunneling oxide layer. In this embodiment, the first doped layer can be a boron-doped polycrystalline silicon layer, and the second doped layer can be a phosphorus-doped polycrystalline silicon layer.

[0028] Specifically, the essence of this step is to construct carrier-selective transport interfaces in different regions on the back side. Specifically, firstly, an ultrathin tunneling oxide layer is grown over the entire back side of the N-type silicon substrate. This tunneling oxide layer forms a dense and uniform SiO2 film at high temperature. Its extremely thin thickness makes it difficult for majority carriers (electrons) to tunnel through, while minority carriers (holes or electrons) can tunnel into the doped layer under a bias voltage. Subsequently, the tunneling oxide layer formed on one side of the N-type silicon substrate is patterned and etched to remove the tunneling oxide layer in the spacer region between the first and second regions, retaining only the first tunneling oxide layer formed in the first region and the second tunneling oxide layer formed in the second region. Next, a first doped layer is deposited and doped in the first region. The first doped layer, in conjunction with the first tunneling oxide layer, forms a selective collection channel for holes. Holes tunnel through the first tunneling oxide layer and are received by the first doped layer and transported laterally. Similarly, a second doped layer is formed in the second region, constituting a selective collection channel for electrons. Because the tunneling oxide layer effectively suppresses carrier recombination at the interface, and the first and second doped layers provide good conductive pathways, this structure can achieve extremely low contact recombination current density. Furthermore, the interdigitated alternating arrangement ensures that holes and electrons are guided to their respective electrodes on the back side, avoiding the leakage risk caused by direct contact between the PN junctions.

[0029] S130. A textured structure is formed on the front side of the N-type silicon substrate and in the spacer between the first and second regions, and a composite passivation layer is formed on the side of the textured structure on the front side that faces away from the N-type silicon substrate.

[0030] The composite passivation layer comprises a thermally oxidized silicon layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer, and a silicon oxynitride layer stacked sequentially.

[0031] The textured surface is formed on the silicon surface using alkaline or acidic etching solutions, creating a micron-sized pyramidal morphology to reduce the reflectivity of incident light and increase the propagation path of light within the silicon. The composite passivation layer is a multilayer film system consisting of a thermally oxidized silicon layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer, and a silicon oxynitride layer, stacked sequentially from the inside out. The thermally oxidized silicon layer serves as a dangling bond on the saturated silicon surface, providing high-quality chemical passivation. The intrinsic hydrogenated amorphous silicon layer acts as an intermediate layer, providing additional interface passivation and serving as a hydrogen reservoir. The silicon nitride and silicon oxynitride layers, as outer layers, achieve a broadband antireflection effect with a gradually changing refractive index, while also acting as a dense barrier layer to protect against environmental damage and releasing hydrogen during subsequent heat treatment to repair interface defects.

[0032] Specifically, after forming a doped layer on the back side, a textured structure is fabricated on the front and back interdigitated spacer regions (i.e., the isolation region between the first and second regions). In other words, an N-type silicon substrate is immersed in an alkaline etching solution, and utilizing the difference in etching rates between different silicon crystal planes, a pyramidal textured structure spontaneously grows on the front surface and the back interdigitated spacer region. This textured structure allows incident light to undergo multiple reflections and refractions, reducing the effective reflectivity from approximately 30% on a flat surface to below 10%, while simultaneously increasing the optical path length within the silicon substrate, significantly improving light absorption efficiency. The textured junction structure in the back interdigitated spacer region prevents residual parasitic conductive channels in this area, enhancing electrical isolation.

[0033] Furthermore, after forming the textured structure on the front side, a composite passivation layer is grown on the surface of the textured structure facing away from the N-type silicon substrate. The composite passivation layer includes a thermally oxidized silicon layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer, and a silicon oxynitride layer stacked sequentially. In this embodiment, the composite passivation layer can be formed in various ways, including: the thermally oxidized silicon layer can be formed by, but is not limited to, high-temperature thermal oxidation, ozone oxidation, or plasma oxidation; the intrinsic hydrogenated amorphous silicon layer can be deposited by, but is not limited to, PECVD, chemical vapor deposition, or sputtering; the silicon nitride layer and the silicon oxynitride layer can be formed by, but is not limited to, PECVD, reactive sputtering, or plasma chemical vapor deposition, and both can be deposited continuously or uninterruptedly in the same chamber, or they can be deposited separately in steps; in addition to silicon oxynitride, each layer material can also use oxygen-doped silicon nitride or silicon oxynitride stacks with gradient refractive index as the surface layer. In short, as long as the four functional film layers of thermally oxidized silicon, intrinsic hydrogenated amorphous silicon, silicon nitride, and silicon oxynitride are formed sequentially on the front side, they all fall within the protection scope of this embodiment.

[0034] S140, a first electrode in contact with the first doped layer is formed on the surface of the first region away from the N-type silicon substrate, and a second electrode in contact with the second doped layer is formed on the surface of the second region away from the N-type silicon substrate.

[0035] The first electrode is a metal electrode that forms an ohmic contact with the first doped layer and is used to collect photogenerated holes. The second electrode is a metal electrode that forms an ohmic contact with the second doped layer and is used to collect photogenerated electrons. Both the first and second electrodes are fabricated on the back of the battery, arranged in an interdigitated pattern and insulated from each other. The materials of the metal grid lines of the first electrode and the second electrode can be the same or different, and there is no restriction on this.

[0036] Specifically, the purpose of forming electrodes on the front and back sides is to convert photogenerated carriers from solar energy into current that flows to the external circuit. In this embodiment, screen printing is performed on the surfaces of the first and second doped layers on the back side to form metal grid lines, including fine grids and main grids. After forming the metal grid lines, they need to be sintered at high temperature. The conditions for high-temperature sintering can be determined according to actual conditions and are not limited here. After high-temperature sintering, the metal grid lines can enter the first and second doped layers, making contact with them to form ohmic contacts. Specifically, after high-temperature sintering, a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer are formed on the back side. By placing all electrodes on the back side, the front side is completely unobstructed, completely eliminating the light loss caused by the front grid lines of traditional batteries (typically 5%~8%). At the same time, the interdigitated close arrangement shortens the lateral transport distance of carriers within the doped layers, reduces the series resistance, and helps to improve the fill factor. Furthermore, the first and second electrodes have opposite polarities; when the first electrode is positive, the corresponding second electrode is negative, and vice versa. In this embodiment, the first electrode is positive and the second electrode is negative.

[0037] S150, The N-type silicon substrate forming the first and second electrodes is subjected to low-temperature annealing.

[0038] Low-temperature annealing refers to heat treatment of the battery with completed electrode fabrication at a lower temperature in a reducing atmosphere containing hydrogen. Its core function is to activate the hydrogen stored in the composite passivation layer, allowing it to diffuse to the silicon and dielectric interface, neutralize dangling bonds and saturated interface states, thereby further reducing the interface recombination rate.

[0039] Specifically, this step involves activating the hydrogen in the passivation layer through low-temperature heat treatment after the battery metallization is completed. Specifically, the battery with the front surface composite passivation layer and the back metal electrode formed is placed in an annealing apparatus and heated in a hydrogen-containing atmosphere. The hydrogen stored in the composite passivation layer is released, forming active hydrogen atoms. Driven by the concentration gradient, these hydrogen atoms diffuse inward, passing through each film layer to reach the interface between thermally oxidized silicon and silicon, as well as textured defects, where they combine with silicon dangling bonds, thereby saturating the interface states and reducing the interface recombination rate.

[0040] Furthermore, this low-temperature annealing process is scheduled after all other processes are completed, preventing premature hydrogen escape during high-temperature steps. Because the annealing temperature is low, it does not cause thermal damage to the formed metal electrodes and doped layers, ensuring the stability of each functional layer of the battery. This effectively suppresses the recombination rate on the front surface, significantly improving the battery's open-circuit voltage.

[0041] The technical solution of this invention provides an N-type silicon substrate. The N-type silicon substrate includes a front side and a back side, the back side including a first region and a second region arranged in an interdigitated pattern. A first tunneling oxide layer and a first doped layer are formed in the first region of the back side, and a second tunneling oxide layer and a second doped layer are formed in the second region. A textured structure is formed in the spacer region between the front side and the first and second regions of the N-type silicon substrate, and a composite passivation layer is formed on the surface of the textured structure on the front side facing away from the N-type silicon substrate. The composite passivation layer includes a thermally heated silicon oxide layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer, and a silicon oxynitride layer stacked sequentially. A first electrode in contact with the first doped layer is formed on the surface of the first region facing away from the N-type silicon substrate, and a second electrode in contact with the second doped layer is formed on the surface of the second region facing away from the N-type silicon substrate. The N-type silicon substrate with the first and second electrodes is subjected to low-temperature annealing. Using the above method, by sequentially forming a four-layer composite passivation structure on the front side, the synergistic effect of each functional layer is utilized to suppress interface recombination, ensure short-circuit current, and simultaneously improve open-circuit voltage, thereby comprehensively improving the battery conversion efficiency.

[0042] In another specific embodiment, Figure 2 This is a flowchart of another method for fabricating a BC battery according to an embodiment of the present invention. This embodiment refines the specific implementation of S120 in the above embodiment, which involves forming a first tunneling oxide layer and a first doped layer in a first region on the back side, and forming a second tunneling oxide layer and a second doped layer in a second region, as follows: Using a first deposition process, under first preset conditions, a tunneling oxide layer is formed on the back side; Using a second deposition process, under second preset conditions, an intrinsic silicon layer is formed on the side of the tunnel oxide layer facing away from the N-type silicon substrate; The intrinsic silicon layer is patterned to remove the tunneling oxide layer and intrinsic silicon layer in the spacer region between the first region and the second region, so as to form a first tunneling oxide layer and intrinsic silicon layer in the first region and a second tunneling oxide layer and intrinsic silicon layer in the second region. The intrinsic silicon layer formed in the first region and the intrinsic silicon layer formed in the second region are respectively doped with elements to form a first doped layer on the side of the first tunneling oxide layer facing away from the N-type silicon substrate, and a second doped layer on the side of the second tunneling oxide layer facing away from the N-type silicon substrate.

[0043] Furthermore, the specific implementation method of forming a composite passivation layer on the surface of S130 on the side of the textured structure facing away from the N-type silicon substrate is refined as follows: Using the first passivation process, under the first passivation conditions, a thermally oxidized silicon layer is formed on the side of the textured structure facing away from the N-type silicon substrate. Using a second passivation process, under the second passivation conditions, an intrinsic hydrogenated amorphous silicon layer is formed on the surface of the thermally oxidized silicon layer on the side facing away from the N-type silicon substrate; Using the third passivation process, under the third passivation conditions, a silicon nitride layer is formed on the side of the intrinsic hydrogenated amorphous silicon layer that is away from the N-type silicon substrate. Using the fourth passivation process, under the fourth passivation conditions, a silicon oxynitride layer is formed on the side of the silicon nitride layer facing away from the N-type silicon substrate.

[0044] Furthermore, the specific implementation method of low-temperature annealing of S150 and the N-type silicon substrate forming the first and second electrodes is refined as follows: Under preset annealing conditions, the N-type silicon substrate forming the first and second electrodes is subjected to low-temperature annealing. The preset annealing conditions are: a mixture of nitrogen and hydrogen is introduced into the reaction chamber of the annealing process, with the hydrogen gas accounting for 10%-15%, the annealing temperature is 220℃-250℃, and the holding time is 35min-45min.

[0045] Furthermore, after forming the velvet structure in the interval between the first and second regions in S130, the following steps are added: A composite dielectric insulating layer is formed on the back side.

[0046] For details not covered in this embodiment, please refer to the above embodiments; no limitations are imposed here.

[0047] refer to Figure 2 As shown, the method includes: S210, Provides an N-type silicon substrate; the N-type silicon substrate includes an opposing front side and a back side, the back side including a first region and a second region arranged in an interdigitated space.

[0048] S220. Using a first deposition process, under first preset conditions, a tunneling oxide layer is formed on the back side.

[0049] The first preset conditions are to introduce oxygen into the reaction chamber of the first deposition process, with an oxidation time of 15-25 minutes and an oxidation temperature of 540℃-560℃.

[0050] The first deposition process refers to the thermal oxidation process used to grow the ultrathin oxide layer, which typically employs a high-temperature tubular oxidation furnace. The tunneling oxide layer is an ultrathin silicon dioxide (SiO2) layer with a thickness of 1nm-3nm. Its thickness allows charge carriers to pass through through the quantum tunneling effect, while physically isolating the silicon substrate from the subsequently deposited doped layers and effectively suppressing interfacial recombination.

[0051] Specifically, this step involves high-temperature heat treatment of the back surface of an N-type silicon substrate in an oxygen-containing atmosphere to grow a dense and uniform ultrathin silicon oxide film on the back surface of the N-type silicon substrate. The specific process is as follows: the N-type silicon substrate is placed in a high-temperature oxidation furnace. Using a first preset process and under first preset conditions (in this embodiment, the first preset conditions are: pure oxygen is introduced into the reaction chamber of the first deposition process; the oxidation time is 15-25 minutes; and the oxidation temperature is 540℃-560℃), oxygen molecules adsorb onto the silicon surface and decompose into oxygen atoms. The oxygen atoms then react with silicon atoms to generate SiO2. Because the reaction temperature is moderate (lower than conventional thermal oxidation temperatures), the oxidation rate is slow, allowing precise control of the thickness of the formed tunneling oxide layer within the range of 1nm to 3nm. The quality of this ultrathin tunneling oxide layer directly determines the performance of the subsequent passivation contact structure. On the one hand, its density ensures a good interface passivation effect, effectively saturating the dangling bonds on the silicon surface and reducing the interface state density. On the other hand, its extremely thin thickness ensures that minority carriers can tunnel through, while majority carriers are blocked, thus achieving selective carrier transport. The fabrication of this tunneling oxide layer is the foundation of the entire back-side passivation contact structure, and its uniformity and density have a decisive influence on the final open-circuit voltage of the battery.

[0052] S230. Using a second deposition process, under second preset conditions, an intrinsic silicon layer is formed on the surface of the tunnel oxide layer facing away from the N-type silicon substrate.

[0053] The second preset conditions are: silane gas with a flow rate of 1240 sccm / min-1550 sccm / min is introduced into the reaction chamber of the second deposition process; the deposition temperature is 610℃-630℃; the pressure is 140 mTorr-160 mTorr; and the deposition time is 35 min-45 min.

[0054] The intrinsic silicon layer refers to an undoped pure silicon thin film, which will be transformed into a heavily doped polycrystalline silicon layer through subsequent doping to serve as a carrier collection layer.

[0055] Specifically, the purpose of this step is to deposit an undoped intrinsic silicon film on the grown tunneling oxide layer as a substrate material for subsequent doping. Specifically, the N-type silicon substrate with the grown tunneling oxide layer is placed in a reaction chamber of a second deposition process (such as LPCVD). Under second preset conditions, silane gas (SiH4) is introduced at a flow rate controlled at 1240 sccm-1550 sccm, heated to 610℃-630℃, and the chamber pressure is maintained at 140 mTorr-160 mTorr for a deposition time of 35-45 minutes. Under these temperature and pressure conditions, silane molecules undergo thermal decomposition at high temperatures, generating silicon and hydrogen. The silicon atoms generated from this decomposition nucleate, condense, and grow on the surface of the tunneling oxide layer to form an amorphous silicon film. The deposited intrinsic silicon layer does not yet possess selective carrier collection capability and requires subsequent doping and annealing treatment to become a heavily doped polycrystalline silicon layer with conductivity and carrier selectivity. The thickness (approximately 50nm-60nm) and crystallization state (amorphous or microcrystalline in the deposited state, which transforms into polycrystalline after subsequent high-temperature annealing) of the intrinsic silicon layer directly affect the electrical properties and passivation effect of the final doped layer.

[0056] S240. The intrinsic silicon layer is patterned to remove the tunneling oxide layer and intrinsic silicon layer in the spacer region between the first region and the second region, so as to form a first tunneling oxide layer and intrinsic silicon layer in the first region and a second tunneling oxide layer and intrinsic silicon layer in the second region.

[0057] Patterning refers to the process of forming specific patterned structures on a thin film using techniques such as photolithography and etching. The spacer region is the isolation area between the first and second regions in the back-side interdigitated structure. This region has the tunneling oxide layer and intrinsic silicon layer removed to prevent leakage between the P-region and the N-region.

[0058] Specifically, this step involves forming interdigitated, alternating isolation trenches on the back side using a patterning process. This achieves electrical isolation between the subsequent P-type and N-type doped regions and removes the tunneling oxide layer and intrinsic silicon layer in the spacer region. Specifically, photoresist is first coated onto the deposited intrinsic silicon layer surface. Exposure and development using a mask create openings corresponding to the spacer regions on the back side, exposing the underlying intrinsic silicon layer. Then, dry etching (such as reactive ion etching, RIE) or wet etching is used to sequentially remove the intrinsic silicon layer and tunneling oxide layer within the opening regions until the N-type silicon substrate is exposed. Finally, the remaining photoresist is removed. Through this process, the intrinsic silicon layer and tunneling oxide layer on the back side are separated into a first and a second region, while the spacer region exposes the bare N-type silicon substrate. The presence of this spacer region ensures that there is no direct physical contact or conductive channel between the subsequently doped first and second doped layers, effectively avoiding the risk of leakage between PN junctions. Meanwhile, the exposed silicon surface in the spacer area will form a pyramid textured surface during the subsequent textured surface preparation process, further enhancing the light trapping effect and insulation performance of this area.

[0059] S250. The intrinsic silicon layer formed in the first region and the intrinsic silicon layer formed in the second region are respectively doped with elements to form a first doped layer on the side of the first tunneling oxide layer away from the N-type silicon substrate, and a second doped layer on the side of the second tunneling oxide layer away from the N-type silicon substrate.

[0060] Element doping refers to the process of introducing specific impurity elements into the intrinsic silicon layer to change its conductivity and resistivity. The first doped layer is a polycrystalline silicon layer formed on an N-type silicon substrate by boron diffusion. The second doped layer is a polycrystalline silicon layer formed on an N-type silicon substrate by phosphorus diffusion.

[0061] Specifically, this step uses a partitioned doping technique to introduce opposite types of impurity elements into the intrinsic silicon layers of the first and second regions, forming an interdigitated alternating arrangement of the first and second doped layers. The specific process is as follows: First, the N-type silicon substrate is placed in the doping equipment. A certain flow rate and volume of boron trichloride and oxygen are introduced into the reaction chamber, wherein the boron ion concentration is 1.0 × 10⁻⁶. 19 cm -2 -3×10 19 cm -2Boron is deposited at low temperature on the side of the first intrinsic silicon layer away from the N-type silicon substrate through a chemical reaction between boron trichloride, oxygen, and the first intrinsic silicon layer. After the boron is deposited, it is pushed into the first intrinsic silicon layer at high temperature to form a first doped layer. After the first doped layer is formed by high-temperature doping in the first region, boron usually does not completely react into the first intrinsic silicon layer and will produce some residual organic matter. To prevent the residual organic matter from affecting the first doped layer, it can be post-oxidized. By introducing a certain flow rate of oxygen into the post-oxidation reaction chamber, the residual organic matter reacts with oxygen to form a first mask layer, which is usually a borosilicate glass layer.

[0062] Similar to the formation process of the first doped layer, a certain flow rate of nitrogen and oxygen is introduced into the reaction chamber of the low-temperature deposition process. The nitrogen is doped with phosphorus oxychloride, and the phosphorus ion concentration is 3.0 × 10⁻⁶. 20 cm -2 ~5×10 20 cm -2 Phosphorus oxychloride is used as the dopant source in the phosphorus diffusion process. Under preset deposition conditions, a layer of phosphorus can be deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate by utilizing the chemical reaction between phosphorus oxychloride, oxygen, and the second intrinsic silicon layer. After phosphorus formation, it is propagated at high temperature. By setting the propagation temperature, the phosphorus diffuses into the second intrinsic silicon layer to form a second doped layer. After the second doped layer is formed, the residual organic matter generated during the doping process is post-oxidized. A certain flow rate of oxygen is introduced into the post-oxidation reaction chamber, allowing the residual organic matter to react with oxygen to form a second mask layer. Typically, the second mask layer is a phosphorus-silicon glass layer.

[0063] Understandably, since a first mask layer is formed in the first region and a second mask layer is formed in the second region, the first and second mask layers need to be removed before preparing the dielectric insulating layer. Specifically, the N-type silicon substrate can be placed in an acid pickling tank, and the first and second mask layers can be removed under preset acid pickling conditions by adding a mixed solution of hydrofluoric acid and nitric acid of a certain concentration to the acid pickling tank, thus preparing for the subsequent removal of the insulating slurry layer and texturing.

[0064] S260, A textured structure is formed on the front side of the N-type silicon substrate and in the spacer between the first and second regions.

[0065] S270, A composite dielectric insulating layer is formed on the back side.

[0066] The composite dielectric insulating layer refers to a multilayer insulating film deposited on the back side, which may include, but is not limited to, a stack of silicon oxide and silicon nitride, used to protect the back-side doped structure and prevent the metal electrode from contacting the non-target area.

[0067] Specifically, the purpose of this step is to coat the back side with an insulating protective film, providing a mask and protection for the subsequent selective fabrication of metal electrodes. Taking a composite dielectric insulating layer consisting of a stack of silicon oxide and silicon nitride as an example, the specific process involves sequentially depositing a silicon oxide layer and a silicon nitride layer of a predetermined thickness on the back side using PECVD. The deposition temperature is controlled within a low-temperature range of 200℃-250℃ to avoid affecting the already completed high-temperature doped structure. The silicon oxide layer acts as an interface buffer layer, providing good adhesion and stress matching; the silicon nitride layer, as a dense barrier layer, has excellent water vapor and ion contamination resistance. This composite dielectric insulating layer serves as a mask during the back side metallization process, protecting the non-windowed areas from metal deposition. Furthermore, during final battery operation, the insulating layer covers the spacer area, further ensuring electrical isolation between the P-region and N-region, preventing leakage risks caused by external contamination or moisture intrusion, and exhibiting better insulation performance and mechanical stability.

[0068] S280. Using a first passivation process, under the first passivation conditions, a thermally oxidized silicon layer is formed on the side of the textured structure facing away from the N-type silicon substrate.

[0069] The first passivation conditions are: oxygen is introduced into the reaction chamber of the first passivation process, the passivation temperature is 520℃-550℃, and the holding time is 10min-20min.

[0070] The first passivation process refers to a low-temperature thermal oxidation process, used to grow a high-quality chemical passivation layer on the silicon surface. The thermally oxidized silicon layer is a silicon dioxide (SiO2) film grown on the silicon surface through thermal oxidation, with a thickness of 2nm~4nm. It is used for dangling bonds on the saturated silicon surface, providing excellent interfacial chemical passivation.

[0071] Specifically, this step involves growing an extremely thin thermally oxidized silicon layer on the textured surface of the front side, serving as the bottom layer of the entire front surface composite passivation structure. The process is as follows: the N-type silicon substrate with the completed back insulating layer is placed in a low-temperature oxidation furnace. A certain flow rate and volume of oxygen are introduced into the reaction chamber of the first passivation process, and the temperature is maintained at 520℃~550℃ for 10~20 minutes. Under these first passivation conditions, oxygen molecules adsorb onto the silicon surface of the front pyramid textured surface, decompose into oxygen atoms, and then react with silicon atoms to form a thermally oxidized silicon layer. This thermally oxidized silicon layer has the following characteristics: firstly, it forms a perfect coherent interface with the silicon substrate, efficiently saturating the dangling bonds on the silicon surface and reducing the interface state density to 10. 10 cm -2 eV -1First, it provides an interface with extremely low recombination rates; second, it is extremely thin, so it will not significantly obstruct carrier transport and will not affect the optical performance of subsequent layers; third, the thermal oxidation process itself does not contain hydrogen, but it can provide a good adhesion interface for the subsequently deposited hydrogen-rich layer, so that hydrogen can efficiently diffuse to the interface for defect repair during subsequent annealing.

[0072] S290. Using a second passivation process, under the second passivation conditions, an intrinsic hydrogenated amorphous silicon layer is formed on the surface of the thermally oxidized silicon layer on the side facing away from the N-type silicon substrate.

[0073] The second passivation conditions are achieved by introducing a mixed gas of silane and hydrogen with a gas flow ratio of 1:4 to 1:5 into the reaction chamber of the second passivation process, with a passivation temperature of 210℃-230℃, a pressure of 1.7mbar-2.1mbar, and a radio frequency power of 13000W-16000W.

[0074] The second passivation process refers to the process of depositing intrinsic hydrogenated amorphous silicon using PECVD. The intrinsic hydrogenated amorphous silicon layer is an undoped hydrogen-containing amorphous silicon thin film (a-Si:H) with a thickness of 10nm-15nm, used to further passivate interface defects and provide a hydrogen source.

[0075] Specifically, the purpose of this step is to deposit an intrinsic hydrogenated amorphous silicon thin film on a thermally oxidized silicon layer as an intermediate functional layer of the composite passivation layer. The specific process is as follows: A second passivation process is employed, raising the silicon wafer temperature to 210℃-230℃. A mixture of silane and hydrogen is introduced into the reaction chamber of the second passivation process, where the SiH4:H2 flow ratio is controlled at 1:4~1:5, the chamber pressure is maintained at 1.7mbar-2.1mbar, and the RF power is 13kW-16kW. Under these second passivation conditions, SiH4 and H2 molecules are ionized and decomposed, generating active groups such as SiH3, SiH2, and H. These groups undergo surface reactions on the silicon wafer surface and condense to form an amorphous silicon thin film. Simultaneously, a certain amount of hydrogen is incorporated into the film, forming an intrinsic hydrogenated amorphous silicon layer a-Si:H. The intrinsic hydrogenated amorphous silicon layer mainly serves the following functions: it has good interface passivation capabilities, which can further repair interface defects that may remain in the thermally oxidized silicon layer; at the same time, it acts as a hydrogen reservoir, providing a sufficient hydrogen source for subsequent low-temperature annealing.

[0076] S300: Using the third passivation process, under the third passivation conditions, a silicon nitride layer is formed on the side of the intrinsic hydrogenated amorphous silicon layer that is away from the N-type silicon substrate.

[0077] The third passivation conditions are achieved by introducing a mixture of silane and ammonia with a gas flow ratio of 1:1.0 to 1:1.3 into the reaction chamber of the third passivation process, with a passivation temperature of 400℃-500℃, a pressure of 1.8mbar-2.0mbar, and a radio frequency power of 14000W-16000W.

[0078] The third passivation process includes PECVD. The silicon nitride layer is a hydrogen-containing silicon nitride thin film (SiN). x :H), with a thickness of 20nm-30nm, and has both anti-reflection and passivation functions.

[0079] Specifically, the purpose of this step is to continuously deposit a silicon nitride thin film on the intrinsic hydrogenated amorphous silicon layer, serving as the inner anti-reflection and passivation layer of the composite passivation layer. The specific process is as follows: using the same PECVD equipment as S290 (continuous deposition without vacuum), the silicon wafer temperature is maintained at 400℃-500℃. A mixture of silane (SiH4) and ammonia (NH3) is introduced into the reaction chamber of the third passivation process. The SiH4:NH3 flow rate ratio is controlled at 1:1.0-1:1.3, and the chamber pressure is set at 1.8mbar-2.0mbar, with an RF power of 14kW-16kW. Under these third passivation conditions, the active groups such as Si, N, and H generated from the decomposition of SiH4 and NH3 react on the surface of the intrinsic hydrogenated amorphous silicon layer to form a silicon nitride layer (i.e., SiN). x (H thin film). The silicon nitride layer has a high refractive index (2.15~2.30), serving as the first matching layer in the multilayer antireflective film. It forms a refractive index gradient with the subsequent silicon oxynitride layer, achieving a broadband antireflective effect. In addition, the Si-H and NH bonds contained in the silicon nitride layer will break and release hydrogen atoms during subsequent low-temperature annealing, providing a hydrogen source for interface defect repair. The silicon nitride itself has a dense structure, which can act as a barrier layer to prevent external moisture and sodium ions from penetrating the interior.

[0080] S310. Using the fourth passivation process, under the fourth passivation conditions, a silicon oxynitride layer is formed on the side of the silicon nitride layer facing away from the N-type silicon substrate.

[0081] The fourth passivation condition involves introducing a mixture of silane, ammonia, and nitrous oxide into the reaction chamber of the fourth passivation process. The flow rate of silane is in the range of 1200 sccm-1500 sccm, the flow rate of ammonia is in the range of 4000 sccm-6000 sccm, the flow rate of nitrous oxide is in the range of 3000 sccm-5000 sccm, and the passivation temperature is in the range of 400℃-500℃.

[0082] The fourth passivation process is the same as the third passivation process and will not be described again here. The silicon oxynitride layer is an oxygen-doped silicon nitride thin film (SiON) with a thickness of 40nm-50nm. As the surface layer of the composite passivation layer, it provides triple functions of anti-reflection, dense protection, and hydrogen source.

[0083] Specifically, this step involves continuously depositing a silicon oxynitride (SiON) thin film on the silicon nitride layer to complete the construction of the entire composite passivation layer. The specific process is as follows: Without breaking the vacuum in the PECVD reaction chamber of the S300, a mixed gas is continuously introduced, consisting of silane (SiH4) at a flow rate of 1200-1500 sccm, ammonia (NH3) at a flow rate of 4000-6000 sccm, and nitrous oxide (N2O) at a flow rate of 3000-5000 sccm. Simultaneously, N2 is used as the carrier gas. Under the fourth passivation condition with a deposition temperature of 400℃~500℃, the introduction of N2O gas provides oxygen to the thin film, thereby forming a 40nm-50nm thick silicon oxynitride (SiON) layer on the side of the silicon nitride layer facing away from the N-type silicon substrate. The main functions of the silicon oxynitride layer are as follows: First, its refractive index can be adjusted within the range of 1.6 to 1.8 by adjusting the N2O flow rate, forming a smooth transition of refractive index from the silicon substrate (3.5) to air (1) with the underlying silicon nitride layer (refractive index about 2.2), effectively reducing reflection loss over a wide spectral range; Second, as a surface layer, silicon oxynitride has lower stress and higher density than silicon nitride, providing excellent protection against oxidation, moisture, and mechanical scratches; Third, it also contains a large number of Si-H and NH bonds, serving as an additional hydrogen source to participate in defect repair during subsequent low-temperature annealing.

[0084] S320, a first electrode in contact with the first doped layer is formed on the surface of the first region away from the N-type silicon substrate, and a second electrode in contact with the second doped layer is formed on the surface of the second region away from the N-type silicon substrate.

[0085] S330. Under preset annealing conditions, the N-type silicon substrate forming the first and second electrodes is subjected to low-temperature annealing.

[0086] The preset annealing conditions are as follows: a mixture of nitrogen and hydrogen is introduced into the reaction chamber of the annealing process, with the hydrogen gas accounting for 10%-15%, the annealing temperature is 220℃-250℃, and the holding time is 35min-45min.

[0087] Specifically, this step involves low-temperature hydrogen annealing after battery metallization to activate hydrogen in the composite passivation layer and repair interface defects. The process is as follows: The battery with the front composite passivation layer and back metal electrode formed is placed in an annealing apparatus (such as a tubular or chain annealing furnace). A mixture of nitrogen (N2) and hydrogen (H2) gas (H2 volume percentage 10%-15%) is introduced into the reaction chamber of the annealing apparatus and held at 220℃-250℃ for 35-45 minutes. Under these preset annealing conditions, a large number of Si-H and NH bonds in the outer silicon nitride and silicon oxynitride layers of the composite passivation layer undergo thermal breakage, releasing active hydrogen atoms. These hydrogen atoms diffuse inward under the drive of the concentration gradient, sequentially passing through the silicon oxynitride layer, the silicon nitride layer, and the intrinsic hydrogenated amorphous silicon layer, finally reaching the thermally oxidized silicon layer and the silicon interface, reducing the interface state density by 1-2 orders of magnitude. Ultimately, the positive recombination rate was suppressed to an extremely low level, and the battery open-circuit voltage stabilized at over 750 mV.

[0088] The technical solution of this invention utilizes a first deposition process to form a tunneling oxide layer on the back side under first preset conditions; utilizes a second deposition process to form an intrinsic silicon layer on the surface of the tunneling oxide layer facing away from the N-type silicon substrate under second preset conditions; the intrinsic silicon layer is patterned to remove the tunneling oxide layer and intrinsic silicon layer in the gap between the first region and the second region, so that a first tunneling oxide layer and intrinsic silicon layer are formed in the first region, and a second tunneling oxide layer and intrinsic silicon layer are formed in the second region; the intrinsic silicon layer formed in the first region and the intrinsic silicon layer formed in the second region are respectively elementally doped to form an intrinsic silicon layer on the surface of the first tunneling oxide layer facing away from the N-type silicon substrate. A first doped layer is formed on the surface of the second tunneling oxide layer, and a second doped layer is formed on the side of the surface facing away from the N-type silicon substrate. Using a first passivation process, under the first passivation condition, a thermally applied silicon oxide layer is formed on the side of the textured structure facing away from the N-type silicon substrate. Using a second passivation process, under the second passivation condition, an intrinsic hydrogenated amorphous silicon layer is formed on the side of the thermally applied silicon oxide layer facing away from the N-type silicon substrate. Using a third passivation process, under the third passivation condition, a silicon nitride layer is formed on the side of the intrinsic hydrogenated amorphous silicon layer facing away from the N-type silicon substrate. Using a fourth passivation process, under the fourth passivation condition, a silicon oxynitride layer is formed on the side of the silicon nitride layer facing away from the N-type silicon substrate. This method effectively solves the problems of interface defect regeneration and hydrogen loss caused by high-temperature annealing in existing technologies, while avoiding parasitic light absorption loss in thick intrinsic hydrogenated amorphous silicon layers. Therefore, it improves the open-circuit voltage while ensuring the short-circuit current, thus comprehensively improving the photoelectric conversion efficiency of the BC cell.

[0089] Based on the same inventive concept Figure 3 This is a schematic diagram of the structure of a BC battery provided in an embodiment of the present invention, with reference to... Figure 3As shown, the BC battery includes an N-type silicon substrate 1, which includes a front side and a back side. The back side includes a first region and a second region arranged in an interdigitated pattern. The front side includes a textured structure 2 and a composite passivation layer 3 located on the surface of the textured structure 2 facing away from the N-type silicon substrate 1. The composite passivation layer 3 includes a thermally stacked silicon oxide layer 31, an intrinsic hydrogenated amorphous silicon layer 32, a silicon nitride layer 33, and a silicon oxynitride layer 34. The first region includes a first tunneling oxide layer 41, a first doped layer 42, and a first electrode 6 in contact with the first doped layer 42, which are stacked in sequence. The second region includes a second tunneling oxide layer 51, a second doped layer 52, and a second electrode 7 in contact with the second doped layer 52, which are stacked in sequence. The textured structure 2 is disposed in the spacer region between the first region and the second region.

[0090] Specifically, incident light shines from the front, and the light-trapping effect of the textured structure 2 reduces reflection and increases the optical path, subsequently generating photogenerated carriers in the N-type silicon substrate 1. After electrons and holes are separated, minority carriers are transported to the back side. Holes tunnel through the first tunneling oxide layer 41 in the first region and are collected by the first doped layer 42 and laterally transported to the first electrode 6. Electrons tunnel through the second tunneling oxide layer 51 in the second region and are collected by the second doped layer 52 and laterally transported to the second electrode 7, thereby achieving spatial separation and efficient output of carriers. At the same time, in the composite passivation layer 3 formed on the front side, the saturated interface dangling bonds of the thermally oxidized silicon layer 31 provide chemical passivation, the intrinsic hydrogenated amorphous silicon layer 32 further repairs interface defects and acts as a hydrogen reservoir, and the silicon nitride layer 33 and the silicon oxynitride layer 34 form a refractive index gradient structure to achieve broadband antireflection. Combined with subsequent low-temperature annealing to release hydrogen atoms to repair interface defects, this significantly reduces the recombination rate of the front surface. Furthermore, the felt structure 2 set in the interval between the first and second regions further enhances the electrical isolation effect of this region, prevents leakage between the P and N regions, and ultimately achieves a synergistic improvement in high open-circuit voltage, high short-circuit current and high fill factor.

[0091] It should be noted that the reference Figure 3 A composite dielectric insulating layer 8 is also provided on the side of the back facing away from the N-type silicon substrate 1. This insulating layer can serve as a protective layer. On the one hand, it acts as a mask during the back metallization process to protect the non-windowed areas from metal deposition. On the other hand, when the battery is in operation, the insulating layer covers the spacer area to further ensure the electrical isolation between the P-region and the N-region, prevent leakage risks caused by external contamination or moisture intrusion, and has better insulation performance and mechanical stability.

[0092] The technical solution of this invention achieves excellent interface chemical passivation, broadband antireflection, and selective carrier collection by combining the front textured structure with the multilayer composite passivation layer of thermally oxidized silicon / intrinsic hydrogenated amorphous silicon / silicon nitride / silicon oxynitride, and the back interdigitated tunneling oxide layer / doped polycrystalline silicon passivation contact structure. At the same time, the textured structure of the back spacer enhances electrical isolation, and the low-temperature hydrogen annealing can effectively repair interface defects. This reduces the front surface recombination rate, avoids parasitic light absorption loss, and improves the open-circuit voltage and short-circuit current, thereby comprehensively improving the photoelectric conversion efficiency of the battery.

[0093] Optional, continue to refer to Figure 3 The resistivity of the N-type silicon substrate 1 is 4Ω·cm-16.0Ω·cm, the thickness is 120μm-135μm, and the original minority carrier lifetime is ≥1000μs; and / or, the thickness of the first doped layer 42 or the second doped layer 52 is 50nm-60nm, and the thickness of the first tunneling oxide layer 41 is 1nm-3nm.

[0094] The resistivity of the N-type silicon substrate 1 is 4 Ω·cm-16.0 Ω·cm. Examples include 4 Ω·cm, 8 Ω·cm, 10 Ω·cm, 12 Ω·cm, 14 Ω·cm, or 16.0 Ω·cm, which can be determined based on actual conditions and are not limited here. This setting ensures good bulk conductivity to reduce series resistance and provides sufficient bulk lifetime to maintain a long diffusion length, which is beneficial for the effective diffusion of photogenerated minority carriers to the back side for collection by the selective contact structure. The thickness of the N-type silicon substrate 1 is 120 μm-135 μm. Examples include 120 μm, 125 μm, 128 μm, 130 μm, 132 μm, or 135 μm, which can be determined based on actual conditions and are not limited here. Furthermore, the original minority carrier lifetime of the N-type silicon substrate 1 is ≥1000 μs, ensuring excellent material quality of the silicon substrate itself and providing a fundamental guarantee for maintaining a high open-circuit voltage after subsequent high-temperature processes.

[0095] The thickness of the first doped layer 42 or the second doped layer 52 is 50nm-60nm. For example, the thickness of the first doped layer 42 or the second doped layer 52 is 50nm, 52nm, 54nm, 55nm, 58nm, 59nm, or 60nm, etc., which can be determined according to the actual situation and are not limited here. This can ensure good conductivity (low sheet resistance) while avoiding parasitic absorption and stress problems caused by excessively thick polycrystalline silicon layers. The thickness of the first tunneling oxide layer 41 is 1nm-3nm. For example, the thickness of the first tunneling oxide layer 41 is 1nm, 1.2nm, 1.5nm, 1.8nm, 2nm, 2.2nm, 2.5nm, 2.8nm, or 3nm, etc., which can be determined according to the actual situation and are not limited here. This ensures efficient tunneling of charge carriers while effectively blocking majority carriers, thereby achieving an extremely low interface recombination rate.

[0096] Optionally, the thickness of the thermally oxidized silicon layer 31 is 2nm-4nm; the thickness of the intrinsic hydrogenated amorphous silicon layer 32 is 10nm-15nm; the thickness of the silicon nitride layer 33 is 20nm-30nm and the refractive index is 2.15-2.30; and the thickness of the silicon oxynitride layer 34 is 40nm-50nm and the refractive index is 1.6-1.8.

[0097] The thickness of the thermally oxidized silicon layer 31 is 2nm-4nm. For example, the thickness of the thermally oxidized silicon layer 31 is 2nm, 2.2nm, 2.5nm, 2.8nm, 3nm, 3.2nm, 3.5nm, 3.8nm or 4nm, etc. The specific thickness can be determined according to the actual situation and is not limited here. In this way, the dangling bonds on the silicon surface can be fully saturated through the thermal oxidation process to form a high-quality chemical passivation interface, while not being too thick to hinder carrier tunneling or affect the optical matching of subsequent film layers.

[0098] The thickness of the intrinsic hydrogenated amorphous silicon layer 32 is 10nm-15nm. For example, the thickness of the intrinsic hydrogenated amorphous silicon layer 32 is 10nm, 11nm, 11.5nm, 12nm, 12.5nm, 13nm, 13.5nm, 14nm, 14.5nm or 15nm, etc. The specific thickness can be determined according to the actual situation and is not limited here. This ensures excellent chemical passivation effect and controls parasitic light absorption within an acceptable range, achieving synergistic optimization of passivation performance and optical performance.

[0099] The thickness of the silicon nitride layer 33 is 20nm-30nm. For example, the thickness of the silicon nitride layer 33 is 20nm, 22nm, 25nm, 27nm, 28nm, 29nm or 30nm, etc., which can be determined according to the actual situation and are not limited here. The refractive index is 2.15-2.30. For example, the refractive index of the silicon nitride layer 33 is 2.15, 2.16, 2.17, 2.18, 2.19 or 2.30, etc., which can be determined according to the actual situation and are not limited here. This thickness and refractive index range enable the silicon nitride layer to serve as the inner layer of the multilayer antireflection film, forming a smooth transition gradient of refractive index from N-type silicon substrate (about 3.5) to air (1.0) with the subsequent silicon oxynitride layer, effectively reducing reflection loss over a wide spectral range. At the same time, the silicon nitride layer of this thickness is rich in Si-H and NH bonds, which can serve as a sufficient hydrogen reservoir to release hydrogen atoms during subsequent low-temperature annealing to repair interface defects and further reduce the interface recombination rate.

[0100] The thickness of the silicon oxynitride layer 34 is 40nm-50nm. For example, the thickness of the silicon oxynitride layer 34 can be 40nm, 42nm, 45nm, 47nm, 48nm, 49nm, or 50nm, etc., and can be determined according to the actual situation. No limitation is imposed here. The refractive index is 1.6-1.8. For example, the refractive index of the silicon oxynitride layer 34 can be 1.6, 1.64, 1.66, 1.68, 1.7, 1.74, 1.76, 1.78, or 1.8, etc., and can be determined according to the specific situation. The actual situation will determine the specific requirements, but no restrictions are imposed here. This thickness and refractive index range allow the silicon oxynitride layer to serve as the outermost layer of the multilayer antireflective coating, forming a good optical match with the underlying silicon nitride layer (refractive index of approximately 2.2), further reducing surface reflectivity to below 5%. At the same time, the silicon oxynitride layer has lower stress and higher density than silicon nitride, providing excellent protection against oxidation, moisture, and mechanical scratches. As a dense barrier layer, it effectively prevents external environmental erosion of the internal passivation layer, extending the long-term stability of the battery.

[0101] Optionally, the total thickness of the silicon nitride layer 33 and the silicon oxynitride layer 34 is 70nm-82nm.

[0102] The total thickness of the silicon nitride layer 33 and the silicon oxynitride layer 34 is 70nm-82nm. For example, the total thickness of the silicon nitride layer 33 and the silicon oxynitride layer 34 can be 70nm, 72nm, 75nm, 77nm, 78nm, 80nm or 82nm, etc. The specific thickness can be determined according to the actual situation and is not limited here. This total thickness range, combined with the refractive index gradient design of the two layers, can achieve constructive interference antireflection effect on incident light in a wide spectral range of 300nm-1200nm, and control the weighted average reflectivity within the ideal range. At the same time, the total thickness will not be too thick, which would lead to excessive film stress or excessive deposition time, thus taking into account the compatibility of optical performance, passivation effect and mass production process.

[0103] In another specific embodiment, the method for preparing a BC battery includes: S1. Silicon wafer pretreatment: An N-type Czochralski single crystal silicon wafer with a resistivity of 10.0 Ω·cm, a thickness of 135 μm, and an initial minority carrier lifetime of 1200 μs is selected as the N-type silicon substrate. After double-sided polishing of the N-type silicon substrate, a first tunneling oxide layer and a first doped layer are sequentially stacked in the first region on the back side, and a second tunneling oxide layer and a second doped layer are sequentially stacked in the second region, forming a pyramid textured structure on the front side.

[0104] S2. Deposition of the composite insulating protective layer on the back: A 10nm thick silicon oxide and a 60nm thick silicon nitride composite insulating layer are deposited at a low temperature of 220℃ in the PECVD equipment. S3. Backside metallization sintering to form a first electrode in contact with the first doped layer in a first region and a second electrode in contact with the second doped layer in a second region; S4. Preparation of front-side composite passivation layer: ① Front-side low-temperature thermal silicon oxide layer: A 3nm thick thermal silicon oxide layer was prepared by oxidation in a pure oxygen atmosphere at 530℃ for 15 minutes. ② Deposition of intrinsic hydrogenated amorphous silicon layer: The deposition temperature in the PECVD equipment is set to 220℃, the radio frequency power is 13kW, the cavity pressure is 1.9mbar, and the gas flow ratio of SiH4 and H2 is 1:4.5. Finally, an intrinsic hydrogenated amorphous silicon layer with a thickness of 12nm is formed on the surface of the thermally oxidized silicon layer away from the N-type silicon substrate. ③ Continuous deposition of silicon nitride layer: In the same cavity as ② without breaking the vacuum, the deposition temperature is 440℃, the gas ratio of silane and ammonia is SiH4:NH3=1:1.2, the radio frequency power is 14000W, the cavity pressure is 2.0mbar, and the final deposited silicon nitride layer has a film thickness of 25nm and a refractive index of 2.25. ④ Subsequent deposition of silicon oxynitride layer: N2O gas is introduced to regulate the oxygen content, N2 carrier gas is used, the deposition temperature is 440℃, and the final silicon oxynitride layer has a film thickness of 45nm and a refractive index of 1.65. S5. Hydrogen passivation annealing: Using a mixture of nitrogen (N2) and hydrogen, with hydrogen accounting for 12% of the gas volume, the mixture is kept at 235°C for 40 minutes to complete the annealing and form a BC battery.

[0105] The BC battery obtained by the above method was tested and found to have a stable open-circuit voltage of 752mV, low interfacial recombination, and excellent passivation stability.

[0106] In another specific embodiment, for the N-type silicon substrate in S1, an N-type single-crystal silicon wafer with a resistivity of 10 Ω·cm, a thickness of 135 μm, and an initial minority carrier lifetime of 1200 μs is selected; when preparing the tunneling oxide layer on the back side, it is oxidized in a pure oxygen environment at 540°C for 22 min to form a tunneling silicon oxide with a thickness of 2.5 nm.

[0107] When fabricating the composite passivation layer on the S4 front side, the final thickness of the thermally oxidized silicon layer is 3.5 nm, the thickness of the intrinsic hydrogenated amorphous silicon layer is 14 nm, the thickness of the silicon nitride layer is 28 nm, and the thickness of the silicon oxynitride layer is 42 nm. The remaining steps are the same as in the previous embodiment. The BC battery prepared in this way was tested and found to have an open-circuit voltage of 750 mV, uniform film stress, and good weather resistance.

[0108] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0109] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing a BC battery, characterized in that, include: Provides N-type silicon substrates; The N-type silicon substrate includes opposing front and back sides, the back side including a first region and a second region arranged in an interdigitated pattern; A first tunneling oxide layer and a first doped layer are formed in the first region on the back side, and a second tunneling oxide layer and a second doped layer are formed in the second region, respectively. A textured structure is formed on the front side of the N-type silicon substrate and in the spacer between the first region and the second region, and a composite passivation layer is formed on the side of the textured structure on the front side that faces away from the N-type silicon substrate; the composite passivation layer includes a thermally oxidized silicon layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer and a silicon oxynitride layer stacked sequentially. A first electrode is formed on the surface of the first region away from the N-type silicon substrate, in contact with the first doped layer; and a second electrode is formed on the surface of the second region away from the N-type silicon substrate, in contact with the second doped layer. The N-type silicon substrate on which the first electrode and the second electrode are formed is subjected to low-temperature annealing.

2. The preparation method according to claim 1, characterized in that, A first tunneling oxide layer and a first doped layer are formed in a first region on the back side, and a second tunneling oxide layer and a second doped layer are formed in the second region, respectively, including: Using a first deposition process, under first preset conditions, a tunneling oxide layer is formed on the back side; Using a second deposition process, under second preset conditions, an intrinsic silicon layer is formed on the surface of the tunneling oxide layer on the side facing away from the N-type silicon substrate; The intrinsic silicon layer is patterned to remove the tunneling oxide layer and the intrinsic silicon layer in the spacer region between the first region and the second region, so that the first tunneling oxide layer and the intrinsic silicon layer are formed in the first region, and the second tunneling oxide layer and the intrinsic silicon layer are formed in the second region. The intrinsic silicon layer formed in the first region and the intrinsic silicon layer formed in the second region are respectively doped with elements to form the first doped layer on the side of the first tunneling oxide layer facing away from the N-type silicon substrate, and the second doped layer on the side of the second tunneling oxide layer facing away from the N-type silicon substrate.

3. The preparation method according to claim 2, characterized in that, The first preset condition is to introduce oxygen into the reaction chamber of the first deposition process, with an oxidation time of 15-25 minutes and an oxidation temperature of 540℃-560℃; the second preset condition is to introduce silane gas with a flow rate of 1240 sccm / min-1550 sccm / min into the reaction chamber of the second deposition process, with a deposition temperature of 610℃-630℃, a pressure of 140 mTorr-160 mTorr, and a deposition time of 35-45 minutes.

4. The preparation method according to claim 1, characterized in that, A composite passivation layer is formed on the surface of the textured structure on the front side, away from the N-type silicon substrate, comprising: Using a first passivation process, under first passivation conditions, the thermally oxidized silicon layer is formed on the surface of the textured structure on the front side that is away from the N-type silicon substrate. Using a second passivation process, under second passivation conditions, the intrinsic hydrogenated amorphous silicon layer is formed on the surface of the thermally oxidized silicon layer on the side opposite to the N-type silicon substrate; Using a third passivation process, under third passivation conditions, the silicon nitride layer is formed on the side of the intrinsic hydrogenated amorphous silicon layer facing away from the N-type silicon substrate; Using a fourth passivation process, under fourth passivation conditions, the silicon oxynitride layer is formed on the side of the silicon nitride layer facing away from the N-type silicon substrate.

5. The preparation method according to claim 4, characterized in that, The first passivation condition involves introducing oxygen into the reaction chamber of the first passivation process, with a passivation temperature of 520℃-550℃ and a holding time of 10-20 minutes. The second passivation condition involves introducing a mixed gas of silane and hydrogen at a gas flow ratio of 1:4-1:5 into the reaction chamber of the second passivation process, with a passivation temperature of 210℃-230℃, a pressure of 1.7 mbar-2.1 mbar, and a radio frequency power of 13000W-16000W. The third passivation condition involves introducing a gas at a gas flow ratio of 1:1.0-1: The passivation temperature of the mixed gas formed by silane and ammonia is 400℃-500℃, the pressure is 1.8mbar-2.0mbar, and the radio frequency power is 14000W-16000W. The fourth passivation condition is to introduce a mixed gas formed by silane, ammonia, and nitrous oxide into the reaction chamber of the fourth passivation process. The flow rate of the silane is 1200sccm-1500sccm, the flow rate of the ammonia is 4000sccm-6000sccm, the flow rate of the nitrous oxide is 3000sccm-5000sccm, and the passivation temperature is 400℃-500℃.

6. The preparation method according to claim 1, characterized in that, Low-temperature annealing of the N-type silicon substrate forming the first and second electrodes includes: Under preset annealing conditions, the N-type silicon substrate forming the first electrode and the second electrode is subjected to low-temperature annealing; the preset annealing conditions are: introducing a mixture of nitrogen and hydrogen into the reaction chamber of the annealing process, wherein the hydrogen gas accounts for 10%-15%, the annealing temperature is 220℃-250℃, and the holding time is 35min-45min.

7. The preparation method according to claim 1, characterized in that, After forming a velvety structure in the gap between the first region and the second region, the process further includes: A composite dielectric insulating layer is formed on the back side.

8. A BC battery, characterized in that, Includes: an N-type silicon substrate, the N-type silicon substrate including opposing front and back sides, the back side including a first region and a second region arranged in an interdigitated pattern; The front side includes a textured structure and a composite passivation layer located on the surface of the textured structure facing away from the N-type silicon substrate; the composite passivation layer includes a thermally deposited silicon oxide layer, an intrinsic hydrogenated amorphous silicon layer, a silicon nitride layer, and a silicon oxynitride layer stacked sequentially; the first region includes a first tunneling oxide layer, a first doped layer, and a first electrode in contact with the first doped layer stacked sequentially; the second region includes a second tunneling oxide layer, a second doped layer, and a second electrode in contact with the second doped layer stacked sequentially; a textured structure is provided in the spacer region between the first region and the second region.

9. The BC battery according to claim 8, characterized in that, The resistivity of the N-type silicon substrate is 4 Ω·cm-16.0 Ω·cm, the thickness is 120 μm-135 μm, and the original minority carrier lifetime is ≥1000 μs; and / or, the thickness of the first doped layer or the second doped layer is 50 nm-60 nm, and the thickness of the first tunneling oxide layer is 1 nm-3 nm.

10. The BC battery according to claim 8, characterized in that, The thickness of the thermally oxidized silicon layer is 2nm-4nm; the thickness of the intrinsic hydrogenated amorphous silicon layer is 10nm-15nm; the thickness of the silicon nitride layer is 20nm-30nm and the refractive index is 2.15-2.30; the thickness of the silicon oxynitride layer is 40nm-50nm and the refractive index is 1.6-1.

8.

11. The BC battery according to claim 8, characterized in that, The total thickness of the silicon nitride layer and the silicon oxynitride layer is 70nm-82nm.

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