A solar cell, a photovoltaic module and a method of manufacture

Abstract

This application provides a solar cell, a photovoltaic module, and a fabrication method, relating to the field of photovoltaic technology. The solar cell includes a P-type doped layer and an N-type doped layer, with a gap region formed between the P-type and N-type doped layers. At least a portion of the gap region contains a negative temperature coefficient thermistor layer, which forms ohmic contacts with both the P-type and N-type doped layers. This application can improve the cell's resistance to hot spots, ensuring its lifespan and safety.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a solar cell block, a photovoltaic module, and a method for its fabrication. Background Technology

[0002] Solar cells work on the principle of the photoelectric effect, absorbing photons from sunlight to generate electron-hole pairs, which in turn create an electric current. In practical applications, solar cells are usually in the form of modules, composed of multiple cells connected in series or parallel. When some cells are shaded, have defects, or have inconsistent performance, hot spot effects can easily occur. Hot spot effects refer to the phenomenon where some cells in a solar cell module become a load due to various reasons (such as shading, aging, manufacturing defects, etc.), consuming the energy generated by other normally functioning cells, causing the temperature of those cells to rise abnormally and forming localized hot spots. Hot spot effects can reduce the actual lifespan of solar cells and may also cause fires and other safety accidents, posing a serious threat to personnel and equipment. Summary of the Invention

[0003] In view of this, the purpose of this application is to overcome the shortcomings of the prior art and provide a solar cell, photovoltaic module and preparation method that can improve the cell's resistance to hot spots and ensure the cell's service life and safety.

[0004] This application provides the following technical solution:

[0005] In a first aspect, embodiments of this application provide a solar cell, the solar cell comprising:

[0006] A P-type doped layer and an N-type doped layer are provided, with a GAP region formed between the P-type doped layer and the N-type doped layer; wherein, at least a portion of the GAP region is provided with a negative temperature coefficient thermistor layer, and the negative temperature coefficient thermistor layer forms an ohmic contact with the P-type doped layer and the N-type doped layer respectively.

[0007] In some embodiments of the first aspect, the GAP region is formed with a slot, and the negative temperature coefficient thermistor layer is disposed within the slot.

[0008] In some embodiments of the first aspect, the P-type doped layer and the N-type doped layer are alternately arranged in the lateral or longitudinal direction of the solar cell, and the GAP region is formed between adjacent P-type doped layers and N-type doped layers.

[0009] In some embodiments of the first aspect, the P-type doped layer has a P-region main gate, the N-type doped layer has an N-region fine gate, the negative temperature coefficient thermistor layer is located between the P-region main gate and the N-region fine gate, and the P-region main gate, the N-region fine gate and the negative temperature coefficient thermistor layer form an ohmic contact.

[0010] In some embodiments of the first aspect, the P-type doped layer has a P-region fine gate, the N-type doped layer has an N-region fine gate, the negative temperature coefficient thermistor layer is located between the P-region fine gate and the N-region fine gate, and the P-region fine gate, the N-region fine gate and the negative temperature coefficient thermistor layer form an ohmic contact.

[0011] In some embodiments of the first aspect, the P-type doped layer has a P-region main gate and a P-region fine gate, the N-type doped layer has an N-region fine gate, the negative temperature coefficient thermistor layer is located between the P-region main gate, the P-region fine gate and the N-region fine gate, and the P-region main gate, the P-region fine gate and the N-region fine gate and the negative temperature coefficient thermistor layer form an ohmic contact.

[0012] In some embodiments of the first aspect, the P-type doped layer and the N-type doped layer are sequentially disposed in the thickness direction of the solar cell, and the GAP region is formed between the P-type doped layer and the N-type doped layer.

[0013] Secondly, embodiments of this application also provide a photovoltaic module, which includes a solar cell as described in any of the above embodiments.

[0014] Thirdly, embodiments of this application also provide a method for preparing a solar cell, the method comprising:

[0015] A P-type doped layer and an N-type doped layer are fabricated on a silicon substrate, and a GAP region is formed between the P-type doped layer and the N-type doped layer.

[0016] A negative temperature coefficient thermistor layer is fabricated in the GAP region, and the negative temperature coefficient thermistor layer forms ohmic contacts with the P-type doped layer and the N-type doped layer, respectively.

[0017] In some embodiments of the third aspect, a negative temperature coefficient thermistor layer is fabricated in the GAP region, and the negative temperature coefficient thermistor layer forms ohmic contacts with the P-type doped layer and the N-type doped layer, respectively, including:

[0018] The negative temperature coefficient thermistor layer is covered by screen printing or thin film deposition technology, and high-temperature process compatibility optimization is used to ensure that the negative temperature coefficient thermistor layer forms an ohmic contact with the P-type doped layer and the N-type doped layer.

[0019] The embodiments of this application have the following advantages:

[0020] This application provides a solar cell that dynamically suppresses hot spot effects by incorporating a negative temperature coefficient thermistor layer (NTC layer) in the gap region between a P-type doped layer and an N-type doped layer. Under normal operation: When no hot spot occurs, the NTC layer is at room temperature with a high resistance, having minimal impact on current transport and minimal influence on photovoltaic conversion efficiency. The P-type and N-type layers form an ohmic contact through the NTC layer in the gap region, maintaining normal carrier separation and current output. When a hot spot occurs: When a local cell becomes a load and generates heat due to shading or defects, heat is transferred to the NTC layer in the gap region, and its resistance decreases significantly with increasing temperature (negative temperature coefficient characteristic). This decrease in NTC layer resistance provides a low-resistance bypass path for carriers in the hot spot region, allowing some current to bypass the failure area, reducing energy consumption in that area as a load, and thus suppressing further temperature increases. The ohmic contact design ensures minimal contact loss during current shunting, avoiding the introduction of additional voltage drops. Temperature balance: After the hot spot is eliminated or the temperature decreases, the NTC layer resistance automatically returns to a high resistance state, and the battery returns to normal operation, achieving adaptive regulation.

[0021] Therefore, by dynamically adjusting the local current path through the temperature-resistance characteristics of the NTC layer, heat accumulation in the hot spot region can be effectively dispersed, preventing local temperature runaway and improving the cell's resistance to hot spots. This reduces the risk of cell aging and burnout caused by hot spots, extending the module's lifespan; it also reduces the probability of safety accidents such as fires, ensuring the safety of personnel and equipment. The NTC layer is integrated into the GAP region of the existing PN junction, requiring no additional electrodes or complex processes, making it compatible with conventional solar cell fabrication processes and easy to scale up. During normal operation, the high resistance state of the NTC layer has minimal impact on efficiency; it responds quickly during hot spots, avoiding the voltage loss and delay problems caused by traditional bypass diodes. Furthermore, compared to external bypass diode solutions, this design simplifies the module structure and reduces material and packaging costs.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This illustration shows a schematic diagram of the structure of a solar cell according to an embodiment of this application from one perspective;

[0025] Figure 2 This invention provides a schematic diagram of the structure of a solar cell from one perspective, according to another embodiment of the present application.

[0026] Figure 3 This illustration shows a schematic diagram of the assembly structure of a P-region main gate, an N-region fine gate, and a negative temperature coefficient thermistor layer according to an embodiment of this application.

[0027] Figure 4 This illustration shows a schematic diagram of the assembly structure of a P-region fine gate, an N-region fine gate, and a negative temperature coefficient thermistor layer according to an embodiment of this application.

[0028] Figure 5 This illustration shows a schematic diagram of the assembly structure of a P-region main gate, a P-region fine gate, an N-region fine gate, and a negative temperature coefficient thermistor layer according to an embodiment of this application.

[0029] Explanation of key component symbols:

[0030] 10 - Solar cell; 100 - N-type doped layer; 110 - N-region fine grid; 200 - P-type doped layer; 210 - P-region main grid; 220 - P-region fine grid; 300 - Negative temperature coefficient thermistor layer. Detailed Implementation

[0031] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0032] It should be noted that when an element is said to be "fixed" to another element, it can be directly on the other element or there may be an intervening element. When an element is said to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is said to be "directly" on another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0033] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the template description is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] In related technologies, solar cells operate on the principle of the photoelectric effect, absorbing photons from sunlight to generate electron-hole pairs, which in turn form an electric current. In practical applications, solar cells typically exist in the form of modules, composed of multiple cells connected in series or parallel. When some cells are shaded, have defects, or exhibit inconsistent performance, a hot spot effect can easily occur. The hot spot effect refers to the phenomenon where some cells in a solar cell module become a load due to various reasons (such as shading, aging, manufacturing defects, etc.), consuming the energy generated by other normally functioning cells, causing an abnormal rise in temperature in those cells and forming localized hot spots. The hot spot effect can reduce the actual lifespan of solar cells and may also cause fires and other safety accidents, posing a serious threat to personnel and equipment.

[0037] like Figure 1 and Figure 2 As shown, in order to solve the above-mentioned technical problems, this application provides a solar cell 10. The solar cell 10 includes a P-type doped layer 200 and an N-type doped layer 100, and a GAP region is formed between the P-type doped layer 200 and the N-type doped layer 100. The GAP region is at least partially provided with a negative temperature coefficient thermistor layer 300, and the negative temperature coefficient thermistor layer 300 forms ohmic contacts with the P-type doped layer 200 and the N-type doped layer 100 respectively.

[0038] In these embodiments, the solar cell 10 has a P-type silicon substrate, and a P-type doped layer 200 is formed on the upper surface of the P-type silicon substrate by a diffusion process. An N-type doped layer 100 is disposed on the P-type doped layer 200, and together with the P-type doped layer 200, they form a PN junction structure; or, the N-type doped layer 100 and the P-type doped layer 200 are disposed in the same layer.

[0039] The GAP region, which is the spatial region between the P-type doped layer 200 and the N-type doped layer 100, is the main region for the generation of electron-hole pairs. At least a portion of the GAP region is provided with a negative temperature coefficient thermistor layer 300, which is composed of a semiconductor material with negative temperature coefficient characteristics, such as nickel manganese oxide (MnNiO) or copper cobalt oxide (CuCo2O4).

[0040] The negative temperature coefficient thermistor layer 300 forms ohmic contacts with the P-type doped layer 200 and the N-type doped layer 100, respectively, to ensure that current can pass through the thermistor layer with low loss.

[0041] Under normal illumination, solar cell 10 absorbs photons and generates electron-hole pairs, which generate current output under the influence of the PN junction electric field. At this time, the NTC thermistor layer is in normal working condition, its resistance value is stable, and it does not affect the current output.

[0042] When a portion of the battery cells enters a reverse bias state due to shielding, aging, or defects, this area may become a load, causing localized overheating (hot spot effect). In this situation, the temperature of the negative temperature coefficient thermistor layer 300 rises, and its resistance drops rapidly. Due to the decrease in resistance, the voltage drop in this area decreases, thereby reducing the energy consumed by this portion of the battery cells, suppressing localized overheating, and preventing the hot spot effect.

[0043] To facilitate understanding, the production method is provided below:

[0044] Substrate material: P-type monocrystalline silicon or polycrystalline silicon is used as the substrate.

[0045] Doping process: P-type and N-type doped layers 100 are formed on the substrate surface by high-temperature diffusion process.

[0046] GAP region construction: A GAP region with a certain width is formed by controlling the doping concentration and diffusion depth.

[0047] Fabrication of NTC thermistor layer:

[0048] The NTC material is deposited in the GAP area using a printing method; after high-temperature annealing, it forms a uniform and dense film.

[0049] Ohmic contact is achieved by introducing a low work function metal (such as Al or Ag) or a conductive oxide (such as ITO or AZO) between the negative temperature coefficient thermistor layer 300 and the P-type / N-type layer to reduce contact resistance; electrode connection is completed through photolithography and metallization processes.

[0050] For example, the negative temperature coefficient thermistor layer 300 may only cover a portion of the GAP area, such as areas near the battery edge or prone to shading; the negative temperature coefficient thermistor layer 300 may be made of flexible material to adapt to the application of flexible solar cell 10. Optionally, a temperature sensor may be integrated into the negative temperature coefficient thermistor layer 300 for real-time monitoring of battery temperature changes to achieve intelligent protection.

[0051] In other words, the solar cell 10 utilizes the temperature-sensitive characteristics of a negative temperature coefficient thermistor layer 300 (i.e., an NTC layer) in the GAP region between the P-type doped layer 200 and the N-type doped layer 100 to dynamically suppress hot spot effects. During normal operation: When no hot spot occurs, the NTC layer is at room temperature, with a high resistance, having minimal impact on current transport and minimal influence on photovoltaic conversion efficiency. The P-type and N-type layers form an ohmic contact through the NTC layer in the GAP region, maintaining normal carrier separation and current output. When a hot spot occurs: When a local cell becomes a load and generates heat due to shading or defects, heat is transferred to the NTC layer in the GAP region, and its resistance decreases significantly with increasing temperature (negative temperature coefficient characteristic). This decrease in NTC layer resistance provides a low-resistance bypass path for carriers in the hot spot region, allowing some current to bypass the failure area, reducing the energy consumed by this area as a load, and thus suppressing further temperature increases. The ohmic contact design ensures minimal contact loss during current shunting, avoiding the introduction of additional voltage drops. Temperature balance: After the hot spot is eliminated or the temperature decreases, the NTC layer resistance automatically returns to a high resistance state, and the battery returns to normal operation, achieving adaptive regulation.

[0052] Therefore, by dynamically adjusting the local current path through the temperature-resistance characteristics of the NTC layer, heat accumulation in the hot spot region can be effectively dispersed, preventing local temperature runaway and improving the cell's resistance to hot spots. This reduces the risk of cell aging and burnout caused by hot spots, extending the module's lifespan; it also reduces the probability of safety accidents such as fires, ensuring the safety of personnel and equipment. The NTC layer is integrated into the GAP region of the existing PN junction, requiring no additional electrodes or complex processes, and is compatible with conventional solar cell fabrication processes, facilitating large-scale application. During normal operation, the high resistance state of the NTC layer has minimal impact on efficiency; it responds quickly during hot spots, avoiding the voltage loss and delay problems caused by traditional bypass diodes. Furthermore, compared to external bypass diode solutions, this design simplifies the module structure and reduces material and packaging costs.

[0053] In some embodiments, the GAP region is formed with a groove, and the negative temperature coefficient thermistor layer 300 is disposed within the groove.

[0054] In these embodiments, the present invention also provides an improved solar cell 10 structure, wherein a grooved structure is further provided in the GAP region for embedding a negative temperature coefficient (NTC) thermistor layer to enhance its integration and stability with the PN junction structure.

[0055] In other words, one or more grooved structures are formed in the GAP area using laser etching or dry etching processes. For example, the number of grooves can be 1, 2, 3, 4, or 5, etc.

[0056] The NTC thermistor layer is embedded inside the slot through deposition and filling processes, forming good contact with the sidewalls and bottom of the slot; the two ends of the NTC thermistor layer form ohmic contacts with the P-type doped layer 200 and the N-type doped layer 100, respectively, forming a current path.

[0057] For example, the shape of the groove can be rectangular, V-shaped, U-shaped, etc., and its width and depth can be optimized according to the battery structure and NTC material properties. For example, the groove width can be controlled within the range of 1-10 μm, and the depth can be controlled within the range of 0.5-3 μm.

[0058] Clearly, embedding the NTC material within the groove prevents it from detaching or migrating during subsequent processes. Furthermore, etching to create a regular interface facilitates a more uniform ohmic contact between the NTC material and the P / N type layer. Simultaneously, the grooved structure concentrates the thermal response area, increasing sensitivity to localized temperature changes and thus more effectively suppressing hot spot effects.

[0059] For example, after the P-type doped layer 200 and the N-type doped layer 100 are fabricated, a trench structure is formed in the GAP region using photolithography and dry etching processes. NTC material (such as MnNiO, CuCo2O4, Fe3O4, etc.) is then filled into the trench using sputtering, electron beam evaporation, or chemical vapor deposition (CVD). Alternatively, screen printing technology can be used to uniformly coat Ta3N5 material in part or all of the GAP region between the P-region and the N-region, ensuring sufficient contact between the NTC material and the P / N region, laying the foundation for forming a low-resistance ohmic contact.

[0060] This embodiment introduces a slotted structure in the GAP region and embeds an NTC thermistor layer therein, allowing the thermistor to be tightly integrated with the PN junction structure, thereby improving the structural stability and thermal response capability of the battery. When a hot spot effect occurs, the NTC layer responds rapidly to temperature changes, reducing local resistance, thus effectively dispersing energy, preventing local overheating, and significantly improving the hot spot resistance and operational safety of the solar cell 10.

[0061] like Figure 2 As shown, in some embodiments, P-type doped layers 200 and N-type doped layers 100 are alternately arranged in the horizontal or vertical direction of the solar cell 10, and a GAP region is formed between adjacent P-type doped layers 200 and N-type doped layers 100.

[0062] In these embodiments, the present invention also provides a structurally optimized solar cell 10, wherein a P-type doped layer 200 and an N-type doped layer 100 are alternately arranged in the lateral or longitudinal direction, and multiple GAP regions are formed between adjacent P-type and N-type layers, thereby constructing multiple PN junction units with hot spot suppression function.

[0063] The solar cell 10 has the following structural features:

[0064] A high-purity P-type or N-type silicon substrate is used; on the substrate, alternating P-type doped regions and N-type doped regions are formed through photolithography and doping processes; the P-type doped regions and N-type doped regions are alternately arranged in the lateral or longitudinal direction; a GAP region is formed between each pair of adjacent P-type doped regions and N-type doped regions as the generation region of electron-hole pairs.

[0065] In each GAP region, a negative temperature coefficient thermistor layer 300 is provided to reduce local resistance and suppress energy concentration when hot spots occur; the NTC thermistor layer forms ohmic contacts with the adjacent P-type and N-type doped regions, respectively, to form a current path.

[0066] P-type and N-type doped regions are defined on the substrate by photolithography; alternating P-type and N-type doped regions are formed by ion implantation or diffusion processes; microgroove structures are formed in the GAP region between adjacent P / N type regions by etching; NTC materials (such as MnNiO, CuCo2O4, etc.) are deposited in the microgroove using sputtering or CVD processes to form NTC thermistor layers; the NTC materials are annealed to improve their electrical properties; conductive adhesion layers (such as ITO, TiN, etc.) are introduced to reduce contact resistance and achieve ohmic contact; finally, the metallization process of the front and back electrodes is completed to complete the fabrication of solar cell 10.

[0067] like Figure 3 As shown, in some embodiments, the P-type doped layer 200 has a P-region main gate 210, the N-type doped layer 100 has an N-region fine gate 110, a negative temperature coefficient thermistor layer 300 is provided between the P-region main gate 210 and the N-region fine gate 110, and the P-region main gate 210, the N-region fine gate 110 and the negative temperature coefficient thermistor layer 300 form an ohmic contact.

[0068] In these embodiments, the present invention also provides an improved solar cell 10 structure, wherein the P-type doped layer 200 is provided with a P-region main grid 210, the N-type doped layer 100 is provided with an N-region fine grid 110, and a negative temperature coefficient (NTC) thermistor layer is disposed between the P-region main grid 210 and the N-region fine grid 110 to optimize the current collection path while improving the resistance to hot spots.

[0069] The upper surface of the P-type doped layer 200 has several parallel P-region main gates 210; the lower surface of the N-type doped layer 100 has several N-region fine gates 110 arranged alternately with the P-region main gates 210; a negative temperature coefficient (NTC) thermistor layer is disposed between adjacent P-region main gates 210 and N-region fine gates 110. The NTC thermistor layer forms a good ohmic contact with the P-region main gates 210 and the N-region fine gates 110, thereby forming a current path.

[0070] The P-region main gate 210 is typically wider to reduce series resistance and improve current collection efficiency; the N-region fine gate 110 is narrower but more numerous, covering a large area, which is beneficial for the effective collection of photogenerated carriers; the NTC thermistor layer is disposed in the gap between the P-region main gate 210 and the N-region fine gate 110 to ensure a rapid response in case of local overheating, reduce the resistance value, and prevent concentrated energy consumption.

[0071] For example, a P-type doped layer 200 and an N-type doped layer 100 are formed on a substrate by diffusion or ion implantation; the positions of the P-region main gate 210 and the N-region fine gate 110 are defined using photolithography; a microgroove is formed between the P-region main gate 210 and the N-region fine gate 110 using laser etching or dry etching; NTC material is filled into the microgroove using methods such as sputtering or chemical vapor deposition (CVD) to form an NTC thermistor layer; the NTC material is annealed to improve its crystallinity and conductivity; a low work function metal or conductive oxide (such as TiN, ITO) is introduced as an adhesion layer to reduce contact resistance and ensure good ohmic contact between the P-region main gate 210, the N-region fine gate 110 and the NTC layer; and the metallization process of the front and back electrodes is completed.

[0072] Therefore, the P-region main gate 210 reduces resistance loss in the current transmission path, and the N-region fine gate 110 increases the collection efficiency of photogenerated carriers; the NTC thermistor layer can quickly respond to local temperature changes, reduce the resistance value of hot spot areas, effectively disperse energy, and prevent local overheating.

[0073] like Figure 4As shown, in some embodiments, the P-type doped layer 200 has a P-region fine gate 220, the N-type doped layer 100 has an N-region fine gate 110, a negative temperature coefficient thermistor layer 300 is present between the P-region fine gate 220 and the N-region fine gate 110, and the P-region fine gate 220, the N-region fine gate 110 and the negative temperature coefficient thermistor layer 300 form an ohmic contact.

[0074] In these embodiments, the present invention further provides a solar cell 10 structure, wherein a P-type doped layer 200 is provided with a plurality of P-region fine grids 220. An N-type doped layer 100 is provided with a plurality of N-region fine grids 110 corresponding to the P-region fine grids 220. A negative temperature coefficient (NTC) thermistor layer is disposed between adjacent P-region fine grids 220 and N-region fine grids 110. An ohmic contact is formed between the NTC thermistor layer and the P-region fine grids 220 and N-region fine grids 110.

[0075] The substrate is a P-type or N-type silicon substrate. A P-type doped layer 200 is formed on the substrate, and its upper surface has multiple P-region fine gates 220 arranged in parallel or staggered patterns. An N-type doped layer 100 is formed in the same layer as the P-type doped layer 200, and its surface has multiple N-region fine gates 110 corresponding to the P-region fine gates 220. An NTC thermistor layer is disposed in the gap formed between the P-region fine gates 220 and the N-region fine gates 110. The NTC thermistor layer forms ohmic contacts with both the P-region fine gates 220 and the N-region fine gates 110, forming a current transmission path.

[0076] P-region fine grid 220 and N-region fine grid 110: The fine grid can effectively improve carrier collection efficiency, reduce resistance in the current transport path, and at the same time reduce the light-shielding area, thereby improving photoelectric conversion efficiency. When a local hot spot effect occurs in the battery, the temperature in that area rises, and the resistance of the NTC material drops rapidly, thereby reducing the voltage drop in that area, suppressing energy concentration, and preventing local overheating.

[0077] Therefore, in this embodiment, fine gates are respectively set in the P-type doped layer 200 and the N-type doped layer 100, and an NTC thermistor layer is embedded between the fine gates. The fine gate structure increases the effective collection area of ​​photogenerated carriers and reduces the series resistance. The NTC thermistor layer can respond quickly when there is local overheating, prevent energy concentration, and significantly improve the safety and service life of the battery.

[0078] For example, the arrangement of the fine gate 220 in the P region and the fine gate 110 in the N region can be linear, staggered, or ring-shaped; the NTC thermistor layer can be a continuous thin film or a segmented structure.

[0079] like Figure 5As shown, in some embodiments, the P-type doped layer 200 has a P-region main gate 210 and a P-region fine gate 220, the N-type doped layer 100 has an N-region fine gate 110, a negative temperature coefficient thermistor layer 300 is provided between the P-region main gate 210, the P-region fine gate 220 and the N-region fine gate 110, and the P-region main gate 210, the P-region fine gate 220, the N-region fine gate 110 and the negative temperature coefficient thermistor layer 300 form an ohmic contact.

[0080] In these embodiments, the present invention further provides a solar cell 10 structure, wherein the P-type doped layer 200 is provided with a P-region main grid 210 and a P-region fine grid 220; the N-type doped layer 100 is provided with an N-region fine grid 110; a negative temperature coefficient (NTC) thermistor layer is disposed in the gap between the P-region main grid 210, the P-region fine grid 220 and the N-region fine grid 110; the NTC thermistor layer forms an ohmic contact with the P-region main grid 210, the P-region fine grid 220 and the N-region fine grid 110, forming a current path.

[0081] For example, the substrate of the solar cell 10 is a P-type or N-type silicon substrate; a P-type doped layer 200 is formed on the substrate, and its upper surface is provided with: multiple P-region main grids 210, which are used to reduce series resistance and improve current collection efficiency; and multiple P-region fine grids 220, which are distributed between the main grids to increase the carrier collection area.

[0082] The N-type doped layer 100 has multiple N-region fine gates 110, corresponding to the P-region fine gates 220; the NTC thermistor layer is disposed in the gap between the P-region main gate 210, the P-region fine gate 220 and the N-region fine gate 110; the NTC thermistor layer forms ohmic contacts with the P-region main gate 210, the P-region fine gate 220 and the N-region fine gate 110 respectively, forming a current transmission path.

[0083] In this embodiment, a main gate + fine gate structure is set in the P-type doped layer 200, a fine gate is set in the N-type doped layer 100, and an NTC thermistor layer is embedded between these electrodes. The main gate reduces the resistance, and the fine gate improves the carrier collection efficiency. The NTC thermistor layer responds quickly in the event of local overheating, preventing energy concentration and improving safety.

[0084] For example, the arrangement of the P-region main gate 210 and the fine gate can be linear, staggered, or ring-shaped; the NTC thermistor layer can be a continuous thin film or a segmented structure.

[0085] like Figure 2 As shown, in some embodiments, the P-type doped layer 200 and the N-type doped layer 100 are sequentially disposed in the thickness direction of the solar cell 10, and the GAP region is formed between the P-type doped layer 200 and the N-type doped layer 100.

[0086] In these embodiments, the present invention further provides a solar cell 10 structure, wherein a P-type doped layer 200 and an N-type doped layer 100 are sequentially disposed in the thickness direction of the solar cell 10; a GAP region is formed between the P-type doped layer 200 and the N-type doped layer 100 for generating electron-hole pairs and serving as the main channel for photogenerated carriers.

[0087] The substrate of the solar cell 10 is made of high-purity silicon substrate material; the P-type doped layer 200 is formed on the substrate by diffusion or ion implantation process; the N-type doped layer 100 is formed on the P-type doped layer 200 and forms a PN junction with the P-type doped layer 200; the GAP region is located between the P-type doped layer 200 and the N-type doped layer 100 and is the main generation region of photogenerated electron-hole pairs;

[0088] A negative temperature coefficient (NTC) thermistor layer is provided in at least a portion of the GAP region, and forms an ohmic contact with the P-type doped layer 200 and the N-type doped layer 100; the P-type doped layer 200, the N-type doped layer 100 and the NTC thermistor layer work together to form a complete solar cell 10 unit.

[0089] The P-type doped layer 200 is typically composed of silicon material doped with elements such as boron, and has a high hole concentration; the N-type doped layer 100 is typically composed of silicon material doped with elements such as phosphorus or arsenic, and has a high electron concentration; the electric field formed at the PN junction in the GAP region helps to separate photogenerated electron-hole pairs and promotes the migration of charge carriers to the corresponding electrodes; when overheating occurs in a local area, the resistance of the NTC material decreases with increasing temperature, reducing energy consumption in that area, preventing the formation of local hot spots, and improving the safety and lifespan of the battery.

[0090] Brief description of preparation method:

[0091] Substrate preparation: Select high-purity silicon wafers as the substrate material and perform necessary cleaning and pretreatment;

[0092] Preparation of P-type doped layer 200: A P-type doped layer 200 is formed on the substrate by diffusion or ion implantation process.

[0093] Preparation of N-type doped layer 100: An N-type doped layer 100 is formed on top of the P-type doped layer 200 through the same or different doping processes to form a PN junction.

[0094] GAP area and NTC layer settings:

[0095] Microgrooves are formed in the GAP region between the P-type and N-type doped layers 100 using laser etching or dry etching processes.

[0096] NTC material is filled into microgrooves using sputtering or chemical vapor deposition (CVD) methods to form an NTC thermistor layer.

[0097] Annealing treatment: Annealing is performed on NTC materials to improve their crystallinity and conductivity.

[0098] Electrode metallization: Complete the metallization process for the front and back electrodes to ensure good current collection efficiency.

[0099] In this embodiment, a P-type doped layer 200 and an N-type doped layer 100 are sequentially disposed in the thickness direction of the solar cell 10, and an NTC thermistor layer is introduced between them. The PN junction structure can effectively separate photogenerated carriers and improve photoelectric conversion efficiency; the NTC thermistor layer can respond quickly when local overheating occurs, prevent energy concentration, and extend the battery life.

[0100] For example, the thickness of the P-type and N-type doped layers 100 can be adjusted according to specific application requirements; the NTC thermistor layer can be a continuous thin film or a segmented structure.

[0101] In some embodiments, this application also provides a photovoltaic module, which includes a solar cell 10.

[0102] In these embodiments, the number of solar cells 10 is at least one. For example, the number of solar cells 10 may be 1, 2, 3, 4, 5, 6, 7, 8, or 9, etc.

[0103] Since the solar cell 10 has the aforementioned technical effects, the photovoltaic module including the solar cell 10 should have the same technical effects, which will not be elaborated here.

[0104] In some embodiments, this application also provides a method for preparing a solar cell 10, the method comprising the following steps:

[0105] Step S100: A P-type doped layer 200 and an N-type doped layer 100 are fabricated on a silicon substrate, and a GAP region is formed between the P-type doped layer 200 and the N-type doped layer 100.

[0106] In this step, the silicon substrate is prepared: a high-purity monocrystalline or polycrystalline silicon wafer is selected as the substrate material (e.g., a P-type or N-type silicon substrate) and cleaned to remove surface contaminants.

[0107] Forming a P-type doped layer 200: Through diffusion processes or ion implantation techniques, P-type dopants such as boron and gallium are introduced on one side of the silicon substrate to form a P-type doped layer 200.

[0108] Forming the N-type doped layer 100: On top of or to one side of the P-type doped layer 200, N-type dopants such as phosphorus and arsenic are introduced through a similar diffusion or ion implantation process to form the N-type doped layer 100. The interface between the P-type and N-type doped layers 100 is the GAP region, which is the main region for the generation of photogenerated electron-hole pairs.

[0109] Step S200: A negative temperature coefficient thermistor layer 300 is fabricated in the GAP region, and the negative temperature coefficient thermistor layer 300 forms ohmic contacts with the P-type doped layer 200 and the N-type doped layer 100, respectively.

[0110] In this step, the trench preparation involves using laser etching or dry etching techniques to create microgroove structures at appropriate locations in the GAP area for subsequent deposition of the NTC thermistor layer.

[0111] NTC material deposition: Semiconductor materials with negative temperature coefficient characteristics (such as nickel manganese oxide MnNiO, copper cobalt oxide CuCo2O4, etc.) are filled into the above-mentioned micro-grooves using sputtering, chemical vapor deposition (CVD) or other suitable thin film deposition techniques to form an NTC thermistor layer.

[0112] Annealing treatment: The deposited NTC material is subjected to high-temperature annealing treatment to improve its crystallinity and electrical properties, ensuring that it can effectively respond to temperature changes and reduce the resistance value.

[0113] To form ohmic contacts, a low work function metal or conductive oxide (such as TiN, ITO, etc.) is introduced between the NTC thermistor layer and the P-type doped layer 200 and N-type doped layer 100 to reduce contact resistance and ensure good ohmic contact.

[0114] Electrode metallization is completed: Finally, metal electrodes are added to the front and back sides of the solar cell 10 to complete the fabrication of the entire device.

[0115] Obviously, the solar cell 10 prepared through the above steps not only has the basic functions of a traditional solar cell 10, but also effectively suppresses the hot spot effect and improves the safety and lifespan of the cell.

[0116] In some embodiments, a negative temperature coefficient thermistor layer 300 is fabricated in the GAP region, and the negative temperature coefficient thermistor layer 300 forms ohmic contacts with the P-type doped layer 200 and the N-type doped layer 100, respectively, including:

[0117] The negative temperature coefficient thermistor layer 300 is covered by screen printing or thin film deposition technology, and high-temperature process compatibility optimization (such as Ta3N5 / ALD passivation layer) is used to ensure that the negative temperature coefficient thermistor layer 300 forms an ohmic contact with the P-type doped layer 200 and the N-type doped layer 100.

[0118] In this step, a suitable NTC material (such as MnNiO, CuCo2O4, etc.) is selected based on the required temperature response characteristics and process compatibility.

[0119] Among them, the screen printing method involves: preparing a paste containing NTC material powder and an organic carrier; using screen printing equipment to precisely coat the paste into the micro-grooves of the GAP area; and performing preliminary drying treatment to remove organic solvents.

[0120] Thin film deposition method: Using physical vapor deposition (PVD), chemical vapor deposition (CVD) or other thin film deposition techniques (such as atomic layer deposition ALD), NTC material is uniformly deposited into the microgrooves of the GAP area.

[0121] Optimization for high-temperature processes

[0122] Passivation layer application: A high-temperature-resistant passivation layer, such as Ta3N5 (tantalum pentanitride), is applied to the NTC thermistor layer to protect the NTC layer and improve its high-temperature stability.

[0123] Alternatively, atomic layer deposition (ALD) technology can be used to deposit an ultrathin and uniform passivation layer to ensure optimal interface quality and electrical performance.

[0124] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0125] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes: A P-type doped layer and an N-type doped layer are provided, with a GAP region formed between the P-type doped layer and the N-type doped layer; wherein, at least a portion of the GAP region is provided with a negative temperature coefficient thermistor layer, and the negative temperature coefficient thermistor layer forms an ohmic contact with the P-type doped layer and the N-type doped layer respectively.

2. The solar cell according to claim 1, characterized in that, The GAP area has a groove, and the negative temperature coefficient thermistor layer is disposed in the groove.

3. The solar cell according to claim 2, characterized in that, In the horizontal or vertical direction of the solar cell, the P-type doped layer and the N-type doped layer are alternately arranged, and the GAP region is formed between adjacent P-type doped layers and N-type doped layers.

4. The solar cell according to claim 3, characterized in that, The P-type doped layer has a P-region main gate, the N-type doped layer has an N-region fine gate, and the negative temperature coefficient thermistor layer is located between the P-region main gate and the N-region fine gate. The P-region main gate, the N-region fine gate and the negative temperature coefficient thermistor layer form an ohmic contact.

5. The solar cell according to claim 3, characterized in that, The P-type doped layer has a P-region fine gate, the N-type doped layer has an N-region fine gate, and the negative temperature coefficient thermistor layer is located between the P-region fine gate and the N-region fine gate. The P-region fine gate, the N-region fine gate, and the negative temperature coefficient thermistor layer form an ohmic contact.

6. The solar cell according to claim 3, characterized in that, The P-type doped layer has a P-region main gate and a P-region fine gate, the N-type doped layer has an N-region fine gate, and the negative temperature coefficient thermistor layer is located between the P-region main gate, the P-region fine gate and the N-region fine gate. The P-region main gate, the P-region fine gate, the N-region fine gate and the negative temperature coefficient thermistor layer form an ohmic contact.

7. The solar cell according to any one of claims 1 to 6, characterized in that, In the thickness direction of the solar cell, the P-type doped layer and the N-type doped layer are arranged sequentially, and the GAP region is formed between the P-type doped layer and the N-type doped layer.

8. A photovoltaic module, characterized in that, The photovoltaic module includes a solar cell as described in any one of claims 1 to 7.

9. A method for preparing a solar cell, characterized in that, The preparation method includes: A P-type doped layer and an N-type doped layer are fabricated on a silicon substrate, and a GAP region is formed between the P-type doped layer and the N-type doped layer. A negative temperature coefficient thermistor layer is fabricated in the GAP region, and the negative temperature coefficient thermistor layer forms ohmic contacts with the P-type doped layer and the N-type doped layer, respectively.

10. The method for preparing a solar cell according to claim 9, characterized in that, Fabricating a negative temperature coefficient thermistor layer in the GAP region and forming ohmic contacts between the negative temperature coefficient thermistor layer and the P-type doped layer and the N-type doped layer, respectively, includes: The negative temperature coefficient thermistor layer is covered by screen printing or thin film deposition technology, and high-temperature process compatibility optimization is used to ensure that the negative temperature coefficient thermistor layer forms an ohmic contact with the P-type doped layer and the N-type doped layer.

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