Solar cell and preparation method thereof, solar cell and electrical device

Abstract

The application provides a solar cell piece, a preparation method thereof, a solar cell and an electrical equipment, and relates to the technical field of solar energy. The solar cell piece is provided with a microstructure surface for light trapping; the microstructure surface is a rough surface composed of a plurality of single-pyramid structures; and the single-pyramid structure is provided with a nano-cone-shaped recess. The solar cell piece effectively reduces reflectivity, improves photon trapping efficiency and carrier transport path length, and improves the deposition uniformity of an anti-reflection layer, so that the photoelectric conversion efficiency and overall performance of the solar cell are significantly improved.

Description

Technical Field

[0001] This invention relates to the field of solar energy technology, and more specifically, to a solar cell and its preparation method, a solar cell, and electrical equipment. Background Technology

[0002] As a crucial component of the renewable energy sector, photovoltaic (PV) technology has demonstrated immense potential in addressing the global energy crisis and environmental pollution in recent years. The core function of PV cells is to directly convert sunlight into electricity, and their conversion efficiency directly determines the power generation capacity and economic benefits of a PV system. With the continued growth in demand for low-carbon green energy, PV technology has evolved, from early monocrystalline and polycrystalline silicon cells to more recent developments such as thin-film and perovskite cells, resulting in increasingly diverse technological approaches. However, regardless of material and structural innovations, the key to cell performance remains the optimization of its microstructure design and manufacturing process, particularly how to effectively improve light absorption and carrier collection efficiency.

[0003] In current mainstream photovoltaic cell designs, a pyramidal textured surface is commonly used on the front of the cell to enhance light capture. This microstructure, through multiple sloping refractions and reflections, significantly increases the residence time and incident angle of light on the surface, helping more photons enter the cell. However, current pyramidal structures mostly remain at the overall geometric shape level, with relatively coarse processing of microscopic details. Especially in the apex and sidewall areas, smooth or slightly rough treatments are commonly used, lacking targeted structural design and functional enhancement. This causes some photons to escape in key reflection paths and not be fully utilized.

[0004] Furthermore, in the spire and sidewall regions, the geometric characteristics make it difficult to deposit the antireflective film uniformly, often resulting in uneven material accumulation and varying thicknesses, leading to increased local reflectivity. Existing research indicates that the reflectivity in the spire and sidewall regions can reach 8% to 12%, significantly higher than other regions. This not only weakens the overall light absorption effect but also directly negatively impacts the battery conversion efficiency. Simultaneously, these regions struggle to provide continuous and efficient transport paths for charge carriers. During the movement of charge carriers from the photogenerated location to the electrode, recombination easily occurs at lattice defects or doping interfaces, reducing current output capability. Moreover, conventional structural designs limit effective control over the direction and path length of charge carrier transport, further affecting collection efficiency.

[0005] To address these shortcomings, some studies have proposed strategies such as using multilayer optical structures, nanomaterial-enhanced films, or complex surface configurations to improve photon capture rate and electron transport efficiency. However, these solutions often rely on expensive materials or sophisticated manufacturing equipment, resulting in high costs and a lack of industrial-scale process compatibility. In actual manufacturing, complex processes may also reduce yield or increase process difficulty, making it difficult to meet the photovoltaic industry's demands for large-scale, low-cost, and standardized production. Overall, while existing technologies have made progress in improving efficiency, they still generally suffer from prominent problems such as unreasonable structural design, high process complexity, and uncontrollable costs, necessitating more practical and economical solutions.

[0006] In view of this, the present invention is hereby proposed. Summary of the Invention

[0007] The purpose of this invention is to provide a solar cell and its preparation method, a solar cell, and an electrical device. The solar cell effectively reduces reflectivity, improves photon capture efficiency and carrier transport path length by setting nano-conical recesses in the pyramid structure, and improves the uniformity of anti-reflection layer deposition, thereby significantly improving the photoelectric conversion efficiency and overall performance of the solar cell.

[0008] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: In a first aspect, the present invention provides a solar cell having a microstructured surface for light capture; the microstructured surface is a velvety surface composed of a plurality of individual pyramidal structures. The monolithic pyramid structure contains nano-conical recesses.

[0009] In some embodiments, the nanoconical recesses are distributed in the apex region of the monolithic pyramid structure and in the sidewall region extending away from the apex region.

[0010] In an optional embodiment, the nanoconical depression has at least one of the following features: A. Depth is 1μm~3μm; B. Diameter range of 5μm to 20μm; C. The spacing between the nanoconical depressions is 2μm~5μm.

[0011] In a second aspect, the present invention provides a solar cell, comprising a solar cell as described in any of the foregoing embodiments.

[0012] Thirdly, the present invention provides an electrical device including a solar cell as described in the foregoing embodiments.

[0013] Fourthly, the present invention provides a method for preparing a solar cell as described in any of the foregoing embodiments, comprising: The silicon wafer undergoes initial surface treatment, one side of the silicon wafer is designated as the light-receiving surface, the other side is designated as the backlight surface, and an isolation area is provided on the backlight surface. The isolation area of ​​the light-receiving surface and the backlight surface is used as the surface to be processed, and the surface to be processed is subjected to a texturing process to form a pyramid structure with a texturing surface. Catalyst localization deposition and anisotropic etching of the deposited catalyst are performed on the surface to be treated after forming a pyramid structure to form nanoconical depressions distributed in the pyramid structure, thereby obtaining a solar cell.

[0014] In a preferred embodiment, the catalyst localization deposition includes: The surface to be treated is coated with photosensitive adhesive to form a photosensitive adhesive film; A photomask is placed over the surface of the photosensitive adhesive film. The light area of ​​the photolithography equipment is used to expose the pyramid structure’s apex and sidewall areas, causing the photosensitive adhesive in the apex and sidewall areas to undergo a photochemical reaction based on the pattern on the photomask, forming the exposure area. The exposed silicon wafer is placed in a deposition solution containing metal particles to perform metal nanocatalyst deposition treatment, thereby obtaining a silicon wafer in which the metal particles are deposited in the exposed area. The surface to be treated after catalyst localization deposition is obtained by cleaning and removing the photosensitive adhesive and undeposited metal particles from the non-exposed areas where no photochemical reaction has occurred.

[0015] In a preferred embodiment, the metal particles in the deposition solution are Cu nanoparticles and / or Ag nanoparticles; The particle size of the metal particles is 50nm~200nm.

[0016] In a preferred embodiment, the anisotropic etching process includes: The silicon wafer, which has been deposited with the catalyst, is placed in an etching solution for selective catalytic etching to obtain an etched silicon wafer. The etched silicon wafer is removed from the etching solution and cleaned to obtain a solar cell.

[0017] In a preferred embodiment, the conditions for the selective catalytic etching reaction include at least one of the following reaction conditions: A. The reaction temperature is 30℃~60℃; B. The reaction time is 5 to 15 minutes; C. The etching solution is a mixed acid solution prepared from HNO3 and H2SO4; D. The etching solution is a mixed acid solution prepared from HNO3 and H2SO4, and satisfies HNO3:H2SO4=1:(2~4).

[0018] Compared with existing technologies, the solar cell provided by this invention significantly reduces the reflectivity of the cell surface, improves photon capture efficiency, extends the carrier transport path, and improves the deposition uniformity of the anti-reflection layer by setting nano-conical recesses in the monolithic pyramid structure. These improvements enable the cell to absorb and utilize light energy more effectively, reduce photon reflection loss and carrier recombination probability, thereby improving the photoelectric conversion efficiency and overall performance of the cell, and providing important technical support for the development of photovoltaic cell technology. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of the method for preparing solar cells in the embodiments of this application; Figure 2 The bar chart shows the reflectance test results of the embodiments and comparative examples of this application. Detailed Implementation

[0021] The embodiments of the present invention will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of the invention. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer are followed. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0022] In this embodiment of the application, a solar cell is provided, wherein the solar cell has a microstructure surface for light capture; the microstructure surface is a velvety surface composed of multiple individual pyramidal structures; the individual pyramidal structures have nanoconical recesses.

[0023] The aforementioned solar cell is a semiconductor device that converts solar energy into electrical energy. It can be made from a silicon wafer as a substrate, and through a series of processes (such as texturing, diffusion, and coating) on ​​its surface and interior, a structure capable of generating a photoelectric conversion effect is formed. Solar cells are the core component of solar photovoltaic power generation systems and are widely used in photovoltaic power generation, solar streetlights, solar chargers, and other fields. In this embodiment, the design focus of the solar cell is on optimizing its surface structure to improve light capture efficiency and the overall performance of the cell.

[0024] Microstructured surfaces refer to the textured structures with specific geometric shapes formed on the surface of solar cells after special treatment. The purpose of these structures is to improve light absorption efficiency by altering the reflection and refraction paths of light, reducing light reflection losses, and increasing the light propagation path on the cell surface. In this embodiment, the design of the microstructured surface is crucial for improving cell performance.

[0025] The aforementioned microstructured surface is a velvety surface composed of multiple individual pyramidal structures. A velvety surface refers to a surface morphology formed by the uniform distribution of multiple individual pyramidal structures. This structure, similar to wool, has a rough surface characteristic that further reduces reflectivity. In traditional photovoltaic cells, velvety surfaces are typically prepared using processes such as chemical etching, and the size of their pyramidal structures is usually on the micrometer scale.

[0026] The single pyramid structure is the basic unit of the microstructure surface. Each pyramid structure can have multiple slopes and can be tetrahedral or polyhedral in shape. The design inspiration for the pyramid structure comes from the multiple reflection characteristics of light on slopes, which can effectively increase the propagation path of light on the battery surface and reduce direct light reflection.

[0027] Nanoconical recesses are special microstructures designed at the nanoscale for surface modification of materials in this example to achieve specific functions. The following is their definition and structural characteristics: A nanoconical recess is a nanoscale recess structure with a cone-shaped geometry formed on the surface of a material. This structure is typically precisely fabricated on the material surface using nanofabrication techniques (such as chemical etching, photolithography, self-assembly, etc.), and its size is usually at the nanoscale (e.g., 1~1000 nanometers).

[0028] Structurally, nanoconical depressions possess a conical geometry, with a sharper top and a wider base, resembling a cone or pyramid. Their base diameter typically ranges from tens to hundreds of nanometers, with their height falling within a similar range. These nanoconical depressions can be uniformly distributed or arranged in specific patterns on the material surface, and their distribution density and spacing can be adjusted according to specific application requirements.

[0029] The surface of nanoconical depressions may have a certain degree of roughness, which can be achieved by designing multiple longitudinally extending depression structures on their outer periphery, thereby increasing the specific surface area. Nanoconical depressions can be made of a variety of materials, including metals, semiconductors, oxides, etc., depending on the application requirements.

[0030] In some embodiments, the nanoconical recesses are distributed in the apex region of the monolithic pyramid structure and in the sidewall region extending away from the apex region.

[0031] The apex region is the highest point of a single pyramid structure. In traditional pyramid structures, the apex region is typically where light reflection is concentrated, as light directly hitting the apex is easily reflected away. This invention, by incorporating nanoconical recesses in the apex region, effectively alters the light reflection path, reduces direct light reflection, and increases light capture efficiency.

[0032] The sidewalls are the portion of a pyramid structure that extends from the apex to the base. In traditional pyramid structures, while the sidewalls can increase the light propagation path through reflection from their sloping surfaces, there is still a problem that some photons cannot be effectively captured.

[0033] In this embodiment, nanoconical recesses are also provided in the sidewall region. These recesses can further optimize the refraction and reflection path of light, allowing more photons to enter the battery and participate in photoelectric conversion.

[0034] Based on the sidewall regions extending away from the apex region, it was clarified that the nanoconical depressions are not only distributed in the apex region, but also extend away from the apex along the sidewalls. This distribution pattern ensures that light incident from different angles can be effectively captured, further improving light utilization.

[0035] By incorporating nanoconical recesses in the spire and sidewall regions, light reflection can be effectively reduced, lowering the average reflectivity of the battery surface to approximately 2.8%, a significant decrease compared to the 8.5% of traditional structures. The distribution of nanoconical recesses in the spire and sidewall regions allows for multiple refractions and reflections of incident light, further increasing the light propagation path on the battery surface and improving photon capture efficiency. The nanoconical recesses alter the carrier transport environment, causing carriers to interact with the sidewalls and bottom of the recesses during transport, thereby lengthening the transport path, reducing the recombination probability, and improving carrier collection efficiency. The nanoconical recesses provide more attachment points and space for the antireflective layer material, guiding its more uniform deposition on the battery surface, reducing antireflective layer thickness variations, and improving the stability and consistency of light absorption and utilization by the battery.

[0036] In some embodiments, the nanoconical depression has at least one of the following features: A. Depth is 1μm~3μm; for example, it can be 1μm, 2μm, 3μm, etc.

[0037] B. Diameter ranges from 5μm to 20μm; for example, it can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 12μm, 14μm, 16μm, 18μm, 20μm, etc.

[0038] C. The spacing between the nanoconical recesses is 2μm to 5μm. For example, it can be 2μm, 3μm, 4μm, 5μm, etc.

[0039] This embodiment further defines the specific characteristics of the nanoconical recesses, including depth, diameter, and spacing. These parameters are chosen based on the goal of optimizing light-harvesting efficiency and carrier transport efficiency.

[0040] The depth of the nanoconical depression directly affects the light propagation path and reflection characteristics on the battery surface. Deeper depressions increase the light propagation path and reduce light reflection, thereby improving light absorption efficiency. The depth of the nanoconical depression is 1–3 micrometers, a range determined through experimental optimization, which effectively reduces reflectivity and improves photon capture efficiency. Nanoconical depressions with a depth of 1–3 micrometers significantly reduce light reflection, lowering the average reflectivity of the battery surface to approximately 2.8%, a substantial reduction compared to the 8.5% of traditional structures.

[0041] The diameter of the nanoconical recesses determines their distribution density on the battery surface and their light-trapping ability. An appropriate diameter ensures that the recess structure can effectively capture photons incident at different angles. The diameter of the nanoconical recesses is between 5 and 20 micrometers. This size range was obtained through experimental optimization, effectively increasing the light propagation path and improving photon capture efficiency. Nanoconical recesses with diameters of 5–20 micrometers can refract and reflect incident light multiple times, further increasing the light propagation path on the battery surface and improving photon capture efficiency.

[0042] The spacing between nanoconical recesses affects the light propagation path and reflection characteristics on the battery surface. An appropriate spacing ensures that the recessed structures do not interfere with each other while maximizing light capture efficiency. The spacing between the nanoconical recesses is 2–5 micrometers. This spacing range was experimentally optimized to ensure uniform distribution of the recessed structures on the battery surface, reducing light reflection. At this spacing, the nanoconical recesses ensure that they do not interfere with each other, while maximizing light capture efficiency and further reducing reflectivity.

[0043] This application provides a solar cell, including a solar cell as described in any of the foregoing embodiments.

[0044] In solar cells, besides the solar cells themselves, there may be encapsulation materials (such as front panels, encapsulating films, and backsheets) to protect the cells and provide optical and electrical performance; junction boxes to connect electrodes and provide external circuit interfaces; frames to fix and support the cells; electrical connections (such as solder ribbons and busbars) to connect the cells in series or parallel; inverters to convert direct current to alternating current; energy storage systems to store excess energy; cooling systems to reduce operating temperature; and monitoring systems to monitor operating status in real time. These components work together to ensure the efficient operation, stability, and safety of solar cells, while extending their lifespan.

[0045] This application provides an electrical device, including a solar cell as described in the foregoing embodiments.

[0046] Electrically powered equipment is a device that uses electricity as its energy source or power source, and may include the aforementioned solar cells. The core component of this solar cell is a solar cell sheet with a special microstructure surface. Its surface is a velvety surface composed of multiple individual pyramidal structures, with nano-conical recesses at the apex and sidewalls of the pyramids. These recesses have specific dimensional parameters (e.g., depth 1μm-3μm, diameter 5μm-20μm, spacing 2μm-5μm), which significantly improves light capture efficiency and reduces reflectivity, thereby enhancing the cell's photoelectric conversion efficiency. By integrating this high-efficiency solar cell into electrically powered equipment, a clean and renewable energy supply can be provided, enhancing its autonomous power supply capability in grid-free or mobile scenarios. It also helps improve energy utilization efficiency and reduce dependence on traditional energy sources, making it suitable for various devices and systems requiring power support, such as portable electronic devices, outdoor lighting systems, electric vehicles, and communication base stations.

[0047] refer to Figure 1 This application provides a method for preparing a solar cell as described in any of the foregoing embodiments, comprising: Step S1: Perform initial surface treatment on the silicon wafer, set one side of the silicon wafer as the light-receiving surface, set the side different from the light-receiving surface as the back-light surface, and set an isolation area on the back-light surface.

[0048] The initial surface treatment is to prepare the silicon wafer for subsequent texturing and structure formation processes.

[0049] Initial surface treatment is the starting step in solar cell fabrication and mainly includes, but is not limited to, cleaning (chemical cleaning, ultrasonic cleaning, deionized water rinsing and drying), surface planarization (chemical mechanical polishing or wet etching), edge isolation (laser cutting or chemical etching), back-side treatment (back-side polishing, back-side texturing and back-side isolation area setup), polishing, and inspection and quality control (surface roughness, impurities and thickness inspection). These operations aim to remove impurities and defects from the silicon wafer surface, ensuring a smooth and clean surface, providing a high-quality substrate for subsequent processes, thereby guaranteeing the performance and reliability of the solar cell.

[0050] A silicon wafer has a light-receiving side and a back-lighting side. The light-receiving side is one side of the silicon wafer, directly facing the light source, and is used to absorb sunlight. The back-lighting side is the other side of the silicon wafer, opposite to the light-receiving side, and is typically used to mount electrodes and other auxiliary structures. The main function of the isolation zone is to prevent current leakage and impurity diffusion, ensuring the performance and reliability of the solar cell.

[0051] Setting an isolation zone on the backside of a solar cell effectively prevents current leakage through the edges or back of the silicon wafer, thereby improving the cell's efficiency and stability. The isolation zone is typically formed through laser cutting or chemical etching, ensuring sufficient insulation between the electrode area on the backside and other areas. During fabrication, impurities or contaminants may remain on the silicon wafer surface. The isolation zone prevents these impurities from diffusing into the effective area of ​​the cell, thus improving its performance. The isolation zone also prevents impurities introduced in subsequent processes (such as electrode fabrication) from affecting the cell's performance.

[0052] In addition, P-regions and N-regions can be formed on the backlight surface. A P-region is a semiconductor region doped with acceptor impurities (typically boron, B), possessing positively charged carriers (holes) as the majority carriers. In solar cells, P-regions are typically used to form PN junctions, a crucial structure for photoelectric conversion. An N-region is a semiconductor region doped with donor impurities (typically phosphorus, P), possessing negatively charged carriers (electrons) as the majority carriers. N-regions are also used to form PN junctions in solar cells. P-regions and N-regions are typically formed through diffusion processes. For example, phosphorus is diffused onto the silicon wafer surface at high temperatures to form N-regions, and boron is diffused onto the silicon wafer surface to form P-regions. Isolation regions can be formed on the back of the silicon wafer by laser cutting or chemical etching, ensuring sufficient insulation between the electrode areas on the backlight surface and other areas.

[0053] The light-receiving surface is the surface directly facing the light source, and its structural design (such as pyramid structures and nanoconical recesses) is primarily aimed at maximizing light absorption. Therefore, the light-receiving surface needs to maintain the highest possible light-capturing efficiency, while the backlight surface can be used for other functional structures. Placing the isolation zone on the backlight surface avoids interference with the light-capturing structure of the light-receiving surface, while ensuring the normal operation of the electrodes and other auxiliary structures on the backlight surface. The backlight surface is typically used to mount electrodes and other auxiliary structures, such as junction boxes and bypass diodes. Placing the isolation zone on the backlight surface provides sufficient space for these structures while ensuring adequate insulation between them and the effective area of ​​the solar cell. This design improves the overall performance and reliability of the solar cell while simplifying the manufacturing process.

[0054] Step S2: Using the isolation area of ​​the light-receiving surface and the backlight surface as the surface to be processed, the surface to be processed is subjected to a texturing process to form a pyramid structure with a texturing surface.

[0055] In this step, texturing is performed to create a textured surface on the silicon wafer. This surface consists of multiple monolithic pyramidal structures, which reduces light reflection, increases the light propagation path, and thus improves light absorption efficiency. Through a double-sided texturing process, the P-region is etched down to the boron-doped polysilicon layer, the N-region down to the phosphorus-doped polysilicon layer, and the isolation region down to the silicon wafer, forming the textured surface.

[0056] Step S3 involves performing catalyst localization deposition and anisotropic etching on the surface to be treated after the formation of the pyramid structure, thereby forming nano-conical depressions distributed in the pyramid structure to obtain a solar cell.

[0057] Catalyst localization deposition is used to precisely deposit catalyst in specific regions (the apex and sidewalls) of a pyramid structure so that subsequent anisotropic etching can form nanocone-shaped depressions.

[0058] Anisotropic etching is used to create nanoconical depressions in the apex and sidewall regions of the pyramid structure, which can further optimize light capture and carrier transport paths.

[0059] The catalyst deposited on the silicon wafer can be etched at the top and sidewalls to form nanoconical depressions with a depth of 1-3 micrometers and a spacing of 2-5 micrometers.

[0060] The fabrication method in this embodiment, through initial surface treatment, texturing, catalyst positioning, and anisotropic etching, successfully formed a pyramid structure with nano-conical depressions on the silicon wafer surface. These steps significantly reduce the reflectivity of the solar cell, improve photon capture efficiency, and extend the carrier transport path, thereby enhancing the overall performance of the solar cell.

[0061] Furthermore, the catalyst localization deposition in step S3 includes: Step S31: Apply photosensitive adhesive to the surface to be treated to form a photosensitive adhesive film.

[0062] In this step, a layer of photosensitive adhesive is uniformly coated onto the surfaces of the silicon wafer to be treated (the light-receiving surface and the isolation area) to form a photosensitive adhesive film. Photosensitive adhesive is a photosensitive material that can undergo a photochemical reaction under light of a specific wavelength, thereby changing its chemical properties and solubility.

[0063] Spin coating can be used to uniformly coat the photoresist onto the silicon wafer surface, ensuring a consistent thickness of the photoresist film. The selection of the photoresist should be based on the requirements of subsequent photolithography processes, ensuring its sensitivity to specific wavelengths of light and its ability to form clear patterns after exposure.

[0064] Step S32: Cover the surface of the photosensitive adhesive film with a photomask, and expose the pyramid structure’s apex and sidewall regions using the illumination area of ​​the photolithography equipment, so that the photosensitive adhesive in the apex and sidewall regions undergoes a photochemical reaction based on the pattern on the photomask to form the exposure area.

[0065] A specific pattern is formed on the photosensitive adhesive film using photolithography, causing the photosensitive adhesive in the top and sidewall areas to undergo a photochemical reaction, while the photosensitive adhesive in other areas remains unexposed.

[0066] The photomask is designed with patterns corresponding to the apex and sidewalls of the pyramid structure, which determine the exposure areas of the photosensitive adhesive. Using photolithography equipment (such as an ultraviolet lithography machine), light of a specific wavelength is passed through the photomask and irradiated onto the photosensitive adhesive film, causing a photochemical reaction in the exposed areas, typically manifested as a change in the solubility or chemical properties of the photosensitive adhesive. After exposure, the photosensitive adhesive film is developed in a developer solution, removing the photosensitive adhesive from the exposed areas and exposing the silicon wafer surface.

[0067] Step S33: The exposed silicon wafer is placed into a deposition solution containing metal particles for metal nanocatalyst deposition treatment, to obtain a silicon wafer in which the metal particles are deposited in the exposed area.

[0068] In this step, suitable metal nanoparticles are selected, and the exposed silicon wafer is immersed in a deposition solution containing the metal nanoparticles. The metal particles are then deposited on the exposed silicon wafer surface using a chemical deposition method. During the deposition process, the metal particles selectively deposit in the exposed areas, while deposition does not occur in the unexposed areas due to the protection of the photosensitive adhesive.

[0069] In a preferred embodiment, the metal particles in the deposition solution may be Cu nanoparticles and / or Ag nanoparticles.

[0070] Furthermore, the particle size of the metal particles is 50nm to 200nm. For example, it can be 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 120nm, 150nm, 180nm, 200nm, etc.

[0071] Step S34: The photosensitive adhesive and undeposited metal particles in the non-exposed areas where no photochemical reaction has occurred are removed by cleaning to obtain the surface to be treated after catalyst positioning deposition.

[0072] In this step, photoresist and undeposited metal particles are removed from the unexposed areas, ensuring that the catalyst is only distributed in the top and sidewall regions. Deionized water or other suitable cleaning solutions are used to remove the photoresist and undeposited metal particles from the unexposed areas. After cleaning, the silicon wafer surface has metal nanoparticles deposited only in the exposed areas; these particles will serve as catalysts for subsequent etching.

[0073] In the above steps, the catalyst localization deposition method achieves precise catalyst localization in the apex and sidewall regions of the pyramid structure through photosensitive adhesive coating, photolithography exposure, metal nanoparticle deposition, and cleaning. This process is a key step in forming the nanoconical depressions, which can significantly improve the light capture efficiency and carrier transport efficiency of solar cells, thereby enhancing the overall performance of the cell.

[0074] In some embodiments, the anisotropic etching process includes: Step S35: The silicon wafer deposited with the catalyst is placed in an etching solution for selective catalytic etching to obtain an etched silicon wafer.

[0075] In this step, metal nanocatalysts (such as Cu or Ag nanoparticles) are used as local catalysts to form nanoconical depressions in the apex and sidewall regions of the pyramid structure through selective catalytic etching reactions.

[0076] The etching solution described above can be a mixed acid solution prepared from HNO3 and H2SO4.

[0077] In one embodiment, the etching solution contains HNO3:H2SO4 in a ratio of 1:(2~4). For example, the ratio can be 1:2, 1:3, 1:4, etc.

[0078] In one embodiment, the reaction temperature is 30°C to 60°C; for example, the temperature can be 30°C, 40°C, 50°C, 60°C, etc.

[0079] In one embodiment, the reaction time is 5 to 15 minutes; for example, the reaction time can be 5 minutes, 6 minutes, 7 minutes, 8 minutes, 9 minutes, 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes, 15 minutes, etc.

[0080] For example, the etching solution is a mixture of HNO3 and H2SO4, with a formulation ratio of HNO3:H2SO4=1:3; the etching temperature is strictly controlled between 30~60℃ to ensure the uniformity and controllability of the etching reaction. The etching time is controlled between 5~15 minutes, and the specific time is adjusted according to the required depth (1~3μm) and spacing (2~5μm) of the nanocone depressions.

[0081] During the etching process, metal nanoparticles act as local catalysts, accelerating the corrosion of the spire and sidewall regions through the Joule thermal effect. Silicon atoms are gradually corroded and dissolved under the action of the catalyst, forming nanoconical depressions.

[0082] The Joule thermal effect (also known as the Joule heating effect) refers to the phenomenon where electrical energy is converted into heat energy when an electric current passes through a conductor due to the conductor's internal resistance. In the fabrication of solar cells, especially during the anisotropic etching process, the Joule thermal effect is used to accelerate the etching reaction.

[0083] The specific process can be as follows: In the etching solution, metal nanoparticles (such as Cu or Ag) are deposited as catalysts on specific areas of the silicon wafer surface (such as the apex and sidewalls of a pyramid structure). These metal particles have low electrical resistance; when current passes through these metal nanoparticles, according to the Joule thermal effect, the current generates heat in the metal particles; the generated heat accelerates the chemical reaction between the etching solution and the silicon wafer surface, causing the silicon atoms in the apex and sidewall regions to be etched and dissolved more quickly, thereby forming nanoconical depressions.

[0084] In the fabrication of solar cells, particularly during the anisotropic etching process, the Joule thermal effect accelerates the etching reaction through the heat generated by the electric current. This allows for the precise formation of nanoconical depressions at the apex and sidewalls of the pyramid structure. This effect not only improves etching efficiency but also ensures the accurate fabrication of the nanostructure, thereby optimizing the light-harvesting performance and overall efficiency of the solar cell.

[0085] Step S36: Remove the etched silicon wafer from the etching solution, clean it, and obtain a solar cell.

[0086] In this step, the silicon wafer needs to be treated to remove etching solution residues to ensure that the silicon wafer surface is clean and ready for subsequent processes (such as passivation layer deposition, electrode preparation, etc.).

[0087] Specific operations may include, but are not limited to: (1) Preliminary cleaning: Remove the etched silicon wafer from the etching solution and immediately rinse it with a large amount of deionized water to remove residual acid and impurities on the surface.

[0088] (2) Ultrasonic cleaning: Place the silicon wafer in an ultrasonic cleaning tank, add an appropriate amount of deionized water, and turn on the ultrasonic cleaning equipment. Ultrasonic cleaning utilizes the cavitation effect of ultrasonic waves to remove tiny impurities and metal particles from the surface of the silicon wafer.

[0089] (3) Chemical cleaning: The silicon wafer is further cleaned using a specific chemical cleaning agent to remove metal ions and compounds from the surface. For example, hydrofluoric acid (HF) solution can be used to remove the oxide layer on the surface of the silicon wafer.

[0090] (4) Drying treatment: After cleaning, the silicon wafer is dried with nitrogen or placed in an oven to ensure that the surface of the silicon wafer is dry and free of moisture residue.

[0091] The present invention will be further illustrated below with specific embodiments. However, it should be understood that these embodiments are merely for the purpose of more detailed illustration and should not be construed as limiting the present invention in any way.

[0092] Table 1. Comparison of key parameters in the examples and comparative examples.

[0093] Example 1 In this embodiment, the solar electrode and solar cell were fabricated.

[0094] Experimental methods: 1. Initial surface treatment: Perform the first double-sided polishing treatment on the silicon substrate (silicon wafer).

[0095] 2. Set up the light-receiving surface and the backlight surface (N-zone, P-zone, isolation zone), and prepare the backlight surface: (1) A first tunneling silicon oxide layer, a boron-doped polycrystalline silicon layer and a borosilicate glass layer are sequentially formed on the back side (backlight side); (2) Perform the first laser patterning process on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region.

[0096] (3) Perform a second double-sided polishing process to remove the first tunneling oxide layer and boron-doped polysilicon layer in the N-region and isolation region on the back side.

[0097] (4) A second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are formed on both sides of the silicon wafer.

[0098] (5) Perform a second laser patterning process on the back of the silicon wafer to remove the phosphorus silicate glass layer in the P-region and the isolation region.

[0099] 3. Texturing, positioning, and etching: (1) Perform wet etching on the front side (light-receiving side) of the silicon wafer to remove all layers on the front side and remove the coating around the side.

[0100] (2) Double-sided texturing: the P region is etched to the boron-doped polycrystalline silicon layer, the N region is etched to the phosphorus-doped polycrystalline silicon layer, and the isolation region is etched to the silicon wafer. The isolation region on the back side of the silicon wafer and the front side of the silicon wafer form a texturized surface.

[0101] (3) Catalyst positioning on the front side of the solar cell: Photolithography is used to accurately position the catalyst. First, photosensitive adhesive is uniformly spin-coated on the front side of the silicon wafer to form a photosensitive adhesive film of uniform thickness.

[0102] Using a photomask, the top region and some sidewall areas are exposed using photolithography equipment. During the exposure process, the pattern on the photomask is transferred to the photosensitive adhesive, causing a photochemical reaction in the photosensitive adhesive in these areas, which alters its properties.

[0103] Subsequently, the silicon wafer was placed in a solution containing mixed Cu and Ag nanoparticles (125 nm in diameter). Through a specific deposition process, the mixed Cu and Ag nanoparticles were deposited in the exposed areas (i.e., the tip region and the sidewall region). Photosensitive adhesive in the unexposed areas did not deposit. Finally, the silicon wafer was rinsed with deionized water to remove the photosensitive adhesive and undeposited Cu and Ag nanoparticles from the unexposed areas, thus achieving the precise deposition of Cu / Ag nanoparticles in the tip region and the sidewall region (12.5 μm in diameter).

[0104] (4) Anisotropic etching: The silicon wafer with the catalyst positioned is immersed in a mixed acid solution with a formulation of HNO3:H2SO4 = 1:3. During the etching process, the temperature is strictly controlled at 40℃. Cu and Ag mixed particles are used as local catalysts, and the corrosion of the tip and sidewall regions is accelerated by the Joule thermal effect. Under the Joule thermal effect, the chemical reaction rate in the tip and sidewall regions is accelerated, and silicon atoms are gradually corroded and dissolved. The etching time is precisely controlled at 10 minutes. After etching, nanoconical depressions with a depth of 2μm are formed in the tip and sidewall regions, and the spacing between these depressions is 3.5μm.

[0105] 4. Post-processing: (1) Cleaning: Preliminary cleaning: After etching is complete, remove the silicon wafer from the etching solution and immediately rinse it with plenty of deionized water to remove residual acid and impurities from the surface.

[0106] Ultrasonic cleaning: Place the silicon wafer in an ultrasonic cleaning tank, add an appropriate amount of deionized water, turn on the ultrasonic cleaning equipment, and perform ultrasonic cleaning. Ultrasonic cleaning utilizes the cavitation effect of ultrasonic waves to remove tiny impurities and metal particles from the surface of the silicon wafer.

[0107] Chemical cleaning: Specific chemical cleaning agents are used to further clean the silicon wafers, removing metal ions and compounds from the surface. For example, solutions such as hydrofluoric acid (HF) can be used to remove the oxide layer on the silicon wafer surface.

[0108] Drying process: After cleaning, the silicon wafers are dried with nitrogen or placed in an oven to ensure that the surface of the silicon wafers is dry and free of moisture residue.

[0109] (2) A passivation layer and an anti-reflection layer are deposited on both sides to complete the preparation of the solar electrode.

[0110] (3) A positive electrode is prepared in the P region on the back side and a negative electrode is prepared in the N region to obtain a solar cell.

[0111] Example 2 In this embodiment, the solar electrode and solar cell were fabricated.

[0112] Experimental methods: 1. Initial surface treatment: Select an N-type silicon wafer with a thickness of 130μm, and perform texturing and cleaning. After efficient cleaning, a textured surface layer is formed on the front side of the silicon wafer.

[0113] 2. Texturing, positioning, and etching: Catalyst positioning on the front of the solar cell: (1) Spin coat the photosensitive adhesive evenly onto the front side of the silicon wafer to form a photosensitive adhesive film of uniform thickness.

[0114] (2) Exposure is performed on the top region and some sidewall regions using a photolithography device through a photomask. The pattern on the photomask is transferred to the photosensitive adhesive, causing the photosensitive adhesive in these regions to undergo a photochemical reaction and its properties to change.

[0115] (3) The silicon wafer is placed in a solution containing Cu nanoparticles (115 nm in diameter). Through a specific deposition process, the Cu nanoparticles will be deposited in the exposed areas (i.e., the top area and the sidewall area). The photosensitive adhesive in the unexposed areas will not be deposited.

[0116] (4) Finally, rinse the silicon wafer with deionized water to remove the photoresist in the unexposed areas and the undeposited Cu nanoparticles, thereby achieving precise deposition.

[0117] Anisotropic etching: (1) Immerse the silicon wafer with the catalyst positioned into the etching solution. The etching solution has the formula of HNO3:H2SO4=1:2.

[0118] (2) During the etching process, the temperature is strictly controlled at 30℃. Cu particles are used as local catalysts to accelerate the corrosion of the tower tip and side wall area through the Joule thermal effect.

[0119] (3) The etching time is precisely controlled at 15 minutes. After etching, nano-conical depressions with a depth of 1-3 μm are formed in the tower tip and side wall area, and the spacing between these depressions is 4 μm.

[0120] 3. Cleaning: (1) Preliminary cleaning: After etching is completed, the silicon wafer is removed from the mixed acid solution and immediately rinsed with a large amount of deionized water to remove residual acid and impurities on the surface.

[0121] (2) Ultrasonic cleaning: Place the silicon wafer in an ultrasonic cleaning tank, add an appropriate amount of deionized water, turn on the ultrasonic cleaning equipment, and perform ultrasonic cleaning. Ultrasonic cleaning can utilize the cavitation effect of ultrasonic waves to remove tiny impurities and metal particles from the surface of the silicon wafer.

[0122] (3) Chemical cleaning: The silicon wafer is further cleaned using specific chemical cleaning agents to remove metal ions and compounds from the surface. For example, a solution such as hydrofluoric acid (HF) can be used to remove the oxide layer on the surface of the silicon wafer.

[0123] (4) Drying treatment: After cleaning, the silicon wafer is dried with nitrogen or placed in an oven to ensure that the surface of the silicon wafer is dry and free of moisture residue.

[0124] 4. Growth of tunneling oxide layer, polycrystalline silicon and deposition: (1) The cleaned silicon wafer is then subjected to LPVCVD or PECVD techniques to form a tunneling oxide layer and a polycrystalline silicon layer on the back side of the silicon wafer. The tunneling oxide layer is made of silicon dioxide and has a thickness of 1.2 nm; the polycrystalline silicon layer has a thickness of 100 nm.

[0125] (2) Phosphorus is diffused into the polycrystalline silicon layer at high temperature to form an effective doped layer. The phosphorus doping concentration is not less than 1e20 / cm. 3 .

[0126] Laser Etching (1) The tunneling oxide layer and polysilicon of the N-region on the back side are ablated and etched by laser etching. The laser etching area is the sum of the N-region on the back side and the insulating gap.

[0127] (2) The insulation gap is 1 μm to ensure the insulation between the P region and the N region during the power generation process.

[0128] 5. High-efficiency cleaning of silicon wafers: (1) High-efficiency cleaning of silicon wafers to remove the damaged layer and other impurities generated during laser processing. (2) The cleaning process must remove the coating generated during LPCVD processing of silicon wafers.

[0129] 6. Deposition of intrinsic amorphous silicon layer on the front side: An intrinsic amorphous silicon thin film with a thickness of 5nm is deposited on the front side of the cell using PECVD, HWCVD or LPCVD technology.

[0130] 7. Deposition of antireflective coating on the front side: An antireflective coating is deposited on the front side of the solar cell using PECVD technology. The antireflective coating is made of micro silicon nitride and has a thickness of 90nm.

[0131] 8. Deposition of intrinsic amorphous silicon layer on the back side: An intrinsic amorphous silicon thin film with a thickness of 5nm is deposited on the back side of the solar cell using PECVD, HWCVD or LPCVD technology.

[0132] 9. Deposition of P-type amorphous silicon layer on the back side: (1) A P-type amorphous silicon layer is deposited on the back side of the cell using a mask-etching process. The size of the protected area is the sum of the size of the N-doped area and the gap size, and the gap size is 1 μm. (2) A P-type doped amorphous silicon thin film with a thickness of 8 nm is deposited on the cell using PECVD, HWCVD or LPCVD technology.

[0133] 12. Deposition of TCO and metal composite film: (1) A composite film of TCO and metal film is deposited on the P and N regions of the back of the solar cell using a mask-etching process. (2) A transparent conductive film is deposited on the solar cell using PVD or RPD equipment. The work function of the target material in the N region is less than 4.2 eV, and In2O3 / SnO2 is used with a mass ratio of 97:3 and a thickness of 40 nm. The work function of the target material in the P region is greater than 5.2 eV, and In2O3 / SnO2 is used with a mass ratio of 95:5 and a thickness of 40 nm. (3) The metal film is deposited using PVD equipment. The metal film material is silver and has a thickness of 100 nm.

[0134] 13. Electrode preparation: (1) The conductive paste is printed using screen printing technology to print the battery pattern. The conductive paste is low-temperature silver paste. (2) The battery pattern is designed using multi-busbar technology, with 17 main busbar lines.

[0135] Example 3 In this embodiment, the solar electrode and solar cell were fabricated.

[0136] Experimental methods: The method used in this embodiment is basically the same as that in Embodiment 1, except that the process parameters for preparing the nano-depression textured surface are different.

[0137] Experimental methods: 1. Initial surface treatment: Perform the first double-sided polishing treatment on the silicon substrate (silicon wafer).

[0138] 2. Set up the light-receiving surface and the backlight surface (N-zone, P-zone, isolation zone), and prepare the backlight surface: (1) A first tunneling silicon oxide layer, a boron-doped polycrystalline silicon layer and a borosilicate glass layer are sequentially formed on the back side (backlight side); (2) Perform the first laser patterning process on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region.

[0139] (3) Perform a second double-sided polishing process to remove the first tunneling oxide layer and boron-doped polysilicon layer in the N-region and isolation region on the back side.

[0140] (4) A second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are formed on both sides of the silicon wafer.

[0141] (5) Perform a second laser patterning process on the back of the silicon wafer to remove the phosphorus silicate glass layer in the P-region and the isolation region.

[0142] 3. Texturing, positioning, and etching: (1) Perform wet etching on the front side (light-receiving side) of the silicon wafer to remove all layers on the front side and remove the coating around the side.

[0143] (2) Double-sided texturing: the P region is etched to the boron-doped polycrystalline silicon layer, the N region is etched to the phosphorus-doped polycrystalline silicon layer, and the isolation region is etched to the silicon wafer. The isolation region on the back side of the silicon wafer and the front side of the silicon wafer form a texturized surface.

[0144] (3) Catalyst positioning on the front side of the solar cell: Photolithography is used to accurately position the catalyst. First, photosensitive adhesive is uniformly spin-coated on the front side of the silicon wafer to form a photosensitive adhesive film of uniform thickness.

[0145] Using a photomask, the top region and some sidewall areas are exposed using photolithography equipment. During the exposure process, the pattern on the photomask is transferred to the photosensitive adhesive, causing a photochemical reaction in the photosensitive adhesive in these areas, which alters its properties.

[0146] Subsequently, the silicon wafer was placed in a solution containing Ag mixed nanoparticles (75 nm in diameter). Through a specific deposition process, the Ag nanoparticles were deposited in the exposed areas (i.e., the tip region and the sidewall portion). The photosensitive adhesive in the unexposed areas did not deposit. Finally, the silicon wafer was rinsed with deionized water to remove the photosensitive adhesive and undeposited Ag nanoparticles from the unexposed areas, thus achieving the goal of precisely depositing Ag nanoparticles in the tip region and the sidewall portion (7.5 μm in diameter).

[0147] (4) Anisotropic etching: The silicon wafer with the catalyst positioned is immersed in a mixed acid solution with a formulation of HNO3:H2SO4 = 1:4. During the etching process, the temperature is strictly controlled at 60℃, and Ag particles are used as local catalysts to accelerate the corrosion of the tip and sidewall regions through the Joule thermal effect. Under the Joule thermal effect, the chemical reaction rate in the tip and sidewall regions is accelerated, and silicon atoms are gradually corroded and dissolved. The etching time is precisely controlled at 5 minutes. After etching, nanoconical depressions with a depth of 1.5 μm are formed in the tip and sidewall regions, and the spacing between these depressions is 3 μm.

[0148] 4. Post-processing: (1) Cleaning: Preliminary cleaning: After etching is complete, remove the silicon wafer from the etching solution and immediately rinse it with plenty of deionized water to remove residual acid and impurities from the surface.

[0149] Ultrasonic cleaning: Place the silicon wafer in an ultrasonic cleaning tank, add an appropriate amount of deionized water, turn on the ultrasonic cleaning equipment, and perform ultrasonic cleaning. Ultrasonic cleaning utilizes the cavitation effect of ultrasonic waves to remove tiny impurities and metal particles from the surface of the silicon wafer.

[0150] Chemical cleaning: Specific chemical cleaning agents are used to further clean the silicon wafers, removing metal ions and compounds from the surface. For example, solutions such as hydrofluoric acid (HF) can be used to remove the oxide layer on the silicon wafer surface.

[0151] Drying process: After cleaning, the silicon wafers are dried with nitrogen or placed in an oven to ensure that the surface of the silicon wafers is dry and free of moisture residue.

[0152] (2) A passivation layer and an anti-reflection layer are deposited on both sides to complete the preparation of the solar electrode.

[0153] (3) A positive electrode is prepared in the P region on the back side and a negative electrode is prepared in the N region to obtain a solar cell.

[0154] Example 4 In this embodiment, the solar electrode and solar cell were fabricated.

[0155] Experimental methods: The method used in this embodiment is basically the same as that in Embodiment 1, except that the process parameters for preparing the nano-depression textured surface are different.

[0156] Experimental methods: 1. Initial surface treatment: Perform the first double-sided polishing treatment on the silicon substrate (silicon wafer).

[0157] 2. Set up the light-receiving surface and the backlight surface (N-zone, P-zone, isolation zone), and prepare the backlight surface: (1) A first tunneling silicon oxide layer, a boron-doped polycrystalline silicon layer and a borosilicate glass layer are sequentially formed on the back side (backlight side); (2) Perform the first laser patterning process on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region.

[0158] (3) Perform a second double-sided polishing process to remove the first tunneling oxide layer and boron-doped polysilicon layer in the N-region and isolation region on the back side.

[0159] (4) A second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are formed on both sides of the silicon wafer.

[0160] (5) Perform a second laser patterning process on the back of the silicon wafer to remove the phosphorus silicate glass layer in the P-region and the isolation region.

[0161] 3. Texturing, positioning, and etching: (1) Perform wet etching on the front side (light-receiving side) of the silicon wafer to remove all layers on the front side and remove the coating around the side.

[0162] (2) Double-sided texturing: the P region is etched to the boron-doped polycrystalline silicon layer, the N region is etched to the phosphorus-doped polycrystalline silicon layer, and the isolation region is etched to the silicon wafer. The isolation region on the back side of the silicon wafer and the front side of the silicon wafer form a texturized surface.

[0163] (3) Catalyst positioning on the front side of the solar cell: Photolithography is used to accurately position the catalyst. First, photosensitive adhesive is uniformly spin-coated on the front side of the silicon wafer to form a photosensitive adhesive film of uniform thickness.

[0164] Using a photomask, the top region and some sidewall areas are exposed using photolithography equipment. During the exposure process, the pattern on the photomask is transferred to the photosensitive adhesive, causing a photochemical reaction in the photosensitive adhesive in these areas, which alters its properties.

[0165] Subsequently, the silicon wafer was placed in a solution containing mixed Cu nanoparticles (150 nm in diameter). Through a specific deposition process, the Cu nanoparticles were deposited in the exposed areas (i.e., the tip region and the sidewall portion). The photoresist in the unexposed areas did not deposit. Finally, the silicon wafer was rinsed with deionized water to remove the photoresist in the unexposed areas and the undeposited Cu nanoparticles, thus achieving the goal of precisely depositing Cu nanoparticles in the tip region and the sidewall portion (15 μm in diameter).

[0166] (4) Anisotropic etching: The silicon wafer with the catalyst positioned is immersed in a mixed acid solution with a ratio of HNO3:H2SO4 = 1:2.7. During the etching process, the temperature is strictly controlled at 50℃, and Cu particles are used as local catalysts to accelerate the corrosion of the tip and sidewall regions through the Joule thermal effect. Under the Joule thermal effect, the chemical reaction rate in the tip and sidewall regions is accelerated, and silicon atoms are gradually corroded and dissolved. The etching time is precisely controlled at 8 minutes. After etching, nanoconical depressions with a depth of 2.75 μm are formed in the tip and sidewall regions, and the spacing between these depressions is 3.75 μm.

[0167] 4. Post-processing: (1) Cleaning: Preliminary cleaning: After etching is complete, remove the silicon wafer from the etching solution and immediately rinse it with plenty of deionized water to remove residual acid and impurities from the surface.

[0168] Ultrasonic cleaning: Place the silicon wafer in an ultrasonic cleaning tank, add an appropriate amount of deionized water, turn on the ultrasonic cleaning equipment, and perform ultrasonic cleaning. Ultrasonic cleaning utilizes the cavitation effect of ultrasonic waves to remove tiny impurities and metal particles from the surface of the silicon wafer.

[0169] Chemical cleaning: Specific chemical cleaning agents are used to further clean the silicon wafers, removing metal ions and compounds from the surface. For example, solutions such as hydrofluoric acid (HF) can be used to remove the oxide layer on the silicon wafer surface.

[0170] Drying process: After cleaning, the silicon wafers are dried with nitrogen or placed in an oven to ensure that the surface of the silicon wafers is dry and free of moisture residue.

[0171] (2) A passivation layer and an anti-reflection layer are deposited on both sides to complete the preparation of the solar electrode.

[0172] (3) A positive electrode is prepared in the P region on the back side and a negative electrode is prepared in the N region to obtain a solar cell.

[0173] Example 5 In this embodiment, the solar electrode and solar cell were fabricated.

[0174] Experimental methods: The method used in this embodiment is basically the same as that in Embodiment 1, except that the process parameters for preparing the nano-depression textured surface are different.

[0175] Experimental methods: 1. Initial surface treatment: Perform the first double-sided polishing treatment on the silicon substrate (silicon wafer).

[0176] 2. Set up the light-receiving surface and the backlight surface (N-zone, P-zone, isolation zone), and prepare the backlight surface: (1) A first tunneling silicon oxide layer, a boron-doped polycrystalline silicon layer and a borosilicate glass layer are sequentially formed on the back side (backlight side); (2) Perform the first laser patterning process on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region.

[0177] (3) Perform a second double-sided polishing process to remove the first tunneling oxide layer and boron-doped polysilicon layer in the N-region and isolation region on the back side.

[0178] (4) A second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are formed on both sides of the silicon wafer.

[0179] (5) Perform a second laser patterning process on the back of the silicon wafer to remove the phosphorus silicate glass layer in the P-region and the isolation region.

[0180] 3. Texturing, positioning, and etching: (1) Perform wet etching on the front side (light-receiving side) of the silicon wafer to remove all layers on the front side and remove the coating around the side.

[0181] (2) Double-sided texturing: the P region is etched to the boron-doped polycrystalline silicon layer, the N region is etched to the phosphorus-doped polycrystalline silicon layer, and the isolation region is etched to the silicon wafer. The isolation region on the back side of the silicon wafer and the front side of the silicon wafer form a texturized surface.

[0182] (3) Catalyst positioning on the front side of the solar cell: Photolithography is used to accurately position the catalyst. First, photosensitive adhesive is uniformly spin-coated on the front side of the silicon wafer to form a photosensitive adhesive film of uniform thickness.

[0183] Using a photomask, the top region and some sidewall areas are exposed using photolithography equipment. During the exposure process, the pattern on the photomask is transferred to the photosensitive adhesive, causing a photochemical reaction in the photosensitive adhesive in these areas, which alters its properties.

[0184] Subsequently, the silicon wafer was placed in a solution containing mixed Cu and Ag nanoparticles (100 nm in diameter). Through a specific deposition process, the mixed Cu and Ag nanoparticles were deposited in the exposed areas (i.e., the tip region and the sidewall region). Photosensitive adhesive in the unexposed areas did not deposit. Finally, the silicon wafer was rinsed with deionized water to remove the photosensitive adhesive and undeposited Cu and Ag nanoparticles from the unexposed areas, thus achieving the precise deposition of Cu / Ag nanoparticles in the tip region and the sidewall region (12 μm in diameter).

[0185] (4) Anisotropic etching: The silicon wafer with the catalyst positioned is immersed in a mixed acid solution with a formulation of HNO3:H2SO4 = 1:3. During the etching process, the temperature is strictly controlled at 45℃. Cu and Ag mixed particles are used as local catalysts, and the corrosion of the tip and sidewall regions is accelerated by the Joule thermal effect. Under the Joule thermal effect, the chemical reaction rate in the tip and sidewall regions is accelerated, and silicon atoms are gradually corroded and dissolved. The etching time is precisely controlled at 12 minutes. After etching, nanoconical depressions with a depth of 2μm are formed in the tip and sidewall regions, and the spacing between these depressions is 3μm.

[0186] 4. Post-processing: (1) Cleaning: Preliminary cleaning: After etching is complete, remove the silicon wafer from the etching solution and immediately rinse it with plenty of deionized water to remove residual acid and impurities from the surface.

[0187] Ultrasonic cleaning: Place the silicon wafer in an ultrasonic cleaning tank, add an appropriate amount of deionized water, turn on the ultrasonic cleaning equipment, and perform ultrasonic cleaning. Ultrasonic cleaning utilizes the cavitation effect of ultrasonic waves to remove tiny impurities and metal particles from the surface of the silicon wafer.

[0188] Chemical cleaning: Specific chemical cleaning agents are used to further clean the silicon wafers, removing metal ions and compounds from the surface. For example, solutions such as hydrofluoric acid (HF) can be used to remove the oxide layer on the silicon wafer surface.

[0189] Drying process: After cleaning, the silicon wafers are dried with nitrogen or placed in an oven to ensure that the surface of the silicon wafers is dry and free of moisture residue.

[0190] (2) A passivation layer and an anti-reflection layer are deposited on both sides to complete the preparation of the solar electrode.

[0191] (3) A positive electrode is prepared in the P region on the back side and a negative electrode is prepared in the N region to obtain a solar cell.

[0192] Comparative Example 1 In this comparative example, an inverted pyramid scheme is used to fabricate solar electrodes and solar cells.

[0193] Experimental methods: 1. Initial surface treatment: Perform the first double-sided polishing treatment on the silicon substrate (silicon wafer).

[0194] 2. Set up the light-receiving surface and the backlight surface (N-zone, P-zone, isolation zone), and prepare the backlight surface: (1) A first tunneling silicon oxide layer, a boron-doped polycrystalline silicon layer and a borosilicate glass layer are sequentially formed on the back side (backlight side); (2) Perform the first laser patterning process on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region.

[0195] (3) Perform a second double-sided polishing process to remove the first tunneling oxide layer and boron-doped polysilicon layer in the N-region and isolation region on the back side.

[0196] (4) A second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are formed on both sides of the silicon wafer.

[0197] (5) Perform a second laser patterning process on the back of the silicon wafer to remove the phosphorus silicate glass layer in the P-region and the isolation region.

[0198] 3. Texturing and etching: (1) Perform wet etching on the front side (light-receiving side) of the silicon wafer to remove all layers on the front side and remove the coating around the side.

[0199] (2) Double-sided texturing: the P region is etched to the boron-doped polycrystalline silicon layer, the N region is etched to the phosphorus-doped polycrystalline silicon layer, and the isolation region is etched to the silicon wafer. The isolation region on the back side of the silicon wafer and the front side of the silicon wafer form a texturized surface.

[0200] The formation of the inverted pyramid: ① Solution formulation: NaOH / KOH (1.5%) + nucleating agent (cyclodextrin, concentration 0.00007wt%) ② Two-step process: Step 1: High-concentration nucleating agent alkaline solution (85℃) forms an inverted pyramid-like substrate; Step 2: Low-concentration nucleating agent alkaline solution (70℃) modifies and removes the damaged layer.

[0201] ③ Performance: Reflectivity 7.25%, TBC cell efficiency gain 0.19%.

[0202] ④ Alkali etching with special additives: Additive components: nonionic surfactant (25%) + cationic surfactant (35%) + polyethylene glycol (6%).

[0203] ⑤ Process: Alkaline solution (NaOH 1%) + additives, etched at 82℃ for 13 minutes to form (111) crystal face inverted pyramid.

[0204] 4. Post-processing: (1) Cleaning: Preliminary cleaning: After etching is complete, remove the silicon wafer from the etching solution and immediately rinse it with plenty of deionized water to remove residual acid and impurities from the surface.

[0205] Ultrasonic cleaning: Place the silicon wafer in an ultrasonic cleaning tank, add an appropriate amount of deionized water, turn on the ultrasonic cleaning equipment, and perform ultrasonic cleaning. Ultrasonic cleaning utilizes the cavitation effect of ultrasonic waves to remove tiny impurities and metal particles from the surface of the silicon wafer.

[0206] Chemical cleaning: Specific chemical cleaning agents are used to further clean the silicon wafers, removing metal ions and compounds from the surface. For example, solutions such as hydrofluoric acid (HF) can be used to remove the oxide layer on the silicon wafer surface.

[0207] Drying process: After cleaning, the silicon wafers are dried with nitrogen or placed in an oven to ensure that the surface of the silicon wafers is dry and free of moisture residue.

[0208] (2) A passivation layer and an anti-reflection layer are deposited on both sides to complete the preparation of the solar electrode.

[0209] (3) A positive electrode is prepared in the P region on the back side and a negative electrode is prepared in the N region to obtain a solar cell.

[0210] Comparative Example 2 In this comparative example, a "large-small" composite textured surface structure was formed by secondary growth of small pyramids on the surface of a large pyramid to prepare solar electrodes and solar cells.

[0211] Experimental methods: 1. Initial surface treatment: Perform the first double-sided polishing treatment on the silicon substrate (silicon wafer).

[0212] 2. Set up the light-receiving surface and the backlight surface (N-zone, P-zone, isolation zone), and prepare the backlight surface: (1) A first tunneling silicon oxide layer, a boron-doped polycrystalline silicon layer and a borosilicate glass layer are sequentially formed on the back side (backlight side); (2) Perform the first laser patterning process on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region.

[0213] (3) Perform a second double-sided polishing process to remove the first tunneling oxide layer and boron-doped polysilicon layer in the N-region and isolation region on the back side.

[0214] (4) A second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are formed on both sides of the silicon wafer.

[0215] (5) Perform a second laser patterning process on the back of the silicon wafer to remove the phosphorus silicate glass layer in the P-region and the isolation region.

[0216] 3. Texturing and etching: (1) Perform wet etching on the front side (light-receiving side) of the silicon wafer to remove all layers on the front side and remove the coating around the side.

[0217] (2) Double-sided texturing: the P region is etched to the boron-doped polycrystalline silicon layer, the N region is etched to the phosphorus-doped polycrystalline silicon layer, and the isolation region is etched to the silicon wafer. The isolation region on the back side of the silicon wafer and the front side of the silicon wafer form a texturized surface.

[0218] The "large-small" composite velvet structure is formed: The first texturing process is performed on the solar cell after the first etching to form the first pyramid textured surface structure, resulting in a silicon wafer with a first texturing process. The first texturing process is followed by a second etching process to remove the top of the first pyramid texturing structure, resulting in a second-etched silicon wafer. The polished solar cell is then texturized a second time to form a second pyramid textured structure at the top of the first pyramid textured structure and at the connection between the first pyramid textured structures, thus obtaining the silicon wafer used to prepare the solar cell; wherein, the base side length of the second pyramid textured structure is smaller than the base side length of the first pyramid textured structure, and the height of the second pyramid textured structure is smaller than the height of the first pyramid textured structure.

[0219] The silicon wafer is etched first and second using etching additives and alkaline solutions. The etching additive, by weight percentage, comprises: sodium benzoate: 1.3%, defoamer: 3.5%, surfactant: 7.5%, etching optimization additive: 5%, and the balance being water, totaling 100%. The etching optimization additive is composed of isopropanol and other solvents in any proportion, wherein the other solvents are any one or more of glucose, sodium gluconate, potassium gluconate, propylene glycol, sodium silicate, sodium carbonate, and sodium bicarbonate.

[0220] The first etching uses a first etching solution obtained by mixing etching additives and an alkaline solution. The first etching solution, by mass percentage, includes: alkali: 1%, etching additive: 1.3%, and the balance being water, totaling 100%. The second etching process uses a second polishing solution obtained by mixing etching additives and an alkaline solution. The second etching solution comprises, by mass percentage: alkali: 0.8%, etching additive: 0.9%, and the balance being water, totaling 100%.

[0221] During the first etching of the silicon wafer, the temperature was controlled at 76°C and the time was controlled at 105 seconds; and / or The texturing solution used in the first texturing process comprises, by weight percentage: alkali: 0.7%, texturing additive: 0.3%, and the balance being water, totaling 100%; and / or The texturing solution used in the second texturing process, by mass percentage, includes: alkali: 0.8%, texturing additive: 0.5%, and the balance being water, totaling 100%.

[0222] The fabrication additive, by weight percentage, comprises: potassium sorbate: 1%; sodium acetate: 2%; defoamer: 5%; surfactant: 5%; fabrication optimization additive: 6%; and the balance is water, totaling 100%. The fabrication optimization additive is prepared by mixing isopropanol and fabrication solvent in any proportion, wherein the fabrication solvent is any one or more of glucose, sodium gluconate, potassium gluconate, propylene glycol, sodium silicate, sodium carbonate, and sodium bicarbonate.

[0223] During the first texturing process, the temperature is controlled at 70℃, the time at 100s, and the pH value at 9; and / or During the second texturing process, the temperature is controlled at 82℃, the time is controlled at 350s, and the pH value is controlled at 14.

[0224] 4. Post-processing: (1) Cleaning: Preliminary cleaning: After etching is complete, remove the silicon wafer from the etching solution and immediately rinse it with plenty of deionized water to remove residual acid and impurities from the surface.

[0225] Ultrasonic cleaning: Place the silicon wafer in an ultrasonic cleaning tank, add an appropriate amount of deionized water, turn on the ultrasonic cleaning equipment, and perform ultrasonic cleaning. Ultrasonic cleaning utilizes the cavitation effect of ultrasonic waves to remove tiny impurities and metal particles from the surface of the silicon wafer.

[0226] Chemical cleaning: Specific chemical cleaning agents are used to further clean the silicon wafers, removing metal ions and compounds from the surface. For example, solutions such as hydrofluoric acid (HF) can be used to remove the oxide layer on the silicon wafer surface.

[0227] Drying process: After cleaning, the silicon wafers are dried with nitrogen or placed in an oven to ensure that the surface of the silicon wafers is dry and free of moisture residue.

[0228] (2) A passivation layer and an anti-reflection layer are deposited on both sides to complete the preparation of the solar electrode.

[0229] (3) A positive electrode is prepared in the P region on the back side and a negative electrode is prepared in the N region to obtain a solar cell.

[0230] Test experiment: 1. Test items: A. Light capture efficiency test: In this test, the reflectivity of the battery surface is measured to evaluate the light-harvesting efficiency.

[0231] Test method: Equipment: Ultraviolet-visible spectrophotometer.

[0232] Wavelength range: The test wavelength range is 300nm~1100nm.

[0233] Steps: (1) Place the prepared BC cell on the sample holder of the spectrophotometer. (2) Adjust the equipment to ensure stable measurement conditions. (3) Record the reflectance data at different wavelengths. (4) Calculate the average reflectance and compare it with the traditional BC cell structure.

[0234] B. Photoelectric conversion efficiency test: This test item evaluates the photoelectric conversion efficiency of the battery.

[0235] Test method: Equipment: A standard sunlight simulator is used.

[0236] Test conditions: The test was conducted under standard AM1.5G illumination conditions.

[0237] Steps: (1) Place the prepared BC cell on the test platform of the solar simulator. (2) Adjust the equipment to ensure that the light intensity and spectral distribution meet the AM1.5G standard. (3) Measure the output current and voltage of the cell and calculate the photoelectric conversion efficiency. (4) Repeat the test multiple times to ensure the reliability of the data.

[0238] Analysis of C-carrier transport characteristics: This test evaluates the transport characteristics and lifetime of charge carriers.

[0239] Test method: Equipment: Time-resolved photoluminescence spectroscopy (TRPL) technology is used.

[0240] Steps: (1) Place the prepared BC cell on the sample holder of the TRPL device. (2) Excite the cell to generate a photoluminescence signal. (3) Record the decay curve of the photoluminescence signal. (4) Calculate the carrier lifetime by analyzing the decay curve.

[0241] Analysis of the uniformity of antireflective layer deposition: In this test, the uniformity of the anti-reflective layer deposition was evaluated.

[0242] Test method: Equipment: Scanning electron microscope (SEM) and atomic force microscope (AFM) were used.

[0243] Steps: (1) Observe the surface of the prepared BC battery using a scanning electron microscope (SEM) and record the surface morphology of the antireflective layer. (2) Measure the thickness distribution of the antireflective layer using an atomic force microscope (AFM). (3) Analyze the thickness distribution data and calculate the thickness deviation.

[0244] 2. Test Results: Table 2. Performance test results of the examples and comparative examples

[0245] analyze: To verify the technical effectiveness of the solar cell structure design and fabrication process of this application, this application conducted performance comparison tests between Examples 1 to 5 and Comparative Examples 1 and 2, and tested the key electrical performance parameters of the solar cell under the same test conditions, including open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), and photoelectric conversion efficiency (Eff). The test results are summarized in Table 2 above.

[0246] The test results show that: (1) The Voc values ​​of the embodiments were generally higher than those of the comparative examples, with values ​​concentrated between 0.7378 and 0.7402 V. Among them, the highest value of 0.7402 V was achieved in Example 4, which was slightly higher than 0.7385 V and 0.7375 V of Comparative Examples 1 and 2, respectively. This result shows that the present invention effectively enhances the surface passivation quality, suppresses carrier recombination, and improves minority carrier lifetime by introducing a nanoconical recessed structure into the pyramidal textured surface structure, thereby achieving a steady increase in open-circuit voltage.

[0247] (2) The Jsc (expressed in current form) of the embodiments was generally slightly higher than that of the comparative examples, with values ​​between 8.22 and 8.26 A. Among them, the highest value of 8.26 A was achieved in embodiment 4, which was higher than that of comparative example 1 (8.19 A) and comparative example 2 (8.22 A). The nano-recessed structure improved the scattering and trapping effect of incident light, effectively enhanced the absorption capacity in the mid-to-long wavelength range, and improved the photocurrent.

[0248] (3) The FF values ​​of the examples were all higher than those of the comparative examples, ranging from 84.12% to 84.47%, with Example 4 reaching the highest value of 84.47%, which was significantly better than Comparative Example 1 (83.27%) and Comparative Example 2 (84.03%). The optimized nanostructure improved the electrode contact morphology, reduced the series resistance, and enhanced the extraction and transport efficiency of charge carriers.

[0249] (4) The overall Eff of the examples is higher than that of the comparative examples. Among them, Example 4 achieved the highest efficiency of 26.91%, which is higher than that of Comparative Example 1 (26.34%) and Comparative Example 2 (26.63%), with a maximum improvement of 0.57%. This shows that by constructing a nano-conical concave structure and optimizing the preparation process, the light-harvesting ability and charge separation and transport efficiency of the solar cell are significantly enhanced, and the overall performance is steadily improved.

[0250] (5) In addition, refer to Figure 2The auxiliary test results show that the average surface reflectivity of the solar cell in the embodiment is controlled between 2.76% and 3.12%, which is much lower than that of Comparative Example 1 (7.25%) and Comparative Example 2 (5.53%), further verifying the effectiveness of nanostructure design in reducing reflection loss and improving photon utilization.

[0251] In summary, all key test indicators of the present invention in the embodiments are superior to those of the comparative examples, which fully demonstrates that the nanostructure design and fabrication process adopted has significant technical advantages in improving light absorption efficiency, reducing carrier recombination, and optimizing electrode contact, effectively achieving the technical objectives and expected effects proposed in this application, and has good practicality and industrialization value.

[0252] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A solar cell, characterized in that, The solar cell has a microstructured surface for light capture; the microstructured surface is a velvety surface composed of multiple individual pyramidal structures. The monolithic pyramid structure contains nano-conical recesses.

2. The solar cell as described in claim 1, characterized in that, The nanoconical recesses are distributed in the apex region of the monolithic pyramid structure and in the sidewall region extending away from the apex region.

3. The solar cell as described in claim 1, characterized in that, The nanoconical depression has at least one of the following characteristics: A. Depth is 1μm~3μm; B. Diameter range of 5μm to 20μm; C. The spacing between the nanoconical depressions is 2μm~5μm.

4. A solar cell, characterized in that, Includes the solar cell as described in any one of claims 1-3.

5. An electrical-related device, characterized in that, Including the solar cell as described in claim 4.

6. A method for preparing a solar cell as described in any one of claims 1-3, characterized in that, include: The silicon wafer undergoes initial surface treatment, one side of the silicon wafer is designated as the light-receiving surface, the other side is designated as the backlight surface, and an isolation area is provided on the backlight surface. The isolation area of ​​the light-receiving surface and the backlight surface is used as the surface to be processed, and the surface to be processed is subjected to a texturing process to form a pyramid structure with a texturing surface. Catalyst localization deposition and anisotropic etching of the deposited catalyst are performed on the surface to be treated after forming a pyramid structure to form nanoconical depressions distributed in the pyramid structure, thereby obtaining a solar cell.

7. The method for preparing a solar cell as described in claim 6, characterized in that, The catalyst localization deposition includes: The surface to be treated is coated with photosensitive adhesive to form a photosensitive adhesive film; A photomask is placed over the surface of the photosensitive adhesive film. The light area of ​​the photolithography equipment is used to expose the pyramid structure’s apex and sidewall areas, causing the photosensitive adhesive in the apex and sidewall areas to undergo a photochemical reaction based on the pattern on the photomask, forming the exposure area. The exposed silicon wafer is placed in a deposition solution containing metal particles to perform metal nanocatalyst deposition treatment, thereby obtaining a silicon wafer in which the metal particles are deposited in the exposed area. The surface to be treated after catalyst localization deposition is obtained by cleaning and removing the photosensitive adhesive and undeposited metal particles from the non-exposed areas where no photochemical reaction has occurred.

8. The method for preparing a solar cell as described in claim 7, characterized in that, In the deposition solution, the metal particles are Cu nanoparticles and / or Ag nanoparticles; The particle size of the metal particles is 50nm~200nm.

9. The method for preparing a solar cell as described in claim 6, characterized in that, The anisotropic etching process includes: The silicon wafer, which has been deposited with the catalyst, is placed in an etching solution for selective catalytic etching to obtain an etched silicon wafer. The etched silicon wafer is removed from the etching solution and cleaned to obtain a solar cell.

10. The method for preparing a solar cell as described in claim 9, characterized in that, The conditions for the selective catalytic etching reaction include at least one of the following reaction conditions: A. The reaction temperature is 30℃~60℃; B. The reaction time is 5 to 15 minutes; C. The etching solution is a mixed acid solution prepared from HNO3 and H2SO4; D. The etching solution is a mixed acid solution prepared from HNO3 and H2SO4, and satisfies HNO3:H2SO4=1:(2~4).

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