A light emitting diode chip and a method of manufacturing the same

Abstract

The application discloses a light emitting diode chip and a preparation method thereof. The preparation method comprises the following steps: providing a sapphire substrate, depositing an N-type GaN layer, an active light emitting layer and a P-type GaN layer on the sapphire substrate in sequence to form a first epitaxial layer on the substrate; etching part of the P-type GaN layer on the first epitaxial layer until the N-type GaN layer is exposed to form an N-type GaN layer conductive step on the first epitaxial layer and form a second epitaxial layer on the substrate; etching part of the P-type GaN layer on the second epitaxial layer to form a groove, the groove extends into the N-type GaN layer, the groove divides the epitaxial layer into a main light emitting part and an isolation channel part, and a third epitaxial layer is formed. The application aims to solve the technical problem that, in the prior art, the photoetching alignment deviation is caused by the wafer warping after laser stripping, thereby affecting the isolation channel forming precision and the chip yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to a light-emitting diode chip and its fabrication method. Background Technology

[0002] Light-emitting diodes (LEDs), as an energy-saving and environmentally friendly solid-state light source, have been widely used in lighting, display, and backlighting. Among them, vertical LED chips are particularly suitable for high-power applications such as automotive lighting due to their advantages such as large bonding area and high thermal conductivity.

[0003] However, fabricating vertical LED chips requires bonding and laser lift-off processes. After bonding and laser lift-off, the LED wafer warps, with the warping increasing closer to the wafer edge. In current processes, the isolation channels of LED chips are typically fabricated after laser lift-off using photolithography and plasma etching. Due to wafer warping, lithography misalignment occurs during photolithography; the greater the warping, the greater the misalignment, leading to an increased failure rate in the chip edge region and a decreased yield.

[0004] Existing technologies primarily reduce warpage by optimizing bonding process parameters, adjusting substrate materials, or introducing temporary bonding or debonding techniques. However, these methods all increase process complexity and cost, and cannot completely eliminate the impact of warpage on photolithography alignment. Some solutions also employ laser lift-off followed by direct etching to form isolation channels, but the etching depth control and uniformity are significantly affected by warpage. Therefore, how to form isolation channels for LED chips with high precision and low cost while avoiding the impact of warpage on photolithography alignment has become a pressing technical problem to be solved in this field. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a light-emitting diode chip and its fabrication method, thereby solving the technical problem in the prior art where wafer warping after laser stripping leads to photolithography alignment deviations, which in turn affect the accuracy of isolation channel formation and chip yield.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: A method for fabricating a light-emitting diode (LED) chip includes the following steps: S1, a sapphire substrate is provided, and an N-type GaN layer, an active light-emitting layer and a P-type GaN layer are sequentially deposited on the sapphire substrate to form a first epitaxial layer on the substrate; S2, etching a portion of the P-type GaN layer on the first epitaxial layer until the N-type GaN layer is exposed, so as to form an N-type GaN layer conductive step on the first epitaxial layer and form a second epitaxial layer on the substrate; S3, a portion of the P-type GaN layer is etched on the second epitaxial layer to form a trench. The trench extends into the N-type GaN layer. There is an N-type GaN layer between the bottom of the trench and the sapphire substrate. The trench divides the second epitaxial layer into a main light-emitting part and an isolation channel part, and forms a third epitaxial layer. S4, a transition dielectric layer and a P-type pad are prepared on the side of the third epitaxial layer facing away from the sapphire substrate. The transition dielectric layer covers the isolation channel, the inner wall of the trench, and the bottom of the trench. The P-type pad covers the transition dielectric layer and extends to the main light-emitting part. One end of the P-type pad is flush with the transition dielectric layer, and there is a distance between the other end of the P-type pad and the other end of the transition dielectric layer, forming a fourth epitaxial layer. S5, a semiconductor layer is prepared on the side of the fourth epitaxial layer opposite to the sapphire substrate. The semiconductor layer includes a current spreading layer, a first insulating protective layer, a metal reflective layer, a second insulating layer, a bonding metal layer, and a conductive silicon substrate arranged sequentially. S6, remove the sapphire substrate to expose the N-type GaN layer, vaporize and decompose the N-type GaN layer corresponding to the trench location to expose the transition dielectric layer, and etch the transition dielectric layer with an etchant to cause the isolation channel to automatically detach.

[0007] Further, the step of preparing a P-type pad on the side of the third epitaxial layer facing away from the sapphire substrate includes: coating a negative photoresist on the area of ​​the P-type GaN layer not covered by the transition dielectric layer within the transition dielectric layer and the main light-emitting part; exposing the photoresist in the area to be formed of the P-type pad by exposure using a mask; removing the photoresist in the unexposed area after development; sequentially depositing a first Ti metal layer, an Au metal layer, a first Ni metal layer, and a second Ti metal layer using an electron beam evaporation process; and then removing the photoresist and the metal on it using a lift-off process to form the P-type pad, wherein the thickness of the first Ti metal layer is 30 Å to 50 Å, the thickness of the Au metal layer is 5000 Å to 10000 Å, the thickness of the first Ni metal layer is 1000 Å to 2000 Å, and the thickness of the second Ti metal layer is 1000 Å to 2000 Å.

[0008] Furthermore, the step of fabricating a semiconductor layer on the side of the fourth epitaxial layer opposite to the sapphire substrate includes: A current spreading layer is prepared on the side of the fourth epitaxial layer opposite to the sapphire substrate to form a fifth epitaxial layer; A first insulating protective layer is prepared on the side of the fifth epitaxial layer facing away from the sapphire substrate, and a pad-type first insulating protective layer via, a P-type first insulating protective layer and an N-type first insulating protective layer are formed in the first insulating protective layer to form a sixth epitaxial layer; A metal reflective layer is prepared on the side of the sixth epitaxial layer that faces away from the sapphire substrate to form the seventh epitaxial layer; A second insulating layer is prepared on the side of the seventh epitaxial layer facing away from the sapphire substrate, and an N-type second insulating layer via is formed in the second insulating layer to form an eighth epitaxial layer; A first bonding metal is prepared on the side of the eighth epitaxial layer that is opposite to the sapphire substrate; A conductive silicon substrate is provided, and a second bonding metal is fabricated on the conductive silicon substrate; The first bonding metal is bonded to the second bonding metal to form the bonding metal layer.

[0009] Furthermore, the specific steps for fabricating a current spreading layer on the side of the fourth epitaxial layer facing away from the sapphire substrate include: A negative photoresist is applied to the surfaces of the transition dielectric layer, the P-type pad, and the fourth epitaxial layer that are not covered by the transition dielectric layer and the P-type pad. The photoresist in the area where the current spreading layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. An ITO thin film is sputtered using a magnetron sputtering process. Then, the photoresist and the ITO thin film on it are removed using a lift-off process to form the current spreading layer.

[0010] Furthermore, the specific steps for fabricating a metal reflective layer on the side of the sixth epitaxial layer facing away from the sapphire substrate include: Negative photoresist is coated in the first insulating protective layer and the via of the pad-type first insulating protective layer. The photoresist in the area to be formed of the metal reflective layer is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. An Ag metal layer, a third Ti metal layer, a second Ni metal layer, a fourth Ti metal layer, a third Ni metal layer, and a fifth Ti metal layer are sequentially deposited using an electron beam evaporation process. Then, the photoresist and the metal on it are removed using a lift-off process to form the metal reflective layer. The thickness of the Ag metal layer is 1200 Å to 2000 Å, the thickness of the third Ti metal layer is 1000 Å to 2000 Å, the thickness of the second Ni metal layer is 1000 Å to 2000 Å, the thickness of the fourth Ti metal layer is 1000 Å to 2000 Å, the thickness of the third Ni metal layer is 1000 Å to 2000 Å, and the thickness of the fifth Ti metal layer is 30 Å to 50 Å.

[0011] Furthermore, the specific steps of fabricating a first bonding metal on the side of the eighth epitaxial layer facing away from the sapphire substrate and fabricating a second bonding metal on the conductive silicon substrate include: Negative photoresist is coated in the second insulating layer and the vias of the N-type second insulating layer. Exposure is achieved using a photomask to expose the photoresist in the region where the first bonding metal is to be formed. After development, the unexposed photoresist is removed. Electron beam evaporation is then used to sequentially deposit the first Cr metal layer, the sixth Ti metal layer, the fourth Ni metal layer, the seventh Ti metal layer, the fifth Ni metal layer, and the first AuSn alloy metal layer. A lift-off process is then used to remove the photoresist and the metal on it to form the first bonding metal. On the conductive silicon substrate, electron beam evaporation is then used to sequentially deposit the second Cr metal layer, the eighth Ti metal layer, the sixth Ni metal layer, the ninth Ti metal layer, the seventh Ni metal layer, and the second AuSn alloy metal layer. A gold metal layer is formed to form a second bonding metal; wherein the thickness of the first Cr metal layer and the second Cr metal layer is 30 Å to 50 Å, the thickness of the sixth Ti metal layer and the eighth Ti metal layer is 1000 Å to 2000 Å, the thickness of the fourth Ni metal layer and the sixth Ni metal layer is 1000 Å to 2000 Å, the thickness of the seventh Ti metal layer and the ninth Ti metal layer is 1000 Å to 2000 Å, the thickness of the fifth Ni metal layer and the seventh Ni metal layer is 10000 Å to 15000 Å, and the thickness of the first AuSn alloy metal layer and the second AuSn alloy metal layer is 15000 Å to 20000 Å.

[0012] Furthermore, the thickness between the bottom of the trench and the sapphire substrate ranges from 100 Å to 1000 Å, and the distance between the other end of the P-type pad and the other end of the transition dielectric layer is from 3 μm to 5 μm.

[0013] Furthermore, the material of the transition medium layer is SiO2, and the etching solution is BOE solution.

[0014] A light-emitting diode (LED) chip is fabricated using the above-described LED chip fabrication method.

[0015] Compared with existing technologies, the advantages of this invention are as follows: By preparing trenches and transition dielectric layers before the bonding process, and then automatically detaching the epitaxial layer's isolation channels after the laser lift-off process by etching the transition dielectric layer, the method avoids the photolithographic alignment deviation problem caused by existing methods that form isolation channels through photolithography and plasma etching after the laser lift-off process. Since both the trenches and transition dielectric layers are prepared before bonding, the wafer is warped, photolithographic alignment is precise, and only one BOE etching step is needed after laser lift-off to form the isolation channels, eliminating the need for additional photolithography and etching processes, simplifying the process and improving yield. Simultaneously, the thickness of the N-type GaN layer between the bottom of the trench and the sapphire substrate is vaporized and decomposed during the laser lift-off process, effectively protecting the transition dielectric layer within the trench from cracking during laser lift-off, thereby avoiding the impact of warping on photolithographic alignment and achieving high-precision, low-cost fabrication of the isolation channels. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of the first epitaxial layer after step S1 is completed in the method for fabricating a light-emitting diode chip according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the second epitaxial layer after step S2 is completed in the method for fabricating a light-emitting diode chip according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the third epitaxial layer after step S3 in the fabrication method of the light-emitting diode chip according to an embodiment of the present invention, which shows the trench; Figure 4 This is a schematic diagram of the structure after step S4 of the method for fabricating a light-emitting diode chip according to an embodiment of the present invention, showing the transition dielectric layer and the P-type pad; Figure 5 This is a schematic diagram of the structure after the current spreading layer is prepared in step S5 of the method for preparing a light-emitting diode chip according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the first insulating protective layer and the pad-type through-hole of the first insulating protective layer are prepared in step S5 of the method for preparing a light-emitting diode chip according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure after the metal reflective layer is prepared in step S5 of the method for preparing a light-emitting diode chip according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure after the second insulating layer and the N-type second insulating layer through-hole are prepared in step S5 of the method for preparing a light-emitting diode chip according to an embodiment of the present invention. Figure 9This is a schematic diagram of the structure after the first bonding metal is prepared in step S5 of the method for preparing a light-emitting diode chip according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure after providing a conductive silicon substrate, preparing a second bonding metal, and bonding in step S5 of the method for fabricating a light-emitting diode chip according to an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure after step S6 of the method for fabricating a light-emitting diode chip according to an embodiment of the present invention, in which the sapphire substrate is peeled off and the N-type GaN layer is exposed. Figure 12 This is a schematic diagram of the structure formed by the isolation channel after step S6 in the fabrication method of the light-emitting diode chip according to an embodiment of the present invention.

[0017] 10. Sapphire substrate; 11. First epitaxial layer; 111. N-type GaN layer; 112. Active light-emitting layer; 113. P-type GaN layer; 114. Conductive step of N-type GaN layer; 115. Trench; 12. Transition dielectric layer; 13. P-type pad; 14. Current spreading layer; 151. Pad-type first insulating protective layer via; 152. P-type first insulating protective layer; 153. N-type first insulating protective layer; 16. Metal reflective layer; 17. Second insulating layer; 171. N-type second insulating layer via; 181. First bonding metal; 182. Second bonding metal; 19. Conductive silicon substrate; 20. Isolation channel; 21. Main light-emitting part.

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0020] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," "up," "down," and similar expressions used herein are for illustrative purposes only and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0021] In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0022] Example 1: Please see Figures 1 to 12 A method for fabricating a light-emitting diode chip includes the following steps: S1, a sapphire substrate 10 is provided, and an N-type GaN layer 111, an active light-emitting layer 112, and a P-type GaN layer 113 are sequentially deposited on the sapphire substrate 10 to form a first epitaxial layer 11 on the substrate, such as... Figure 1 As shown; S2, a portion of the P-type GaN layer 113 is etched on the first epitaxial layer 11 until the N-type GaN layer 111 is exposed, so as to form an N-type GaN layer conductive step 114 on the first epitaxial layer 11, and a second epitaxial layer is formed on the substrate, as follows. Figure 2 As shown; S3, a portion of the P-type GaN layer 113 is etched on the second epitaxial layer to form a trench 115. The trench 115 extends into the N-type GaN layer 111, and the distance between the bottom of the trench 115 and the sapphire substrate 10 is 500 Å. That is, there is a 500 Å thick N-type GaN layer 111 between the bottom of the trench 115 and the sapphire substrate 10. The trench 115 divides the second epitaxial layer into a main light-emitting portion 21 and an isolation channel portion 20, forming a third epitaxial layer, such as... Figure 3 As shown; S4, a transition dielectric layer 12 and a P-type pad 13 are prepared on the side of the third epitaxial layer facing away from the sapphire substrate 10: The specific steps for preparing the transition dielectric layer 12 are as follows: a negative photoresist is coated on the side of the third epitaxial layer facing away from the sapphire substrate 10; part of the photoresist is removed by exposure and development; SiO2 is deposited using an electron beam evaporation process; and then the photoresist and the SiO2 on it are removed using a lift-off process to form the transition dielectric layer 12; the transition dielectric layer 12 covers the isolation channel 20, the inner wall of the trench 115, and the bottom of the trench; The specific steps for preparing the P-type pad 13 are as follows: A negative photoresist is coated on the area of ​​the P-type GaN layer 113 within the transition dielectric layer 12 and the main light-emitting part 21 that is not covered by the transition dielectric layer 12. The photoresist in the area to be formed as the P-type pad is exposed using a photomask. After development, the photoresist in the unexposed area is removed. Then, a first Ti metal layer, an Au metal layer, a first Ni metal layer, and a second Ti metal layer are sequentially deposited using an electron beam evaporation process. The thickness of the first Ti metal layer is 30 Å to 50 Å, and the thickness of the Au metal layer is 5000 Å to 5000 Å. The thickness of the first Ni metal layer is 10000 Å, the thickness of the second Ti metal layer is 1000 Å to 2000 Å, and the photoresist and its metal are removed using a lift-off process to form a P-type pad 13. The P-type pad 13 covers the transition dielectric layer 12 and extends to the main light-emitting part 21. One end of the P-type pad 13 is flush with the transition dielectric layer 12, and there is a distance of 4 μm between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12. This forms the fourth epitaxial layer, such as... Figure 4 As shown; S5, a semiconductor layer is fabricated on the side of the fourth epitaxial layer facing away from the sapphire substrate 10. The semiconductor layer includes a current spreading layer 14, a first insulating protective layer, a metal reflective layer 16, a second insulating layer 17, a bonding metal layer, and a conductive silicon substrate 19, which are sequentially disposed thereon. The specific steps include: A current spreading layer 14 is fabricated on the side of the fourth epitaxial layer facing away from the sapphire substrate 10 to form a fifth epitaxial layer. The specific steps for fabricating the current spreading layer 14 are as follows: negative photoresist is coated on the transition dielectric layer 12, the P-type pad 13, and the surfaces of the fourth epitaxial layer not covered by the transition dielectric layer 12 and the P-type pad 13. The photoresist in the area where the current spreading layer is to be formed is exposed using a photomask. After development, the photoresist in the unexposed areas is removed. An ITO thin film is sputtered using magnetron sputtering. Then, the photoresist and the ITO thin film on it are removed using a lift-off process to form the current spreading layer 14. Figure 5 As shown; A first insulating protective layer is prepared on the side of the fifth epitaxial layer facing away from the sapphire substrate 10. A pad-type first insulating protective layer via 151, a P-type first insulating protective layer 152, and an N-type first insulating protective layer 153 are formed within the first insulating protective layer to form a sixth epitaxial layer. The specific steps for preparing the first insulating protective layer are as follows: a SiO2 thin film is prepared using PECVD as the first insulating protective layer; photoresist is coated onto the surface of the first insulating protective layer; part of the photoresist is removed by exposure and development, exposing part of the first insulating protective layer; the exposed first insulating protective layer is removed using inductively coupled plasma etching; the photoresist is removed, forming the pad-type first insulating protective layer via 151, the P-type first insulating protective layer 152, and the N-type first insulating protective layer 153. Figure 6 As shown; A metal reflective layer 16 is prepared on the side of the sixth epitaxial layer facing away from the sapphire substrate 10 to form a seventh epitaxial layer. The specific steps for preparing the metal reflective layer 16 are as follows: negative photoresist is coated in the first insulating protective layer and the via 151 of the pad-type first insulating protective layer; the photoresist in the area to be formed of the metal reflective layer is exposed using a photomask; after development, the photoresist in the unexposed areas is removed; and an Ag metal layer, a third Ti metal layer, a second Ni metal layer, a fourth Ti metal layer, and a third Ni metal layer are sequentially deposited using an electron beam evaporation process. The metal layers are a first layer and a fifth Ti metal layer, wherein the thickness of the evaporated Ag metal layer is 1200 Å–2000 Å, the thickness of the third Ti metal layer is 1000 Å–2000 Å, the thickness of the second Ni metal layer is 1000 Å–2000 Å, the thickness of the fourth Ti metal layer is 1000 Å–2000 Å, the thickness of the third Ni metal layer is 1000 Å–2000 Å, and the thickness of the fifth Ti metal layer is 30 Å–50 Å. Then, the photoresist and the metal on it are removed using a lift-off process to form a metal reflective layer 16, such as... Figure 7 As shown; A second insulating layer 17 is prepared on the side of the seventh epitaxial layer facing away from the sapphire substrate 10, and an N-type second insulating layer via 171 is formed in the second insulating layer 17 to form the eighth epitaxial layer. The specific steps for preparing the second insulating layer 17 are as follows: a SiO2 thin film is prepared as the second insulating layer 17 on the surface of the metal reflective layer 16 and the first insulating protective layer not covered by the metal reflective layer 16 using a PECVD process; photoresist is coated on the surface of the second insulating layer 17; part of the photoresist is removed by exposure and development, exposing part of the second insulating layer; the exposed second insulating layer is removed using an inductively coupled plasma etching process; the photoresist is removed, forming the N-type second insulating layer via 171. Figure 8 As shown; A first bonding metal 181 is prepared on the side of the eighth epitaxial layer facing away from the sapphire substrate 10. The specific steps for preparing the first bonding metal 181 are as follows: negative photoresist is coated in the second insulating layer 17 and the N-type second insulating layer via 171; the photoresist in the area to be formed of the first bonding metal is exposed by a photomask; after development, the photoresist in the unexposed area is removed; and the first Cr metal layer, the sixth Ti metal layer, the fourth Ni metal layer, the seventh Ti metal layer, the fifth Ni metal layer, and the first AuSn alloy are sequentially deposited using an electron beam evaporation process. The metal layers are as follows: the thickness of the first Cr metal layer is 30 Å to 50 Å; the thickness of the sixth Ti metal layer is 1000 Å to 2000 Å; the thickness of the fourth Ni metal layer is 1000 Å to 2000 Å; the thickness of the seventh Ti metal layer is 1000 Å to 2000 Å; the thickness of the fifth Ni metal layer is 10000 Å to 15000 Å; and the thickness of the first AuSn alloy metal layer is 15000 Å to 20000 Å. Then, the photoresist and the metal on it are removed using a lift-off process to form the first bonding metal 181. Figure 9 As shown; A conductive silicon substrate 19 is provided, and a second bonding metal 182 is prepared on the conductive silicon substrate 19. The specific steps for preparing the second bonding metal 182 are as follows: a second Cr metal layer, an eighth Ti metal layer, a sixth Ni metal layer, a ninth Ti metal layer, a seventh Ni metal layer, and a second AuSn alloy metal layer are sequentially deposited using an electron beam evaporation process. The thickness of each metal deposited is the same as that of the first bonding metal 181, so as to form the second bonding metal 182. The first bonding metal 181 and the second bonding metal 182 are bonded to form a bonding metal layer, such as Figure 10 As shown; S6, the sapphire substrate 10 is removed using a laser lift-off process, exposing the N-type GaN layer 111. The N-type GaN layer 111 at the bottom of the trench 115 is then vaporized and decomposed to expose the transition dielectric layer 12. The layer is then immersed in BOE etching solution and rinsed with water to etch the transition dielectric layer 12, causing the isolation channel 20 to automatically detach, forming an isolation channel. Figure 11 and Figure 12 As shown.

[0023] Example 2 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the thickness of the N-type GaN layer 111 between the bottom of the trench 115 and the sapphire substrate 10 is 100 Å.

[0024] Example 3 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the thickness of the N-type GaN layer 111 between the bottom of the trench 115 and the sapphire substrate 10 is 1000 Å.

[0025] Example 4 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the distance between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12 is 3μm.

[0026] Example 5 This embodiment is basically the same as embodiment 1, except that in this embodiment, the distance between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12 is 5μm.

[0027] Comparative Example 1 This comparative example is basically the same as Example 1, except that the thickness of the N-type GaN layer 111 between the bottom of the trench 115 and the sapphire substrate 10 is 50 Å.

[0028] Comparative Example 2 This comparative example is basically the same as Example 1, except that the thickness of the N-type GaN layer 111 between the bottom of the trench 115 and the sapphire substrate 10 is 1200 Å.

[0029] Comparative Example 3 This comparative example is basically the same as Example 1, except that in this comparative example, the thickness of the N-type GaN layer 111 between the bottom of the trench 115 and the sapphire substrate 10 is 0 Å (i.e., completely etched through).

[0030] Comparative Example 4 This comparative example is basically the same as Example 1, except that in this comparative example, the distance between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12 is 2μm.

[0031] Comparative Example 5 This comparative example is basically the same as Example 1, except that in this comparative example, the distance between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12 is 6μm.

[0032] Comparative Example 6 This comparative example is basically the same as Example 1, except that in this comparative example, the P-type pad 13 covers the entire upper surface of the transition dielectric layer 12, and there is no distance between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12.

[0033] Comparative Example 7 This comparative example is basically the same as Example 1, except that the trench 115 and the transition dielectric layer 12 are not formed in this comparative example. After laser stripping, the isolation channel is formed by photolithography and inductively coupled plasma etching process.

[0034] The present invention also provides a light-emitting diode chip, which is manufactured using the preparation method described above.

[0035] Furthermore, performance tests were performed on the light-emitting diode chips prepared in all embodiments and comparative examples, as detailed below: Photolithography alignment deviation testing was performed using a KLA-Tencor Archer500 overlay accuracy measurement system. After the P-type pads were formed, three regions were selected on the wafer surface: the center, the midpoint of the radius (R / 2), and the edge. Nine measurement points were set in each region, for a total of 27 points. The positional deviation of the current layer's P-type pad overlay mark relative to the reference mark of the previous transition dielectric layer was measured. Test conditions: measurement wavelength 546nm, magnification 100×, alignment mark type Box-in-Box. The X and Y direction offsets of each measurement point were recorded, and the vector-synthesized photolithography alignment deviation was calculated, where R is the wafer radius.

[0036] Post-laser lift-off warpage testing was performed using a Bruker Contour GT-K white light interferometer. The laser-lifted 4-inch wafer (100mm diameter) was placed on a three-point support platform, with the support points evenly distributed at 120° intervals along the wafer edge. A scanning step of 1mm was set, covering the entire wafer, and surface height data was collected. The data was imported into Cobra software, and the least squares method was used to fit a reference plane to calculate the Bow value (height difference between the wafer center point and the reference plane). Each sample was measured three times, and the average value was taken as the warpage.

[0037] Isolation channel formation rate test: Using a Nikon LV100ND optical microscope (100× objective, 10× eyepiece, total magnification 1000×), after the wafer has undergone BOE etching and been dried with a nitrogen gun, each chip on the wafer surface was scanned individually. Observation criteria: A continuous, unbroken, and residue-free isolation channel was formed around the chip. The isolation channel formation rate was calculated as follows: Isolation channel formation rate = (Number of chips with complete isolation channels / Total number of chips) × 100%.

[0038] Chip yield testing: A Cascade Summit 12000B-M fully automated wafer prober, paired with a Keithley 2636B dual-channel source meter, was used to perform wafer-level optoelectronic testing on chips with completed isolation channels. Test conditions: injection current 350mA, voltage limit 5V, integration time 10ms, ambient temperature 25℃. Rejection criteria: leakage current >1μA@-5V, optical output power <standard value (based on 80% of the average optical power of chips using conventional processes), emission wavelength deviation 450nm±10nm. Yield calculation formula: Yield = (Number of chips passing test / Total number of chips) × 100%.

[0039] Relative luminous efficacy testing was conducted: Using a Labsphere LMS-100 integrating sphere testing system (1m diameter, equipped with an Ocean Optics QE Pro spectrometer), the optical output power Po of the example chip and the comparative example chip (conventional process) was measured under an injection current of 350mA. The system was calibrated using a standard halogen lamp before testing. Thirty chips were randomly selected from each sample to measure the optical output power, and the average value was taken. The formula for calculating the relative luminous efficacy improvement rate is: Relative luminous efficacy improvement rate = (P_example - P_conventional) / P_conventional × 100%, where P_example is the average optical output power measured for the example chip, and P_conventional is the average optical output power measured for the conventional process chip without trenches and transition dielectric layers in Comparative Example 7.

[0040] The specific parameters used in Examples 1 to 5 and Comparative Examples 1 to 7 during the manufacturing process of this invention, and the corresponding test results obtained, are shown in Table 1.

[0041] Table 1:

[0042] A comparison of Examples 1 to 5 with Comparative Examples 1 to 7 shows that: In Examples 1 to 3, the distance between the bottom of the trench 115 and the sapphire substrate 10, i.e., the existence of an N-type GaN layer 111 of the same thickness between the bottom of the trench and the sapphire substrate, is 500 Å, 100 Å, and 1000 Å, respectively. After laser lift-off, the warpage is 35 μm, 38 μm, and 42 μm, respectively; the isolation channel formation rates are 100%, 98%, and 100%, respectively; and the yields are 88%, 85%, and 86%, respectively. When the retained thickness is 500 Å, the warpage is minimal and the isolation channel is fully formed. When the retained thickness is 100 Å, the warpage slightly increases to 38 μm, and the isolation channel formation rate drops to 98%. When the retained thickness is 1000 Å, the warpage further increases to 42 μm, but the isolation channel can still be fully formed. In Comparative Example 1, the retained thickness is 50 Å. During laser lift-off, the SiO2 transition dielectric layer 12 breaks, the isolation channel formation rate is only 45%, and the chip completely fails. In Comparative Example 2, the thickness was 1200 Å. After laser lift-off, GaN remained at the bottom of trench 115, preventing the isolation channel from detaching. The formation rate was 0%, the warpage reached 45 μm, and the yield was only 35%. In Comparative Example 3, the thickness was 0 Å, which was enough for complete etching. SiO2 directly contacted the sapphire substrate 10. During laser lift-off, SiO2 completely ruptured, and the isolation channel could not be formed. This indicates that when the thickness of the N-type GaN layer 111 at the bottom of trench 115 is in the range of 100 Å to 1000 Å, it can both protect the SiO2 transition dielectric layer 12 from rupture during laser lift-off and ensure subsequent complete vaporization and decomposition to form a complete isolation channel. Below 100 Å, SiO2 ruptures; above 1000 Å, GaN remains, preventing the formation of the isolation channel.

[0043] In Examples 1, 4, and 5, the distances between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12 are 4 μm, 3 μm, and 5 μm, respectively. The isolation channel formation rate is 100% in all examples, with yields of 88%, 86%, and 87%, respectively, and relative luminous efficacy improvements of 12%, 10%, and 11%, respectively. When the distance is 3 μm, the other end of the P-type pad 13 is closer to the other end of the transition dielectric layer 12, resulting in a slight decrease in yield. When the distance is 5 μm, the area of ​​the P-type pad 13 is slightly smaller, resulting in a slight decrease in luminous efficacy improvement. In Comparative Example 4, the distance is 2 μm. During BOE etching, the edge of the P-type pad 13 is damaged, the isolation channel formation rate is 100%, and the yield drops to 68%. In Comparative Example 5, the distance is 6 μm. The area of ​​the P-type pad 13 is too small, the area of ​​the main light-emitting part 21 is reduced, the relative luminous efficacy is only improved by 6%, the isolation channel formation rate is 100%, and the yield remains at 87%. In Comparative Example 6, the distance was 0 μm, meaning there was no such distance between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12. During BOE etching, the transition dielectric layer 12 dissolved, causing the P-type pad 13 to be lifted and detached from the bottom. Although the isolation channel formation rate was 98%, the chip yield was 0. It is evident that a distance within the range of 3 μm to 5 μm can ensure the safety of the P-type pad 13 while maximizing the light-emitting area and yield.

[0044] Comparative Example 7 uses a conventional process without trenches 115 and a transition dielectric layer 12. After laser lift-off, isolation channels are formed using photolithography and inductively coupled plasma etching. Because photolithography is performed on the warped wafer after laser lift-off, the alignment deviation is as high as 3.20 μm, and the warpage is 65 μm. Although the isolation channel formation rate is 100%, the large positional deviation results in a yield of only 62%, with relative light efficiency as a baseline. Compared to Example 1, which has an alignment deviation of 0.12 μm, a warpage of 35 μm, a yield of 88%, and a relative light efficiency improvement of 12%, this invention avoids the influence of warpage on photolithography alignment by placing the trenches 115 and transition dielectric layer 12 before bonding, thereby achieving high-precision isolation channel formation and a significant improvement in yield and light efficiency.

[0045] It is worth noting that this invention forms isolation channels by preparing trenches 115 and transition dielectric layers 12 before the bonding process, and by etching the transition dielectric layer 12 after the laser lift-off process to automatically detach the isolation channels 20 of the epitaxial layer. The introduction and pre-preparation of the transition dielectric layer 12 play multiple roles: First, before the bonding process, both trenches 115 and the transition dielectric layer 12 are prepared on a flat, warp-free wafer surface, ensuring precise photolithography alignment and facilitating high-precision definition of the isolation channel position, thereby reducing the adverse effects of wafer warping after laser lift-off on photolithography alignment; Second, during bonding and subsequent processes, the transition dielectric layer 12 filling the trenches 115 can act as a sacrificial support layer, providing mechanical support to the trench sidewalls and bottom under high-temperature and high-pressure bonding conditions, helping to reduce the risk of trench collapse or deformation; Third, during laser lift-off... In the process, the N-type GaN layer 111 retained at the bottom of the trench 115 can act as a sacrificial layer to absorb laser energy and preferentially vaporize and decompose, thus protecting the underlying transition dielectric layer 12 from direct laser impact and cracking to a certain extent, allowing the transition dielectric layer 12 to maintain structural integrity after laser stripping. Fourth, after laser stripping, the intact transition dielectric layer 12 can act as an etching sacrificial layer, which can be dissolved and removed with only one BOE wet etching step, allowing the isolation channel 20 to automatically fall off and form an isolation channel. This eliminates the need for the laser stripping and plasma etching processes in traditional processes, which helps to simplify the process and reduce manufacturing costs.

[0046] In summary, by advancing the fabrication process of trench 115 and transition dielectric layer 12 before bonding, and strictly controlling the thickness of the N-type GaN layer 111 at the bottom of trench 115 to be between 100 Å and 1000 Å, and the distance between the other end of the P-type pad 13 and the other end of the transition dielectric layer 12 to between 3 μm and 5 μm, this invention can reduce the photolithography alignment deviation from 3.20 μm in traditional processes to 0.12 μm, reduce the warpage after laser lift-off from 65 μm to 35 μm to 42 μm, increase the isolation channel formation rate to 98% to 100%, improve the relative luminous efficiency by 10% to 12%, and increase the chip yield from 62% to 85% to 88%. This invention effectively solves the technical problems of photolithography alignment deviation, poor isolation channel formation accuracy, and low yield in vertical structure light-emitting diode chips caused by wafer warpage after laser lift-off.

[0047] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0048] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a light-emitting diode chip, characterized in that, Includes the following steps: S1, a sapphire substrate is provided, and an N-type GaN layer, an active light-emitting layer and a P-type GaN layer are sequentially deposited on the sapphire substrate to form a first epitaxial layer on the substrate; S2, etching a portion of the P-type GaN layer on the first epitaxial layer until the N-type GaN layer is exposed, so as to form an N-type GaN layer conductive step on the first epitaxial layer and form a second epitaxial layer on the substrate; S3, a portion of the P-type GaN layer is etched on the second epitaxial layer to form a trench. The trench extends into the N-type GaN layer. There is an N-type GaN layer between the bottom of the trench and the sapphire substrate. The trench divides the second epitaxial layer into a main light-emitting part and an isolation channel part, and forms a third epitaxial layer. S4, a transition dielectric layer and a P-type pad are prepared on the side of the third epitaxial layer facing away from the sapphire substrate. The transition dielectric layer covers the isolation channel, the inner wall of the trench, and the bottom of the trench. The P-type pad covers the transition dielectric layer and extends to the main light-emitting part. One end of the P-type pad is flush with the transition dielectric layer, and there is a distance between the other end of the P-type pad and the other end of the transition dielectric layer, forming a fourth epitaxial layer. S5, a semiconductor layer is prepared on the side of the fourth epitaxial layer opposite to the sapphire substrate. The semiconductor layer includes a current spreading layer, a first insulating protective layer, a metal reflective layer, a second insulating layer, a bonding metal layer, and a conductive silicon substrate arranged sequentially. S6, remove the sapphire substrate to expose the N-type GaN layer, vaporize and decompose the N-type GaN layer corresponding to the trench location to expose the transition dielectric layer, and etch the transition dielectric layer with an etchant to cause the isolation channel to automatically detach.

2. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The step of fabricating a P-type pad on the side of the third epitaxial layer opposite to the sapphire substrate includes: A negative photoresist is applied to the area of ​​the P-type GaN layer not covered by the transition dielectric layer within the transition dielectric layer and the main light-emitting part. The photoresist in the area to be formed as a P-type pad is exposed by a photomask. After development, the photoresist in the unexposed area is removed. A first Ti metal layer, an Au metal layer, a first Ni metal layer, and a second Ti metal layer are sequentially deposited using an electron beam evaporation process. Then, the photoresist and the metal on it are removed using a lift-off process to form the P-type pad. The thickness of the first Ti metal layer is 30 Å to 50 Å, the thickness of the Au metal layer is 5000 Å to 10000 Å, the thickness of the first Ni metal layer is 1000 Å to 2000 Å, and the thickness of the second Ti metal layer is 1000 Å to 2000 Å.

3. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The step of fabricating a semiconductor layer on the side of the fourth epitaxial layer opposite to the sapphire substrate includes: A current spreading layer is prepared on the side of the fourth epitaxial layer opposite to the sapphire substrate to form a fifth epitaxial layer; A first insulating protective layer is prepared on the side of the fifth epitaxial layer facing away from the sapphire substrate, and a pad-type first insulating protective layer via, a P-type first insulating protective layer and an N-type first insulating protective layer are formed in the first insulating protective layer to form a sixth epitaxial layer; A metal reflective layer is prepared on the side of the sixth epitaxial layer that faces away from the sapphire substrate to form the seventh epitaxial layer; A second insulating layer is prepared on the side of the seventh epitaxial layer facing away from the sapphire substrate, and an N-type second insulating layer via is formed in the second insulating layer to form an eighth epitaxial layer; A first bonding metal is prepared on the side of the eighth epitaxial layer that is opposite to the sapphire substrate; A conductive silicon substrate is provided, and a second bonding metal is fabricated on the conductive silicon substrate; The first bonding metal is bonded to the second bonding metal to form the bonding metal layer.

4. The method for fabricating a light-emitting diode chip according to claim 3, characterized in that, The specific steps for fabricating a current spreading layer on the side of the fourth epitaxial layer opposite to the sapphire substrate include: A negative photoresist is applied to the surfaces of the transition dielectric layer, the P-type pad, and the fourth epitaxial layer that are not covered by the transition dielectric layer and the P-type pad. The photoresist in the area where the current spreading layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. An ITO thin film is sputtered using a magnetron sputtering process. Then, the photoresist and the ITO thin film on it are removed using a lift-off process to form the current spreading layer.

5. The method for fabricating a light-emitting diode chip according to claim 3, characterized in that, The specific steps for fabricating the metal reflective layer on the side of the sixth epitaxial layer facing away from the sapphire substrate include: Negative photoresist is coated in the first insulating protective layer and the via of the pad-type first insulating protective layer. The photoresist in the area to be formed of the metal reflective layer is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. An Ag metal layer, a third Ti metal layer, a second Ni metal layer, a fourth Ti metal layer, a third Ni metal layer, and a fifth Ti metal layer are sequentially deposited using an electron beam evaporation process. Then, the photoresist and the metal on it are removed using a lift-off process to form the metal reflective layer. The thickness of the Ag metal layer is 1200 Å to 2000 Å, the thickness of the third Ti metal layer is 1000 Å to 2000 Å, the thickness of the second Ni metal layer is 1000 Å to 2000 Å, the thickness of the fourth Ti metal layer is 1000 Å to 2000 Å, the thickness of the third Ni metal layer is 1000 Å to 2000 Å, and the thickness of the fifth Ti metal layer is 30 Å to 50 Å.

6. The method for fabricating a light-emitting diode chip according to claim 3, characterized in that, The specific steps for fabricating a first bonding metal on the side of the eighth epitaxial layer facing away from the sapphire substrate and for fabricating a second bonding metal on the conductive silicon substrate include: Negative photoresist is coated in the second insulating layer and the vias of the N-type second insulating layer. Exposure is achieved using a photomask to expose the photoresist in the region where the first bonding metal is to be formed. After development, the unexposed photoresist is removed. Electron beam evaporation is then used to sequentially deposit the first Cr metal layer, the sixth Ti metal layer, the fourth Ni metal layer, the seventh Ti metal layer, the fifth Ni metal layer, and the first AuSn alloy metal layer. A lift-off process is then used to remove the photoresist and the metal on it to form the first bonding metal. On the conductive silicon substrate, electron beam evaporation is then used to sequentially deposit the second Cr metal layer, the eighth Ti metal layer, the sixth Ni metal layer, the ninth Ti metal layer, the seventh Ni metal layer, and the second AuSn alloy metal layer. A gold metal layer is formed to form a second bonding metal; wherein the thickness of the first Cr metal layer and the second Cr metal layer is 30 Å to 50 Å, the thickness of the sixth Ti metal layer and the eighth Ti metal layer is 1000 Å to 2000 Å, the thickness of the fourth Ni metal layer and the sixth Ni metal layer is 1000 Å to 2000 Å, the thickness of the seventh Ti metal layer and the ninth Ti metal layer is 1000 Å to 2000 Å, the thickness of the fifth Ni metal layer and the seventh Ni metal layer is 10000 Å to 15000 Å, and the thickness of the first AuSn alloy metal layer and the second AuSn alloy metal layer is 15000 Å to 20000 Å.

7. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The thickness between the bottom of the trench and the sapphire substrate ranges from 100 Å to 1000 Å, and the distance between the other end of the P-type pad and the other end of the transition dielectric layer is from 3 μm to 5 μm.

8. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The material of the transition medium layer is SiO2, and the etching solution is BOE solution.

9. A light-emitting diode chip, characterized in that, It is manufactured using the method for preparing a light-emitting diode chip according to any one of claims 1 to 8.

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