Semiconductor epitaxial structure and method of manufacturing the same

Abstract

The application provides a semiconductor epitaxial structure and a manufacturing method thereof. The application is characterized in that each active layer comprises alternately-stacked barrier layers and quantum well layers, each barrier layer comprises alternately-stacked first sub-layers and second sub-layers, the starting layer and the ending layer of the barrier layer are the first sub-layers, the first sub-layer is an undoped layer, the first sub-layer adjacent to the quantum well layer is an undoped layer, so as to block the diffusion of P-type doping atoms in the second sub-layer into the quantum well layer and cause damage, the second sub-layer is a P-type doping layer, the donor positive charges of the second sub-layer and the acceptor negative charges of the first sub-layers on both sides form dipoles, the direction of the dipole electric field is opposite to the direction of the built-in electric field of the main PN junction formed by the N-type semiconductor layer and the P-type semiconductor layer, so that the built-in electric field can partially offset the dipole electric field, the effective electric field near the quantum well layer is reduced, and the internal quantum efficiency and the reliability of the semiconductor device are improved. The process is simple, convenient and easy to produce.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication technology, and more specifically, relates to a semiconductor epitaxial structure and its fabrication method. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device that converts electrical energy into light energy. Due to its advantages such as small size, long lifespan, rich colors, and low energy consumption, it is widely used in lighting, displays, backlighting, and other fields. A typical LED chip uses multiple quantum wells (MQWs) as the active region, consisting of alternating barrier layers and quantum well layers sandwiched between P-type and N-type semiconductor layers to achieve effective confinement and radiative recombination of charge carriers.

[0003] However, in traditional LED chips, the hole mobility in the P-type semiconductor layer is significantly lower than that in the N-type semiconductor layer, resulting in a significantly lower hole injection efficiency than electron injection efficiency in the active layer. This leads to a severely uneven distribution of charge carriers (electrons or holes) in the active layer, causing local overheating and consequently resulting in low internal quantum efficiency and reliability issues in the device. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor epitaxial structure and its fabrication method to solve the problems in the prior art where the hole mobility in the P-type semiconductor layer is significantly lower than that in the N-type semiconductor layer, and the valence band shift is smaller, resulting in a significantly lower hole injection efficiency than electron injection efficiency in the active layer, causing severe uneven distribution of charge carriers in the active layer, leading to local overheating in the region, and consequently low internal quantum efficiency and reliability of the device.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A semiconductor epitaxial structure, characterized in that it comprises:

[0007] Substrate;

[0008] A stacked structure located on one side of the substrate, the stacked structure comprising at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer stacked sequentially;

[0009] The active region includes M active layers stacked sequentially, where M is an integer not less than 3; each active layer includes alternating layers of barrier layers and quantum well layers.

[0010] Each of the aforementioned barrier layers includes alternating layers of a first sublayer and a second sublayer. The start layer and the end layer of the barrier layer are both the first sublayer. The first sublayer is an undoped layer, and the second sublayer is a P-type doped layer.

[0011] Preferably, the thickness of the barrier layer gradually increases along the direction from the N-type semiconductor layer to the P-type semiconductor layer, and the thickness of each quantum well layer is equal. The closer to the P-type semiconductor layer, the greater the thickness ratio of the barrier layer to the adjacent quantum well layer.

[0012] Preferably, along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the larger the product of the barrier layer thickness and the aluminum composition of the barrier layer, the greater the product of the barrier layer thickness and the aluminum composition of the barrier layer is, and the value of b is in the range of 1.8nm-9.0nm, including the endpoint value.

[0013] Preferably, the bandgap of the barrier layer gradually increases along the direction from the N-type semiconductor layer to the P-type semiconductor layer, and the bandgap of the barrier layer increases from 2.09 eV to 2.28 eV.

[0014] Preferably, the first sublayer and the second sublayer in a single barrier layer have the same thickness, and a barrier buffer layer is provided between the first sublayer and the second sublayer.

[0015] Preferably, along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the effective barrier height of the second sub-layer gradually increases, and the effective barrier height of each second sub-layer is greater than the effective barrier height of the first sub-layer adjacent to it.

[0016] Preferably, the doping concentration of the second sublayer gradually increases along the direction from the N-type semiconductor layer to the P-type semiconductor layer.

[0017] Preferably, along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the aluminum composition of the barrier layer increases with the increase of the doping concentration of the second sub-layer, and the ratio of the doping concentration of the second sub-layer to the aluminum composition of the barrier layer is equal for each of the active layers.

[0018] Preferably, the N-type semiconductor layer includes at least an N-side space layer, and an N-side interface buffer layer is provided between the N-side space layer and the active region; the P-type semiconductor layer includes at least a P-side space layer, and a P-side interface buffer layer is provided between the P-side space layer and the active region, wherein both the N-side interface buffer layer and the P-side interface buffer layer are superlattice structures.

[0019] Preferably, the overall thickness of the N-side interface buffer layer is h1, and the overall thickness of the N-side space layer is h2, then h1:h2=1:5-1:4; the overall thickness of the P-side interface buffer layer is h3, and the overall thickness of the P-side space layer is h4, then h3:h4=1:5-1:4.

[0020] Preferably, the start layer and end layer of the active region are both the barrier layer, the N-side interface buffer layer includes alternating e-layers and f-layers, the P-side interface buffer layer includes alternating j-layers and k-layers, the contact surface between the N-side interface buffer layer and the N-side space layer is A, the contact surface between the N-side interface buffer layer and the active region is B, the contact surface between the P-side interface buffer layer and the active region is C, and the contact surface between the P-side interface buffer layer and the P-side space layer is D.

[0021] Preferably, the contact layer between the N-side interface buffer layer and the N-side space layer is an e-layer, and the e-layer near the A-side space layer is made of the same material or has the same material and composition as the N-side space layer.

[0022] The contact layer between the N-side interface buffer layer and the active region is layer f. The material of layer f and barrier layer near B is the same or the material and composition are the same.

[0023] The contact layer between the P-side interface buffer layer and the active region is layer j. The materials of layer j and the barrier layer near C are the same or the materials and compositions are the same.

[0024] The contact layer between the P-side interface buffer layer and the P-side space layer is layer k. The material of layer k near D is the same as that of the P-side space layer, or the material and composition are the same.

[0025] Preferably, the thickness of the e layer and the f layer near points A and B is less than the thickness of the other e layers and f layers;

[0026] The thickness of layer j and layer k near points C and D is less than the thickness of the other layers j and layer k.

[0027] Preferably, the N-type semiconductor layer includes, along the direction away from the active region, the N-side space layer, the N-type confinement layer, the N-type roughening layer, and the N-type current spreading layer stacked sequentially; the P-type semiconductor layer includes, along the direction away from the active region, the P-side space layer and the P-type confinement layer stacked sequentially.

[0028] The present invention also provides a method for fabricating a semiconductor epitaxial structure, characterized in that it includes:

[0029] Step 1: Provide a substrate;

[0030] Step 2: Fabricate a stacked structure on the substrate, the stacked structure comprising at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer stacked sequentially.

[0031] The active region includes M active layers stacked sequentially, where M is an integer not less than 3; each active layer includes alternating layers of barrier layers and quantum well layers; each barrier layer includes alternating layers of first sub-layers and second sub-layers, where the start layer and end layer of the barrier layer are both the first sub-layer, the first sub-layer is an undoped layer, and the second sub-layer is a P-type doped layer.

[0032] By employing the above technical solution, this application provides a semiconductor epitaxial structure and its fabrication method. Each active layer comprises alternating layers of barrier layers and quantum well layers. Each barrier layer includes alternating layers of first and second sub-layers. The start and end layers of the barrier layer are both first sub-layers, which are undoped. That is, the first sub-layer adjacent to the quantum well layer is undoped to prevent the diffusion of P-type doped atoms from the second sub-layer into the quantum well layer and causing damage. The second sub-layer is a P-type doped layer. The donor positive charge of the second sub-layer forms a dipole with the acceptor negative charge of the adjacent first sub-layers on both sides. The direction of the dipole electric field is opposite to the direction of the built-in electric field of the main PN junction formed by the N-type semiconductor layer and the P-type semiconductor layer. This allows the built-in electric field to partially cancel the dipole electric field, reducing the effective electric field near the quantum well layer, thereby improving the internal quantum efficiency and reliability of the semiconductor device. The fabrication process is simple and convenient, facilitating mass production. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a semiconductor epitaxial structure provided in an embodiment of this application;

[0035] Figure 2 This is a schematic diagram of a barrier layer provided in an embodiment of this application;

[0036] Figure 3 A schematic diagram of the band structure of the active layer of a semiconductor epitaxial structure provided in this application embodiment;

[0037] Figure 4 A schematic diagram of the energy band structure of the active layer of another semiconductor epitaxial structure provided in this application embodiment;

[0038] Figure 5 This is a schematic diagram of the structure of an active region provided in an embodiment of this application;

[0039] Figure 6This is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of this application;

[0040] Figure 7 This is a schematic diagram of another semiconductor epitaxial structure provided in an embodiment of this application;

[0041] Figure 8 A flowchart illustrating a method for fabricating a semiconductor epitaxial structure, as provided in this application embodiment;

[0042] Explanation of symbols in the diagram:

[0043] a. The thickness ratio of the barrier layer to the adjacent quantum well layer;

[0044] a1. The thickness ratio of the barrier layer to the adjacent quantum well layer in the first active layer;

[0045] a2. The thickness ratio of the barrier layer to the adjacent quantum well layer in the second active layer;

[0046] a3. The thickness ratio of the barrier layer to the adjacent quantum well layer in the third active layer;

[0047] b. The product of the barrier layer thickness and the aluminum composition of the barrier layer;

[0048] b1. The product of the barrier layer thickness and the aluminum composition of the barrier layer in the first active layer;

[0049] b2. The product of the barrier layer thickness and the aluminum composition of the barrier layer in the second active layer;

[0050] b3. The product of the barrier layer thickness and the aluminum composition of the barrier layer in the third active layer;

[0051] c. The ratio of the doping concentration of the second sublayer to the aluminum composition of the barrier layer;

[0052] h1, overall thickness of the N-side interface buffer layer;

[0053] h2, overall thickness of the N-side space layer;

[0054] h3, overall thickness of the P-side interface buffer layer;

[0055] h4, overall thickness of the P-side space layer;

[0056] A. The contact surface between the N-side interface buffer layer and the N-side space layer;

[0057] B, N-side interface buffer layer and contact surface with active region;

[0058] The contact surface between the C and P side interface buffer layer and the active region;

[0059] The contact surface between the D and P side interface buffer layer and the P side space layer;

[0060] 01. Buffer layer; 02. Corrosion stop layer;

[0061] 1. Substrate; 2. N-type semiconductor layer; 21. N-side space layer; 22. N-type confinement layer; 23. N-type roughening layer; 24. N-type current spreading layer; 3. Active region; 30. Active layer; 31. Barrier layer; 31a. First sublayer; 31b. Second sublayer; 31c. Barrier buffer layer; 32. Quantum well layer; 3a. First active layer; 3b. Second active layer; 3c. Third active layer; 4. P-type semiconductor layer; 41. P-side space layer; 42. P-type confinement layer; 5. N-side interface buffer layer; 51. e-layer; 52. f-layer; 6. P-side interface buffer layer; 61. j-layer; 62. k-layer; 7. Ohmic contact layer; 8. Adhesion layer; 9. Transition layer; 10. Window layer. Detailed Implementation

[0062] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0063] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0064] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0065] In view of this, the present application provides a semiconductor epitaxial structure, such as Figure 1 and Figure 2 The following are included:

[0066] Substrate 1;

[0067] A stacked structure located on one side of substrate 1, the stacked structure includes at least an N-type semiconductor layer 2, an active region 3 and a P-type semiconductor layer 4 stacked sequentially;

[0068] The active region 3 includes M active layers 30 stacked sequentially, where M is an integer not less than 3; each active layer 30 includes alternating layers of barrier layers 31 and quantum well layers 32.

[0069] Each barrier layer 31 includes alternating layers of first sublayer 31a and second sublayer 31b. The start and end layers of the barrier layer 31 are both first sublayer 31a, which is an undoped layer, and the second sublayer 31b is a P-type doped layer.

[0070] It should be noted that, in combination Figures 1 to 3 As shown, each barrier layer 31 includes alternating layers of first sublayer 31a and second sublayer 31b. The start and end layers of the barrier layer 31 are both first sublayer 31a, which is an undoped layer. That is, the first sublayer 31a adjacent to the quantum well layer 32 is an undoped layer to prevent the P-type doped atoms of the second sublayer 31b from diffusing into the quantum well layer 32 and causing damage. This allows for adjustment of the electric field distribution without degrading the material quality and maintains a steep interface between the quantum well layer 32 and the barrier layer 31, thereby reducing nonradiative recombination, maintaining the designed energy band, and improving the internal quantum efficiency. The second sublayer 31b is a P-type doped layer, and the donor positive charge (h) of the second sublayer 31b is... + ) and the acceptor negative charge (e) of the first sublayer 31a adjacent to both sides - ) forms a dipole, the direction of the dipole's electric field ( Figure 3 The direction from the P-side to the N-side) and the direction of the built-in electric field of the main PN junction formed by the N-type semiconductor layer 2 and the P-type semiconductor layer 4 ( Figure 3 In contrast to the direction from the N side to the P side, this reverse relationship allows the built-in electric field to partially cancel the dipole electric field, reducing the effective electric field near the quantum well layer 32. This enables each barrier layer 31 in the active region to simultaneously achieve interface quality optimization and carrier (electron or hole) injection enhancement, thereby increasing the radiative recombination probability and improving the internal quantum efficiency and reliability of the semiconductor device.

[0071] In an optional embodiment of this application, substrate 1 can be a temporary substrate or the final target substrate. The application document only uses a temporary substrate as an example for illustration.

[0072] In an optional embodiment of this application, reference is made to Figure 1 As shown, substrate 1 is a growth substrate, which includes, but is not limited to, a GaAs substrate. A stacked structure consisting of an N-type semiconductor layer 2, an active region 3, and a P-type semiconductor layer 3 stacked sequentially is grown on substrate 1. In an optional embodiment of this application, the growth substrate can be removed in subsequent chip processes.

[0073] In one optional embodiment of this application, the thickness of the barrier layer 31 monolayer ranges from 6nm to 15nm, including the endpoint values.

[0074] In one optional embodiment of this application, the thickness of the quantum well layer 32 monolayer ranges from 5nm to 10nm, including the endpoint values.

[0075] In an optional embodiment of this application, the barrier layer 31 includes, but is not limited to, one or more of AlGaInP barrier layer, AlGaAs barrier layer, and AlInP barrier layer;

[0076] The quantum well layer 32 includes, but is not limited to, one or more of GaAs quantum well layers and GaInP quantum well layers.

[0077] In an optional embodiment of this application, the active layer 30 includes 2 to 8 alternating AlGaInP barrier layers and GaInP quantum well layers.

[0078] In an optional embodiment of this application, the active layer 30 includes 2 to 8 alternating AlGaAs barrier layers and GaAs quantum well layers.

[0079] In an optional embodiment of this application, the active layer 30 includes 2 to 8 alternating AlInP barrier layers and GaInP quantum well layers.

[0080] Based on the above embodiments, in an optional embodiment of this application, the thickness of the barrier layer 31 gradually increases along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, and the thickness of each quantum well layer 32 is equal. The closer to the P-type semiconductor layer 4, the greater the thickness ratio of the barrier layer 31 to the adjacent quantum well layer 32.

[0081] It should be noted that, in combination Figure 1 , Figure 4As shown in the figure, due to the higher mobility of electrons, it is necessary to strengthen the confinement of electrons. By setting the thickness of the barrier layer 31 close to the N-type semiconductor layer 2 to be relatively thin, and the thickness ratio of the barrier layer 31 to the quantum well layer 32 to be small, the probability of electrons tunneling or thermally emitting into the quantum well layer 32 is high. After electrons are injected from the N-type semiconductor layer 2 into the active region 3, they can be easily "trapped" in the quantum well layer 32 close to the N-type semiconductor layer 2. The thickness of the barrier layer 31 gradually increases to form an asymmetric barrier distribution, guiding electrons to move layer by layer in the direction of the P-type semiconductor layer 4 and distributing them into each quantum well layer 32. The thickness of the barrier layer 31 close to the P-type semiconductor layer 4 is relatively thick, and the thickness ratio of the barrier layer 31 to the quantum well layer 32 is large. The thick barrier layer 31 significantly reduces the tunneling probability of electrons, making it difficult for electrons to continue moving towards the P-type semiconductor layer 4 and preventing electrons from leaking into the P-type semiconductor layer 4. After being blocked, electrons diffuse back in the reverse direction to the quantum well layer 32 in the middle of the active region 3. At the same time, holes are injected from the P-type semiconductor layer 4 into the active region 3, increasing the overlapping area of electrons and holes in space, so as to make the carrier (electron or hole) filling in the quantum well layer 32 in the active region 3 tend to be balanced, improve the spatial distribution uniformity of the carrier (electron or hole), reduce local overheating in the active region 3, increase the radiative recombination probability, and thus improve the internal quantum efficiency and reliability of the semiconductor device.

[0082] In addition, the quantum well layer 32 is the main light-emitting region (radiative recombination region). By setting the thicknesses of each quantum well layer 32 to be equal, it can ensure that each quantum well layer 32 has a similar energy level structure, avoid local wavelength shift and carrier localization traps caused by differences in the quantum well layer 32, achieve spectral consistency, reduce the broadening of the emission peak, and improve the color purity and stability of the semiconductor device.

[0083] In an optional embodiment of the present application, the thickness ratio of the barrier layer to the adjacent quantum well layer in the active layer is a, and the value range of a is 0.8 - 1.5, including the endpoint values.

[0084] In an optional embodiment of the present application, as Figure 5 shown, along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, the active region 3 includes a first active layer 3a, a second active layer 3b, and a third active layer 3c stacked in sequence.

[0085] In an optional embodiment of the present application, the thickness ratio of the barrier layer to the adjacent quantum well layer in the first active layer is a1, the thickness ratio of the barrier layer to the adjacent quantum well layer in the second active layer is a2, and the thickness ratio of the barrier layer to the adjacent quantum well layer in the third active layer is a3. Among them, a1 < a2 < a3, and 0.8 ≤ a1 ≤ 1.2; 1.0 ≤ a2 ≤ 1.4; 1.2 ≤ a3 ≤ 1.5.

[0086] Based on the above embodiments, in an optional embodiment of the present application, continue to refer to Figure 1As shown, along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, the larger the product of the thickness of the barrier layer 31 and the aluminum component of the barrier layer 31, where the product of the thickness of the barrier layer and the aluminum component of the barrier layer is b, and the value range of b is 1.8 nm - 9.0 nm, including the end values.

[0087] It should be noted that in the LED chip, a strong polarization electric field will cause the energy band tilt of the quantum well (QCSE), separating the electron and hole wave functions. By setting the product of the thickness of the barrier layer 31 and the aluminum component of the barrier layer 31 to be larger along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, so that the effective barrier strength of the active region 3 gradually increases along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, the polarization electric field can be effectively shielded or balanced to weaken the quantum-confined Stark effect and improve the radiative recombination rate.

[0088] At the same time, the effective barrier strength of the active region 3 close to the N-type semiconductor layer 2 is weak, and electrons can easily enter. The effective barrier strength of the active region 3 close to the P-type semiconductor layer 4 is strong, and the value range of the product of the thickness of the barrier layer and the aluminum component of the barrier layer, which is b, is 1.8 nm - 9.0 nm, including the end values, can significantly reduce the probability of electron tunneling leakage from the active region 3 without affecting hole injection.

[0089] In an optional embodiment of the present application, the product of the thickness of the barrier layer and the aluminum component of the barrier layer in the first active layer is b1, the product of the thickness of the barrier layer and the aluminum component of the barrier layer in the second active layer is b2, and the product of the thickness of the barrier layer and the aluminum component of the barrier layer in the third active layer is b3, where b1 < b2 < b3, and 1.5 ≤ b2 / b1 ≤ 2.0, 1.2 ≤ b3 / b2 ≤ 1.5, b2 / b1 represents b2 compared to b1, and b3 / b2 represents b3 compared to b2.

[0090] In an optional embodiment of the present application, the value range of b1 is 1.8 nm - 3.0 nm, including the end values; the value range of b2 is 3.0 nm - 6.0 nm, including the end values; the value range of b3 is 6.0 nm - 9.0 nm, including the end values.

[0091] Based on the above embodiments, in an optional embodiment of the present application, along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, the bandgap width of the barrier layer 31 gradually increases, and the bandgap width of the barrier layer 31 increases from 2.09 eV to 2.28 eV.

[0092] It should be noted that, along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, the band gap of the barrier layer 31 gradually increases, forming an increasingly higher barrier to enhance electron confinement. The larger the band gap, the greater the conduction band shift. Near the P-type semiconductor layer 4, the wider barrier forms a higher electron barrier, making it difficult for electrons to cross and enter the P-type semiconductor layer 4. Electrons are reflected back to the active region 3 and confined within the active region 3, preventing electron leakage. Simultaneously, from the P-region to the active region 3, the band gap of the barrier layer 31 gradually narrows, forming a gradually decreasing valence band slope. Holes, under the influence of the quasi-electric field, can more easily move towards the active region 3, promoting hole injection, improving hole distribution, and achieving efficient recombination of charge carriers (electrons or holes), further improving the internal quantum efficiency and reliability of the semiconductor device.

[0093] Based on the above embodiments, in an optional embodiment of this application, reference continues to be made to... Figure 2 As shown, the first sublayer 31a and the second sublayer 31b in a single barrier layer 31 have the same thickness, and a barrier buffer layer 31c is provided between the first sublayer 31a and the second sublayer 31b.

[0094] It should be noted that when multiple active layers 30 and multiple periods of barrier layers 31 and quantum well layers 32 are repeatedly set, strain accumulates continuously, which can easily induce crystal defects such as dislocations and slip lines, becoming non-radiative recombination centers and affecting luminescence efficiency and lifetime. In this embodiment, each barrier layer 31 includes alternating layers of first sub-layer 31a and second sub-layer 31b, and the thickness of the first sub-layer 31a and second sub-layer 31b in a single barrier layer 31 is equal. A barrier buffer layer 31c is provided between the first sub-layer 31a and the second sub-layer 31b. That is, the barrier layer 31 is set as multiple thin sub-layers of equal thickness, and a barrier buffer layer 31c is inserted between the thin sub-layers. This provides a gradient transition for the strain / polarization / defect density at the boundary between the sub-layers, preventing a single boundary from bearing all the lattice mismatch and polarization abrupt changes. This can reduce the defect density, improve the internal quantum efficiency, avoid lattice mismatch strain in a single thick barrier layer 31 that could lead to dislocation defects, improve the crystal quality of the active region 3, enhance carrier transport and confinement capabilities, and thus enhance the long-term reliability of the semiconductor device.

[0095] It should also be noted that nonradiative recombination centers refer to a special type of defect or impurity energy level in a semiconductor that can promote the recombination of electrons and holes but does not emit photons. Instead, it dissipates the energy released during recombination in other forms (mainly heat), which is in stark contrast to radiative recombination.

[0096] In an optional embodiment of this application, the single-layer thickness of both the first sublayer 31a and the second sublayer 31b is in the range of 2nm-5nm, including the endpoint values.

[0097] In an optional embodiment of this application, the thickness of the barrier buffer layer 31c ranges from 2nm to 5nm, including the endpoint values, and the material of the barrier buffer layer 31c includes, but is not limited to, AlGaInP.

[0098] Based on the above embodiments, in an optional embodiment of this application, along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, the effective barrier height of the second sub-layer 31b gradually increases, and the effective barrier height of each second sub-layer 31b is greater than the effective barrier height of the first sub-layer 31a adjacent to it.

[0099] It should be noted that the effective barrier height refers to the net energy barrier that a charge carrier (electron or hole) needs to overcome to escape from the bound state of the quantum well layer 32 to the continuous state of the adjacent barrier layer 31 under the operating condition. Along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, the effective barrier height of the second sub-layer 31b gradually increases, and the effective barrier height of the second sub-layer 31b is greater than that of the adjacent first sub-layer 31a. This not only reduces electron leakage to the P-type semiconductor layer 4 but also enables a gradual band transition, effectively creating a ramp for charge carriers (electrons or holes) to enter the quantum well layer 32, lowering the capture barrier, and making it easier for charge carriers (electrons or holes) to be captured by the active region 3, thereby improving the injection efficiency.

[0100] In an optional embodiment of this application, the effective barrier height of the barrier layer 31 increases from 0.01 eV to 0.03 eV along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4.

[0101] Based on the above embodiments, in an optional embodiment of this application, the doping concentration of the second sublayer 31b gradually increases along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4.

[0102] It should be noted that the doping concentration of the second sublayer 31b gradually increases along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4. The doping concentration of the second sublayer 31b is greater in the direction closer to the P-type semiconductor layer 4, so as to enhance hole injection, increase the probability of radiative recombination, and thus improve the internal quantum efficiency of the semiconductor device.

[0103] In an optional embodiment of this application, the doping concentration of the second sublayer 31b is from 1×10⁻⁶. 17 cm -3 Increase to 5×10 17 cm -3 .

[0104] Based on the above embodiments, in an optional embodiment of this application, along the direction from the N-type semiconductor layer 2 to the P-type semiconductor layer 4, the aluminum composition of the barrier layer 31 increases with the increase of the doping concentration of the second sub-layer 31b, and the ratio of the doping concentration of the second sub-layer 31b to the aluminum composition of the barrier layer 31 is equal between each active layer 30.

[0105] It should be noted that by setting the aluminum composition of the barrier layer 31 in the active layer 30 to be proportional to the doping concentration of its second sublayer 31b, the series resistance between each active layer 30 is reduced, the conductivity of each active layer 30 is kept balanced, and excessive accumulation of charge carriers at a certain interface is avoided.

[0106] In an optional embodiment of this application, the ratio of the doping concentration of the second sublayer to the aluminum composition of the barrier layer is c, and the value of c is equal for each active layer 30, with a value ranging from 5 × 10⁻⁶. 16 -5×10 17 cm -3 ·% -1 This includes endpoint values.

[0107] In an optional embodiment of this application, the mass percentage of aluminum component in barrier layer 31 ranges from 30% to 60%, including endpoint values.

[0108] Based on the above embodiments, in an optional embodiment of this application, such as Figure 6 As shown, the N-type semiconductor layer 2 includes at least an N-side space layer 21, and an N-side interface buffer layer 5 is provided between the N-side space layer 21 and the active region 3; the P-type semiconductor layer 4 includes at least a P-side space layer 41, and a P-side interface buffer layer 6 is provided between the P-side space layer 41 and the active region 3. Both the N-side interface buffer layer 5 and the P-side interface buffer layer 6 are superlattice structures.

[0109] It should be noted that before electrons are injected into the active region 3, they are first pre-distributed through the N-side space layer 21, then further buffered through the N-side interface buffer layer 5 of the superlattice structure, and finally enter the barrier layers 31 and quantum well layers 32 in sequence. Before holes are injected into the active region 3, they are first pre-distributed through the P-side space layer 41, then further buffered through the P-side interface buffer layer 6 of the superlattice structure, and finally enter the barrier layers 31 and quantum well layers 32 in sequence. The cascade injection of charge carriers (electrons or holes) and their uniform distribution in the recombination region ensure that each active layer 30 can obtain sufficient charge carriers (electrons or holes), avoiding direct injection of electrons and holes into the active region 3, which would lead to deterioration in aging. This can further improve the internal quantum efficiency and reliability of semiconductor devices.

[0110] Based on the above embodiments, in an optional embodiment of this application, the overall thickness of the N-side interface buffer layer is h1, the overall thickness of the N-side space layer is h2, and h1:h2=1:5-1:4; the overall thickness of the P-side interface buffer layer 6 is h3, the overall thickness of the P-side space layer 41 is h4, and h3:h4=1:5-1:4.

[0111] It should be noted that by setting the thickness ratio of the N-side interface buffer layer 5 to the N-side space layer 21, and the thickness ratio of the P-side interface buffer layer 6 to the P-side space layer 41, the buffering effect on charge carriers (electrons or holes) is guaranteed, and the series resistance is significantly reduced, thereby improving the reliability of semiconductor devices.

[0112] Based on the above embodiments, in an optional embodiment of this application, reference continues to be made to... Figure 6 As shown, the start and end layers of the active region 3 are both barrier layers 31. The N-side interface buffer layer 5 includes alternating layers e 51 and f 52. The P-side interface buffer layer 6 includes alternating layers j 61 and k 62. The contact surface between the N-side interface buffer layer and the N-side space layer is A. The contact surface between the N-side interface buffer layer and the active region is B. The contact surface between the P-side interface buffer layer and the active region is C. The contact surface between the P-side interface buffer layer and the P-side space layer is D.

[0113] Based on the above embodiments, in an optional embodiment of this application, the contact layer between the N-side interface buffer layer 5 and the N-side space layer 21 is the e-layer 51, and the e-layer 51 near A is made of the same material as the N-side space layer 21.

[0114] The contact layer between the N-side interface buffer layer 5 and the active region 3 is the f layer 52. The f layer 52 and the barrier layer 31 near B are made of the same material.

[0115] The contact layer between the P-side interface buffer layer 6 and the active region 3 is layer j 61. The materials of layer j 61 and barrier layer 31 near C are the same.

[0116] The contact layer between the P-side interface buffer layer 6 and the P-side space layer 41 is layer k 62, and layer k 62 near D is made of the same material as the P-side space layer 41.

[0117] It should be noted that by using the same material at the contact interfaces between the N-side interface buffer layer 5 and the N-side space layer 21, the N-side interface buffer layer 5 and the active region 3, the P-side interface buffer layer 6 and the active region 3, and the P-side interface buffer layer 6 and the P-side space layer 41, interface defects can be reduced, carrier (electron or hole) injection can be improved, and internal quantum efficiency can be enhanced.

[0118] In another optional embodiment of this application, the contact layer between the N-side interface buffer layer 5 and the N-side space layer 21 is the e-layer 51, and the e-layer 51 near A has the same material and composition as the N-side space layer 21.

[0119] The contact layer between the N-side interface buffer layer 5 and the active region 3 is the f layer 52. The f layer 52 and the barrier layer 31 near B have the same material and composition.

[0120] The contact layer between the P-side interface buffer layer 6 and the active region 3 is layer j 61. The materials and compositions of layer j 61 and barrier layer 31 near C are the same.

[0121] The contact layer between the P-side interface buffer layer 6 and the P-side space layer 41 is layer k 62. The material and composition of layer k 62 near D are the same as those of the P-side space layer 41.

[0122] It should be noted that by setting the same materials and compositions at the contact interfaces between the N-side interface buffer layer 5 and the N-side space layer 21, the N-side interface buffer layer 5 and the active region 3, the P-side interface buffer layer 6 and the active region 3, and the P-side interface buffer layer 6 and the P-side space layer 41, interface defects can be reduced and carrier (electron or hole) injection can be improved to achieve atomically perfect interfaces, thereby maximizing the improvement of internal quantum efficiency and device reliability.

[0123] Based on the above embodiments, in an optional embodiment of this application, the thickness of layer e 51 and layer f 52 near points A and B is less than the thickness of other layers e 51 and layer f 52.

[0124] The thickness of layer j (61) and layer k (62) near points C and D is less than the thickness of the other layers j (61) and layer k (62).

[0125] Based on the above embodiments, in an optional embodiment of this application, the single-layer thickness of e-layer 51, f-layer 52, j-layer 61, and k-layer 62 is 2-5 nm, including the endpoint value; the number of alternating stacking cycles of N-side interface buffer layer 5 includes 2-4 cycles, including the endpoint value; the number of alternating stacking cycles of P-side interface buffer layer 6 includes 2-4 cycles, including the endpoint value.

[0126] It should be noted that the N-side interface buffer layer 5 and the P-side interface buffer layer 6 are combined with thin layers and short cycles, which can reduce the lattice mismatch between the N-type semiconductor layer 2 and the active region 3, and between the P-type semiconductor layer 4 and the active region 3, thereby improving the overall crystal quality of the stacked structure.

[0127] In an optional embodiment of this application, both the N-side interface buffer layer 5 and the P-side interface buffer layer 6 include a 2-4 period AlGaInP / AlGaInP superlattice structure.

[0128] In an optional embodiment of this application, both the N-side interface buffer layer 5 and the P-side interface buffer layer 6 include 2-4 cycles of Al. x Ga 1-x InP / Al y Ga 1-yInP superlattice structure, where 0.3≤x≤y≤1.

[0129] Based on the above embodiments, in an optional embodiment of this application, reference continues to be made to... Figure 6 As shown, the N-type semiconductor layer 2 includes an N-side space layer 21, an N-type confinement layer 22, an N-type roughening layer 23 and an N-type current spreading layer 24 stacked sequentially in the direction away from the active region 3; the P-type semiconductor layer 4 includes a P-side space layer 41 and a P-type confinement layer 42 stacked sequentially in the direction away from the active region 3.

[0130] In an optional embodiment of this application, the thickness of both the N-type current spreading layer 24 and the N-type roughening layer 23 is in the range of 300nm-3000nm, including the endpoint values; the materials of both the N-type current spreading layer 24 and the N-type roughening layer 23 are including but not limited to AlGaInP.

[0131] In an optional embodiment of this application, the materials of the N-type current spreading layer 24 and the N-type roughening layer 23 are, but are not limited to, N-type doped Al. z Ga 1-z InP, where z = 0.1 - 1.

[0132] In an optional embodiment of this application, the thickness of the N-type confinement layer 22 is in the range of 100nm-1000nm, including the endpoint values; the thickness of the N-side space layer 21 is in the range of 50nm-500nm, including the endpoint values; the materials of the N-type confinement layer 22 and the N-side space layer 21 are both including but not limited to AlGaInP.

[0133] In an optional embodiment of this application, the materials of the N-type confinement layer 22 and the N-side space layer 21 are both including, but not limited to, N-type doped Al. g Ga 1-g InP, where g = 0.3-1.

[0134] In an optional embodiment of this application, the thickness of the P-side space layer 41 is in the range of 50nm-500nm, including the endpoint values; the thickness of the P-type confinement layer 42 is in the range of 100nm-1000nm, including the endpoint values; the materials of the P-side space layer 41 and the P-type confinement layer 42 are both including but not limited to AlGaInP.

[0135] In an optional embodiment of this application, the materials of both the P-side space layer 41 and the P-type confinement layer 42 include, but are not limited to, P-type doped Al. q Ga 1-q InP, where q = 0.3 - 1.

[0136] In various embodiments of this application, N-type doping can be Si doping, Te doping, or Se doping; P-type doping can be Zn doping, C doping, Mg doping, or Be doping.

[0137] Based on the above embodiments, in an optional embodiment of this application, the stacked structure further includes an ohmic contact layer 7, which is located between the substrate 1 and the N-type semiconductor layer 2.

[0138] In an optional embodiment of this application, the thickness of the ohmic contact layer 7 ranges from 30 nm to 300 nm, including the endpoint values; the material of the ohmic contact layer 7 includes, but is not limited to, GaAs.

[0139] Based on the above embodiments, in an optional embodiment of this application, such as Figure 7 As shown, an adhesion layer 8 is also provided between the ohmic contact layer 7 and the N-type semiconductor layer 2, which can prevent the electrode from falling off during chip manufacturing.

[0140] In an optional embodiment of this application, the thickness of the adhesion layer 8 ranges from 10 nm to 100 nm; the material of the adhesion layer 8 includes, but is not limited to, GaInP.

[0141] Based on the above embodiments, in an optional embodiment of this application, the stacked structure further includes a transition layer 9 and a window layer 10 that are sequentially stacked on the surface of the P-type semiconductor layer 4 in a direction away from the active region 3.

[0142] It should be noted that in this embodiment, a transition layer 9 is provided to alleviate the lattice mismatch between the window layer 10 and the P-type semiconductor layer 4; the window layer 10 can perform P-plane current expansion and form ohmic contacts with the metal layer in the chip process.

[0143] In one optional embodiment of this application, the material of the window layer 10 includes, but is not limited to, GaP.

[0144] Based on the above embodiments of this application, another embodiment of this application also provides a method for fabricating a semiconductor epitaxial structure, such as... Figure 8 As shown, the manufacturing method includes:

[0145] Step 1: Provide a substrate 1;

[0146] Step Two, Reference Figure 1 , Figure 2 As shown, a stacked structure is fabricated on substrate 1. The stacked structure includes at least an N-type semiconductor layer 2, an active region 3, and a P-type semiconductor layer 4 stacked sequentially.

[0147] The active region 3 includes M active layers 30 stacked sequentially, where M is an integer not less than 3; each active layer 30 includes alternatingly stacked barrier layers 31 and quantum well layers 32; each barrier layer 31 includes alternatingly stacked first sub-layer 31a and second sub-layer 31b, the start layer and end layer of the barrier layer 31 are both the first sub-layer 31a, the first sub-layer 31a is an undoped layer, and the second sub-layer 31b is a P-type doped layer.

[0148] It should be noted that the semiconductor epitaxial structure formed by the semiconductor epitaxial structure fabrication method provided in this embodiment refers to... Figures 1 to 3 As shown, each barrier layer 31 includes alternating layers of first sublayer 31a and second sublayer 31b. The start and end layers of the barrier layer 31 are both first sublayer 31a, which is an undoped layer. That is, the first sublayer 31a adjacent to the quantum well layer 32 is an undoped layer to prevent the P-type doped atoms of the second sublayer 31b from diffusing into the quantum well layer 32 and causing damage. This allows for adjustment of the electric field distribution without degrading the material quality and maintains a steep interface between the quantum well layer 32 and the barrier layer 31, thereby reducing nonradiative recombination, maintaining the designed energy band, and improving the internal quantum efficiency. The second sublayer 31b is a P-type doped layer, and the donor positive charge (h) of the second sublayer 31b is... + ) and the acceptor negative charge (e) of the first sublayer 31a adjacent to both sides - ) forms a dipole, the direction of the dipole's electric field ( Figure 3 The direction from the P-side to the N-side) and the direction of the built-in electric field of the main PN junction formed by the N-type semiconductor layer 2 and the P-type semiconductor layer 4 ( Figure 3 Conversely, the direction from the N side to the P side is reversed. This inverse relationship allows the built-in electric field to partially cancel the dipole electric field, reducing the effective electric field near the quantum well layer 32. This enables the barrier layers 31 in the active region to simultaneously achieve interface quality optimization and carrier (electron or hole) injection enhancement, thereby increasing the radiative recombination probability and ultimately improving the internal quantum efficiency and reliability of the semiconductor device. Its fabrication process is simple and convenient, facilitating mass production.

[0149] In an optional embodiment of this application, substrate 1 can be a temporary substrate or the final target substrate. The application document only uses a temporary substrate as an example for illustration.

[0150] In an optional embodiment of this application, reference is made to Figure 1 As shown, substrate 1 is a growth substrate, and a stacked structure is prepared on the growth substrate. The stacked structure includes at least an N-type semiconductor layer 2, an active region 3, and a P-type semiconductor layer 4 stacked sequentially along the growth direction.

[0151] Based on the above embodiments, in an optional embodiment of this application, the first sublayer 31a and the second sublayer 31b in a single barrier layer 31 have equal thicknesses, and a barrier buffer layer 31c is provided between the first sublayer 31a and the second sublayer 31b.

[0152] It should be noted that when multiple active layers 30 are repeatedly configured with multi-period barrier layers 31 and quantum well layers 32, strain accumulates continuously, easily inducing crystal defects such as dislocations and slip lines, which become non-radiative recombination centers, affecting luminescence efficiency and lifetime. In this embodiment, a single barrier layer 31 is grown from multiple thin sublayers of equal thickness, which can significantly reduce strain energy accumulation during epitaxial growth, suppress defect generation (such as microcracks and stacking faults), and improve the crystal quality of the active region 3.

[0153] In one optional embodiment of this application, stacked structures are grown using a method including but not limited to metal-organic chemical vapor deposition (MOCVD).

[0154] In an optional embodiment of this application, the following process conditions can be used when preparing the active region 3: the growth pressure inside the reaction chamber is set to 40-60 mbar, including the endpoint value; the V / III ratio inside the reaction chamber is set to 50-200, including the endpoint value; and the growth rate of the active region 3 is in the range of 3 A / s-6 A / s, including the endpoint value; the growth time of the active region 3 is in the range of 10s-60s, including the endpoint value; and the growth temperature of the active region 3 is in the range of 650 degrees Celsius-750 degrees Celsius.

[0155] It should be noted that the V / III ratio represents the ratio of the five-generation source to the three-generation source.

[0156] Based on the above embodiments, in an optional embodiment of this application, reference is made to... Figure 6 As shown, the N-type semiconductor layer 2 includes at least an N-side space layer 21, and an N-side interface buffer layer 5 is provided between the N-side space layer 21 and the active region 3; the P-type semiconductor layer 4 includes at least a P-side space layer 41, and a P-side interface buffer layer 6 is provided between the P-side space layer 41 and the active region 3. Both the N-side interface buffer layer 5 and the P-side interface buffer layer 6 are superlattice structures.

[0157] Based on the above embodiments, in an optional embodiment of this application, the N-type semiconductor layer 2 includes, along the growth direction, a sequentially stacked N-type current spreading layer 24, an N-type roughening layer 23, an N-type confinement layer 22, and an N-side space layer 21; the P-type semiconductor layer 4 includes, along the growth direction, a sequentially stacked P-side space layer 41 and a P-type confinement layer 42.

[0158] Based on the above embodiments, in an optional embodiment of this application, an ohmic contact layer 7 is first grown on the substrate 1 before forming the N-type semiconductor layer 2.

[0159] Based on the above embodiments, in an optional embodiment of this application, reference is made to... Figure 7 As shown, after the ohmic contact layer 7 is grown and before the N-type semiconductor layer 2 is formed, an adhesion layer 8 is grown on the ohmic contact layer 7.

[0160] Based on the above embodiments, in an optional embodiment of this application, the preparation of the stacked structure further includes forming a transition layer 9 and a window layer 10 sequentially on the surface of the P-type semiconductor layer 4 along the growth direction.

[0161] Based on the above embodiments, in an optional embodiment of this application, reference continues to be made to... Figure 7 As shown, a buffer layer 01 and an etching stop layer 02 are sequentially stacked between the growth substrate and the N-type semiconductor layer 2 along the growth direction. The buffer layer 01 is in contact with the growth substrate, and the etching stop layer 02 is in contact with the ohmic contact layer 7.

[0162] It should be noted that in this embodiment, a buffer layer 01 is set to alleviate stress mismatch, reduce dislocation density, and improve the crystal quality of the stacked structure, while an etch stop layer 02 is used to achieve precise etching depth and avoid the risk of over-etching of the stacked structure.

[0163] In an optional embodiment of this application, the thickness of the buffer layer 01 ranges from 100nm to 1000nm, including the endpoint values; the material of the buffer layer 01 includes, but is not limited to, GaAs.

[0164] In an optional embodiment of this application, the thickness of the corrosion stop layer 02 ranges from 100nm to 1000nm, including the endpoint values; the material of the corrosion stop layer 02 includes, but is not limited to, GaInP.

[0165] In an optional embodiment of this application, the doping type of the buffer layer 01 and the corrosion stop layer 02 can be N-type doping.

[0166] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting the invention.

[0167] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0168] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor epitaxial structure, characterized by, include: Substrate; A stacked structure located on one side of the substrate, the stacked structure comprising at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer stacked sequentially; The active region includes M active layers stacked sequentially, where M is an integer not less than 3; each active layer includes alternating layers of barrier layers and quantum well layers. Each of the aforementioned barrier layers includes alternating layers of a first sublayer and a second sublayer. The start layer and the end layer of the barrier layer are both the first sublayer. The first sublayer is an undoped layer, and the second sublayer is a P-type doped layer.

2. The semiconductor epitaxial structure of claim 1, wherein: Along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the thickness of the barrier layer gradually increases, and the thickness of each quantum well layer is equal. The closer to the P-type semiconductor layer, the greater the ratio of the thickness of the barrier layer to the thickness of the adjacent quantum well layer.

3. The semiconductor epitaxial structure of claim 1, wherein: Along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the larger the product of the barrier layer thickness and the aluminum composition of the barrier layer, the greater the product of the barrier layer thickness and the aluminum composition of the barrier layer is, b. The value of b ranges from 1.8nm to 9.0nm, including the endpoint value.

4. The semiconductor epitaxial structure of claim 1, wherein: Along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the band gap of the barrier layer gradually increases, and the band gap of the barrier layer increases from 2.09 eV to 2.28 eV.

5. The semiconductor epitaxial structure of claim 1, wherein: The first sublayer and the second sublayer in a single barrier layer have the same thickness, and a barrier buffer layer is provided between the first sublayer and the second sublayer.

6. The semiconductor epitaxial structure of claim 1, wherein: Along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the effective barrier height of the second sub-layer gradually increases, and the effective barrier height of each second sub-layer is greater than the effective barrier height of the first sub-layer adjacent to it.

7. The semiconductor epitaxial structure of claim 1, wherein: Along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the doping concentration of the second sublayer gradually increases.

8. The semiconductor epitaxial structure of claim 7, wherein: Along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the aluminum composition of the barrier layer increases with the increase of the doping concentration of the second sub-layer, and the ratio of the doping concentration of the second sub-layer to the aluminum composition of the barrier layer is equal for each active layer.

9. The semiconductor epitaxial structure of claim 1, wherein: The N-type semiconductor layer includes at least an N-side space layer, and an N-side interface buffer layer is provided between the N-side space layer and the active region; the P-type semiconductor layer includes at least a P-side space layer, and a P-side interface buffer layer is provided between the P-side space layer and the active region, wherein both the N-side interface buffer layer and the P-side interface buffer layer are superlattice structures.

10. The semiconductor epitaxial structure according to claim 9, characterized in that: If the overall thickness of the N-side interface buffer layer is h1 and the overall thickness of the N-side space layer is h2, then h1:h2 = 1:5 - 1:4; if the overall thickness of the P-side interface buffer layer is h3 and the overall thickness of the P-side space layer is h4, then h3:h4 = 1:5 - 1:

4.

11. The semiconductor epitaxial structure according to claim 9, characterized in that: The start and end layers of the active region are both the barrier layers. The N-side interface buffer layer includes alternating e and f layers. The P-side interface buffer layer includes alternating j and k layers. The contact surface between the N-side interface buffer layer and the N-side space layer is A. The contact surface between the N-side interface buffer layer and the active region is B. The contact surface between the P-side interface buffer layer and the active region is C. The contact surface between the P-side interface buffer layer and the P-side space layer is D.

12. The semiconductor epitaxial structure according to claim 11, characterized in that: The contact layer between the N-side interface buffer layer and the N-side space layer is layer e. The layer e near point A is made of the same material as the N-side space layer or has the same material and composition. The contact layer between the N-side interface buffer layer and the active region is layer f. The material of layer f and barrier layer near B is the same or the material and composition are the same. The contact layer between the P-side interface buffer layer and the active region is layer j. The materials of layer j and the barrier layer near C are the same or the materials and compositions are the same. The contact layer between the P-side interface buffer layer and the P-side space layer is layer k. The material of layer k near D is the same as that of the P-side space layer, or the material and composition are the same.

13. The semiconductor epitaxial structure according to claim 11, characterized in that: The thickness of layer e and layer f near points A and B is less than the thickness of the other layers e and layer f; The thickness of layer j and layer k near points C and D is less than the thickness of the other layers j and layer k.

14. The semiconductor epitaxial structure according to claim 9, characterized in that: The N-type semiconductor layer includes, along the direction away from the active region, the N-side space layer, the N-type confinement layer, the N-type roughening layer, and the N-type current spreading layer stacked sequentially; the P-type semiconductor layer includes, along the direction away from the active region, the P-side space layer and the P-type confinement layer stacked sequentially.

15. A method for fabricating a semiconductor epitaxial structure, characterized in that, include: Step 1: Provide a substrate; Step 2: Fabricate a stacked structure on the substrate, the stacked structure comprising at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer stacked sequentially. The active region includes M active layers stacked sequentially, where M is an integer not less than 3; each active layer includes alternating layers of barrier layers and quantum well layers; each barrier layer includes alternating layers of first sub-layers and second sub-layers, where the start layer and end layer of the barrier layer are both the first sub-layer, the first sub-layer is an undoped layer, and the second sub-layer is a P-type doped layer.

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