Light emitting device and method of fabricating the same

Abstract

The application provides a light-emitting device and a preparation method thereof, which comprises a substrate, an epitaxial layer, a first pad and a second pad. The epitaxial layer is located on the substrate and comprises a first semiconductor layer and a second semiconductor layer which are stacked in a direction away from the substrate. The epitaxial layer has pixel areas and pad areas which are arranged at intervals. The surfaces of the epitaxial layer of the pixel areas and the pad areas away from the substrate each have a plurality of epitaxial bumps which are arranged at intervals. The first semiconductor layer of each epitaxial bump is connected, and the second semiconductor layer of each epitaxial bump is spaced. The first pad is located in the pad area and is electrically connected with the first semiconductor layer of the epitaxial bump of the pixel area. The second pad is located in the pixel area and is electrically connected with the second semiconductor layer of the epitaxial bump of the pixel area. The application can improve the pixel density of the light-emitting device and optimize the heat dissipation effect of the light-emitting device.

Description

Technical Field

[0001] This application relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting device and its fabrication method. Background Technology

[0002] As a core component for achieving high-resolution image presentation, array light-emitting devices (LEDs) are widely used in Mini / MicroLED displays, high-definition LED array devices, and various backlight zone display scenarios. With the market's ever-increasing demands for visual experience, various display scenarios are placing even higher performance requirements on array light-emitting devices.

[0003] In related technologies, array light-emitting devices typically employ a multi-chip assembly process to construct pixel arrays, which involves arranging and interconnecting multiple independent LED chips on a substrate at high density to form an array LED chip structure.

[0004] However, this multi-chip-based technology still has many problems. For example, it is difficult to further improve pixel resolution, there is serious optical crosstalk between pixels leading to color mixing problems, and uneven heat generation during operation makes thermal management difficult. Summary of the Invention

[0005] This application provides a light-emitting device and its fabrication method, which can improve the pixel density of the light-emitting device and optimize its heat dissipation effect. The technical solution is as follows: This application provides a light-emitting device, comprising: a substrate, an epitaxial layer, a first pad, and a second pad. The epitaxial layer is located on the substrate and includes a first semiconductor layer and a second semiconductor layer stacked along a direction away from the substrate. The epitaxial layer has pixel regions and pad regions arranged at intervals. The surfaces of the epitaxial layers in the pixel regions and the epitaxial layers in the pad regions away from the substrate each have a plurality of epitaxial bumps arranged at intervals. The first semiconductor layers of each epitaxial bump are connected, and the second semiconductor layers of each epitaxial bump are spaced apart. The first pad is located in the pad region and is electrically connected to the first semiconductor layer of the epitaxial bump in the pixel region. The second pad is located in the pixel region and is electrically connected to the second semiconductor layer of the epitaxial bump in the pixel region.

[0006] In one implementation of this application, in the pixel region, the first semiconductor layer between adjacent epitaxial bumps has an isolation trench, which is used to fill at least one of a reflective material and a light-absorbing material; the orthographic projection of the epitaxial bump on the surface of the substrate is polygonal, and each side of each epitaxial bump is provided with an isolation trench, and the isolation trenches corresponding to each side of the epitaxial bump are not interconnected.

[0007] In another implementation of this application, the light-emitting device further includes a first electrode, which is located in the gap between adjacent epitaxial bumps within the pixel area and between adjacent isolation grooves.

[0008] In another implementation of this application, the light-emitting device further includes a first dielectric layer, which is located at least in the pixel region. The first dielectric layer in the pixel region has a plurality of vias, some of which expose the second semiconductor layer of the epitaxial bump, and others of which expose the first electrode.

[0009] In another implementation of this application, each of the external bumps is provided with a plurality of vias arranged at intervals, and the plurality of vias provided for each external bump are arranged axially symmetrically.

[0010] In another implementation of this application, the first dielectric layer is further located in the pad area, and the first dielectric layer in the pad area covers each of the epitaxial bumps; the light-emitting device further includes a first metal layer, which is located on the side of each of the epitaxial bumps away from the substrate; the first metal layer in the pixel area is connected to the second semiconductor layer of the epitaxial bumps through the via; the first metal layer in the pad area is located on the first dielectric layer and is insulated from each of the epitaxial bumps.

[0011] In another implementation of this application, the light-emitting device further includes: a second dielectric layer, a first connecting electrode, and a second connecting electrode. The second dielectric layer is located on the surface of the first dielectric layer away from the substrate. The second dielectric layer in the pixel region has a first through-hole and a second through-hole. The first through-hole exposes the first electrode, and the second through-hole exposes the first metal layer. The second dielectric layer in the pad region at least covers the first metal layer. The first connecting electrode is located on the second dielectric layer in the pixel region and the pad region, and is connected to the first electrode through the first through-hole. The second connecting electrode is located on the second dielectric layer in the pixel region, and is connected to the first metal layer through the second through-hole. The first connecting electrode and the second connecting electrode are arranged at intervals. The first pad is connected to the first connecting electrode in the pad region, and the second pad is connected to the second connecting electrode in the pixel region.

[0012] In another implementation of this application, the light-emitting device further includes a third dielectric layer located on the first connection electrode and the second connection electrode. The third dielectric layer has a through-hole exposing the second connection electrode of the pixel area and a through-hole exposing the first connection electrode of the pad area. The first pad is connected to the first connection electrode of the pad area through the through-hole of the third dielectric layer, and the second pad is connected to the second connection electrode of the pixel area through the through-hole of the third dielectric layer. The first dielectric layer, the second dielectric layer, and the third dielectric layer are all insulating reflective layers. The first metal layer, the first connection electrode, and the second connection electrode are all metal reflective layers.

[0013] In another implementation of this application, the orthographic projection of the pad area on the substrate is a closed loop, and the pad area surrounds the pixel area.

[0014] This application provides a method for fabricating a light-emitting device. The method includes: forming an epitaxial layer on a substrate, the epitaxial layer including a first semiconductor layer and a second semiconductor layer stacked in a direction away from the substrate; patterning the epitaxial layer to form pixel regions and pad regions spaced apart, wherein the surfaces of the epitaxial layers in the pixel regions and the epitaxial layers in the pad regions away from the substrate each have a plurality of spaced epitaxial bumps, the first semiconductor layers of each epitaxial bump are connected, and the second semiconductor layers of each epitaxial bump are spaced apart; etching the first semiconductor layer of the pad regions to form cleaving paths surrounding the epitaxial bumps of the pad regions and exposing the substrate; and fabricating a first pad and a second pad, the first pad being located in the pad regions and electrically connected to the first semiconductor layer of the epitaxial bumps in the pixel regions, and the second pad being located in the pixel regions and electrically connected to the second semiconductor layer of the epitaxial bumps in the pixel regions.

[0015] The beneficial effects of the technical solutions provided in this application include at least the following: The light-emitting device provided in this application achieves high-density pixel array integration on a single wafer by directly fabricating spaced epitaxial bumps on the epitaxial layer. In related technologies, multi-chip assembly processes require manufacturing multiple independent LED chips separately, then arranging them one by one on a substrate through mass transfer and bonding processes. Each chip requires reserved independent electrode pads, dicing paths, and interconnection gaps between chips. These non-light-emitting areas significantly reduce the usable space per unit area, making it difficult to further reduce the pixel pitch. In contrast, this application directly fabricates spaced epitaxial bumps on the same epitaxial layer, allowing each bump to function as an independent pixel. This eliminates the need for independent manufacturing, transfer, and splicing processes for multiple chips, thereby eliminating space losses caused by chip dicing, independent packaging, and interconnection gaps, and increasing the number of pixels that can be accommodated per unit area. Furthermore, all epitaxial bumps in the single-wafer integrated structure are formed in the same epitaxial growth process. The pixel position and spacing are directly defined by wafer-level photolithography, resulting in a pixel arrangement consistency and regularity far exceeding that of multi-chip splicing schemes. Uniform arrangement can be achieved at smaller pitches, thus increasing pixel density.

[0016] Simultaneously, the first pad is positioned in the pad area and the second pad in the pixel area, with the pads arranged in the spaced-apart pixel and pad areas. The pad area does not need to support pixel illumination, allowing for the integration of larger pads and reducing additional heat generation. Furthermore, the epitaxial bumps in both the pixel and pad areas belong to the same single-wafer epitaxial structure, resulting in continuous heat conduction paths and higher thermal resistance consistency across regions. The large first pad in the pad area serves as a highly efficient heat conduction channel, rapidly dissipating heat generated in the pixel area to the external heat dissipation structure, significantly improving overall heat conduction efficiency and achieving uniform temperature dissipation across the entire area. This keeps the junction temperature difference between pixels within the array at a low level, suppressing issues such as light decay, color shift, and uneven brightness, ensuring consistent and stable display output during long-term operation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view of a light-emitting device provided in an embodiment of this application; Figure 2 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application; Figure 3 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application; Figure 5 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application; Figure 7 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application; Figure 9 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application; Figure 10 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application; Figure 11 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application; Figure 12 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application; Figure 13 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application; Figure 14 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application; Figure 15 This is a flowchart of a method for fabricating a light-emitting device provided in an embodiment of this application.

[0019] The markings in the diagram are explained as follows: 10. Substrate; 2. Epitaxial layer; 201. Pixel area; 202. Pad area; 203. Gap area; 204. Cutting track; 20. Epitaxial bump; 21. First semiconductor layer; 22. Multiple quantum well layer; 23. Second semiconductor layer; 30. Isolation trench; 40. First electrode; 51. First dielectric layer; 52. Second dielectric layer; 53. Third dielectric layer; 61. Through hole; 62. First through hole; 63. Second through hole; 71. First metal layer; 72. First connecting electrode; 73. Second connecting electrode; 81. First pad; 82. Second pad. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Figure 1 This is a top view of a light-emitting device provided in an embodiment of this application. Figure 2 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application. Figure 2 It is along Figure 1 A cross-sectional view obtained by cutting along the XX section line. (Example) Figure 1 , 2 As shown, the light-emitting device includes: a substrate 10, an epitaxial layer 2, a first pad 81 and a second pad 82. The epitaxial layer 2 is located on the substrate 10 and includes a first semiconductor layer 21 and a second semiconductor layer 23 stacked in a direction away from the substrate 10.

[0023] like Figure 1 , 2 As shown, the epitaxial layer 2 has pixel regions 201 and pad regions 202 arranged at intervals. The surfaces of the epitaxial layer 2 in the pixel region 201 and the epitaxial layer 2 in the pad region 202 that are away from the substrate 10 have a plurality of epitaxial bumps 20 arranged at intervals. The first semiconductor layer 21 of each epitaxial bump 20 is connected, and the second semiconductor layer 23 of each epitaxial bump 20 is spaced apart.

[0024] like Figure 1 , 2As shown, the first pad 81 is located in the pad area 202 and is electrically connected to the first semiconductor layer 21 of the epitaxial bump 20 of the pixel area 201, and the second pad 82 is located in the pixel area 201 and is electrically connected to the second semiconductor layer 23 of the epitaxial bump 20 of the pixel area 201.

[0025] The light-emitting device provided in this application achieves high-density pixel array integration on a single wafer by directly fabricating spaced epitaxial bumps 20 on the epitaxial layer 2. In related technologies, multi-chip assembly processes require manufacturing multiple independent LED chips separately, and then arranging them one by one on the substrate 10 through mass transfer, bonding, and other processes. Each chip requires reserved independent electrode pads, dicing paths, and interconnection gaps between chips. These non-light-emitting areas significantly reduce the usable space per unit area, making it difficult to further reduce the pixel pitch. In contrast, this application directly fabricates spaced epitaxial bumps 20 on the same epitaxial layer 2. Each epitaxial bump 20 can function as an independent pixel, eliminating the need for independent manufacturing, transfer, and splicing processes for multiple chips. This eliminates space losses caused by chip dicing, independent packaging, and interconnection gaps, increasing the number of pixels that can be accommodated per unit area. Furthermore, all epitaxial bumps 20 in the single-wafer integrated structure are formed in the same epitaxial growth process. The position and spacing of the pixels are directly defined by the wafer-level photolithography process. The consistency and regularity of the pixel arrangement are far higher than those of the multi-chip splicing scheme. Uniform arrangement can be achieved with smaller spacing to improve pixel density.

[0026] Simultaneously, the first pad 81 is positioned in the pad area 202, and the second pad 82 is positioned in the pixel area 201. This arrangement of pads in the spaced-apart pixel area 201 and pad area 202 eliminates the need for the pad area to support pixel illumination, allowing for the integration of a larger pad area and reducing additional heat generation. Furthermore, the epitaxial bumps 20 of the pixel area 201 and the epitaxial bumps 20 of the pad area 202 both belong to a single-wafer epitaxial structure. The heat conduction paths in each region are continuous, and the thermal resistance is more consistent. The large-size first pad 81 of the pad area 202 can serve as a highly efficient heat conduction channel, quickly dissipating the heat generated in the pixel area 201 to the external heat dissipation structure, significantly improving overall heat conduction efficiency, achieving uniform temperature dissipation across the entire area, and keeping the junction temperature difference between pixels within the array at a low level. This suppresses issues such as light decay, color shift, and uneven brightness, ensuring the consistency and stability of the display output during long-term operation.

[0027] Figure 3 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application. Figure 4 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application. Figure 4 It is along Figure 3 A cross-sectional view obtained by cutting along the YY section line. (See figure) Figure 3 , 4As shown, in pixel region 201, the first semiconductor layer 21 between adjacent epitaxial bumps 20 has an isolation trench 30, which is used to fill at least one of a reflective material and a light-absorbing material.

[0028] By setting an isolation trench 30 in the first semiconductor layer 21 between adjacent epitaxial bumps 20, and filling the isolation trench 30 with reflective and light-absorbing materials to form a complete physical barrier between pixels, crosstalk can be blocked from the light transmission path.

[0029] Among them, reflective materials such as aluminum oxide, silicon oxide and titanium oxide form a refractive index difference with the semiconductor layer, so that the light incident on the sidewall of the isolation trench 30 undergoes total internal reflection and is confined inside the epitaxial bump 20 of a single pixel, preventing the light from spilling into adjacent pixels laterally; light-absorbing materials such as tungsten and titanium nitride can directly absorb the light that penetrates into the isolation trench 30, eliminate light crosstalk between pixels, and thus solve the color mixing problem caused by the mixing of light signals from different pixels.

[0030] Optionally, such as Figure 3 , 4 As shown, the orthographic projection of the epitaxial bump 20 on the surface of the substrate 10 is polygonal, and each side of each epitaxial bump 20 is provided with an isolation groove 30. The isolation grooves 30 corresponding to each side of the epitaxial bump 20 are not interconnected.

[0031] In this embodiment, the orthographic projection of the epitaxial bump 20 adopts a polygonal shape such as a rectangle or hexagon, which can achieve seamless tiling arrangement under the array. Compared with shapes such as circles that have arrangement gaps, more epitaxial bumps 20 can be accommodated in the unit substrate 10 area, further improving the pixel density, while ensuring the uniformity of pixel distribution.

[0032] Simultaneously, each of the four sides of the epitaxial bump 20 is provided with an isolation groove 30, and the isolation grooves 30 on each side are not interconnected, which is equivalent to constructing an independent isolation groove 30 for each pixel. The reflective / light-absorbing material filled in the isolation groove 30 can completely block the lateral overflow of light in each pixel, avoid optical crosstalk between adjacent pixels, and eliminate color mixing problems. The non-interconnected isolation grooves 30 can weaken the lateral connection of the first semiconductor layer 21, suppress the diffusion of charge carriers between different pixels, and improve the pixel signal abnormalities caused by electrical crosstalk.

[0033] Figure 5 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application. Figure 6 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application. Figure 6 It is along Figure 5 A cross-sectional view obtained by cutting along the XX section line. (Example) Figure 5 , 6As shown, the light-emitting device also includes a first electrode 40, which is located in the gap between adjacent epitaxial bumps 20 within the pixel area 201, and is located between adjacent isolation grooves 30.

[0034] Since the isolation groove 30 itself is filled with reflective / light-absorbing material, it can achieve light blocking between pixels. The first electrode 40 is located in the gap between the isolation grooves 30 and will not encroach on the light-emitting area of ​​the epitaxial bump 20. At the same time, the electrode surface can also be used to reflect light, forming a dual optical blocking path with the isolation groove 30, further reducing the probability of pixel cross-lighting and color mixing, and improving display contrast and image purity.

[0035] Furthermore, by integrating the first electrode 40 into the gap of the epitaxial bump 20 inside the pixel area 201, no additional space is needed for electrode arrangement. This maximizes the light-emitting area of ​​the epitaxial bump 20 under the same pixel pitch, improves the pixel aperture ratio, and thus increases the overall light-emitting brightness per unit area.

[0036] For example, such as Figure 5 , 6 As shown, the orthographic projection of the epitaxial bump 20 on the surface of the substrate 10 is rectangular, and each of the four sides of the epitaxial bump 20 is provided with an isolation groove 30, and the ends of adjacent isolation grooves 30 are not connected to each other.

[0037] The width of the isolation groove 30 is less than or equal to the spacing between adjacent extensional bumps 20, and the length of each isolation groove 30 is at least 3µm less than the single-side length of the adjacent extensional bump 20.

[0038] As an example, the depth of the isolation trench 30 is 1 μm to 5 μm, so that at least 1 μm of the first semiconductor layer 21 cannot be etched onto the substrate 10.

[0039] For example, such as Figure 5 , 6 As shown, each of the four corners of the epitaxial bump 20 is provided with a first electrode 40. The first electrode 40 is located between the ends of adjacent isolation grooves 30 and is not connected to the isolation grooves 30. That is, multiple first electrodes 40 are distributed in a rectangular array at the four corners of the epitaxial bump 20.

[0040] Optionally, the material used to fabricate the first electrode 40 may include at least one of Cr, Ti, Ni, Pt, Al, Au, and Ag.

[0041] For example, the shape of the orthographic projection of the first electrode 40 onto the substrate 10 can be circular or polygonal.

[0042] As an example, the first electrode 40 is cylindrical, and the diameter of the first electrode 40 is more than 2 μm smaller than the spacing between adjacent epitaxial bumps 20.

[0043] For example, the thickness of the first electrode 40 is 0.1 μm to 1 μm, and the top surface of the first electrode 40 is lower than the top surface of the epitaxial bump 20.

[0044] Figure 7 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application. Figure 8 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application. For example... Figure 7 , 8 As shown, the light-emitting device also includes a first dielectric layer 51, which is located at least in the pixel region 201. The first dielectric layer 51 in the pixel region 201 has a plurality of vias 61, a portion of which expose the second semiconductor layer 23 of the epitaxial bump 20, and another portion of which expose the first electrode 40.

[0045] The first dielectric layer 51 serves as an insulating layer, and the second semiconductor layer 23 and the first electrode 40 are exposed through the via 61, allowing each epitaxial bump 20 to achieve independent electrical connection through the via 61, without the need for additional etching and buried wires, reducing wiring difficulty and device etching damage, and improving yield.

[0046] For example, the first dielectric layer 51 includes at least one of a silicon nitride layer, an aluminum oxide layer, a silicon oxide layer, and a titanium oxide layer.

[0047] For example, the first dielectric layer 51 comprises alternating layers of silicon oxide and titanium oxide to form a DBR mirror. The thickness of the first dielectric layer 51 is from 0.1 μm to 2 μm.

[0048] For example, the via 61 can be circular or polygonal. When the via 61 is polygonal, the corners of the via 61 can be rounded.

[0049] As an example, when the via 61 located above the extension bump 20 is circular, the diameter of the via 61 is 5 μm to 50 μm.

[0050] As an example, when the via 61 located above the extension bump 20 is rectangular, the side length of the via 61 is 5μm to 50μm.

[0051] Optionally, the distance between the via 61 above the epitaxial bump 20 and the edge of the epitaxial bump 20 is 2 μm to 10 μm.

[0052] As an example, when the via 61 exposing the first electrode 40 is circular, the diameter of the via 61 is 1 μm to 20 μm.

[0053] As an example, when the via 61 exposing the first electrode 40 is rectangular, the side length of the via 61 is 1 μm to 20 μm.

[0054] Optionally, the distance between the via 61 exposing the first electrode 40 and the edge of the epitaxial bump 20 is 2 μm to 10 μm.

[0055] Optionally, such as Figure 7 As shown, each epitaxial bump 20 has a corresponding via 61. A single via 61 is easy to fabricate, and the size of a single via 61 can be designed to be larger, which facilitates the subsequent fabrication of a film layer electrically connected to the epitaxial bump 20 within the via 61.

[0056] Optionally, the light-emitting device further includes a transparent conductive layer located on the epitaxial bump 20 and on the surface of the second semiconductor layer 23.

[0057] Example of selecting a location, such as Figure 8 As shown, a portion of the via 61 in the first dielectric layer 51 within the pixel region 201 exposes the transparent conductive layer of the epitaxial bump 20, and the first dielectric layer 51 in the pad region 202 covers the transparent conductive layer of the epitaxial bump 20.

[0058] For example, the transparent conductive layer may be an ITO layer or an IZO layer.

[0059] Figure 9 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application. Figure 10 This is a top view of a partial film layer of a light-emitting device provided in an embodiment of this application.

[0060] like Figure 9 , 10 As shown, each extension bump 20 is provided with a plurality of vias 61 arranged at intervals, and the plurality of vias 61 provided for each extension bump 20 are arranged axially symmetrically.

[0061] Each epitaxial bump 20 is provided with multiple vias 61, which allow current to be injected into the second semiconductor layer 23 of the epitaxial bump 20 from multiple points, thereby improving the uniformity of current distribution, avoiding current congestion, and improving light efficiency.

[0062] Each epitaxial bump 20 corresponds to multiple vias 61 arranged axially symmetrically. This ensures that the pads and metal layers subsequently fabricated on the surface of the first dielectric layer 51 are subjected to uniform stress and heat during fabrication, avoiding localized depressions in the dielectric layer or pad warping caused by concentrated vias 61 on one side. Structurally, this guarantees the flatness of the pad and metal layer surfaces. This results in a uniform contact area of ​​the pads during bonding, preventing gas residue caused by localized gaps and significantly reducing the bonding void rate.

[0063] Furthermore, the axisymmetric multi-hole design allows current to be injected into the epitaxial bump 20 from multiple symmetrical points, avoiding uneven heating caused by local current accumulation; at the same time, multiple vias 61 can form a uniform heat dissipation channel, uniformly conducting the heat generated by the epitaxial bump 20 to the pads, avoiding local heat accumulation.

[0064] For example, such as Figure 9 As shown, each of the extended protrusions 20 has four vias 61 above it, and the four vias 61 are arranged in a rectangular array.

[0065] The via 61 can be circular or polygonal. When the via 61 is polygonal, the corners of the via 61 can be rounded.

[0066] As an example, when the via 61 located above the extension bump 20 is circular, the diameter of the via 61 is 5 μm to 20 μm.

[0067] As an example, when the via 61 located above the extension bump 20 is rectangular, the side length of the via 61 is 5μm to 20μm.

[0068] Optionally, the distance between the via 61 above the epitaxial bump 20 and the edge of the epitaxial bump 20 is 2 μm to 10 μm.

[0069] For example, such as Figure 10 As shown, each of the extended protrusions 20 has five vias 61 above it, and four of the vias 61 are arranged in a rectangular array, with the other via 61 located at the geometric center of the rectangle formed by the four vias 61.

[0070] The via 61 can be circular or polygonal. When the via 61 is polygonal, the corners of the via 61 can be rounded.

[0071] As an example, when the via 61 located above the extension bump 20 is circular, the diameter of the via 61 is 5 μm to 20 μm.

[0072] As an example, when the via 61 located above the extension bump 20 is rectangular, the side length of the via 61 is 5μm to 20μm.

[0073] Optionally, the distance between the via 61 above the epitaxial bump 20 and the edge of the epitaxial bump 20 is 2 μm to 10 μm.

[0074] In the above implementation, the five vias are arranged axially symmetrically, which ensures that the pads and metal layers subsequently fabricated on the surface of the first dielectric layer are subjected to uniform stress and heat during the fabrication process. This avoids localized depressions in the dielectric layer or warping of the pads caused by concentrated vias on one side, structurally ensuring the flatness of the pad and metal layer surfaces. This results in a uniform contact area of ​​the pads during bonding, avoiding gas residue caused by localized gaps and significantly reducing the bonding void rate.

[0075] Furthermore, the axisymmetric multi-hole design allows current to be injected into the epitaxial bumps from multiple symmetrical points, avoiding uneven heating caused by local current accumulation; at the same time, multiple vias can form a uniform heat dissipation channel, evenly conducting the heat generated by the epitaxial bumps to the pads, avoiding local heat accumulation.

[0076] Figure 11 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application. For example... Figure 11 As shown, the first dielectric layer 51 is also located in the pad area 202, and the first dielectric layer 51 in the pad area 202 covers each epitaxial bump 20.

[0077] like Figure 11 As shown, the light-emitting device also includes a first metal layer 71, which is located on the side of each epitaxial bump 20 away from the substrate 10.

[0078] like Figure 11 As shown, the first metal layer 71 in the pixel region 201 is connected to the second semiconductor layer 23 of the epitaxial bump 20 through a via 61.

[0079] like Figure 11 As shown, the first metal layer 71 in the pad area 202 is located on the first dielectric layer 51 and is insulated from each of the epitaxial bumps 20.

[0080] The dielectric and metal layers of pixel area 201 and pad area 202 are deposited and patterned simultaneously, avoiding positioning deviations and process parameter fluctuations caused by step-by-step fabrication. This ensures that the surface flatness of the first dielectric layer 51 in pad area 202 is perfectly matched with the mesa height of the dielectric layer in pixel area 201 and the epitaxial bump 20. When fabricating the first pad 81 and the second pad 82 subsequently, they can be arranged coplanarly based on mesa of the same height, avoiding uneven bonding pressure and poor contact caused by differences in pad height.

[0081] Consistent pad height ensures even solder force during bonding, preventing voids caused by residual gas. Excessive void ratio leads to increased solder joint resistance and impaired heat conduction, potentially causing solder joint cracking and localized overheating over time. Integrated processes, however, can control the bonding void ratio to extremely low levels, ensuring stable transmission of pixel drive signals while uniformly dissipating pixel heat and suppressing issues such as light decay and color shift.

[0082] For example, the first metal layer 71 may include at least one of Ag, Al, Cr, Ti, Pt, Au, TiW, and Ni layers. Using the above-mentioned metal materials as the first metal layer 71 can ensure the reflective effect of the first metal layer 71 and improve the light output of the light-emitting device.

[0083] For example, the thickness of the first metal layer 71 is 0.1 μm to 1 μm. The distance between the side of the first metal layer 71 and each edge of the epitaxial bump 20 is consistent, and the distance between the side of the first metal layer 71 and each edge of the epitaxial bump 20 is 1 μm to 10 μm.

[0084] Figure 12 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application. Figure 13 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application. For example... Figure 12 , 13 As shown, the light-emitting device further includes: a second dielectric layer 52, a first connecting electrode 72 and a second connecting electrode 73, wherein the second dielectric layer 52 is located on the surface of the first dielectric layer 51 away from the substrate 10.

[0085] like Figure 12 , 13 As shown, the second dielectric layer 52 in the pixel region 201 has a first through hole 62 and a second through hole 63. The first through hole 62 exposes the first electrode 40, and the second through hole 63 exposes the first metal layer 71. The second dielectric layer 52 in the pad region 202 at least covers the first metal layer 71.

[0086] like Figure 12 , 13 As shown, the first connection electrode 72 is located on the second dielectric layer 52 of the pixel region 201 and the pad region 202, and is connected to the first electrode 40 through the first via 62. That is, the first connection electrode 72 covers each of the epitaxial bumps 20 of the pad region 202, extends into the gap between the pixel region 201 and the pad region 202, and is connected to the first electrode 40 in the pixel region 201.

[0087] like Figure 12 , 13 As shown, the second connection electrode 73 is located on the second dielectric layer 52 of the pixel area 201 and is connected to the first metal layer 71 through the second through hole 63. The first connection electrode 72 and the second connection electrode 73 are arranged at intervals.

[0088] like Figure 12 , 13 As shown, the first pad 81 is connected to the first connection electrode 72 of the pad area 202, and the second pad 82 is connected to the second connection electrode 73 of the pixel area 201.

[0089] For example, the second dielectric layer 52 includes at least one of a silicon nitride layer, an aluminum oxide layer, a silicon oxide layer, and a titanium oxide layer.

[0090] For example, the second dielectric layer 52 comprises alternating layers of silicon oxide and titanium oxide to form a DBR reflector. The thickness of the second dielectric layer 52 is from 0.1 μm to 2 μm.

[0091] The second dielectric layer 52 adopts a distributed Bragg reflector (DBR) structure. By periodically stacking dielectric films with different refractive indices, the multiple interference effects of reflected light from each layer are utilized to form a high reflectivity for specific wavelength light emitted from the epitaxial bump 20 of the pixel area 201, reflecting the light back to the light-emitting direction, reducing light absorption loss, and directly improving the light-emitting efficiency and brightness of the device.

[0092] For example, both the first connecting electrode 72 and the second connecting electrode 73 include at least one of Ag layer, Al layer, Cr layer, Ti layer, Pt layer, Au layer, TiW layer and Ni layer.

[0093] As an example, the thickness of the first connecting electrode 72 and the second connecting electrode 73 is 0.5 μm to 5 μm.

[0094] The first connecting electrode 72 and the second connecting electrode 73 are fabricated using a metal layer. Metal itself has high reflectivity and can be used as a reflective structure. On the one hand, it reflects the light emitted from the epitaxial bump 20 that passes through the gap in the second dielectric layer 52 back to the light-emitting direction, forming a dual optical path optimization with the reflection effect of the DBR layer, thereby improving the overall luminous brightness.

[0095] For example, such as Figure 13 As shown, the first connection electrode 72 in the pixel area 201 surrounds the second connection electrode 73, so that an annular isolation gap is formed between the first connection electrode 72 and the second connection electrode 73.

[0096] The width of the annular isolation gap is 1 μm to 5 μm.

[0097] For example, the second connecting electrode 73 is disposed at the center of the top surface of the epitaxial bump 20, and the distance between the four sides of the second connecting electrode 73 and the four sides of the epitaxial bump 20 is the same, with a distance range of 3μm to 10μm.

[0098] Figure 14 This is a schematic diagram of the hierarchy of a light-emitting device provided in an embodiment of this application. For example... Figure 14 As shown, the light-emitting device also includes a third dielectric layer 53, which is located on the first connection electrode 72 and the second connection electrode 73. The third dielectric layer 53 has a through hole exposing the second connection electrode 73 of the pixel area 201 and a through hole exposing the first connection electrode 72 of the pad area 202.

[0099] like Figure 2 As shown, the first pad 81 is connected to the first connection electrode 72 of the pad area 202 through the through hole of the third dielectric layer 53, and the second pad 82 is connected to the second connection electrode 73 of the pixel area 201 through the through hole of the third dielectric layer 53.

[0100] For example, the third dielectric layer 53 includes at least one of a silicon nitride layer, an aluminum oxide layer, a silicon oxide layer, and a titanium oxide layer.

[0101] For example, the third dielectric layer 53 comprises alternating layers of silicon oxide and titanium oxide to form a DBR reflector. The thickness of the third dielectric layer 53 is 0.1 μm to 1 μm.

[0102] The third dielectric layer 53 adopts a distributed Bragg reflector structure. By periodically stacking dielectric films with different refractive indices, and utilizing the multiple interference effects of reflected light from each layer, it forms a high reflectivity for specific wavelength light emitted from the epitaxial bump 20 of the pixel area 201, reflecting the light back to the light-emitting direction and reducing light absorption loss.

[0103] Optionally, the first dielectric layer 51, the second dielectric layer 52, and the third dielectric layer 53 are all insulating reflective layers; the first metal layer 71, the first connecting electrode 72, and the second connecting electrode 73 are all metal reflective layers.

[0104] For example, the first dielectric layer 51, the second dielectric layer 52 and the third dielectric layer 53 can all be DBR reflectors. By using three stacked DBR reflectors, the reflective effect of the dielectric layers can be greatly improved.

[0105] For example, the first metal layer 71, the first connecting electrode 72, and the second connecting electrode 73 are all metal material layers, which also have good reflective properties. The three metal material layers and the three DBR reflective mirror layers are alternately stacked on the epitaxial layer, forming a multi-layered optical blocking and high-reflection structure that efficiently reflects light back to the light-emitting surface. The metal material layers also function as current conductors and reflectors, while the DBR suppresses light absorption and heat generation in the dielectric, jointly optimizing the heat dissipation path, suppressing long-term light decay and color shift, and ensuring the display consistency and reliability of the high-density array.

[0106] For example, both the first pad 81 and the second pad 82 may include at least one of the following: a Cr layer, a Ti layer, a Pt layer, an Au layer, a Ni layer, and an AuSn layer.

[0107] As an example, the thickness of the first pad 81 and the second pad 82 is 2 μm to 8 μm.

[0108] Optionally, such as Figure 1 As shown, the orthographic projection of the pad area 202 on the substrate 10 is a closed loop, and the pad area 202 surrounds the pixel area 201.

[0109] For example, each epitaxial bump 20 in the pixel area 201 is arranged in a rectangular array, the width of each epitaxial bump 20 is 5μm to 100μm, and the spacing between adjacent epitaxial bumps 20 is 1μm to 10μm.

[0110] For example, the pad area 202 includes two rings of external bumps 20, each ring of external bumps 20 being arranged circumferentially around the pixel area 201.

[0111] For example, the gap region 203 between the pixel region 201 and the pad region 202 can be an integer multiple of the spacing between adjacent epitaxial bumps 20.

[0112] For example, the width of the gap region 203 ranges from 20 μm to 200 μm. Setting the width of the gap region within the above range can effectively physically isolate the pixel area and the pad area, thereby improving heat dissipation.

[0113] For example, such as Figure 1 As shown, a dicing channel 204 is also provided outside the pad area 202, and the dicing channel 204 circumferentially surrounds the pad area 202. By setting the dicing channel around the pad area, the problem of internal pixel epitaxial damage caused by laser stripping can be solved.

[0114] The width of the cutting channel 204 can be an integer multiple of the spacing between adjacent extension protrusions 20.

[0115] For example, the width of the dicing channel ranges from 20 μm to 200 μm. Setting the width of the dicing channel within the above range can effectively physically isolate and protect the dot matrix LED of this application from physical tearing damage to the epitaxial layer of the product during the subsequent laser lift-off step after bonding with CMOS and uncovering the substrate, which could lead to reliability failure.

[0116] In this embodiment, the pad area 202 surrounds the pixel area 201 in a closed ring shape. With the help of two circumferentially spaced outer bumps 20, the heat dissipation area of ​​the pad area 202 can be expanded, forming a surrounding heat dissipation structure with the pixel area 201, which can effectively suppress light decay and color shift caused by heat accumulation.

[0117] Among them, the gap area 203 between the pixel area 201 and the pad area 202 and the width of the outer cutting track 204 are both integer multiples of the pixel pitch, which can ensure the uniformity of pattern density in processes such as photolithography and etching, and avoid surface unevenness in CMP process; at the same time, the cutting track 204 surrounds the pad area 202 to block the diffusion of cutting stress to the internal pixels, prevent moisture and impurities from entering, and improve device yield and long-term reliability.

[0118] Optionally, such as Figure 2As shown, the epitaxial layer 2 includes a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23, which are sequentially stacked on the substrate 10.

[0119] Optionally, the substrate 10 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 10 can be a flat substrate or a patterned substrate.

[0120] As an example, in this embodiment, substrate 10 is a sapphire substrate. Sapphire substrates are commonly used substrates, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate.

[0121] In this embodiment of the application, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0122] As an example, the first semiconductor layer 21 is an n-type layer and the second semiconductor layer 23 is a p-type layer.

[0123] Optionally, the n-type layer can be an n-type AlGaN layer, and the thickness of the n-type AlGaN layer can be from 0.5 μm to 3 μm.

[0124] Optionally, the multi-quantum well layer 22 includes 3 to 8 Al x Ga 1-x N quantum well layer and Al y Ga 1-y N quantum barrier layers, where 0 < x < y < 1. That is, the multi-quantum well layer 22 comprises alternating stacked Al phases of 3 to 8 periods. x Ga 1-x N quantum well layer and Al y Ga 1-y N-quantum barrier layer.

[0125] As an example, in this embodiment of the application, the multi-quantum well layer 22 includes five alternating stacked periods of Al. x Ga 1-x N quantum well layer and Al y Ga 1-y N-quantum barrier layer.

[0126] For example, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0127] Optionally, the p-type layer can be a p-type AlGaN layer. The thickness of the p-type AlGaN layer can be from 0.5 μm to 3 μm.

[0128] Figure 15 This is a flowchart illustrating a method for fabricating a light-emitting device according to an embodiment of this application. Figure 15 As shown, the preparation method includes: Step S11: An epitaxial layer 2 is formed on the substrate 10.

[0129] The epitaxial layer 2 includes a first semiconductor layer 21 and a second semiconductor layer 23 stacked in a direction away from the substrate 10.

[0130] Step S12: Graphicalize the epitaxial layer 2 to form pixel regions 201 and pad regions 202 arranged at intervals.

[0131] In this embodiment, the epitaxial layer 2 of pixel region 201 and the epitaxial layer 2 of pad region 202 both have multiple epitaxial bumps 20 arranged at intervals on the surface away from substrate 10. The first semiconductor layer 21 of each epitaxial bump 20 is connected, and the second semiconductor layer 23 of each epitaxial bump 20 is spaced apart.

[0132] Step S13: Etch the first semiconductor layer 21 of the pad area 202 to form each epitaxial bump 20 surrounding the pad area 202 and expose the dicing channel 204 of the substrate 10.

[0133] Step S14: Create the first pad 81 and the second pad 82.

[0134] The first pad 81 is located in the pad area 202 and is electrically connected to the first semiconductor layer 21 of the epitaxial bump 20 of the pixel area 201. The second pad 82 is located in the pixel area 201 and is electrically connected to the second semiconductor layer 23 of the epitaxial bump 20 of the pixel area 201.

[0135] The light-emitting device fabricated by this method achieves high-density pixel array integration on a single wafer by directly fabricating spaced epitaxial bumps 20 on the epitaxial layer 2. In related technologies, multi-chip assembly processes require the separate fabrication of multiple independent LED chips, followed by mass transfer and bonding processes to arrange them one by one on the substrate 10. Each chip requires reserved independent electrode pads, dicing paths, and interconnection gaps between chips. These non-light-emitting areas significantly reduce the usable space per unit area, making it difficult to further reduce the pixel pitch. In contrast, this application directly fabricates spaced epitaxial bumps 20 on the same epitaxial layer 2. Each epitaxial bump 20 can function as an independent pixel, eliminating the need for independent manufacturing, transfer, and splicing processes for multiple chips. This eliminates space losses caused by chip dicing, independent packaging, and interconnection gaps, thereby increasing the number of pixels that can be accommodated per unit area. Furthermore, all epitaxial bumps 20 in the single-wafer integrated structure are formed in the same epitaxial growth process. The position and spacing of the pixels are directly defined by the wafer-level photolithography process. The consistency and regularity of the pixel arrangement are far higher than those of the multi-chip splicing scheme. Uniform arrangement can be achieved with smaller spacing to improve pixel density.

[0136] Simultaneously, the first pad 81 is positioned in the pad area 202, and the second pad 82 is positioned in the pixel area 201. This arrangement of pads in the spaced-apart pixel area 201 and pad area 202 eliminates the need for the pad area to support pixel illumination, allowing for the integration of a larger pad area and reducing additional heat generation. Furthermore, the epitaxial bumps 20 of the pixel area 201 and the epitaxial bumps 20 of the pad area 202 both belong to a single-wafer epitaxial structure. The heat conduction paths in each region are continuous, and the thermal resistance is more consistent. The large-size first pad 81 of the pad area 202 can serve as a highly efficient heat conduction channel, quickly dissipating the heat generated in the pixel area 201 to the external heat dissipation structure, significantly improving overall heat conduction efficiency, achieving uniform temperature dissipation across the entire area, and keeping the junction temperature difference between pixels within the array at a low level. This suppresses issues such as light decay, color shift, and uneven brightness, ensuring the consistency and stability of the display output during long-term operation.

[0137] Step S11 may include: selecting a sapphire flat substrate, a PSS patterned sapphire substrate, or a silicon substrate as substrate 10, performing offline cleaning to ensure surface cleanliness; and then using a metal-organic chemical vapor deposition process to sequentially grow and stack a first semiconductor layer 21, a multi-quantum well active region, and a second semiconductor layer 23 on substrate 10 to form an epitaxial wafer with satisfactory optoelectronic performance and uniformity.

[0138] During epitaxial growth, temperature, gas flow rate, and reaction time must be precisely controlled to ensure crystal quality. After growth, post-treatment such as cooling and cleaning is performed to remove non-ideal substances from the surface.

[0139] In this embodiment of the application, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0140] As an example, the first semiconductor layer 21 is an n-type layer and the second semiconductor layer 23 is a p-type layer.

[0141] Optionally, the n-type layer can be an n-type AlGaN layer, and the thickness of the n-type AlGaN layer can be from 0.5 μm to 3 μm.

[0142] Optionally, the multi-quantum well layer 22 includes 3 to 8 Al x Ga 1-x N quantum well layer and Al y Ga 1-y N quantum barrier layers, where 0 < x < y < 1. That is, the multi-quantum well layer 22 comprises alternating stacked Al phases of 3 to 8 periods. x Ga 1-x N quantum well layer and Al y Ga 1-y N-quantum barrier layer.

[0143] As an example, in this embodiment of the application, the multi-quantum well layer 22 includes five alternating stacked periods of Al. x Ga 1-x N quantum well layer and Al y Ga 1-y N-quantum barrier layer.

[0144] For example, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0145] Optionally, the p-type layer can be a p-type AlGaN layer. The thickness of the p-type AlGaN layer can be from 0.5 μm to 3 μm.

[0146] Step S12 may include the following steps: First, a transparent conductive layer is prepared on the surface of the second semiconductor layer 23 using magnetron sputtering / electron beam evaporation / reactive plasma evaporation equipment, and good ohmic contact is formed by RTA or diffusion furnace tube annealing.

[0147] Then, by using photolithography patterning transfer technology and ICP etching technology, the second semiconductor layer 23, the multi-quantum well layer 22 and the first semiconductor layer 21 at a certain depth are etched to prepare the initial epitaxial structure of the pixel region 201 and the pad region 202.

[0148] For example, a plurality of epitaxial bumps 20 are formed in the pixel region 201 and the pad region 202. The epitaxial bumps 20 are arranged in a rectangular array. The width of a single epitaxial bump 20 is 5μm to 100μm. The spacing between adjacent epitaxial bumps 20 is 1μm to 10μm. The first semiconductor layer 21 of each epitaxial bump 20 is connected, and the second semiconductor layer 23 is independently spaced.

[0149] The pad area 202 surrounds the pixel area 201 in a closed ring shape, and includes two circumferentially spaced outer bumps 20, the structure of which is consistent with the size and height of the outer bumps 20 of the pixel area 201.

[0150] Optionally, such as Figure 1 , 2 As shown, after the epitaxial layer is patterned, a gap region 203 is formed between the pixel region 201 and the pad region 202. The width of the gap region 203 is an integer multiple of the spacing between adjacent epitaxial bumps 20. The gap region 203 exposes the first semiconductor layer 21 of the epitaxial layer 2.

[0151] Next, the first semiconductor layer 21 between adjacent epitaxial bumps 20 in the pixel area 201 is deeply etched using photolithography and ICP etching technology to form non-interconnected isolation trenches 30. The width of the isolation trenches 30 is less than or equal to the distance between adjacent epitaxial bumps 20, and the depth is 1μm to 5μm. At least 1μm of the first semiconductor layer 21 is left unetched to the substrate 10. Subsequently, reflective / light-absorbing materials are filled to achieve pixel-level full-depth optical isolation and eliminate crosstalk and color mixing problems.

[0152] Then, the first electrode 40 is fabricated. The first electrode 40 is fabricated in the region between adjacent epitaxial bumps 20 and between adjacent isolation trenches 30 within the pixel region 201 by photolithography and electron beam / magnetron sputtering processes.

[0153] For example, the material used to prepare the first electrode 40 may be a single or combined material such as Cr, Ti, Ni, Pt, Al, Au, etc.

[0154] For example, the first electrode 40 is in the shape of a circle or square, the diameter of the first electrode 40 is more than 2 μm smaller than the spacing between adjacent epitaxial bumps 20, and the thickness is 0.1 μm to 1 μm, which is lower than the height of the epitaxial bumps 20.

[0155] Step S12 may be followed by the following steps: First, the first dielectric layer 51 is fabricated. The first dielectric layer 51 is prepared in the pixel region 201 and the pad region 202 using a plasma-enhanced chemical vapor deposition / atomic layer deposition (PECVD) coating system.

[0156] For example, the material used to prepare the first dielectric layer 51 may be at least one of SiNx, Al2O3, SiO2, and TiO2. Alternatively, it may be two of the materials used in the preparation, with the two materials being alternately layered to form a DBR reflective structure.

[0157] For example, the thickness of the first dielectric layer 51 is 0.1 μm to 2 μm.

[0158] Optionally, in pixel region 201, a first dielectric layer 51 covers each epitaxial bump 20, and multiple sets of vias 61 are fabricated by photolithography and dry / wet etching. A portion of the vias 61 expose the second semiconductor layer 23 of the epitaxial bump 20, and each epitaxial bump 20 corresponds to multiple vias 61 arranged axially symmetrically. Another portion of the vias 61 exposes the first electrode 40 of the gap region 203. The via patterns 61 can be circular, square, or polygonal, with dimensions and positions matching the corresponding structure.

[0159] Optionally, in the pad area 202, the first dielectric layer 51 has no vias 61 exposed to the underlying epitaxial bumps 20, and only serves as an insulating layer to cover the epitaxial bumps 20 and the first metal layer 71 of the pad area 202, ensuring that the pad area 202 and the mesa of the pixel area 201 have the same height.

[0160] Next, a first metal layer 71 is prepared on the side of the first dielectric layer 51 away from the substrate 10.

[0161] For example, the material used to prepare the first metal layer 71 may be a single or combined metal structure such as Ag, Al, Cr, Ti, Pt, Au, etc. The thickness of the first metal layer 71 is 0.1 μm to 1 μm.

[0162] In pixel region 201, the first metal layer 71 is electrically connected to the second semiconductor layer 23 of the epitaxial bump 20 through via 61, and the distance from the outer periphery to the edge of the epitaxial bump 20 is 1μm to 10μm, which serves as a reflector to improve light extraction efficiency.

[0163] In pad area 202, the first metal layer 71 is located on the first dielectric layer 51 and is insulated from each epitaxial bump 20. It is prepared in the same batch as the first metal layer 71 in pixel area 201 to ensure that the two are highly consistent.

[0164] Step S13: Etch the first semiconductor layer 21 of the pad area 202 to form each epitaxial bump 20 surrounding the pad area 202 and expose the dicing channel 204 of the substrate 10.

[0165] like Figure 11 , 12 As shown, a cutting channel 204 is also formed around the pad area 202, with a width that is also an integer multiple of the spacing between adjacent extension bumps 20, and is distributed around the pad area 202.

[0166] In this design, the dicing channel 204 completely etches through the epitaxial layer to expose the patterned surface of the substrate. By setting the dicing channel around the pad area, the problem of epitaxial damage to internal pixels caused by laser lift-off can be solved.

[0167] The process after step S13 further includes preparing a second dielectric layer 52 using a plasma-enhanced chemical vapor deposition / atomic layer deposition apparatus.

[0168] For example, the second dielectric layer 52 includes at least one of a silicon nitride layer, an aluminum oxide layer, a silicon oxide layer, and a titanium oxide layer.

[0169] For example, the second dielectric layer 52 comprises alternating layers of silicon oxide and titanium oxide to form a DBR mirror. The thickness of the second dielectric layer 52 is from 0.1 μm to 1 μm.

[0170] In pixel area 201, the second dielectric layer 52 forms a first through hole 62 to expose the first electrode 40 and a second through hole 63 to expose the first metal layer 71, and the diameter of the through hole is larger than the corresponding through hole diameter of the first dielectric layer 51 to improve heat dissipation efficiency; the second dielectric layer 52 covers the first metal layer 71 in pad area 202.

[0171] Next, the electrode connecting to the third dielectric layer 53 is prepared.

[0172] A first connection electrode 72 is fabricated on the second dielectric layer 52 of the pixel region 201 and the pad region 202, and is connected to the first electrode 40 through the first via 62; a second connection electrode 73 is fabricated on the second dielectric layer 52 of the pixel region 201, and is connected to the first metal layer 71 through the second via 63. The two electrodes are arranged at intervals to avoid short circuits.

[0173] Optionally, the third dielectric layer 53 is located on the first connection electrode 72 and the second connection electrode 73. The third dielectric layer 53 has a through-hole exposing the second connection electrode 73 of the pixel area 201 and a through-hole exposing the first connection electrode 72 of the pad area 202.

[0174] For example, the third dielectric layer 53 includes at least one of a silicon nitride layer, an aluminum oxide layer, a silicon oxide layer, and a titanium oxide layer.

[0175] For example, the third dielectric layer 53 comprises alternating layers of silicon oxide and titanium oxide to form a DBR reflector. The thickness of the third dielectric layer 53 is 0.1 μm to 1 μm.

[0176] Step S14: Prepare the first pad 81 and the second pad 82.

[0177] The first pad 81 is located in the pad area 202 and is connected to the first connection electrode 72 of the pad area 202, thereby achieving an electrical connection with the first semiconductor layer 21 of the epitaxial bump 20 of the pixel area 201; the second pad 82 is located in the pixel area 201 and is connected to the second connection electrode 73 of the pixel area 201, thereby achieving an electrical connection with the second semiconductor layer 23 of the epitaxial bump 20 of the pixel area 201.

[0178] For example, both the first pad 81 and the second pad 82 may include at least one of the following: a Cr layer, a Ti layer, a Pt layer, an Au layer, a Ni layer, and an AuSn layer.

[0179] As an example, the thickness of the first pad 81 and the second pad 82 is 2 μm to 8 μm.

[0180] The above does not constitute any limitation on this application. Although this application has been disclosed above through embodiments, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A light-emitting device, characterized in that, The light-emitting device includes: a substrate (10), an epitaxial layer (2), a first pad (81) and a second pad (82). The epitaxial layer (2) is located on the substrate (10). The epitaxial layer (2) includes a first semiconductor layer (21) and a second semiconductor layer (23) stacked in a direction away from the substrate (10). The epitaxial layer (2) has pixel regions (201) and pad regions (202) arranged at intervals. The surfaces of the epitaxial layer (2) of the pixel region (201) and the epitaxial layer (2) of the pad region (202) away from the substrate (10) each have a plurality of epitaxial bumps (20) arranged at intervals. The first semiconductor layer (21) of each epitaxial bump (20) is connected, and the second semiconductor layer (23) of each epitaxial bump (20) is spaced apart. The first pad (81) is located in the pad area (202) and is electrically connected to the first semiconductor layer (21) of the epitaxial bump (20) of the pixel area (201). The second pad (82) is located in the pixel area (201) and is electrically connected to the second semiconductor layer (23) of the epitaxial bump (20) of the pixel area (201).

2. The light-emitting device according to claim 1, characterized in that, In the pixel region (201), the first semiconductor layer (21) between adjacent epitaxial bumps (20) has an isolation trench (30) for filling at least one of a reflective material and a light-absorbing material; The orthographic projection of the epitaxial bump (20) on the surface of the substrate (10) is polygonal, and each side of the epitaxial bump (20) is provided with the isolation groove (30), and the isolation grooves (30) corresponding to each side of the epitaxial bump (20) are not connected to each other.

3. The light-emitting device according to claim 2, characterized in that, The light-emitting device further includes a first electrode (40), which is located in the gap between adjacent epitaxial bumps (20) in the pixel area (201) and between adjacent isolation grooves (30).

4. The light-emitting device according to claim 3, characterized in that, The light-emitting device further includes a first dielectric layer (51), which is located at least in the pixel region (201). The first dielectric layer (51) in the pixel region (201) has a plurality of vias (61), a portion of which expose the second semiconductor layer (23) of the epitaxial bump (20), and another portion of which expose the first electrode (40).

5. The light-emitting device according to claim 4, characterized in that, Each of the external protrusions (20) is provided with a plurality of vias (61) arranged at intervals, and the plurality of vias (61) provided for each external protrusion (20) are arranged symmetrically along the axis.

6. The light-emitting device according to claim 4, characterized in that, The first dielectric layer (51) is also located in the pad area (202), and the first dielectric layer (51) in the pad area (202) covers each of the epitaxial bumps (20). The light-emitting device further includes a first metal layer (71), which is located on the side of each of the epitaxial bumps (20) away from the substrate (10); The first metal layer (71) in the pixel region (201) is connected to the second semiconductor layer (23) of the epitaxial bump (20) through the via (61); The first metal layer (71) in the pad area (202) is located on the first dielectric layer (51) and is insulated from each of the epitaxial bumps (20).

7. The light-emitting device according to claim 6, characterized in that, The light-emitting device further includes: a second dielectric layer (52), a first connecting electrode (72), and a second connecting electrode (73), wherein the second dielectric layer (52) is located on the surface of the first dielectric layer (51) away from the substrate (10); The second dielectric layer (52) in the pixel area (201) has a first through hole (62) and a second through hole (63), the first through hole (62) exposes the first electrode (40), and the second through hole (63) exposes the first metal layer (71). The second dielectric layer (52) in the pad area (202) at least covers the first metal layer (71). The first connecting electrode (72) is located on the second dielectric layer (52) of the pixel area (201) and the pad area (202), and is connected to the first electrode (40) through the first via (62); The second connection electrode (73) is located on the second dielectric layer (52) of the pixel area (201) and is connected to the first metal layer (71) through the second via (63). The first connection electrode (72) and the second connection electrode (73) are arranged at intervals. The first pad (81) is connected to the first connection electrode (72) of the pad area (202), and the second pad (82) is connected to the second connection electrode (73) of the pixel area (201).

8. The light-emitting device according to claim 7, characterized in that, The light-emitting device further includes a third dielectric layer (53), which is located on the first connecting electrode (72) and the second connecting electrode (73). The third dielectric layer (53) has a through hole exposing the second connecting electrode (73) of the pixel area (201) and a through hole exposing the first connecting electrode (72) of the pad area (202). The first pad (81) is connected to the first connecting electrode (72) of the pad area (202) through the through hole of the third dielectric layer (53), and the second pad (82) is connected to the second connecting electrode (73) of the pixel area (201) through the through hole of the third dielectric layer (53). The first dielectric layer (51), the second dielectric layer (52), and the third dielectric layer (53) are all insulating reflective layers; The first metal layer (71), the first connecting electrode (72) and the second connecting electrode (73) are all metal reflective layers.

9. The light-emitting device according to any one of claims 1 to 8, characterized in that, The pad area (202) is projected onto the substrate (10) in a closed loop shape, and the pad area (202) surrounds the pixel area (201).

10. A method for fabricating a light-emitting device, characterized in that, The preparation method includes: An epitaxial layer (2) is formed on a substrate (10), the epitaxial layer (2) comprising a first semiconductor layer (21) and a second semiconductor layer (23) stacked in a direction away from the substrate (10). The epitaxial layer (2) is patterned to form pixel regions (201) and pad regions (202) arranged at intervals. The epitaxial layer (2) of the pixel region (201) and the epitaxial layer (2) of the pad region (202) away from the substrate (10) each have a plurality of epitaxial bumps (20) arranged at intervals. The first semiconductor layer (21) of each epitaxial bump (20) is connected, and the second semiconductor layer (23) of each epitaxial bump (20) is spaced apart. The first semiconductor layer (21) of the pad area (202) is etched to form epitaxial bumps (20) surrounding the pad area (202) and expose the cleavage (204) of the substrate (10). A first pad (81) and a second pad (82) are fabricated. The first pad (81) is located in the pad area (202) and is electrically connected to the first semiconductor layer (21) of the epitaxial bump (20) of the pixel area (201). The second pad (82) is located in the pixel area (201) and is electrically connected to the second semiconductor layer (23) of the epitaxial bump (20) of the pixel area (201).

Images