A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer and a preparation method thereof

Abstract

The present application relates to the technical field of CMOS inverter, and particularly relates to a CMOS inverter based on a single-layer bipolar polymer semiconductor active layer and a preparation method thereof. The CMOS inverter based on a single-layer bipolar semiconductor polymer thin film as an active layer often cannot be completely turned off under the conditions of on-state and off-state, the static power consumption is relatively high, and the signal-to-noise ratio is also poor. In view of the above problems, the present application provides a CMOS inverter based on a single-layer bipolar polymer semiconductor active layer, which is a top gate bottom contact structure, the N-type source-drain layer and the P-type source-drain layer are arranged side by side and spaced apart on the surface of an insulating substrate, and bipolar semiconductor polymer DPP-DTT is used as the active layer. By optimizing the electrode material combination, the leakage current of the inverter under the off-state condition is effectively suppressed, and the low-power-consumption, high-reliability logic inversion function is realized.

Description

Technical Field

[0001] This invention relates to the field of CMOS inverter technology, and specifically to a CMOS inverter based on a single-layer bipolar polymer semiconductor active layer and its fabrication method. Background Technology

[0002] Organic integrated circuits have become an important development direction in the field of organic electronics. However, problems such as charge transport characteristic control and electrical contact engineering still pose serious challenges to the development of organic circuits. Taking the current mainstream digital integrated circuits as an example, in order to achieve the goals of low power consumption, wide noise margin, and high gain, the industry generally adopts the complementary metal-oxide-semiconductor (CMOS) structure. This structure is composed of a P-type transistor and an N-type transistor, which can effectively reduce static power consumption and improve the signal-to-noise ratio performance of the circuit.

[0003] There are two main technical paths to realizing organic CMOS inverters. The first path involves fabricating N-type and P-type devices on the same substrate using two different organic semiconductor materials, i.e., constructing conductive channels by separately depositing P-type and N-type organic semiconductors. The second path uses a single bipolar organic semiconductor material, enabling it to possess both N-type and P-type functionality. Bipolar organic semiconductor materials have the ability to transport both electrons and holes; therefore, using this material to construct inverters eliminates the need for precise separate deposition of P-type and N-type materials, significantly simplifying the device fabrication process.

[0004] Regardless of the technical approach used, achieving optimal performance for CMOS inverters requires well-matched P-type and N-type OFETs. However, the current development level of N-type OFETs lags far behind that of P-type OFETs, and this gap has become a key bottleneck restricting the performance improvement of organic CMOS circuits. Research indicates that this gap is mainly due to two factors. First, N-type transistors have poor operational stability and are easily affected by the water and oxygen content in the natural environment. When devices are exposed to environments containing water and oxygen, water and oxygen molecules can penetrate into the semiconductor layer, producing an effect similar to P-type doping, forming defect centers and trapping freely moving electrons, thereby degrading device performance.

[0005] Secondly, the contact problem is particularly prominent in N-type OFETs. When an N-type organic semiconductor comes into contact with a metal electrode, an energy level barrier is formed between them, resulting in a corresponding contact resistance. The higher the energy level barrier, the greater the contact resistance, which is less conducive to electron injection and transport between the N-type organic semiconductor and the electrode. Most N-type semiconductors have a lowest unoccupied molecular orbital energy level higher than -4.0 eV, and the metals that match their energy levels are low work function metals, such as calcium, magnesium, silver, and aluminum. Although these metals are suitable as electrode materials for contacting N-type organic semiconductors from an energy level matching perspective, they are easily oxidized in air, which seriously affects the stability of the OFET. In contrast, gold has excellent air stability and good conductivity, making it one of the preferred materials for fabricating OFET electrodes. However, gold has a high work function (about 5 eV), which forms a high energy level barrier when in contact with most N-type organic semiconductors, and gold electrodes are also expensive, limiting their application in large-scale integration processes.

[0006] In addition, there have been reports of using bipolar materials to construct inverters, but these bipolar inverters often cannot be completely turned off under both on and off conditions, and their static power consumption is higher than that of traditional CMOS inverters, and their signal-to-noise ratio is also reduced.

[0007] To address the aforementioned technical issues, a novel CMOS inverter structure is needed. This structure should not only simplify the device fabrication process by utilizing bipolar organic semiconductor materials but also overcome the contact and stability problems of N-type OFETs through reasonable electrode engineering design. This would enable the achievement of high-performance P-type and N-type organic transistors with matched performance, thereby obtaining an organic CMOS inverter that meets the requirements of low power consumption, high gain, and wide noise margin. Summary of the Invention

[0008] The existing technology has the problem that CMOS inverters based on a single-layer bipolar polymer semiconductor thin film as the active layer often cannot be completely turned off under both on and off states, resulting in high static power consumption and poor signal-to-noise ratio. To address these issues, this invention provides a CMOS inverter based on a single-layer bipolar polymer semiconductor active layer. Its structure is a top-gate-bottom-contact structure, comprising, from bottom to top, an insulating substrate, source / drain electrode layers, an active layer, a gate dielectric layer, and a gate electrode layer; the source / drain electrode layers are completely covered by the active layer, and the active layer is completely covered by the gate dielectric layer. The source / drain electrode layer includes N-type source / drain electrode pairs and P-type source / drain electrode pairs; Both N-type source and drain electrode pairs have a layered structure. Each electrode is composed of a Ni electrode layer and an Au electrode layer from bottom to top. The thickness of the Ni electrode layer is 3-6 nm, and the thickness of the Au electrode layer is 45-55 nm. The adjacent end faces of the N-type source and drain electrode pairs are parallel and spaced apart. Both P-type source and drain electrode pairs have a layered structure. Each electrode is composed of a first metal Ti electrode layer (thickness is 3-6 nm), an Al electrode layer, and a second metal Ti electrode layer (thickness is 3-6 nm) from bottom to top. The thickness of the Al electrode layer is 30-40 nm. The adjacent end faces of the P-type source and drain electrode pairs are parallel and spaced apart. The N-type source / drain electrode pair and the P-type source / drain electrode pair have the same width along the length of the glass substrate, and the conductive metal layers on their adjacent end faces are in contact and bonded together; the active layer is made of bipolar semiconductor polymer DPP-DTT.

[0009] Preferably, the insulating substrate is a common glass substrate.

[0010] Preferably, the material used for the gate dielectric layer is polymethyl methacrylate (PMMA).

[0011] Preferably, the thickness of the gate dielectric layer (the vertical distance between the highest point on the upper surface of the gate dielectric layer and the lowest point on the upper surface of the active layer) is 500-1000 nm.

[0012] Preferably, the gate electrode layer is a metallic aluminum layer.

[0013] Preferably, the thickness of the gate electrode layer (the vertical distance between the highest point on the upper surface of the gate electrode layer and the lowest point on the upper surface of the gate dielectric layer) is 80-100 nm.

[0014] Preferably, the thickness of the active layer (the vertical distance between the highest point of the upper surface of the active layer and the upper surface of the glass substrate) is 20-30 nm.

[0015] Preferably, the length of the N-type source-drain electrode pair or the P-type source-drain electrode pair along the width direction of the glass substrate is 1000-1200 μm.

[0016] Preferably, the parallel spacing between the P-type source / drain electrode pairs or the N-type source / drain electrode pairs along the length of the glass substrate is 80-100 μm.

[0017] Beneficial effects: (1) This invention employs a structure in which N-type source-drain electrode pairs and P-type source-drain electrode pairs are arranged side by side, combined with bipolar semiconductor polymer DPP-DTT as the active layer. By optimizing the electrode material combination, the leakage current of the inverter under the off-state condition is effectively suppressed. Tests show that the off-state voltage of the CMOS inverter fabricated by this invention can be reduced to below 3 V, and the static power consumption is reduced by 79% compared to traditional single-layer bipolar inverters. Simultaneously, the noise margin is increased to over 62%, achieving low-power, high-reliability logic switching functionality.

[0018] (2) In this invention, the P-type source-drain electrode pair adopts a composite structure of nickel and gold layers, with the nickel layer as the bottom layer and the gold layer as the top layer. The nickel layer forms a good energy level match with the organic semiconductor, reducing the electron injection barrier; the gold layer provides excellent anti-oxidation protection, avoiding the problem of low work function metals being oxidized in air. Tests have shown that the contact resistance of the P-type organic field-effect transistor under this structure can be as low as 50 × 10⁻⁶. 6 Ω·cm.

[0019] (3) In this invention, the N-type source-drain electrode pair adopts a composite structure of a first titanium layer, an aluminum layer, and a second titanium layer. The first titanium layer improves the adhesion between the aluminum layer and the insulating substrate, the aluminum layer provides a low-resistance path as the main conductive layer, and the second titanium layer prevents the aluminum layer from oxidizing in subsequent processes. By optimizing the thickness of each metal layer, the ratio of hole mobility of the N-type organic field-effect transistor to electron mobility of the P-type organic field-effect transistor is controlled within the range of 0.8 to 1, and the threshold voltage deviation between the two is less than 5V. The above design ensures that the CMOS inverter achieves high gain, with a measured gain of over 50, and has a wide noise margin, with a low-level noise margin of 62.2%.

[0020] (4) This invention achieves the channel functions of both P-type and N-type transistors simultaneously with a single deposition of a bipolar polymer semiconductor layer, avoiding the complex process of depositing two different semiconductor materials separately. Furthermore, the metal materials used—nickel, gold, titanium, and aluminum—are all commonly used in the microelectronics field. The source and drain electrode layers can be patterned using a single mask evaporation process, and the gate dielectric layer is made of polymethyl methacrylate deposited via solution deposition. The overall process is highly compatible and suitable for large-area, low-cost manufacturing. It is estimated that compared to organic CMOS inverters using two independent semiconductors, this invention reduces the number of process steps by more than 30% and lowers the manufacturing cost of a single device by 40%. Attached Figure Description

[0021] Figure 1 : This is a 3D structural schematic diagram of the CMOS inverter (Al / Ti-Au inverter) obtained in Embodiment 1 of the present invention.

[0022] Figure 2 This is a schematic diagram of the process for fabricating a CMOS inverter (Al / Ti-Au inverter) in Embodiment 1 of the present invention.

[0023] Figure 3 The red curve represents the transfer characteristic curve of the N-type and P-type transistors in the CMOS inverter obtained in Embodiment 1 of the present invention, and the blue curve represents the transfer characteristic curve of the P-type transistor.

[0024] Figure 4: This is a comparison chart of the voltage transfer characteristic curves (VTC) of the CMOS inverters obtained in Comparative Example 1 and Example 1, respectively.

[0025] Figure 5 : Comparison chart of the gains of the CMOS inverters obtained in Comparative Example 1 and Example 1 (power supply voltage Vdd is set to -50 V, -60 V, and -70 V respectively).

[0026] Figure 6 : Schematic diagram of the Au-Au inverter obtained in Comparative Example 1. Detailed Implementation

[0027] The present invention will be described in detail below with reference to embodiments. However, it should be understood that the following embodiments are merely illustrative examples of implementation of the present invention and are not intended to limit the scope of the present invention.

[0028] Example 1 A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer has a top-gate bottom contact structure, which is composed of an insulating substrate, a source / drain electrode layer, an active layer, a gate dielectric layer and a gate electrode layer from bottom to top; the source / drain electrode layer is completely and uniformly covered by the active layer, and the active layer is completely and uniformly covered by the gate dielectric layer. The source / drain electrode layer includes N-type source / drain electrode pairs and P-type source / drain electrode pairs; Both P-type source and drain electrode pairs have a layered structure. Each electrode is composed of a Ni electrode layer (5nm thick) and an Au electrode layer (50nm thick) from bottom to top. The adjacent end faces of the N-type source and drain electrode pairs are parallel and spaced apart. Both N-type source and drain electrode pairs have a layered structure. Each electrode is composed of a first metal Ti electrode layer (5 nm thick), an Al electrode layer (40 nm thick), and a second metal Ti electrode layer (5 nm thick) from bottom to top. The adjacent end faces of the N-type source and drain electrode pairs are parallel and spaced apart. The N-type source-drain electrode pair and the P-type source-drain electrode pair have the same width (200 μm) along the length of the glass substrate, and the conductive metal layers on their adjacent end faces are in contact and bonded together; the active layer is made of bipolar semiconductor polymer DPP-DTT (CAS No. 1260685-66-2).

[0029] The insulating substrate is a glass substrate with a thickness of 1 mm.

[0030] The gate dielectric layer is made of polymethyl methacrylate (PMMA). The thickness of the gate dielectric layer (the vertical distance between the highest point on the upper surface of the gate dielectric layer and the lowest point on the upper surface of the active layer) is 1 μm.

[0031] The gate electrode layer is an aluminum layer. The thickness of the gate electrode layer (the vertical distance between the highest point on the upper surface of the gate electrode layer and the lowest point on the upper surface of the gate dielectric layer) is 80 nm.

[0032] The thickness of the active layer (the vertical distance between the highest point of the upper surface of the active layer and the upper surface of the glass substrate) is 20 nm.

[0033] The lengths of the N-type source / drain electrode pair and the P-type source / drain electrode pair along the width of the glass substrate are 1200 μm.

[0034] The parallel spacing between P-type source / drain electrode pairs or N-type source / drain electrode pairs along the length of the glass substrate is 2400 μm.

[0035] The specific fabrication steps of a CMOS inverter are as follows: Step 1: Solution Preparation A1: Preparation of semiconductor solution The bipolar semiconductor polymer DPP-DTT was added to chlorobenzene to obtain a semiconductor solution with a mass concentration of 5 mg / mL. A2: Preparation of gate dielectric solution The polymer PMMA was added to n-butyl acrylate to obtain a gate dielectric solution with a mass concentration of 80 mg / mL; A3: Dissolution of the solution The prepared semiconductor solution was heated at 80°C for 48 hours; the prepared gate dielectric solution was heated at 80°C for 24 hours. Step 2: Fabrication of the inverter B1: Substrate cleaning The glass substrate was placed in deionized water and 75% alcohol in sequence, and ultrasonically cleaned for 20 minutes each. Then it was dried with a nitrogen gun and heated at 100°C for 15 minutes. B2: Fabrication of N-type and P-type source / drain electrodes Fabrication of source and drain electrodes (N-type source and drain layer) for N-type transistors: Using thermal evaporation technology, titanium and aluminum metal particles are first placed on vacuum evaporation boats one and two, respectively. Then, an N-type stainless steel source / drain mask is cleaned, placed on the glass substrate, and introduced into the evaporation apparatus chamber. A mechanical pump and a molecular pump are used to evaporate the chamber to a vacuum level of 10. -4Pa; then rotate the power control knob to heat the first evaporation boat. Finally, the thermal evaporation current reaches about 170A, and a titanium electrode layer with a thickness of 5 nm is prepared at a rate of 0.02 nm / s. Then, slowly reduce the power. After the power is finished, rotate the power control knob again to heat the second evaporation boat. Finally, the thermal evaporation current reaches about 100A, and an aluminum electrode layer with a thickness of 40 nm is prepared at a rate of 0.02 nm / s. Then, slowly reduce the power. After the power is finished, rotate the power control knob again to heat the first evaporation boat. Finally, the thermal evaporation current reaches about 170A, and a titanium electrode layer with a thickness of 5 nm is prepared at a rate of 0.01 nm / s, thus obtaining the N-type source and drain electrode layer; Fabrication of source and drain electrodes (P-type source and drain layer) of a P-type transistor: First, gold and nickel metal particles are placed on two separate evaporation boats. Then, a clean P-type stainless steel source / drain mask is placed on the upper surface of the glass substrate and sent into the cavity of the evaporation apparatus. A mechanical pump and a molecular pump are used to evaporate the cavity of the evaporation apparatus to a vacuum of 10. -4 Pa; then rotate the power control knob to heat the first evaporation boat, with the thermal evaporation current reaching about 100A, to prepare a nickel electrode layer with a thickness of 5 nm at a rate of 0.02 nm / s; then slowly reduce the power until it reaches zero, then heat the second evaporation boat, with the thermal evaporation current reaching about 100A, to prepare a gold electrode layer with a thickness of 50 nm at a rate of 0.02 nm / s; finally, slowly reduce the power, and after the chamber has cooled for about 30 minutes, fill it with nitrogen gas, open the chamber, and take out the sample to obtain the P-type source and drain layer; B3: Preparation of semiconductor thin films The surface of the source and drain electrode layers was cleaned using air blowing. A semiconductor solution that had been prepared and kept at a constant temperature for 48 hours was dropped onto the surface of the P-type source and drain electrode layers using a pipette, covering the entire surface of the glass substrate. A spin coater was used to pre-coat the layers at 500 rpm for 5 seconds, followed by spin coating at 2000 rpm for 60 seconds. After spin coating, the layers were annealed at 200°C for 1 hour, and then allowed to cool naturally for 40 minutes to obtain the QSC layer (active layer). B4: Fabrication of gate dielectric thin films The surface containing the QSC layer was cleaned with air blowing. The prepared gate dielectric solution was spread on the surface of the glass slide using a pipette. The slide was pre-coated at 500 rpm for 3 seconds and then at 2000 rpm for 60 seconds using a spin coater. After spin coating, the slide was annealed at 80°C for 2 hours to obtain the gate dielectric layer. B5: Gate Fabrication Using thermal evaporation technology, aluminum metal particles are first placed on a vacuum evaporation boat. Then, a cleaned stainless steel source / drain mask is placed on top of a glass slide and sent into the cavity of the evaporation apparatus. Mechanical and molecular pumps are used to evaporate the cavity of the evaporation apparatus to a vacuum level of 10. -4 Pa; turn on the evaporation boat and gradually increase the evaporation power by adjusting the power control knob; finally, the thermal evaporation current reaches about 100 A, and an aluminum gate electrode layer with a thickness of 80 nm is prepared at a rate of 0.02 nm / s; finally, slowly reduce the power, wait for the chamber to cool for about 30 minutes, fill with nitrogen, open the chamber and take out the sample, and a CMOS inverter based on a single-layer bipolar polymer semiconductor active layer is obtained.

[0036] Comparative Example 1 (The structural schematic diagram of the obtained Au-Au inverter is shown in the attached instruction manual) Figure 6 (As shown) An Au-Au inverter is fabricated using the same steps as in Example 1, except that its N-type source-drain electrode pair differs from that in Example 1. The fabrication method of the N-type source-drain electrode pair in Comparative Example 1 is the same as that of the P-type source-drain electrode pair in Example 1. The N-type source-drain electrode pair in Comparative Example 1 has a layered structure, with each electrode composed of a Ni electrode layer (5 nm thick) and an Au electrode layer (50 nm thick) sequentially from bottom to top. The adjacent end faces of the N-type source-drain electrode pairs are parallel and spaced apart. The length of each electrode in the N-type source-drain electrode pair along the width direction of the glass substrate is 1200 μm, and the parallel spacing between the P-type source-drain electrode pairs along the length direction of the glass substrate is 2400 μm.

[0037] Instruction manual attached Figure 1 This is a schematic diagram of the 3D structure of the CMOS inverter based on a single-layer bipolar polymer semiconductor active layer obtained in Example 1.

[0038] Instruction manual attached Figure 2 This is a schematic diagram of the process for fabricating a CMOS inverter (denoted as Al / Ti-Au inverter in the figure) according to Embodiment 1 of the present invention.

[0039] Instruction manual attached Figure 3 These are the transfer characteristic curves of the N-type and P-type transistors in the CMOS inverter obtained in Embodiment 1 of the present invention. Figure 3 It is understood that the N-type transistor with Al / Ti contact and the P-type transistor with Au contact in the CMOS inverter obtained in Embodiment 1 of the present invention have matching performance (especially their turn-on voltage and on-state current), and the combination of N-type and P-type transistors with matching performance can realize a high-performance CMOS inverter.

[0040] Instruction manual attached Figure 4 This is a comparison chart of the voltage transfer characteristic curves (VTC) of the CMOS inverters obtained in Comparative Example 1 and Example 1, respectively.

[0041] Instruction manual attached Figure 5 This is a comparison chart of the gains of the CMOS inverters obtained in Comparative Example 1 and Example 1 (with power supply voltage Vdd set to -50 V, -60 V, and -70 V respectively).

[0042] Depend on Figure 4 , Figure 5 Analysis shows that the CMOS inverters obtained in Example 1, based on titanium / aluminum / titanium and nickel / gold as N-type and P-type source / drain electrodes respectively, have significantly better VTC curve performance than the CMOS inverters obtained in Comparative Example 1, which use traditional nickel / gold as source / drain electrodes for both N-type and P-type inverters. The former surpasses the latter in all basic electrical parameters. Table 1 lists the electrical parameters of the two inverters, including gain, power consumption, and noise margin. V dd = -70 V). The CMOS inverter obtained in Comparative Example 1 has a gain of 38V, a power consumption of 37.6 μW, and a noise margin of 45.7%. The CMOS inverter obtained in Example 1 of this invention has a gain of 51V, a power consumption of 7.8 μW, and a noise margin of 62.2%. Thus, it can be seen from the electrical parameters in Table 1 that the electrical performance of the CMOS inverter obtained in Example 1 of this invention has been significantly improved.

[0043] Table 1

[0044] In Table 1, the CMOS inverter obtained in Comparative Example 1 is denoted as Au-Au inverter and the CMOS inverter obtained in Example 1 is denoted as Al / Ti-Au inverter.

[0045] The CMOS inverters obtained in Example 1, based on titanium / aluminum / titanium and nickel / gold as N-type and P-type source / drain electrodes respectively, show significantly better gains than the CMOS inverters obtained in Comparative Example 1, which use conventional nickel / gold as both N-type and P-type source / drain electrodes. The results demonstrate a significant performance improvement in the CMOS inverters obtained in Example 1, based on titanium / aluminum / titanium and nickel / gold as N-type and P-type source / drain electrodes respectively. Simultaneously, the fabrication cost is greatly reduced, providing a direction for future large-scale integration.

[0046] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer, characterized in that, It has a top-gate bottom-contact structure, which includes, from bottom to top, an insulating substrate, a source / drain electrode layer, an active layer, a gate dielectric layer, and a gate electrode layer; the source / drain electrode layer is completely covered by the active layer, and the active layer is completely covered by the gate dielectric layer; The source / drain electrode layer includes N-type source / drain electrode pairs and P-type source / drain electrode pairs; Both N-type source and drain electrode pairs have a layered structure. Each electrode is composed of a Ni electrode layer and an Au electrode layer from bottom to top. The thickness of the Ni electrode layer is 3-6 nm, and the thickness of the Au electrode layer is 45-55 nm. The adjacent end faces of the N-type source and drain electrode pairs are parallel and spaced apart. Both P-type source and drain electrode pairs have a layered structure. Each electrode is composed of a first metal Ti electrode layer, an Al electrode layer, and a second metal Ti electrode layer from bottom to top. The thickness of the Ti electrode layer is 3-6 nm, and the thickness of the Al electrode layer is 30-40 nm. The adjacent end faces of the P-type source and drain electrode pairs are parallel and spaced apart. The N-type source / drain electrode pair and the P-type source / drain electrode pair have the same width along the length of the glass substrate, and the conductive metal layers on their adjacent end faces are in contact and bonded together; the active layer is made of bipolar semiconductor polymer DPP-DTT.

2. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer according to claim 1, characterized in that, The insulating substrate is a common glass substrate.

3. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer according to claim 1, characterized in that, The material used for the gate dielectric layer is PMMA.

4. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer according to claim 3, characterized in that, The thickness of the gate dielectric layer is 500-1000 nm.

5. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer according to claim 1, characterized in that, The gate electrode layer is a metallic aluminum layer.

6. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer according to claim 1, characterized in that, The thickness of the gate electrode layer is 80-100 nm.

7. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer according to claim 1, characterized in that, The thickness of the active layer is 20-30 nm.

8. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer according to claim 1, characterized in that, The length of the N-type source / drain electrode pair or the P-type source / drain electrode pair along the width of the glass substrate is 1000-1200 μm.

9. A CMOS inverter based on a single-layer bipolar polymer semiconductor active layer according to claim 1, characterized in that, The parallel spacing between P-type source / drain electrode pairs or N-type source / drain electrode pairs along the length of the glass substrate is 80-100 μm.

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