Display device and electronic device including the same
Patent Information
- Application Number
- CN202512006095.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-02-18
- Filing Date
- 2025-12-29
- Publication Date
- 2026-08-18
Smart Images
Figure CN122602748A_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0020923, filed on February 18, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field
[0003] Some aspects of the implementation relate to a display device and an electronic device including the display device. Background Technology
[0004] With the advancement of information technology, the importance of display devices, which serve as a medium connecting users and information, has become increasingly prominent. For example, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), plasma displays, and quantum dot displays is increasing.
[0005] The display device includes pixels that display visible light. Each pixel may include an emissive layer. The emissive layer can be formed using an inkjet printing method.
[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention
[0007] Some aspects of embodiments of this disclosure include display devices and electronic devices in which two different emission regions are alternately arranged in a single pixel column, and the thickness of each emission region is uniform, thereby reducing display quality degradation and defect rate.
[0008] However, the features of embodiments according to this disclosure are not limited to the above description, and those skilled in the art will understand more clearly from the following description other features not mentioned herein.
[0009] According to some embodiments of the present disclosure, a display device includes: a substrate having a pixel column thereon, each of the pixel columns including a plurality of emission regions arranged in a first direction; a pixel electrode disposed on the substrate; a pixel defining layer surrounding the edge of the pixel electrode and configured to define each of the emission regions; a plurality of pixel column defining layers extending along the first direction on the pixel defining layer and spaced apart from each other in a second direction perpendicular to the first direction to define the pixel column; and an emission layer disposed on the pixel electrode, wherein the pixel column includes a first pixel column, a first emission region and a second emission region are alternately arranged in each of the first pixel column, and a waveform defining layer having a waveform along the first direction is disposed between the two pixel column defining layers defining each of the first pixel column on the pixel defining layer, and the first emission region or the second emission region is respectively arranged in the positive half-cycle or the negative half-cycle of the waveform defining layer.
[0010] According to some embodiments, the pixel column defining layer may include a first pixel column defining layer and a second pixel column defining layer defining each of the first pixel columns, a first emission region may be arranged such that the second pixel column defining layer is closer to the first pixel column defining layer, a second emission region may be arranged such that the first pixel column defining layer is closer to the second pixel column defining layer, and a waveform defining layer may extend between the first emission region and the first pixel column defining layer, between the first emission region and the second emission region, and between the second emission region and the second pixel column defining layer.
[0011] According to some implementations, the waveform defining layer can be arranged spaced apart from the pixel column defining layer.
[0012] According to some embodiments, the display device may further include a microchannel defined between a pulse width portion and a pixel column defining layer closest to the pulse width portion, the pulse width portion being a region extending in a first direction of the waveform defining layer.
[0013] According to some implementations, a microchannel may include: a first microchannel configured to connect two first transmission regions in a first transmission region that are adjacent to the second transmission region along a first direction based on the second transmission region; and a second microchannel configured to connect two second transmission regions in a second transmission region that are adjacent to the first transmission region along a first direction based on the first transmission region.
[0014] According to some implementations, the pixel column may further include a second pixel column adjacent to the first pixel column, and each of the second pixel columns may include a plurality of third emission regions arranged along the first direction.
[0015] According to some implementations, the first pixel column and the second pixel column can be arranged alternately along a second direction.
[0016] According to some implementations, each of the third launch regions may be arranged adjacent to the first launch region and the second launch region adjacent to the first launch region in the second direction.
[0017] According to some implementations, the length of the third launch region may correspond to the total length of the first launch region and the second launch region adjacent to the first launch region.
[0018] According to some implementations, the upper surface of the waveform defining layer and the upper surface of the pixel column defining layer may be hydrophobic.
[0019] According to some implementations, the upper surface of the pixel defining layer may be hydrophilic.
[0020] According to some implementations, the upper surface of the pixel column defining layer and the upper surface of the waveform defining layer can be positioned at a level higher than the upper surface of the emission layer.
[0021] According to some implementations, light-emitting elements, including pixel electrodes, an emission layer, and a common electrode on the emission layer, can be arranged in each of the emission regions.
[0022] According to some embodiments of the present disclosure, a display device includes: a substrate having a pixel column thereon, each of the pixel columns including a plurality of emission regions arranged in a first direction; a pixel electrode disposed on the substrate; a pixel defining layer surrounding an edge of the pixel electrode and configured to define each of the emission regions; a plurality of pixel column defining layers extending along the first direction on the pixel defining layer and spaced apart from each other in a second direction perpendicular to the first direction to define the pixel column; and an emission layer disposed on the pixel electrode, wherein the pixel column includes a first pixel column, a first emission region and a second emission region are alternately arranged in each of the first pixel column, and a waveform defining layer having a waveform along the first direction is disposed between two pixel column defining layers defining each of the first pixel column on the pixel defining layer, and each edge of the waveform defining layer is disposed between the first emission region and the second emission region.
[0023] According to some implementations, the pixel column defining layer may include a first pixel column defining layer and a second pixel column defining layer defining each of the first pixel columns, the first emission region may include a first side adjacent to the first pixel column defining layer, the second emission region may include a second side adjacent to the second pixel column defining layer, and the waveform defining layer may extend between the first side and the first pixel column defining layer, between the first emission region and the second emission region, and between the second side and the second pixel column defining layer.
[0024] According to some embodiments, the display device may further include: a microchannel defined between a pulse width portion and a pixel column defining layer closest to the pulse width portion, the pulse width portion being a region extending in a first direction of the waveform defining layer, wherein the microchannel may include: a first microchannel configured to connect two first emission regions in the first emission region that are adjacent to the second emission region along the first direction based on the second emission region; and a second microchannel configured to connect two second emission regions in the second emission region that are adjacent to the first emission region along the first direction based on the first emission region.
[0025] According to some implementations, the pixel column may further include a second pixel column adjacent to the first pixel column, each of the second pixel columns may include a plurality of third emission regions arranged along the first direction, and the first pixel column and the second pixel column may be arranged alternately along the second direction.
[0026] According to some implementations, the upper surface of the waveform defining layer and the upper surface of the pixel column defining layer can be hydrophobic, and the upper surface of the pixel defining layer can be hydrophilic.
[0027] According to some implementations, the upper surface of the pixel column defining layer and the upper surface of the waveform defining layer can be positioned at a level higher than the upper surface of the emission layer.
[0028] According to some embodiments of the present disclosure, an electronic device includes: a display device; a processor; a memory; and a power module, wherein the display device includes: a substrate having a pixel column thereon, each of the pixel columns including a plurality of emission regions arranged in a first direction; a pixel electrode disposed on the substrate; a pixel defining layer surrounding the edge of the pixel electrode and configured to define each of the emission regions; a plurality of pixel column defining layers extending along the first direction on the pixel defining layer and spaced apart from each other in a second direction perpendicular to the first direction to define the pixel column; and an emission layer disposed on the pixel electrode, wherein the pixel column includes a first pixel column, in each of the first pixel column a first emission region and a second emission region are alternately arranged, and on the pixel defining layer a waveform defining layer having a waveform along the first direction is arranged between the two pixel column defining layers defining each of the first pixel column, and the first emission region or the second emission region is respectively arranged in the positive half-cycle or the negative half-cycle of the waveform defining layer. Attached Figure Description
[0029] The accompanying drawings illustrate aspects of some embodiments of this disclosure and, together with the following disclosure, are intended to provide a further understanding of the technical spirit of the embodiments according to this disclosure. Therefore, the embodiments according to this disclosure are not to be construed as being limited to the drawings, in which: Figure 1 This is a plan view illustrating a display device according to some embodiments of the present disclosure; Figure 2 yes Figure 1 An enlarged view of an example of region A shown in the image; Figure 3 yes Figure 2 An enlarged view of an example of region B shown in the image; Figure 4 yes Figure 1 An enlarged view of another example of region A shown; Figure 5 yes Figure 1 An enlarged view of another example of region A shown; Figure 6 This is an equivalent circuit diagram of a light-emitting element according to some embodiments of the present disclosure; Figure 7 It is along Figure 2 An enlarged view of the example cross section intercepted by line I-I'; Figure 8 It is along Figure 2 An enlarged view of the example cross section intercepted by line II-II'; Figure 9 It is along Figure 2 An enlarged view of the example section intercepted by line III-III'; Figure 10 This is a block diagram of an electronic device according to some embodiments of the present disclosure; and Figure 11 A schematic diagram of an electronic device according to some embodiments is shown. Detailed Implementation
[0030] Because this disclosure allows for various modifications and multiple implementations, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. Features of some embodiments of this disclosure and methods for implementing them will be described more fully with reference to the accompanying drawings, in which aspects of some embodiments of this disclosure are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.
[0031] It will be understood that although the terms first and second are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.
[0032] As used herein, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
[0033] In the following examples, it should be understood that terms such as “including,” “having,” and “comprising” are intended to indicate the presence of a feature or component disclosed in the specification and are not intended to exclude the possibility that one or more other features or components may be present or may be added.
[0034] It will be understood that when a unit, region, or component is said to be formed on or above another unit, region, or component, it can be formed directly or indirectly on that other unit, region, or component. That is, for example, there can be intermediate units, regions, or components.
[0035] It will be understood that when an element is referred to as “connected” or “linked” to another element, it does not necessarily mean a direct connection or link and / or a fixed connection or link between the two elements, or that there may be an intervening element unless it has a clearly different meaning in the context.
[0036] In the accompanying drawings, the dimensions of the components may be enlarged or reduced for ease of explanation. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.
[0037] In the following, some aspects of embodiments of this disclosure will be described in detail with reference to the accompanying drawings. Identical or corresponding components are given the same reference numerals, and redundant explanations are omitted.
[0038] Figure 1 This is a plan view showing a display device 10 according to some embodiments of the present disclosure.
[0039] refer to Figure 1 According to some embodiments of the present disclosure, the display device 10 can be divided into a display area DA and a peripheral area PA. The display area DA can display an image, and the peripheral area PA can be positioned around the display area DA (e.g., outside the periphery of the display area DA or outside the coverage area of the display area DA). For example, the peripheral area PA can surround (e.g., completely surround) the display area DA.
[0040] According to some embodiments, the display device 10 may have a rectangular shape in a plan view. However, embodiments according to this disclosure are not necessarily limited to this, and the display device 10 may have various shapes in a plan view. The plane may be defined by a first direction DR1 and a second direction DR2 perpendicular to the first direction DR1. A third direction DR3 may be orthogonal to or perpendicular to the plane.
[0041] The light-emitting element PX can be disposed in the display area DA. The light-emitting element PX may include a first light-emitting element PX1 and a second light-emitting element PX2 adjacent to the first light-emitting element PX1. For example, the second light-emitting element PX2 may be adjacent to the first light-emitting element PX1 in the second direction DR2. However, the embodiments according to this disclosure are not limited thereto, and the second light-emitting element PX2 may be adjacent to the first light-emitting element PX1 in the first direction DR1 or in both the first direction DR1 and the second direction DR2.
[0042] The light-emitting element PX can emit light. For example, the first light-emitting element PX1 and the second light-emitting element PX2 can emit light simultaneously. According to some embodiments, when the first light-emitting element PX1 emits light, the second light-emitting element PX2 may not emit light, and when the second light-emitting element PX2 emits light, the first light-emitting element PX1 may not emit light. The display area DA can display an image.
[0043] The driver can be located in the peripheral area PA. The driver can provide signals and / or voltages to pixel P (see [reference]). Figure 6 For example, a driver can include a gate driver, a data driver, etc.
[0044] Display device 10 may include an organic light-emitting display device, an inorganic light-emitting display device, a quantum dot light-emitting display device, a micro light-emitting diode (LED) display device, a nano LED display device, a plasma display device, or a liquid crystal display device. In the following description, examples in which display device 10 is an organic light-emitting display device will be given.
[0045] Figure 2 yes Figure 1 An enlarged view of an example of region A shown, and Figure 3 yes Figure 2 An enlarged view of an example of region B shown.
[0046] refer to Figure 2 and Figure 3 Each pixel column PXC, comprising multiple emission regions EA arranged in rows, can be located on the substrate SUB (see [reference]). Figure 7 On. Figure 2In the diagram, the emission region EA is shown arranged in the first direction DR1, but the embodiments according to this disclosure are not limited thereto. That is, when the emission region EA is arranged in rows in the second direction DR2, each pixel column PXC extends in the second direction DR2, and multiple pixel columns PXC can be arranged in the first direction DR1. Hereinafter, the pixel columns PXC will be described based on the following situation: each pixel column PXC extends in the first direction DR1, multiple pixel columns PXC are arranged in the second direction DR2, and the emission region EA included in each pixel column PXC is arranged in rows in the first direction DR1.
[0047] Each emission region EA, serving as a region for emitting light, can be defined by a pixel-defined layer (PDL). The emission region EA may include a first emission region EA1 and a second emission region EA2, and according to some embodiments, may also include a third emission region EA3. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may be regions that emit light of different colors. For example, the first emission region EA1 may emit red light, the second emission region EA2 may emit green light, and the third emission region EA3 may emit blue light, but the embodiments according to this disclosure are not limited thereto.
[0048] The dimensions of the emission regions EA can be the same or different from each other. For example, the dimensions of each first emission region EA1 can be the same, and this can also apply to the second emission region EA2 and the third emission region EA3.
[0049] A pixel column (PXC) can be defined by pixel column defining layers (CS) spaced apart from each other in a second direction (DR2) perpendicular to the first direction (DR1). The pixel column defining layers (CS) can extend along the first direction (DR1) on the pixel defining layers (PDL). In other words, the region between two adjacent pixel column defining layers (CS) can be referred to as a pixel column (PXC). The width of the pixel column defining layers (CS) can be, for example, 10 μm or greater.
[0050] Each of the pixel columns PXC may include a first pixel column PXC1 in which a first emission region EA1 and a second emission region EA2 are alternately arranged. The first pixel column PXC1 is defined between two adjacent pixel column defining layers CS, and specifically, the pixel column defining layers CS may include a first pixel column defining layer CS1 and a second pixel column defining layer CS2 defining the first pixel column PXC1.
[0051] A waveform defining layer SWS can be arranged on the pixel defining layer PDL. The waveform defining layer SWS has a regular waveform that repeatedly rises and falls along a first direction DR1 within the first pixel column PXC1. Specifically, the waveform defining layer SWS can have a shape that repeats regularly with a constant period.
[0052] According to some implementations, the waveform definition layer SWS can have a square wave shape.
[0053] A square wave is a waveform that alternates rapidly between two values with a constant period, and can appear as a combination of horizontal and vertical lines. A square wave can exhibit sharp rises and falls around an edge E with a constant height. In other words, a square wave can be a waveform in which the transition from one state to another occurs immediately and directly.
[0054] Based on the characteristics of this square wave, the waveform defining layer SWS may include a pulse width portion PW as a region extending in the first direction DR1 and an edge E with a constant height representing a sharp rise or fall.
[0055] For example, in one cycle of the waveform limiting layer SWS, a first transmission region EA1 and a second transmission region EA2 can be arranged. Specifically, the first transmission region EA1 or the second transmission region EA2 can be arranged in the positive half-cycle or the negative half-cycle of the waveform limiting layer SWS, respectively.
[0056] For example, a first transmission region EA1 can be arranged in each positive half-cycle of a waveform limiting layer SWS, and a second transmission region EA2 can be arranged in each negative half-cycle of the waveform limiting layer SWS. The first transmission region EA1 and the second transmission region EA2 can be arranged alternately along a first direction DR1.
[0057] However, embodiments according to this disclosure are not limited thereto, and according to some embodiments, one or more transmit regions EA of the same type may be arranged in a positive half-cycle of the waveform defining layer SWS. In this case, the same number of transmit regions EA of other types may be arranged in a negative half-cycle of the waveform defining layer SWS.
[0058] In other words, each edge E of the waveform defining layer SWS can be positioned between the first transmission region EA1 and the second transmission region EA2. One type of transmission region EA can be positioned in the positive half-cycle of the waveform defining layer SWS, and another type of transmission region EA can be positioned in the negative half-cycle of the waveform defining layer SWS.
[0059] The first emission region EA1 can be arranged such that the second pixel column limiting layer CS2 is closer to the first pixel column limiting layer CS1 than the second pixel column limiting layer CS2, and the second emission region EA2 can be arranged such that the first pixel column limiting layer CS1 is closer to the second pixel column limiting layer CS2 than the first pixel column limiting layer CS1.
[0060] The waveform defining layer SWS can extend between the first emission region EA1 and the first pixel column defining layer CS1, between the first emission region EA1 and the second emission region EA2, and between the second emission region EA2 and the second pixel column defining layer CS2. In other words, the waveform defining layer SWS can be disposed between the emission region EA and the pixel column defining layer CS that is further away from the emission region EA among the two pixel column defining layers CS adjacent to the emission region EA.
[0061] The first emission region EA1 may include a first side F1 adjacent to the first pixel column defining layer CS1, and the second emission region EA2 may include a second side F2 adjacent to the second pixel column defining layer CS2. The first side F1 may be a pixel electrode ADE overlapping the first emission region EA1 (see [link to relevant documentation]). Figure 7 The second side F2 can be the region of the boundary between the pixel electrode ADE overlapping the second emission region EA2 and the pixel defining layer PDL arranged to cover the edge of the pixel electrode ADE. Similarly, the second side F2 can be the region of the boundary between the pixel electrode ADE overlapping the second emission region EA2 and the pixel defining layer PDL arranged to cover the edge of the pixel electrode ADE.
[0062] The waveform defining layer SWS can extend between the first side F1 and the first pixel column defining layer CS1, between the first emission region EA1 and the second emission region EA2, and between the second side F2 and the second pixel column defining layer CS2.
[0063] The waveform defining layer SWS can be arranged spaced apart from the pixel column defining layer CS. The microchannel MC can be defined between the pulse width portion PW of the waveform defining layer SWS and the pixel column defining layer CS closest to the pulse width portion PW.
[0064] Microchannels (MCs) can be used as channels to connect emitting regions (EAs) of the same type to each other. Microchannels (MCs) can connect inks placed in emitting regions (EAs) of the same type to each other. Due to the microchannels (MCs), ink can move between emitting regions (EAs) of the same type, which can result in a uniform overall film thickness throughout the emitting regions (EAs) of the same type. As a result, screen spot problems can be relatively improved, thereby improving the display quality of the display device 10, and ink spillage can be prevented, reduced, or mitigated even when foreign matter is present in a particular emitting region (EA).
[0065] The microchannel MC may include a first microchannel MC1 and a second microchannel MC2, wherein the first microchannel MC1 connects two first transmission regions EA1 that are adjacent to the second transmission region EA2 along the first direction DR1 based on the second transmission region EA2, and the second microchannel MC2 connects two second transmission regions EA2 that are adjacent to the first transmission region EA1 along the first direction DR1 based on the first transmission region EA1.
[0066] In other words, the first microchannel MC1 allows for the distribution and filling of ink within the first emission area EA1 of the same pixel column PXC, while reducing defects caused by foreign matter. Similarly, the second microchannel MC2 allows for the distribution and filling of ink within the second emission area EA2 of the same pixel column PXC, while also reducing defects caused by foreign matter.
[0067] The pixel column PXC may also include a second pixel column PXC2 adjacent to the first pixel column PXC1. According to some embodiments, the first pixel column PXC1 and the second pixel column PXC2 may be arranged alternately along the second direction DR2.
[0068] Each of the second pixel columns PXC2 may include a plurality of third emission regions EA3 arranged along the first direction DR1. For example, the third emission regions EA3 may be arranged adjacent to a pair of adjacent first emission regions EA1 and second emission regions EA2 in the second direction DR2. In other words, in the second pixel column PXC2 adjacent to the first pixel column PXC1 in which a pair of adjacent first emission regions EA1 and second emission regions EA2 are arranged, a third emission region EA3 corresponding to the pair of first emission regions EA1 and second emission regions EA2 may be arranged.
[0069] To increase the resolution of the display device 10, the size of one emission region EA must be reduced. However, in a display device in which the same type of emission regions EA are arranged in each pixel column PXC, the width of the emission regions EA is narrow, making it difficult to ensure sufficient ink deposition margin when ink is deposited on each emission region EA.
[0070] In contrast, in some embodiments of the display device 10 according to this disclosure, a third emission region EA3 corresponding to a pair of first emission regions EA1 and second emission regions EA2 is arranged in a second pixel column PXC2 adjacent to the first pixel column PXC1. Even when the overall size of each emission region EA is reduced, the width of each emission region EA can be increased, thereby ensuring ink deposition margin and facilitating the manufacturing process, as well as reducing production costs. That is, as described above, the display device 10 in which the first emission region EA1, the second emission region EA2, and the third emission region EA3 are arranged can prevent or reduce ink mixing between different types of emission regions EA, thereby reducing the defect rate and achieving high resolution.
[0071] For example, the total number of first launch regions EA1, the total number of second launch regions EA2, and the total number of third launch regions EA3 can be the same. According to some embodiments, the length d3 of the third launch region EA3 can correspond to the total length d of the first launch region EA1 and the second launch region EA2 adjacent to the first launch region EA1. The lengths of the first launch region EA1 and the second launch region EA2 can be the same or different.
[0072] In other words, in the first pixel column PXC1, the first emission region EA1 and the second emission region EA2, which are different types of emission regions EA, can be arranged alternately and separated by the waveform defining layer SWS. Therefore, the ink injected into the first emission region EA1 and the second emission region EA2 does not mix, and the first emission region EA1 and the second emission region EA2 can emit different colors, thereby relatively improving the display quality.
[0073] The first emitting regions EA1 can be connected to each other via the first microchannel MC1, and the second emitting regions EA2 can be connected to each other via the second microchannel MC2. Therefore, the thickness of the emitting regions EA can be constant, and the printing unevenness caused by differences in ink volume between adjacent emitting regions EA during the printing process can be relatively improved. Furthermore, even if foreign objects are present in a particular emitting region EA or the pixel defining layer PDL surrounding the emitting region EA is defective, no line defects will occur in the entire pixel column PXC in which the emitting regions EA are arranged, thereby relatively improving the defect rate of the display device 10.
[0074] Within the second pixel column PXC2, a third emission region EA3, which is of the same type as the emission region EA, is arranged, thereby controlling the volume difference of injected ink between adjacent third emission regions EA3 that may occur during the manufacturing process. As a result, printing unevenness can be relatively improved, thereby relatively improving the display quality of the display device 10.
[0075] Figure 4 yes Figure 1 An enlarged view of another example of region A shown.
[0076] refer to Figure 4 The display device 10 may include a plurality of pixel columns PXC, each of which includes an emission region EA defined by a pixel defining layer PDL. Pixel columns PXC may be defined between adjacent pixel column defining layers CS. Pixel columns PXC may include a first pixel column PXC1' in which a first emission region EA' and a second emission region EA2' are alternately arranged.
[0077] On the pixel-defining layer PDL, a waveform-defining layer SWS' having a shape similar to a square wave along the first direction DR1 can be arranged within the first pixel column PXC1'.
[0078] Specifically, the waveform defining layer SWS' can have an incomplete square wave shape that includes noise, rather than a complete square wave shape. In other words, the waveform defining layer SWS' can have a trapezoidal wave shape.
[0079] A trapezoidal wave is a waveform in which a combination of horizontal and sloping lines repeats periodically, and each cycle includes an ascending portion, a plateau portion, and a descending portion. Unlike a square wave, in which the ascending and descending changes are abrupt, a trapezoidal wave can have a linear ascending and descending transition.
[0080] The waveform defining layer SWS' may include a pulse width portion PW' extending in the first direction DR1 and an edge E' rising or falling with a slope. That is, with... Figure 2 The waveform definition layer SWS shown is different from the one with a completely square wave shape. Figure 4 The waveform definition layer SWS' shown may include portions that change at a constant slope rather than rising or falling abruptly.
[0081] A first transmission region EA1' and a second transmission region EA2' can be arranged within one cycle of the waveform limiting layer SWS'. Specifically, the first transmission region EA1' or the second transmission region EA2' can be arranged within the positive half-cycle or the negative half-cycle of the waveform limiting layer SWS', respectively. For example, a first transmission region EA1' can be arranged within each positive half-cycle of the waveform limiting layer SWS', and a second transmission region EA2' can be arranged within each negative half-cycle of the waveform limiting layer SWS'.
[0082] In other words, the edge E' of the waveform defining layer SWS' can be positioned between the first transmission region EA1' and the second transmission region EA2'. As a result, the first transmission region EA1' and the second transmission region EA2' can be arranged alternately along the first direction DR1.
[0083] The first transmission region EA1' and the second transmission region EA2' can correspond to the shape of the waveform defining layer SWS'. In other words, the first transmission region EA1' and the second transmission region EA2' can have a trapezoidal shape.
[0084] The first emission region EA1' may include a first side F1' adjacent to the first pixel column defining layer CS1, and the second emission region EA2' may include a second side F2' adjacent to the second pixel column defining layer CS2.
[0085] The waveform defining layer SWS' can extend between the first side F1' and the first pixel column defining layer CS1, between the first emission region EA1' and the second emission region EA2', and between the second side F2' and the second pixel column defining layer CS2.
[0086] Without conflicting with the above description, Figure 4 The display device 10 described herein may similarly include Figure 2 and Figure 3 The configuration and its effects described in the document.
[0087] Figure 5 yes Figure 1 An enlarged view of another example of region A shown.
[0088] refer to Figure 5 The display device 10 may include a plurality of pixel columns PXC, each of which includes an emission region EA defined by a pixel defining layer PDL. Pixel columns PXC may be defined between adjacent pixel column defining layers CS. Pixel columns PXC may include a first pixel column PXC1'' in which a first emission region EA1'' and a second emission region EA2'' are alternately arranged.
[0089] On the pixel-defining layer PDL, a waveform-defining layer SWS'' with a shape similar to a square wave along the first direction DR1 can be arranged within the first pixel column PXC1''.
[0090] Specifically, the waveform defining layer SWS'' can have an incomplete square wave shape that includes noise, rather than a complete square wave shape. In other words, the waveform defining layer SWS'' can have a shape similar to a sine wave.
[0091] Similar to a sine wave, the waveform limiting layer SWS'' can periodically change up and down, forming a smooth and continuous curve. The waveform limiting layer SWS'' can repeatedly rise, fall, and rise again with a constant period.
[0092] A first transmission region EA1'' and a second transmission region EA2'' can be arranged within one cycle of the waveform defining layer SWS''. Specifically, the first transmission region EA1'' or the second transmission region EA2'' can be arranged within the positive or negative half-cycle of the waveform defining layer SWS'', respectively. For example, a first transmission region EA1'' can be arranged within each positive half-cycle of the waveform defining layer SWS'', and a second transmission region EA2'' can be arranged within each negative half-cycle of the waveform defining layer SWS''. As a result, the first transmission region EA1'' and the second transmission region EA2'' can be arranged alternately along a first direction DR1.
[0093] The first transmission region EA1'' and the second transmission region EA2'' can correspond to the shape of the waveform defining layer SWS''. In other words, the first transmission region EA1'' and the second transmission region EA2'' can have a generally semi-circular or semi-elliptical shape.
[0094] Without conflicting with the above description, Figure 5 The display device 10 described herein may similarly include Figure 2 and Figure 3 The configuration and its effects described in the document.
[0095] Figure 6 This is an equivalent circuit diagram of a light-emitting element PX according to some embodiments of this disclosure. Although Figure 6 Various components of a light-emitting element PX according to some embodiments are shown in the circuit diagram, but the embodiments of this disclosure are not limited thereto, and the circuit may include additional or fewer components according to various embodiments without departing from the spirit and scope of the embodiments of this disclosure.
[0096] refer to Figure 6 Pixel P includes a pixel circuit PC and an organic light-emitting diode OLED, wherein the pixel circuit PC includes a first thin-film transistor T1 to a sixth thin-film transistor T6 and a storage capacitor Cst, and the organic light-emitting diode OLED is configured to emit light by receiving a driving current via the pixel circuit PC.
[0097] Thin-film transistor TR (see Figure 8 It includes a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, an initialization thin-film transistor T4, a first emission control thin-film transistor T5, and a second emission control thin-film transistor T6.
[0098] Pixel P includes a scan line SL that transmits scan signals Sn to switching thin-film transistor T2 and compensation thin-film transistor T3, a pre-scan line SL-1 that transmits pre-scan signals Sn-1 to initialization thin-film transistor T4, an emission control line LL that transmits emission control signals En to first emission control thin-film transistor T5 and second emission control thin-film transistor T6, a data line DL that intersects with scan line SL and transmits data signals Dm, a drive voltage line PL that is substantially parallel to data line DL and transmits the first power supply voltage ELVDD, and an initialization voltage line VL that transmits the initialization voltage VINT for initializing drive thin-film transistor T1.
[0099] The gate electrode G1 of the driving thin-film transistor T1 is connected to the first electrode Cst1 of the storage capacitor Cst. The source electrode S1 of the driving thin-film transistor T1 is connected to the driving voltage line PL via the first emitter control thin-film transistor T5. The drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the anode of the organic light-emitting diode (OLED) via the second emitter control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2 and supplies the driving current Ioled to the OLED.
[0100] The gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL. The source electrode S2 of the switching thin-film transistor T2 is connected to the data line DL. The drain electrode D2 of the switching thin-film transistor T2 is connected to the source electrode S1 of the driving thin-film transistor T1, and is connected to the drive voltage line PL via the first emitter control thin-film transistor T5. The switching thin-film transistor T2 is turned on in response to the scan signal Sn received through the scan line SL, and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the source electrode S1 of the driving thin-film transistor T1.
[0101] The gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL. The source electrode S3 of the compensation thin-film transistor T3 is connected to the drain electrode D1 of the driving thin-film transistor T1, and is also connected to the anode of the organic light-emitting diode (OLED) via the second emission control thin-film transistor T6. The drain electrode D3 of the compensation thin-film transistor T3 is connected to the first electrode Cst1 of the storage capacitor Cst, the drain electrode D4 of the initialization thin-film transistor T4, and the gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on by the scan signal Sn received through the scan line SL, and connects the gate electrode G1 and the drain electrode D1 of the driving thin-film transistor T1 to each other, thereby forming a diode connection for the driving thin-film transistor T1.
[0102] The gate electrode G4 of the initialization thin-film transistor T4 is connected to the front scan line SL-1. The source electrode S4 of the initialization thin-film transistor T4 is connected to the initialization voltage line VL. The drain electrode D4 of the initialization thin-film transistor T4 is connected to the first electrode Cst1 of the storage capacitor Cst, the drain electrode D3 of the compensation thin-film transistor T3, and the gate electrode G1 of the driving thin-film transistor T1. The initialization thin-film transistor T4 is turned on in response to the front scan signal Sn-1 received through the front scan line SL-1, and performs an initialization operation by sending the initialization voltage VINT to the gate electrode G1 of the driving thin-film transistor T1 to initialize the voltage of the gate electrode G1 of the driving thin-film transistor T1.
[0103] The gate electrode G5 of the first emitter control thin-film transistor T5 is connected to the emitter control line LL. The source electrode S5 of the first emitter control thin-film transistor T5 is connected to the drive voltage line PL. The drain electrode D5 of the first emitter control thin-film transistor T5 is connected to the source electrode S1 of the driving thin-film transistor T1 and the drain electrode D2 of the switching thin-film transistor T2.
[0104] The gate electrode G6 of the second emission control thin-film transistor T6 is connected to the emission control line LL. The source electrode S6 of the second emission control thin-film transistor T6 is connected to the drain electrode D1 of the driving thin-film transistor T1 and the source electrode S3 of the compensation thin-film transistor T3. The drain electrode D6 of the second emission control thin-film transistor T6 is electrically connected to the anode of the organic light-emitting diode (OLED). The first emission control thin-film transistor T5 and the second emission control thin-film transistor T6 are simultaneously turned on in response to the emission control signal En received through the emission control line LL, so that the first power supply voltage ELVDD is transmitted to the OLED, allowing the drive current Ioled to flow to the OLED.
[0105] The second electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line PL. The first electrode Cst1 of the storage capacitor Cst is connected to the gate electrode G1 of the driving thin-film transistor T1, the drain electrode D3 of the compensation thin-film transistor T3, and the drain electrode D4 of the initialization thin-film transistor T4.
[0106] The cathode of an organic light-emitting diode (OLED) is connected to a second power supply voltage, ELVSS. An OLED displays an image by emitting light when it receives a driving current Ioled from a driving thin-film transistor T1.
[0107] Pixel P can be, for example, a red pixel, a green pixel, or a blue pixel.
[0108] Figure 7 It is along Figure 2 An enlarged view of the example cross section intercepted by line I-I'. Figure 8 It is along Figure 2 An enlarged view of the example section intercepted by line II-II', and Figure 9 It is along Figure 2 An enlarged view of the example section intercepted by line III-III'.
[0109] refer to Figures 7 to 9 The display device 10 may include a substrate SUB, a buffer layer BFR, a thin film transistor TR, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a pixel defining layer PDL, a light-emitting element PX, and an encapsulation layer ENC.
[0110] The substrate SUB may be provided with pixel columns PXC, each of which includes multiple emission regions EA arranged on the first direction DR1.
[0111] The substrate SUB can comprise transparent or opaque materials. According to some embodiments, examples of materials that can be used for the substrate SUB include glass, quartz, plastic, etc. These materials can be used alone or in combination with each other.
[0112] A buffer layer (BFR) can be disposed on the substrate SUB. The buffer layer (BFR) prevents or reduces the diffusion of contaminants or impurities such as oxygen and moisture through the substrate SUB to the upper portion of the substrate SUB. The buffer layer (BFR) may comprise an inorganic insulating material such as a silicon compound or a metal oxide.
[0113] According to some embodiments, an additional barrier layer may be disposed between the substrate SUB and the buffer layer BFR. This barrier layer may include an inorganic insulating material.
[0114] The thin-film transistor (TR) can be mounted on the substrate SUB, specifically on the buffer layer BFR. Each thin-film transistor TR may include an active pattern ACT, a gate electrode GAT, a first connection electrode CE1, and a second connection electrode CE2.
[0115] The active pattern ACT can be disposed on the buffer layer BFR. According to some embodiments, the active pattern ACT may include silicon semiconductor materials or oxide semiconductor materials. Examples of silicon semiconductor materials that can be used for active pattern ACTs include amorphous silicon, polycrystalline silicon, etc. Examples of oxide semiconductor materials that can be used for active pattern ACTs include IGZO (InGaZnO), ITZO (InSnZnO), etc.
[0116] According to some embodiments, the first insulating layer IL1 may be located on the buffer layer BFR. The first insulating layer IL1 may cover the active pattern ACT. According to some embodiments, the first insulating layer IL1 may be patterned on the active pattern ACT to expose a portion of the active pattern ACT. For example, the first insulating layer IL1 may be patterned on the active pattern ACT to overlap with the gate electrode GAT. The first insulating layer IL1 may include an inorganic insulating material. Examples of inorganic insulating materials that may be used for the first insulating layer IL1 may include silicon oxide, silicon nitride, silicon oxide nitride, etc.
[0117] The gate electrode GAT may be located on the first insulating layer IL1. According to some embodiments, the gate electrode GAT may include metal, alloy, conductive metal oxide, transparent conductive material, etc.
[0118] The second insulating layer IL2 may be located on the first insulating layer IL1. According to some embodiments, the second insulating layer IL2 may cover the gate electrode GAT. The second insulating layer IL2 may include an inorganic insulating material. Examples of inorganic insulating materials that may be used for the second insulating layer IL2 include silicon oxide, silicon nitride, and silicon nitride oxide.
[0119] The first connecting electrode CE1 and the second connecting electrode CE2 can be disposed on the second insulating layer IL2. The first connecting electrode CE1 and the second connecting electrode CE2 can be electrically connected to the active pattern ACT through contact holes formed in the second insulating layer IL2. Each of the first connecting electrode CE1 and the second connecting electrode CE2 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.
[0120] The third insulating layer IL3 may be located on the second insulating layer IL2. The third insulating layer IL3 may cover the first connecting electrode CE1 and the second connecting electrode CE2. The third insulating layer IL3 may include an organic insulating material. Examples of organic insulating materials that may be used for the third insulating layer IL3 may include photoresists, polyacrylamide-based resins, polyimide-based resins, polyamide-based resins, siloxane-based resins, acrolein-based resins, epoxy-based resins, etc.
[0121] refer to Figure 7 The configuration, arrangement, and connection structure of each of the thin-film transistor TR and insulating layers IL1, IL2, and IL3 described are merely examples and can be modified in various ways.
[0122] The light-emitting element PX is electrically connected to the thin-film transistor TR and can be arranged on the substrate SUB, specifically on the thin-film transistor TR and the insulating layers IL1, IL2 and IL3.
[0123] A light-emitting element (PX) may include a pixel electrode (ADE), an emitter layer (EL), and a common electrode (CTE). A single light-emitting element (PX) can be disposed within an emitter region (EA). That is, within each emitter region (EA), a light-emitting element (PX) comprising a pixel electrode (ADE), an emitter layer (EL), and a common electrode (CTE) on the emitter layer (EL) can be disposed.
[0124] The pixel electrode ADE can be located on the third insulating layer IL3. The pixel electrode ADE can be electrically connected to the thin-film transistor TR through contact holes formed in the third insulating layer IL3. The pixel electrode ADE can include metals, alloys, conductive metal oxides, transparent conductive materials, etc.
[0125] The emitting layer (EL) can be located on the pixel electrode (ADE). The emitting layer (EL) can include organic light-emitting materials. According to some embodiments, the emitting layer (EL) can be formed by an inkjet printing process. Organic light-emitting materials can include low-molecular-weight organic compounds or high-molecular-weight organic compounds. Examples of low-molecular-weight organic compounds include copper phthalocyanine, N,N-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc. Examples of high-molecular-weight organic compounds include poly(3,4-vinyldioxythiophene), polyaniline, polyphenylene oxide, polyfluorene, etc. These materials can be used alone or in combination with each other.
[0126] The pixel defining layer (PDL) may be located on the third insulating layer (IL3). According to some embodiments, the pixel defining layer (PDL) may include an organic insulating material. Examples of materials that can be used for the pixel defining layer (PDL) include polyacrylic acid resin, polyimide resin, and acrylic resin. These materials may be used alone or in combination with each other.
[0127] A pixel defining layer (PDL) may surround the edge of a pixel electrode (ADE) and define each of the emission regions (EA). According to some embodiments, the PDL may define a pixel opening that exposes a portion of each pixel electrode (ADE). The PDL may define the area corresponding to the pixel opening as the emission region (EA), and the area where the PDL is disposed may be defined as the non-emission region (NEA).
[0128] On the pixel definition layer PDL, a pixel column definition layer CS for defining pixel column PXC and a waveform definition layer SWS having a certain waveform such as square wave, trapezoidal wave or sine wave in the first pixel column PXC1 can be arranged.
[0129] The upper surface of the emitter layer EL can be positioned on the third-direction DR3 above the upper surface of the pixel-defining layer PDL. However, the upper surface of the emitter layer EL can also be positioned on the third-direction DR3 above the upper surface of the pixel column-defining layer CS and the waveform-defining layer SWS (see...). Figure 8 Below the upper surface of ).
[0130] refer to Figure 7 The emission layer EL of the first emission region EA1 and the emission layer EL of the third emission region EA3 can be defined by a pixel column layer CS (e.g., Figure 7 The second pixel column defined by the layer CS2 shown is separate. In other words, the ink of the emission layer EL constituting the first emission region EA1 may not mix with the ink of the emission layer EL constituting the third emission region EA3.
[0131] refer to Figure 8The emission layer EL of the second emission region EA2 and the emission layer EL of the third emission region EA3 can be defined by a pixel column layer CS (e.g., Figure 8 The second pixel column defining layer (CS2) and the waveform defining layer (SWS) shown are separate. That is, even when the upper surface of the emission layer EL is positioned above the upper surface of the pixel defining layer PDL, the ink of the emission layer EL constituting the second emission region EA2 may not mix with the ink of the emission layer EL constituting the third emission region EA3.
[0132] Furthermore, the first microchannel MC1 can be formed in the emission layer EL between the waveform defining layer SWS and the second pixel column defining layer CS2. That is, the emission layer EL between the waveform defining layer SWS and the second pixel column defining layer CS2 can be connected to the emission layer ELs before and after the first emission region EA1 in the first direction DR1. Due to the first microchannel MC1, the emission layer ELs of all first emission regions EA1 within a single first pixel column PXC1 can be connected.
[0133] refer to Figure 9 In the second pixel column PXC2, there may be multiple third emission regions EA3. Since the upper surface of the emission layer EL is higher than the upper surface of the pixel definition layer PDL, the emission layers EL of the third emission regions EA3 arranged in a single second pixel column PXC2 can all be connected.
[0134] To ensure that the upper surface of the emission layer EL of the same type of emission regions EA within a single pixel column PXC has a uniform height, at least the upper surface of the pixel defining layer PDL can be hydrophilic. The term "hydrophilic" can refer to the property of having high affinity for the ink forming the emission layer EL.
[0135] In another example, the pixel-defining layer (PDL) itself may be hydrophilic, or the surface of the PDL may be surface-treated to have hydrophilic properties. As a result, the display device 10 can have a clearly defined emission area (EA) while reducing screen spot problems, thereby relatively improving display quality.
[0136] However, since the pixel column defining layer CS separates the pixel columns PXC, and the waveform defining layer SWS must separate the emission layers EL of different types of emission regions EA within a single pixel column PXC, the upper surfaces of the waveform defining layer SWS and the pixel column defining layer CS can be hydrophobic. In this specification, the term "hydrophobic" can refer to the property of repelling ink that forms a certain emission layer EL and preventing ink penetration.
[0137] The upper surfaces of the waveform defining layer SWS and the pixel column defining layer CS can be hydrophobic, thereby preventing or reducing ink overflow from the emission layer EL of one emission region EA into the emission layer EL of another emission region EA of a different type. As a result, color mixing between the emission layers EL of different types of emission regions EA can be prevented or reduced, and the defect rate and display quality of the display device 10 can be relatively improved.
[0138] The common electrode (CTE) can be located on the emitter layer (EL), pixel limiting layer (PDL), pixel column limiting layer (CS), and waveform limiting layer (SWS). The common electrode (CTE) can include conductive materials, such as metals, alloys, conductive metal nitrides, conductive metal oxides, and transparent conductive materials. The common electrode (CTE) can have a single-layer structure or a multilayer structure including multiple conductive layers.
[0139] The encapsulation layer ENC may be located on the common electrode CTE. The encapsulation layer ENC may cover the light-emitting element PX. According to some embodiments, the encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. According to some embodiments, the encapsulation layer ENC may include a first inorganic encapsulation layer located on the common electrode CTE, an organic encapsulation layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the organic encapsulation layer.
[0140] The display device 10 according to some embodiments can be applied to various electronic devices 1000. The electronic device 1000 according to some embodiments may include the display device 10 described above, and may also include modules or devices with additional functions in addition to the display device 10.
[0141] Figure 10 This is a block diagram of an electronic device 1000 according to some embodiments of the present disclosure. (See reference...) Figure 10 According to some embodiments, the electronic device 1000 may include a display module 1100, a processor 1200, a memory 1300, and a power module 1400.
[0142] The processor 1200 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.
[0143] The data required for the operation of the processor 1200 or the display module 1100 can be stored in the memory 1300. When the processor 1200 executes the application stored in the memory 1300, image data signals and / or input control signals can be transmitted to the display module 1100, and the display module 1100 can process the received signals and output image information through the display screen.
[0144] The power module 1400 may include a power module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 1000.
[0145] At least one of the components of the electronic device 1000 described above may be included in the display device 10 according to the embodiments described above. Additionally, some individual modules that are functionally included in a single module may be partially included in the display device 10, while other modules may be disposed separately from the display device 10. For example, the display device 10 may include a display module 1100, while the processor 1200, memory 1300, and power module 1400 may be disposed as other devices within the electronic device 1000, rather than devices within the display device 10.
[0146] Figure 11 A schematic diagram of an electronic device according to some embodiments is shown.
[0147] refer to Figure 11 The various electronic devices used in the display device 10 according to the embodiments may include not only image display electronic devices (such as smartphones 1000.1a, tablet PCs 1000.1b, laptop computers 1000.1c, TVs 1000.1d, and desktop monitors 1000.1e), but also wearable electronic devices (such as smart glasses 1000.2a, head-mounted displays 1000.2b, and smartwatches 1000.2c) that include display modules, as well as vehicle electronic devices 1000.3 that include display modules (such as interior mirror displays and central information displays (CIDs) arranged on the instrument panel, center trim, or dashboard of a vehicle).
[0148] Display devices and electronic devices according to some embodiments of this disclosure can have relatively improved display quality and relatively reduced defect rates.
[0149] However, those skilled in the art will understand that the effects that can be achieved with this disclosure are not limited to those specifically described above, and other aspects of some embodiments of this disclosure will be more clearly understood from the above description taken in conjunction with the accompanying drawings.
[0150] The implementation methods described above can be implemented independently. However, it is obvious that the structures of the various implementation methods can also be combined with each other.
[0151] Although this disclosure has been described with reference to embodiments illustrated in the accompanying drawings, these embodiments are merely exemplary. Those skilled in the art will understand that various modifications and equivalent embodiments will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but is limited to the broader scope of the presented claims and various obvious modifications and equivalent arrangements.
[0152] The specific implementations shown and described herein are illustrative examples of embodiments and are not intended to further limit the scope of the embodiments in any way. Furthermore, no element is necessary for the implementation of the embodiments unless specifically described as “essential” or “critical.”
[0153] In the context of describing this invention (particularly in the context of the appended claims), the use of the terms “a,” “an,” and “the,” as well as similar designations, should be interpreted as encompassing both the singular and plural. Furthermore, unless otherwise indicated herein, statements of ranges of values herein are intended only as brief references to each individual value falling within that range, and each individual value is incorporated into this specification as it is individually stated herein. Moreover, unless otherwise indicated herein or clearly contradicted by the context, the steps of all methods described herein may be performed in any suitable order. Embodiments of this disclosure are not limited to the order of the described operations. Unless otherwise required, the use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate this disclosure and does not limit the scope of embodiments of this disclosure. Many modifications and adjustments will be apparent to those skilled in the art without departing from the spirit and scope of embodiments according to this disclosure.
Claims
1. A display device, comprising: A substrate having a pixel column thereon, each of the pixel columns including a plurality of emission regions arranged in a first direction; Pixel electrodes are located on the substrate. A pixel defining layer surrounds the edge of the pixel electrode and is configured to define each of the emission regions; Multiple pixel column defining layers extend along the first direction and are spaced apart from each other in a second direction perpendicular to the first direction to define the pixel columns; as well as The emission layer, on the pixel electrode, The pixel column includes a first pixel column, in which a first emission region and a second emission region are alternately arranged in each of the first pixel columns. On the pixel defining layer, a waveform defining layer having a regular waveform along the first direction is arranged between two pixel column defining layers defining each of the first pixel columns, and The first transmission region or the second transmission region is respectively arranged in the positive half-cycle or the negative half-cycle of the waveform defining layer.
2. The display device according to claim 1, in, The pixel column defining layer includes a first pixel column defining layer and a second pixel column defining layer that define each of the first pixel columns. The first emission region is closer to the second pixel column defining layer than to the first pixel column defining layer. The second emission region is closer to the first pixel column defining layer than to the second pixel column defining layer, and The waveform defining layer extends between the first emission region and the first pixel column defining layer, between the first emission region and the second emission region, and between the second emission region and the second pixel column defining layer.
3. The display device according to claim 1, in, The waveform defining layer is spaced apart from the pixel column defining layer.
4. The display device according to claim 1, further comprising: A microchannel is defined between a pulse width portion and a pixel column defining layer closest to the pulse width portion, the pulse width portion being the region of the waveform defining layer extending in the first direction.
5. The display device according to claim 4, in, The microchannels include: A first microchannel is configured to connect two first transmission regions in the first transmission region that are adjacent to the second transmission region along the first direction, and The second microchannel is configured to connect two second transmission regions in the second transmission region that are adjacent to the first transmission region along the first direction.
6. The display device according to claim 1, in, The pixel column also includes a second pixel column adjacent to the first pixel column, and Each of the second pixel columns includes a plurality of third emission regions arranged along the first direction.
7. The display device according to claim 6, wherein, The first pixel column and the second pixel column are arranged alternately along the second direction.
8. The display device according to claim 6, wherein, Each of the third launch regions is arranged adjacent to the first launch region and the second launch region adjacent to the first launch region in the second direction.
9. The display device according to claim 6, wherein, The length of the third transmission region corresponds to the total length of the first transmission region and the second transmission region adjacent to the first transmission region.
10. The display device according to claim 1, wherein, The upper surface of the waveform defining layer and the upper surface of the pixel column defining layer are hydrophobic.
11. The display device according to claim 1, wherein, The upper surface of the pixel-defining layer is hydrophilic.
12. The display device according to claim 1, wherein, The upper surface of the pixel column defining layer and the upper surface of the waveform defining layer are positioned at a level higher than the upper surface of the emission layer.
13. The display device according to claim 1, wherein, A light-emitting element, including the pixel electrode, the emitting layer, and a common electrode on the emitting layer, is arranged in each of the emitting regions.
14. A display device, comprising: A substrate having a pixel column thereon, each of the pixel columns including a plurality of emission regions arranged in a first direction; Pixel electrodes are located on the substrate. A pixel defining layer surrounds the edge of the pixel electrode and is configured to define each of the emission regions; Multiple pixel column defining layers extend along the first direction and are spaced apart from each other in a second direction perpendicular to the first direction to define the pixel columns; as well as The emission layer, on the pixel electrode, The pixel column includes a first pixel column, in which a first emission region and a second emission region are alternately arranged in each of the first pixel columns. On the pixel defining layer, a waveform defining layer having a waveform along the first direction lies between two pixel column defining layers defining each of the first pixel columns, and The edge of the waveform defining layer is between the first emission region and the second emission region.
15. The display device according to claim 14, in, The pixel column defining layer includes a first pixel column defining layer and a second pixel column defining layer that define each of the first pixel columns. The first emission region includes a first side adjacent to the first pixel column defining layer. The second emission region includes a second side adjacent to the second pixel column defining layer, and The waveform defining layer extends between the first side and the first pixel column defining layer, between the first emission region and the second emission region, and between the second side and the second pixel column defining layer.
16. The display device according to claim 14, further comprising: A microchannel is defined between a pulse width portion and a pixel column defining layer closest to the pulse width portion, the pulse width portion being the region of the waveform defining layer extending in the first direction. The microchannels include: A first microchannel is configured to connect two first transmission regions in the first transmission region that are adjacent to the second transmission region along the first direction; and The second microchannel is configured to connect two second transmission regions in the second transmission region that are adjacent to the first transmission region along the first direction.
17. The display device according to claim 14, in, The pixel column also includes a second pixel column adjacent to the first pixel column. Each of the second pixel columns includes a plurality of third emission regions arranged along the first direction, and The first pixel column and the second pixel column are arranged alternately along the second direction.
18. The display device according to claim 14, in, The upper surface of the waveform defining layer and the upper surface of the pixel column defining layer are hydrophobic. The upper surface of the pixel-defining layer is hydrophilic.
19. The display device according to claim 14, in, The upper surface of the pixel column defining layer and the upper surface of the waveform defining layer are positioned at a level higher than the upper surface of the emission layer.
20. Electronic devices, including: Display device; processor; Memory; as well as Power module, The display device includes: A substrate having a pixel column thereon, each of the pixel columns including a plurality of emission regions arranged in a first direction; Pixel electrodes are located on the substrate. A pixel defining layer surrounds the edge of the pixel electrode and is configured to define each of the emission regions; A plurality of pixel column defining layers, extending along the first direction and spaced apart from each other in a second direction perpendicular to the first direction, to define the pixel columns; and The emission layer, on the pixel electrode, The pixel column includes a first pixel column, in which a first emission region and a second emission region are alternately arranged in each of the first pixel columns. On the pixel defining layer, a waveform defining layer having a waveform along the first direction is arranged between two pixel column defining layers defining each of the first pixel columns, and The first transmission region or the second transmission region is respectively arranged in the positive half-cycle or the negative half-cycle of the waveform defining layer.
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Method and System for Deep Learning Transformer trained by Multivariate Sequence Transformed from Univariate Sequence
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