Display panel and display device

Abstract

The display panel and the display device provided by the present disclosure comprise a display area and a non-display area, the display panel comprises a plurality of pixel rows, a pixel driving circuit comprises a first transistor, the first transistor comprises an oxide transistor, the display panel comprises a first wire, the first wire is located in the display area and at least part of the non-display area, the first wire comprises molybdenum and titanium, and the shortest distance between the first wire and the channel of the first transistor in the direction parallel to the plane of the display panel is less than one-third of the distance between two adjacent pixel rows. The first wire extending to the non-display area can absorb hydrogen ions in the inorganic film layer of the non-display area, reduce the influence of the hydrogen ion concentration on the channel of the first transistor, reduce the negative bias of the turn-on threshold voltage Vth of the first transistor, and thus reduce the occurrence of edge bright spots.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays use organic light-emitting materials that emit light when an electric current passes through them. Oxide semiconductors, such as indium gallium zinc oxide (IGZO), have advantages such as high mobility, good uniformity, and transparency, making them suitable as active layer materials for thin-film transistors in display technology.

[0003] However, due to the narrow bezel design requirements, no dummy pixels are set at the edge of the display panel. Therefore, the IGZO thin film transistors at the edge of the display area may form bright spots during the display process.

[0004] Therefore, how to reduce edge highlights and improve display effect under narrow bezel design has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides a display panel and display device for reducing edge highlights and improving display performance in a narrow bezel design.

[0006] This disclosure provides a display panel, including: a display area and a non-display area, wherein the non-display area is adjacent to the display area; The display panel includes multiple pixel rows, each pixel row includes multiple sub-pixels, each sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes a first transistor, which is an oxide transistor. The display panel includes a first trace located on at least one side of the pixel row; the first trace is located in the display area and at least a portion of the non-display area. The first trace comprises molybdenum and titanium, and along a direction parallel to the plane of the display panel, the shortest distance between the first trace and the channel of the first transistor is less than one-third of the spacing between two adjacent rows of pixels.

[0007] Based on the same inventive concept, this disclosure provides a display device, including the display panel as described above.

[0008] Compared with the prior art, the technical solution provided in this disclosure has the following advantages: This disclosure provides a display panel and a display device, including: a display area and a non-display area, the non-display area and the display area being adjacent; the display panel includes a plurality of pixel rows, the pixel rows include a plurality of sub-pixels, the sub-pixels include a pixel driving circuit, the pixel driving circuit includes a first transistor, the first transistor includes an oxide transistor; the display panel includes a first trace, the first trace being located on at least one side of the pixel row; the first trace is located in the display area and at least part of the non-display area; the first trace includes molybdenum and titanium, and along a direction parallel to the plane of the display panel, the shortest distance between the first trace and the channel of the first transistor is less than one-third of the spacing between two adjacent pixel rows. By providing a first trace comprising molybdenum and titanium in the display area and at least part of the non-display area, the first trace is located on at least one side of a pixel row, and the shortest distance between the first trace and the channel of the first transistor is set to be less than one-third of the spacing between two adjacent pixel rows; in a narrow bezel design, even if no virtual pixels are provided in the non-display area, the first trace extending to the non-display area can help balance the surrounding environment of the first transistor at the edge of the display area and can absorb hydrogen ions in the inorganic film layer of the non-display area; the close distance between the first trace and the channel of the first transistor can effectively reduce the impact of excessively high hydrogen ion concentration on the channel of the first transistor, reduce the negative bias of the conduction threshold voltage Vth of the first transistor, thereby reducing the occurrence of edge bright spots and improving the display effect. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 The figure shown is a plan view of a display panel provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the pixel arrangement in the edge region of a display panel provided in an embodiment of the present disclosure; Figure 3 The diagram shown is a schematic representation of a sub-pixel connection according to an embodiment of this disclosure. Figure 4 The diagram shown is a schematic representation of the positional relationship between a first trace and a gate line according to an embodiment of this disclosure. Figure 5The diagram shown is a schematic representation of the positional relationship between another first trace and an adjacent gate line provided in an embodiment of this disclosure. Figure 6 The diagram shown is a partial film layer schematic of a display panel provided in an embodiment of this disclosure; Figure 7 The diagram shown is a schematic diagram of the connection between a first trace and a second trace according to an embodiment of this disclosure; Figure 8 The diagram shown is a schematic diagram of another connection between the first trace and the second trace provided in an embodiment of this disclosure; Figure 9 The diagram shown is a schematic representation of the location of the perforated area in a display panel according to an embodiment of this disclosure. Figure 10 The diagram shown is a schematic representation of a display device provided in an embodiment of this disclosure; Figure 11 The diagram shown is a schematic diagram of another display device provided in an embodiment of this disclosure. Detailed Implementation

[0012] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0013] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0014] In related technologies, auxiliary pixels are typically set at the edges of display panels. These auxiliary pixels are not used for image display, but their structure is the same as that of the display pixels. Due to the trend towards narrower bezels in display panels, the auxiliary pixels at the edges need to be eliminated to achieve even narrower bezels. This results in a difference between the surrounding environment of the outer display pixels and the surrounding environment of the central display pixels. The hydrogen in the IGZO transistors of the outer display pixels cannot be fully released, leading to a higher hydrogen content in the IGZO transistors. This causes a negative bias in the on-state voltage threshold Vth of the IGZO transistors in the outer display pixels, resulting in bright spots near the edges of the display panel and affecting the display effect.

[0015] To address the aforementioned issues, this disclosure provides a display panel and display device for reducing edge bright spots and improving display performance under narrow bezel conditions.

[0016] Figure 1 The image shown is a plan view of a display panel provided in an embodiment of this disclosure. Please refer to it. Figure 1This disclosure provides a display panel 100, including: a display area AA and a non-display area NA, wherein the non-display area NA is adjacent to the display area AA; optionally, the non-display area NA may be located on one or more sides of the display area AA, and this disclosure does not limit this. Figure 1 The illustration only uses the non-display area NA surrounding the display area AA as an example.

[0017] The display panel 100 includes multiple pixel rows P0, which are arranged along a first direction D1. The first direction D1 intersects the extending direction of the pixel rows P0. This disclosure does not limit the specific direction of the first direction D1. Figure 1 The illustration only takes the example where the first direction D1 is perpendicular to the extension direction of pixel row P0. Pixel row P0 includes multiple sub-pixels P1, and sub-pixels P1 include red sub-pixels, blue sub-pixels, and green sub-pixels.

[0018] It should be noted that, Figure 1 The pixel arrangement in the Q region is for illustrative purposes only. In reality, on the curved edge area of ​​the display panel 100, the pixel row P0 is arranged in a stepped pattern, as shown below. Figure 2 As shown, Figure 2 This is a schematic diagram of the pixel arrangement in the edge region of a display panel provided in an embodiment of this disclosure.

[0019] Figure 3 The diagram shown is a schematic representation of a sub-pixel connection according to an embodiment of this disclosure. Please refer to it. Figure 1 and Figure 3 Sub-pixel P1 includes a pixel driving circuit 00 and a light-emitting element L. Each pixel driving circuit 00 can correspond to one or more light-emitting elements L, used to drive the light-emitting element L to emit light. The light-emitting element L includes light-emitting diodes, organic light-emitting diodes, micro light-emitting diodes, quantum dot light-emitting diodes, etc. The non-display area NA is also provided with a peripheral driving circuit. In the technical solution provided in this disclosure embodiment, only the pixel driving circuit 00 of the display area AA is shown, and the peripheral driving circuit devices of the non-display area NA are not shown. However, in actual products, the display panel 100 may include the above-mentioned peripheral driving circuit of the non-display area NA, which will not be described again hereafter. The peripheral driving circuit can be used to provide operating voltage and / or current to the pixel driving circuit 00, thereby realizing the display function of the display panel 100.

[0020] Please refer to Figure 3The pixel driving circuit 00 includes a first transistor T1, which is an oxide transistor, such as an IGZO transistor (Indium Gallium Zinc Oxide Thin-Film Transistor). The IGZO transistor includes an oxide channel. The inorganic films in the display panel 100, such as silicon oxide or silicon nitride films, typically contain hydrogen. Compared to the channels of low-temperature polycrystalline silicon (LTPS) materials, the oxide channel of the IGZO transistor is more sensitive to hydrogen content. Hydrogen readily releases electrons as charge carriers in the oxide channel, and when the hydrogen content is high, these electrons significantly increase the carrier concentration in the oxide channel. In an oxide transistor, the threshold voltage is the minimum gate voltage required to turn on the transistor. When the carrier concentration in the channel increases, the transistor is easier to turn on, thus shifting the threshold voltage negatively. Therefore, a high hydrogen content affects the operating performance of the oxide channel, causing the turn-on threshold voltage Vth of the first transistor T1 to become negatively biased.

[0021] Figure 4 The diagram shown is a schematic representation of the positional relationship between a first trace and a gate line according to an embodiment of this disclosure. Please refer to it. Figures 1 to 4 The display panel 100 includes a first trace 10, the extension direction of which is the same as the extension direction of the pixel row P0, and the first trace 10 is located on at least one side of the pixel row P0; optionally, the first trace 10 may be located on one or both sides of the pixel row P0, and this disclosure does not limit this. The first trace 10 is located in the display area AA and at least a portion of the non-display area NA; the first trace 10 includes molybdenum and titanium, and along a direction parallel to the plane of the display panel 100, the shortest distance h1 between the first trace 10 and the channel of the first transistor T1 is less than one-third of the spacing h2 between two adjacent pixel rows P0.

[0022] This disclosure ensures that at least one row of first traces 10 exists near the first transistor T1 in the non-display area NA by providing a first trace 10 on at least one side of each row of sub-pixels P1, and the first trace 10 is located in at least part of the non-display area NA. The distance h1 between the first trace 10 and the adjacent first transistor T1 is shorter than the spacing h2 between adjacent pixel rows P0, allowing the titanium in the first trace 10 to effectively absorb excess hydrogen ions in the oxide semiconductor layer 15 of the first transistor T1. This reduces the negative bias of the conduction threshold voltage Vth of the first transistor T1, making the conduction threshold voltage Vth of the first transistor T1 at the edge of the display panel 100 consistent with the conduction threshold voltage Vth of the first transistor T1 in the central region of the display panel 100. This eliminates bright spots appearing at the edge of the display panel 100 during display and improves the display effect of the display panel 100. Furthermore, since the titanium metal crystals in the first trace 10 grow laterally and the molybdenum metal crystals grow vertically, a dense multilayer barrier layer is formed, which can enhance the blocking effect on hydrogen elements in the oxide transistors near the edge of the display area AA close to the non-display area NA.

[0023] Thus, by providing a first trace 10 on at least one side of the pixel row P0 in the display area AA and at least part of the non-display area NA, the first trace 10 includes molybdenum and titanium, and the shortest distance h1 between the first trace 10 and the channel of the first transistor T1 is less than one-third of the spacing h2 between two adjacent pixel rows P0, the excess hydrogen ions in the oxide semiconductor layer 15 of the first transistor T1 in the non-display area NA can be reduced through the first trace 10 located in the non-display area NA, thereby reducing the occurrence of edge bright spots and improving the display effect.

[0024] Please continue to refer to this. Figures 1 to 4 In the display panel 100 provided in this disclosure, the display panel 100 includes multiple gate lines 14. The extension direction of the gate lines 14 is the same as the extension direction of the pixel row P0, and the arrangement direction of the gate lines 14 is the same as the arrangement direction of the pixel row P0. The gate lines 14 are arranged on the same layer as the first trace 10. It should be noted that "the arrangement direction is the same" here does not refer to a strict straight line direction, but only represents the general extension direction, and the same applies below.

[0025] Specifically, pixel row P0 includes multiple sub-pixels P1, and sub-pixels P1 include pixel driving circuit 00. The gate line 14 in the display panel 100 can be used to provide a gate signal to the first transistor T1 in the pixel driving circuit 00. The fact that the first trace 10 and the gate line 14 are arranged on the same layer does not mean that they are the same in absolute height, but rather that they are made using the same film layer. In this embodiment, the first trace 10 is made using the existing gate film layer, which can utilize the existing film layer without adding a new film layer, simplifying the fabrication process of the first trace 10. It can also reduce the bright spots at the edge of the display panel 100 without increasing the thickness of the display panel 100, which is beneficial for the thinning of the display panel 100 and the reduction of production costs.

[0026] Optionally, the gate line 14 and the first trace 10 may be located on the same side of the pixel row P0, or the gate line 14 and the first trace 10 may be located on opposite sides of the pixel row P0, and this disclosure does not limit this. The first trace 10 is disposed on the same layer as the gate line 14. The first trace 10 is located in the display area AA and at least part of the non-display area NA. The first trace 10 includes molybdenum and titanium. The first trace 10 located in at least part of the non-display area NA can absorb hydrogen ions of the first transistor T1 at the edge of the display area AA, which can reduce the negative bias of the conduction threshold voltage Vth of the first transistor T1, so that the conduction threshold voltage Vth of the first transistor T1 at the edge of the display panel 100 is consistent with the conduction threshold voltage Vth of the first transistor T1 in the central area of ​​the display panel 100, thereby eliminating the bright spots that appear at the edge of the display panel 100 during the display process and improving the display effect of the display panel 100.

[0027] Thus, by setting the gate line 14 and the first trace 10 on the same layer, it is possible to reduce the bright spots at the edge of the display panel 100 without adding a new film layer or process, which is beneficial to reducing production costs and making the display panel 100 thinner.

[0028] Please continue to refer to this. Figure 4 In a display panel 100 provided in this disclosure, a first trace 10 includes a first sub-segment 11 and a second sub-segment 12 connected to each other. The first sub-segment 11 is located in the display area AA, and at least part of the second sub-segment 12 is located in the non-display area NA. The distance between the first sub-segment 11 and the adjacent gate line 14 is a first distance d1, and the distance between the second sub-segment 12 and the adjacent gate line 14 is a second distance d2, where the second distance d2 is greater than the first distance d1. It should be noted that, since the arrangement of pixel rows P0 at the curved edge of the display panel 100 is stepped, the length of the first trace 10 adjacent to different pixel rows P0 is also stepped. Compared to the next pixel row P0, the second sub-segment 12 adjacent to the previous pixel row P0 is actually at least partially located at the edge of the display area AA and at least partially located in the non-display area NA.

[0029] Specifically, in one optional embodiment provided in this disclosure, the first trace 10 is located in the display area AA and at least a portion of the non-display area NA. Further, the first trace 10 includes a first sub-segment 11 and a second sub-segment 12 located in the display area AA, and at least a portion of the second sub-segment 12 located in the non-display area NA. The extending directions of the first sub-segment 11 and the second sub-segment 12 are the same as the extending direction of the pixel row P0. Within the same first trace 10, the first distance d1 between the first sub-segment 11 and the adjacent gate line 14 is less than the second distance d2 between the second sub-segment 12 and the adjacent gate line 14. That is, within the same first trace 10, the distance between the first sub-segment 11 and the adjacent gate line 14 is relatively closer, while the distance between the second sub-segment 12 and the adjacent gate line 14 is relatively farther.

[0030] The second sub-segment 12 and the first sub-segment 11 are connected by a connecting line segment 13. The angle formed by the connecting line segment 13 and the second sub-segment 12 is an obtuse angle, and the second sub-segment 12 is a straight line.

[0031] In the actual manufacturing process, since the connecting line segment 13 intersects with the first sub-segment 11, the connecting line segment 13 can be directly extended outward from the side away from the first sub-segment 11 to form the second sub-segment 12. The second sub-segment 12 extends in the same direction as the pixel row P0, so that at least one side of the first transistor T1 at the junction of the display area AA and the non-display area NA, as well as a portion of the first trace 10 in the non-display area NA, also exists. Through the effective absorption or blocking of hydrogen in the inorganic film layer at the junction of the display area AA and the non-display area NA by the connecting line segment 13 and the second sub-segment 12, the influence on the oxide channel of the first transistor T1 in the edge area of ​​the display area AA can be reduced, and the occurrence of edge bright spots can be reduced.

[0032] In this embodiment, the second sub-segment 12 is a straight line. When making the first trace 10, the pattern can be directly extended on the existing mask pattern to obtain the mask pattern required in this embodiment, which can reduce the difficulty of the process. Since it only involves the change of one mask pattern, it is also beneficial to reduce production costs.

[0033] Since the second distance d2 between the second sub-segment 12 and the adjacent gate line 14 is greater than the first distance d1 between the first sub-segment 11 and the adjacent gate line 14, some vias (not shown in the figure) can also be provided in the film layer of the display panel 100 during the manufacturing process. The vias at least penetrate part of the inorganic layer. Optionally, the number of vias between the second sub-segment 12 and the adjacent gate line 14 is greater or the density is higher than the number of vias between the first sub-segment 11 and the adjacent gate line 14. This allows the first transistor T1 in the edge region of the display area AA to discharge hydrogen from the organic film layer through the vias during the hydrogen discharge process, reducing the impact of hydrogen on the oxide channel of the first transistor T1 in the edge position of the display area AA. Combined with the titanium-containing second sub-segment 12 epitaxially in the first trace 10, hydrogen in the inorganic film layer at the edge position of the display area AA can be effectively absorbed. This can also reduce the negative bias of the conduction voltage threshold Vth of the first transistor T1 at the edge position of the display area AA, and reduce the bright spots appearing at the edges of the display panel 100, especially irregular edges such as rounded corners.

[0034] Thus, by setting the first trace 10 as a first sub-segment 11 located in the display area AA and a second sub-segment 12 located in the non-display area NA, with the second sub-segment 12 being a straight line, the original pattern in the mask can be extended only, which can reduce the bright spots at the edge of the display area AA while reducing the process difficulty and production cost.

[0035] Please continue to refer to this. Figure 4 In the display panel 100 provided in this disclosure, the second distance d2 is less than or equal to 15µm. Optionally, the second distance d2 can be less than or equal to 14µm, or 13µm, or 12µm, or 11µm, or 10µm, or 9µm, or 8µm, or 7µm, or 6µm, etc., which are not listed here, as long as the second distance d2 is less than or equal to 15µm. When the second distance d2 is greater than 15µm, the distance between the second sub-segment 12 and the adjacent gate line 14 is too large, that is, the distance between the second sub-segment 12 and the oxide channel of the adjacent first transistor T1 is too large, which makes it impossible to effectively absorb hydrogen in the inorganic film. The high hydrogen concentration will affect the oxide channel of the first transistor T1, causing the conduction threshold voltage Vth of the first transistor T1 to be negatively biased.

[0036] Thus, by setting the second distance d2 within a range of less than or equal to 15µm, the distance between the connecting segment 13 and the adjacent gate line 14 can be controlled within a certain range, and the distance between the second sub-segment 12 and the adjacent gate line 14 can be controlled within a certain range. This enables the effective absorption of hydrogen ions in the inorganic film layer of the first trace 10 at the boundary between the display area AA and the non-display area NA, and makes the surrounding environment of the first transistor T1 at the edge of the display area AA the same as the surrounding environment of the first transistor T1 at the center of the display area AA. This reduces the negative bias of the conduction threshold voltage Vth of the first transistor T1 at the edge of the display area AA, thereby reducing the generation of edge bright spots.

[0037] Figure 5 The diagram shown illustrates another positional relationship between the first trace and adjacent gate lines according to an embodiment of this disclosure. Please refer to it. Figures 1 to 5 In a display panel 100 provided in this disclosure, the first trace 10 includes a first segment 11 and a second segment 12 that are connected to each other. The first segment 11 is located in the display area AA, and at least part of the second segment 12 is located in the non-display area NA. The distance between the first segment 11 and the adjacent gate line 14 is a first distance d1, and the distance between the second segment 12 and the adjacent gate line 14 is a second distance d2. The second distance d2 is equal to the first distance d1.

[0038] Specifically, in another optional embodiment provided in this disclosure, the first trace 10 is located on at least one side of pixel row P0. The first trace 10 includes a first sub-segment 11 and a second sub-segment 12 located in display area AA. At least a portion of the second sub-segment 12 is also located in non-display area NA. The distances between the first sub-segment 11 and the second sub-segment 12 and the adjacent gate line 14 are equal. Compared with the aforementioned embodiment, this embodiment sets the second distance d2 between the second sub-segment 12 and the adjacent gate line 14 to be equal to the first distance d1. That is, the distance between the second sub-segment 12 and the adjacent gate line 14 in at least a portion of the non-display area NA is closer. This can improve the absorption efficiency of hydrogen in each inorganic film layer of the non-display area NA, reduce the influence of hydrogen content on the oxide channel of the first transistor T1 at the edge of the display area AA, and reduce the negative bias of the conduction threshold voltage Vth of the first transistor T1.

[0039] Thus, by setting the second distance d2 to be the same as the first distance d1, at least partially located in the non-display area NA, the distance between the second sub-segment 12 and the adjacent gate line 14 is closer, which is beneficial to setting the surrounding environment of the first transistor T1 at the edge position of the display area AA to be the same as the surrounding environment of the first transistor T1 at the center position of the display area AA, thereby reducing the formation of edge bright spots.

[0040] In this embodiment, the second sub-segment 12 has the same shape as the first sub-segment 11. Compared to the previous embodiment, where the first sub-segment 11 and the second sub-segment 12 are connected by a connecting line segment 13, and the angle formed by the connecting line segment 13 and the second sub-segment 12 is an obtuse angle. This embodiment, while setting the distances between the first sub-segment 11 and the second sub-segment 12 and the adjacent gate line 14 to be equal, further sets the shape of the second sub-segment 12 to be the same as the first sub-segment 11. That is, in the same first trace 10, the shape of the second sub-segment 12 is the same as the shape of the first sub-segment 11, which simplifies the mask pattern design and reduces pattern complexity. It also helps to make the hydrogen absorption capacity of the second sub-segment 12 for each film layer in the display area AA close to that of the first sub-segment 11, making the hydrogen content in the environment surrounding the first transistor T1 located at the edge of the display area AA closer to that of the first transistor T1 located at the center of the display area AA, thereby effectively reducing the occurrence of edge bright spots and improving the display effect.

[0041] In this embodiment, within the same first trace 10, the first sub-segment 11 and the second sub-segment 12 are equidistant from the adjacent gate line 14. The first sub-segment 11 and the second sub-segment 12 can be directly connected, reducing the need for connecting lines 13 between them. This simplifies the process and reduces the complexity of the pattern in the mask. In other embodiments, the connecting line 13 may be positioned on the side of the second sub-segment 12 away from the first sub-segment 11; this disclosure does not limit this to a specific embodiment.

[0042] Thus, by setting the shape of the second sub-segment 12 to be the same as that of the first sub-segment 11, the complexity of the graphics in the mask can be reduced, the design can be simplified, and the production cost can be reduced.

[0043] Please continue to refer to this. Figure 5 In a display panel 100 provided in this disclosure, the second distance d2 is less than or equal to 5µm.

[0044] Specifically, when the second distance d2 is equal to the first distance d1, the distance between the second sub-segment 12 and the adjacent grid line 14 is closer. In this case, the second distance d2 is less than or equal to 5µm. Understandably, the first distance d1 between the first sub-segment 11 located in the display area AA and the adjacent grid line 14 is less than or equal to 5µm. Optionally, the second distance d2 can be less than or equal to 4.5µm, or less than or equal to 4µm, or less than or equal to 3.5µm, or less than or equal to 3µm, or less than or equal to 2.5µm, or less than or equal to 2µm, etc. The above are just examples, and this disclosure does not limit them. The specific settings can be made according to actual needs. Since the second distance d2 is equal to the first distance d1, when the second distance d2 is greater than 5µm, the first distance d1 between the first sub-segment 11 and the adjacent gate line 14 in the display area AA is also greater than 5µm. The distance between the first sub-segment 11 and the adjacent gate line 14 is relatively far. The absorption of hydrogen ions in the inorganic film layer by the first trace 10 adjacent to the pixel row P0 in the display area AA is limited. The hydrogen ion concentration near the oxide semiconductor layer 15 in the first transistor T1 is too high, which may cause abnormal screen display due to the negative bias of the conduction threshold voltage Vth of the first transistor T1 in the display area AA.

[0045] Thus, when the second distance d2 is equal to the first distance d1, by setting the second distance d2 within the range of less than or equal to 5µm, the first distance d1 between the first sub-segment 11 and the adjacent gate line 14 in the display area AA can be controlled within 5µm, so that the first sub-segment 11 can effectively absorb hydrogen ions near the adjacent pixel row P0, reduce the hydrogen ion content near the first transistor T1, and ensure the normal display of the display panel 100.

[0046] Figure 6 The diagram shown is a partial film layer schematic of a display panel according to an embodiment of this disclosure. Please refer to it. Figures 1 to 6 The display panel 100 includes a substrate 50, a driving layer 60, a light-emitting layer 30, and an encapsulation layer 40, etc. Optionally, the substrate 50 includes a flexible substrate or a rigid substrate. For example, the flexible substrate includes polyimide, polyethylene terephthalate, etc., and the rigid substrate includes glass, sapphire, etc. The driving layer 60 is deposited on the substrate 50. The driving layer 60 includes a gate G, a semiconductor layer 15, a source S, and a drain D, as well as insulating layers located between the gate G and the semiconductor layer 15, and between the semiconductor layer 15 and the source S and drain D, etc. The thin-film transistor T in the driving layer 60 can be a single-gate transistor or a dual-gate transistor; this disclosure does not limit this. Figure 6The illustration uses a single-gate transistor as an example only. Optionally, the thin-film transistor T in the driving layer 60 may also include a low-temperature polycrystalline silicon transistor or an oxide transistor. The semiconductor layer material of the low-temperature polycrystalline silicon transistor is polycrystalline silicon, and the semiconductor layer material of the oxide transistor is oxide semiconductor. This embodiment uses an oxide transistor as an example. The light-emitting layer 30 includes multiple light-emitting elements L. Each light-emitting element L includes an anode 32, a cathode 31, and a light-emitting functional layer 33. Electrons in the cathode 31 and holes in the anode 32 recombine in the light-emitting functional layer 33 to achieve light emission.

[0047] Please combine Figure 4 and Figure 5 In a display panel 100 provided in this disclosure, the display panel 100 includes a semiconductor layer 15, the channel of a first transistor T1 is located in the semiconductor layer 15, and at least a portion of the semiconductor layer 15 is located in the non-display area NA.

[0048] Specifically, in this embodiment, the channel of the first transistor T1 is located in the semiconductor layer 15, and at least part of the semiconductor layer 15 is located in the non-display area NA. Compared with the case in the related art where the non-display area NA is not provided with a semiconductor layer 15, in this embodiment, there is also a semiconductor layer 15 around the first transistor T1 at the edge of the display area AA. This makes the surrounding environment of the first transistor T1 at the edge of the display area AA closer to the surrounding environment of the first transistor T1 at the center of the display area AA, which is beneficial to balancing the surrounding environment of the first transistor T1 in different areas of the display area AA, reducing the formation of edge bright spots, and improving display uniformity.

[0049] In the relevant manufacturing process, an opening for the pixel definition layer is typically not provided on the anode connected to the non-display area NA circuit, so that the anode in the non-display area NA is not connected to the vapor deposition device, thereby achieving that the pixels in the non-display area NA are not displayed. In the narrow bezel display panel 100, redundant sub-pixels may not be provided in the non-display area NA, and the semiconductor layer 15 may only be provided in at least part of the non-display area NA. This can achieve a narrow bezel while balancing the differences in the surrounding environment of the first transistor T1 in different areas.

[0050] Thus, by placing at least a portion of the semiconductor layer 15 in the non-display area NA, the surrounding environment of the first transistor T1 in different areas of the display area AA can be balanced, reducing the difference in the surrounding environment of the first transistor T1 in different areas. This makes the conduction threshold voltage Vth of the first transistor T1 at the center of the display area AA basically the same as that of the first transistor T1 at the edge of the display area AA, thereby reducing edge bright spots and improving display uniformity.

[0051] In some other embodiments, the semiconductor layer 15 may not be provided in the non-display area NA, and this disclosure is not limited thereto. When the first trace 10 is located in at least a portion of the non-display area NA, even if the semiconductor layer 15 is not located in the non-display area NA, the first trace 10 located in the non-display area NA can absorb hydrogen ions in the non-display area NA, and can also reduce the negative bias of the conduction threshold voltage Vth of the first transistor T1 at the edge of the display area AA, thereby reducing the formation of edge bright spots.

[0052] Please refer to Figure 3 In a display panel 100 provided in this disclosure, the pixel driving circuit 00 includes a driving transistor T3, and a first transistor T1 is electrically connected to the gate of the driving transistor T3.

[0053] Alternatively, please refer to Figure 3 The pixel circuit includes a driving transistor T3, a data writing module 91, a compensation module 92, a first reset module 93, a light emission control module 94, and a second reset module 95. The gate of the driving transistor T3 is connected to a first node N1, its first terminal is connected to a second node N2, and its second terminal is connected to a third node N3. In the pixel driving circuit 00, the driving transistor T3 provides a driving current to the light-emitting element L. The driving transistor T3 can determine the magnitude of its driving current based on its gate potential, thereby adjusting the brightness of the light-emitting element L by controlling the gate voltage of the driving transistor T3.

[0054] Optionally, the data writing module 91 includes a second transistor T2, the light emission control module 94 includes a fifth transistor T5 and a sixth transistor T6, the compensation module 92 includes a fourth transistor T4, the first reset module 93 includes a first transistor T1, and the second reset module 95 includes a seventh transistor T7. In the first reset module 93, the first transistor T1 is connected to the first reset signal line Vref1 and the first node N1, respectively, and its gate is connected to the first scan line S1. In the data writing module 91, the second transistor T2 is connected to the data line Data and the second node N2, respectively, and its gate, along with the gate of the fourth transistor T4 in the compensation module 92, is connected to the second scan line S2. In the light emission control module 94, the fifth transistor T5 is connected to the first power signal line PVDD and the second node N2, respectively, and its gate is connected to the light emission control line EM. In the second reset module 95, the two terminals of the seventh transistor T7 are connected to the second reset signal line Vref2 and the fourth node N4, respectively. The fourth node N4 is connected to the anode of the light-emitting element L, and the cathode of the light-emitting element L is connected to the second power signal line PVEE. It should be noted that in the driving circuit of this embodiment, only N-type transistors are used as an example for explanation, but the type of transistor is not limited. Figure 3The following explanation uses an oxide transistor (OTT) as an example of a first transistor T1. Specifically, the OTT transistor can be an IGZO transistor, and the first transistor T1 can be an N-type MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor). This disclosure does not limit this to specific types. OTT transistors (such as a-IGZO TFTs) have extremely low leakage current (only 1 / 1000 of LTPS). When connected to the gate of the driving transistor T3, a dynamic voltage regulation mechanism can be formed. When displaying a static image, the first transistor T1 maintains a stable gate voltage of the driving transistor T3 through low leakage current, reducing unnecessary refresh operations and thus lowering static power consumption.

[0055] Figure 7 The diagram shown is a schematic representation of the connection between a first trace and a second trace according to an embodiment of this disclosure. Figure 8 The diagram shown is a schematic representation of another connection between the first trace and the second trace provided in this embodiment of the present disclosure. Please refer to it. Figures 6 to 8 In a display panel 100 provided in this disclosure, the display panel 100 includes a second trace 20, and a first transistor T1 includes a source S and a drain D. The second trace 20 is disposed on the same layer as the source S and the drain D. Along a direction perpendicular to the plane where the display panel 100 is located, the second trace 20 overlaps at least partially with the first trace 10, and the second trace 20 and the first trace 10 are connected through vias.

[0056] Specifically, the second trace 20 is disposed on the same layer as the source S and drain D of the first transistor T1. That is, during the manufacturing process, the second trace 20 can be manufactured in the same process as the source S and drain D, using the same raw materials, without the need for an additional film layer, which is beneficial for the thinning of the display panel 100. It should be noted that... Figure 7 and Figure 8 The only difference is the shape of the first trace 10, which is different, and therefore the connection position of the corresponding second trace 20 is different.

[0057] The second trace 20 at least partially overlaps with the first trace 10 and is connected through a via. Please refer to... Figure 3The second trace 20 may include a reset signal line connected to a reset signal. For example, the second trace 20 may be a second reset signal line Vref2, with the first trace 10 electrically connected to the second trace 20 and connected to the second reset signal Vref2 (in this embodiment, the signal line and the corresponding signal are referred to by the same reference numerals). The second reset signal line Vref2 is used to reset the anode of the light-emitting element L. Alternatively, the second trace 20 may be a first reset signal line Vref1, with the first trace 10 electrically connected to the second trace 20 and connected to the first reset signal Vref1. The first reset signal line Vref1 is used to reset the gate of the driving transistor T3, etc. This disclosure does not limit the signal type transmitted by the first trace 10 and the second trace 20; the specific type can be set according to actual needs. Optionally, when the pixel driving circuit 00 includes multiple oxide transistors, the first trace 10 may also serve as the gate of other oxide transistors.

[0058] Thus, by electrically connecting the first trace 10 to the second trace 20, the first trace 10 is connected to a fixed potential, which can prevent the first trace 10 from floating and prevent the first trace 10 from being damaged by electrostatic discharge.

[0059] Figure 9 The diagram shown is a schematic representation of the location of the punch-hole area in a display panel according to an embodiment of this disclosure. Please refer to it. Figure 9 In a display panel 100 provided in this disclosure, at least a portion of the non-display area NA is located outside the display area AA, and / or at least a portion of the non-display area NA is surrounded by the display area AA.

[0060] Optionally, when the display panel 100 is a rounded rectangle, the non-display area NA may include the four rounded corner areas of the rectangle and a punch-hole area KA located inside the display area AA. Optionally, the punch-hole area KA includes a light-transmitting hole, which can be used to transmit natural light for front-facing camera functions of the display panel 100, or to transmit infrared light for facial recognition. Due to the presence of the punch-hole area KA, the surrounding environment of the first transistor T1 in the display area AA around the punch-hole area KA differs from the surrounding environment of the first transistor T1 in other areas of the display area AA, which may cause the conduction threshold voltage Vth of the first transistor T1 near the punch-hole area KA to be negatively biased. The first trace 10 is at least partially located in the punch-hole area KA, which can enhance the effective absorption of hydrogen ions around the first transistor T1 near the light-transmitting hole and alleviate the edge bright spot problem of the irregularly shaped display area AA around the light-transmitting hole.

[0061] Optionally, when the display panel 100 is circular, the non-display area NA may include the non-display area NA surrounding the display area AA, etc. The display panel 100 may also have other shapes, and the non-display area NA may also include other areas with curved edges; this disclosure does not limit this. By providing a first trace 10 including molybdenum and titanium in the non-display area NA, the first trace 10 absorbs hydrogen ions in the non-display area NA, thereby reducing the negative bias of the first transistor T1 and reducing the occurrence of edge bright spots.

[0062] Figure 10 The diagram shown is a schematic representation of a display device according to an embodiment of this disclosure. Please refer to it. Figure 10 This disclosure provides a display device 200, including the display panel 100 as described in the foregoing embodiments. The display device 200 provided in this disclosure can be any electronic device with display function, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television, or it can also be a large-size display device such as a giant advertisement or a command center screen. The display device 200 provided in this disclosure has the beneficial effects of the display panel provided in this disclosure. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0063] Understandable, Figure 10 The shape of the display device 200 is illustrated using only a right-angled rectangle structure as an example. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it in this regard.

[0064] In some other embodiments of this disclosure, the display device 200 may further include at least two display panels 100, for example, please refer to Figure 11 , Figure 11 The diagram shown illustrates another display device according to an embodiment of this disclosure. This embodiment uses a display device 200 comprising four arrayed display panels 100 as an example for illustration, but does not limit the actual number of display panels included. Since the display panels 100 provided in this embodiment can reduce edge bright spots, when the display device 200 is a spliced ​​display product, the entire display device can effectively and significantly reduce or eliminate edge bright spots, effectively improving the display effect of the large-screen display device.

[0065] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: A display area and a non-display area, wherein the non-display area is adjacent to the display area; The display panel includes multiple pixel rows, each pixel row includes multiple sub-pixels, each sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes a first transistor, which is an oxide transistor. The display panel includes a first trace located on at least one side of the pixel row; the first trace is located in the display area and at least a portion of the non-display area. The first trace comprises molybdenum and titanium, and along a direction parallel to the plane of the display panel, the shortest distance between the first trace and the channel of the first transistor is less than one-third of the spacing between two adjacent rows of pixels.

2. The display panel as described in claim 1, characterized in that, The display panel includes multiple grid lines, the extension direction of which is the same as the extension direction of the pixel row, and the arrangement direction of which is the same as the arrangement direction of the pixel row; the grid lines are disposed on the same layer as the first trace.

3. The display panel as described in claim 2, characterized in that, The first trace includes an interconnected first sub-segment and a second sub-segment, the first sub-segment being located in the display area, and at least a portion of the second sub-segment being located in the non-display area; The distance between the first sub-segment and the adjacent gate line is a first distance, and the distance between the second sub-segment and the adjacent gate line is a second distance, wherein the second distance is greater than the first distance.

4. The display panel as described in claim 3, characterized in that, The second sub-segment and the first sub-segment are connected by a connecting line segment, the angle formed between the connecting line segment and the second sub-segment is an obtuse angle, and the second sub-segment is a straight line.

5. The display panel as described in claim 4, characterized in that, The second distance is less than or equal to 15µm.

6. The display panel as described in claim 2, characterized in that, The first trace includes an interconnected first sub-segment and a second sub-segment, the first sub-segment being located in the display area, and at least a portion of the second sub-segment being located in the non-display area; The distance between the first sub-segment and the adjacent gate line is a first distance, and the distance between the second sub-segment and the adjacent gate line is a second distance, the second distance being equal to the first distance.

7. The display panel as described in claim 6, characterized in that, The second sub-segment has the same shape as the first sub-segment.

8. The display panel as described in claim 7, characterized in that, The second distance is less than or equal to 5µm.

9. The display panel as claimed in claim 1, characterized in that, The display panel includes a semiconductor layer, the channel of the first transistor is located in the semiconductor layer, and at least a portion of the semiconductor layer is located in the non-display area.

10. The display panel as claimed in claim 1, characterized in that, The pixel driving circuit includes a driving transistor, and the first transistor is electrically connected to the gate of the driving transistor.

11. The display panel as claimed in claim 1, characterized in that, The display panel includes a second trace, the first transistor includes a source and a drain, and the second trace is disposed on the same layer as the source and the drain; Along a direction perpendicular to the plane of the display panel, the second trace at least partially overlaps with the first trace, and the second trace and the first trace are connected by vias.

12. The display panel as claimed in claim 1, characterized in that, At least a portion of the non-display area is located outside the display area, and / or at least a portion of the non-display area is surrounded by the display area.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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