A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a first power signal line, a second power signal line and a plurality of sub-pixels. The plurality of sub-pixels are arranged in an array. Each sub-pixel comprises a first light emitting device and a second light emitting device. The first electrode of the first light emitting device and the second light emitting device of the same sub-pixel are electrically connected. The second electrode of the first light emitting device is connected to the first power signal line, and the second electrode of the second light emitting device is connected to the second power signal line. The first power signal line and the second power signal line are insulatively arranged. The embodiment of the application can reduce the pixel layout area and improve the pixel density.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, the application of display panels is becoming more and more widespread, and the requirements for display panels are correspondingly becoming higher and higher.

[0003] Currently, existing display panels suffer from a large pixel layout area, making it difficult to achieve high pixel density displays. Summary of the Invention

[0004] The present invention provides a display panel and a display device to reduce the pixel layout area and increase the pixel density.

[0005] In a first aspect, embodiments of the present invention provide a display panel, comprising: a first power signal line, a second power signal line, and a plurality of sub-pixels; the plurality of sub-pixels are arranged in an array, and each sub-pixel includes a first light-emitting device and a second light-emitting device; the first electrodes of the first light-emitting device and the second light-emitting device of the same sub-pixel are electrically connected; the second electrode of the first light-emitting device is connected to the first power signal line, and the second electrode of the second light-emitting device is connected to the second power signal line; the first power signal line and the second power signal line are insulated from each other.

[0006] Optionally, the display panel further includes an array substrate and an isolation structure; the isolation structure is located on one side of the array substrate, and the isolation structure includes a first isolation structure and a second isolation structure; the first isolation structure is insulated from the second isolation structure; the first isolation structure encloses to form a plurality of first isolation openings, and the second isolation structure encloses to form a plurality of second isolation openings; the second electrode of the first light-emitting device is located in the corresponding first isolation opening and overlaps with the first isolation structure, and the second electrode of the second light-emitting device is located in the corresponding second isolation opening and overlaps with the second isolation structure; a first power signal line and a second power signal line are disposed on the array substrate and electrically connected to the first isolation opening and the second isolation opening, respectively.

[0007] Optionally, the multiple pixel rows include multiple odd rows and multiple even rows; the first light-emitting device of the same sub-pixel is located in the corresponding odd row, and the second light-emitting device is located in the even row adjacent to the odd row.

[0008] Optionally, the second electrodes of multiple first light-emitting devices located in the same row are electrically connected, and the second electrodes of multiple second light-emitting devices located in the same row are electrically connected.

[0009] Optionally, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device are disposed on the same layer and electrically connected as one unit.

[0010] Optionally, the display panel further includes an array substrate, which includes a substrate, a driving circuit layer, and a planarization layer; the driving circuit layer is disposed on one side of the substrate; the planarization layer is disposed on the side of the driving circuit layer away from the substrate; and a first power signal line and a second power signal line are disposed on the driving circuit layer. Optionally, the driving circuit layer includes multiple conductive layers, and the first power signal line and the second power signal line are disposed in at least one of the multiple conductive layers.

[0011] Optionally, the display panel further includes a display area and a lower border area adjacent to the display area; the lower border area is provided with a first signal transmission line and a second signal transmission line; a first power signal line is electrically connected to the first signal transmission line in the lower border area, and the first signal transmission line is electrically connected to a first power management module; a second power signal line is electrically connected to the second signal transmission line in the lower border area, and the second signal transmission line is electrically connected to a second power management module.

[0012] Optionally, the lower bezel area of ​​the display panel includes a virtual light-emitting area and a dam area adjacent to the display area; the virtual light-emitting area is located between the display area and the dam area; the virtual light-emitting area is provided with multiple virtual light-emitting devices; the virtual light-emitting devices include virtual cathodes; the isolation structure also includes a third isolation structure, the third isolation structure encloses to form multiple third isolation openings, the virtual cathodes are located in the corresponding third isolation openings and overlap with the third isolation structure.

[0013] Optionally, the third isolation structure is electrically connected to the second isolation structure corresponding to the second light-emitting device located in the last row of the display area; the second signal transmission line is electrically connected to the third isolation structure near the dam area.

[0014] Optionally, the second signal transmission line is electrically connected to a third isolation structure near the dam area via a third via.

[0015] Optionally, the virtual cathode and the second electrode are arranged in the same layer.

[0016] Optionally, the first signal transmission line includes a first transmission structure, and the second signal transmission line includes a second transmission structure; in the lower frame region, the second transmission structure includes a plurality of first structures spaced apart along a first direction; the first transmission structure includes a second structure and a plurality of third structures, the third structures being located between two adjacent first structures in the first direction; the second structure extends along the first direction and is connected to the first power signal line and the third structure; wherein, the first direction intersects with the direction perpendicular to the array substrate.

[0017] Optionally, the first structure includes a first part and a second part, the first part extending along a first direction, and the second part disposed on the side of the first part away from the second structure.

[0018] Optionally, the sum of the number of the first structure and the number of the third structure is equal to the number of sub-pixels in a row within the display area.

[0019] Optionally, the display panel also includes a pixel definition layer disposed on the array substrate, and an isolation structure is disposed on the side of the pixel definition layer away from the array substrate.

[0020] Optionally, the pixel definition layer is provided with a plurality of first pixel openings and a plurality of second pixel openings; the first pixel openings are connected to the corresponding first isolation openings, and the second pixel openings are connected to the corresponding second isolation openings.

[0021] Optionally, the orthographic projection of the first isolation opening on the array substrate covers the orthographic projection of the first pixel opening on the array substrate, and the orthographic projection of the second isolation opening on the array substrate covers the orthographic projection of the second pixel opening on the array substrate.

[0022] Optionally, the first light-emitting device and the second light-emitting device further include a light-emitting layer; the light-emitting layer of the first light-emitting device is disposed in the corresponding first pixel opening, and the light-emitting layer of the second light-emitting device is disposed in the corresponding second pixel opening.

[0023] Optionally, the display panel includes a display area, and the display area is provided with a first power signal line and a second power signal line in a mesh-like connection structure; wherein, the first power signal line includes a plurality of first signal lines extending along a first direction and spaced apart along a second direction, and a plurality of second signal lines extending along the second direction and spaced apart along the first direction, the first signal lines and the second signal lines are electrically connected, and the first direction and the second direction intersect; the second power signal line includes a plurality of third signal lines extending along the first direction and spaced apart along the second direction, and a plurality of fourth signal lines extending along the second direction and spaced apart along the first direction, the third signal lines and the fourth signal lines are electrically connected; Optionally, the first signal line and the second signal line are disposed on different conductive layers and electrically connected through a fourth via.

[0024] Optionally, the third signal line and the fourth signal line are disposed on different conductive layers and electrically connected through a fifth via.

[0025] Optionally, the first signal line and the third signal line are disposed on the same conductive layer or on different conductive layers.

[0026] Optionally, the second signal line and the fourth signal line are disposed on the same conductive layer or on different conductive layers.

[0027] Optionally, the first direction is perpendicular to the second direction.

[0028] Optionally, the sub-pixel further includes a pixel circuit; the first electrodes of the first and second light-emitting devices corresponding to the same sub-pixel are electrically connected to the same pixel circuit; the pixel circuit includes a driving module, a data writing module, a coupling module, and a light-emitting control module; the first end of the data writing module and the coupling module are connected to the first node, and the second end of the coupling module is connected to the control terminal of the driving module to the second node; the data writing module is used to transmit the data voltage to the first node according to the signal on the second scan line, and write the voltage information associated with the data voltage to the control terminal of the driving module through the coupling module; the first electrodes of the first and second light-emitting devices are connected to the third node; the driving module and the light-emitting control module are connected in series between the positive power signal line and the third node, and the light-emitting control module is used to control the first or second light-emitting device to emit light according to the driving current output by the driving module according to the signal on the first light-emitting control signal line.

[0029] Optionally, in normal display mode, the first power signal line provides a first level and the second power signal line provides a second level, so that the pixel circuit drives the first light-emitting device to emit light and turns off the second light-emitting device; in privacy display mode, the first power signal line provides a second level and the second power signal line provides a first level, so that the pixel circuit drives the second light-emitting device to emit light and turns off the first light-emitting device.

[0030] Optionally, the pixel circuit also includes a compensation module, which is connected between the control terminal and the first terminal of the driving module. The compensation module is used to compensate the threshold voltage of the driving module according to the signal on the second scan line.

[0031] Optionally, the pixel circuit further includes a first initialization module, which is connected between the first initialization signal line and the control terminal of the drive module. The first initialization module is used to transmit the first initialization voltage on the first initialization line to the control terminal of the drive module according to the signal on the first scan line.

[0032] Optionally, the pixel circuit further includes a second initialization module, which is connected between the second initialization signal line and the third node. The second initialization module is used to transmit the second initialization voltage on the second initialization signal line to the third node according to the signal on the second light emission control signal line.

[0033] Optionally, the pixel circuit further includes a third initialization module, which is connected between the third initialization signal line and the first node. The third initialization module is used to transmit the third initialization voltage on the third initialization signal line to the first node according to the signal on the first light emission control signal line.

[0034] Optionally, the coupling module includes a first capacitor and a second capacitor; the first end of the first capacitor serves as the first end of the coupling module, the second end of the first capacitor is connected to the first end of the second capacitor at the fourth node, and the second end of the second capacitor serves as the second end of the coupling module.

[0035] Optionally, the pixel circuit further includes a fourth initialization module, which is connected between the third initialization signal line and the fourth node. The fourth initialization module is used to transmit the third initialization voltage on the third initialization signal line to the fourth node according to the signal on the second light emission control signal line.

[0036] Optionally, the positive power signal line is multiplexed as a third initialization signal line, and the positive power voltage transmitted on the positive power signal line is multiplexed as a third initialization voltage.

[0037] Secondly, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention. The display panel provided in this embodiment of the invention connects the first electrodes of a first light-emitting device and a second light-emitting device in the same sub-pixel to the same pixel circuit. Simultaneously, the second electrode of the first light-emitting device is connected to a first power signal line, and the second electrode of the second light-emitting device is connected to a second power signal line. Therefore, switching between normal display mode and privacy display mode can be achieved simply by changing the output voltage of the first and second power signal lines. This solution eliminates the need for additional transistors or scan signal lines in the pixel circuit, effectively reducing the layout area of ​​the pixel circuit and facilitating higher pixel density.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a sub-pixel structure provided in an embodiment of the present invention; Figure 3 This is a partial cross-sectional view of a display panel provided in an embodiment of the present invention; Figure 4a This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 4b This is a partial cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 6 This is a partial cross-sectional view of another display panel provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0043] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a sub-pixel structure provided in an embodiment of the present invention. For example... Figure 1 and Figure 2 As shown, the display panel includes: a first power signal line VSS1, a second power signal line VSS2, and multiple sub-pixels; Multiple sub-pixels are arranged in an array, and the sub-pixels include a first light-emitting device 13a and a second light-emitting device 13b; The first electrodes 131 of the first light-emitting device 13a and the second light-emitting device 13b of the same sub-pixel 10 are electrically connected; The second electrode 133 of the first light-emitting device 13a is connected to the first power signal line VSS1, and the second electrode 133 of the second light-emitting device 13b is connected to the second power signal line VSS2. The first power signal line VSS1 and the second power signal line VSS2 are insulated from each other.

[0044] Specifically, the display panel can be an Organic Light Emitting Diode (OLED) display panel or a Quantum Dot Light Emitting Diode (QLED) display panel. The display panel includes a display area AA with display functions and a non-display area NAA. The display area AA includes multiple pixels PX arranged in a first direction X and a second direction Y. Pixel PX includes multiple sub-pixels SPX displaying different colors. In some embodiments, pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is a blue sub-pixel, the second sub-pixel SPX2 is a green sub-pixel SPX2, and the third sub-pixel SPX3 is a red sub-pixel SPX3. In some embodiments, in addition to sub-pixels SPX1, SPX2, and SPX3, pixel PX also includes sub-pixels SPX that emit white or other colors of light. Optionally, the first direction X intersects the second direction Y. Exemplarily, the first direction X is perpendicular to the second direction Y.

[0045] The sub-pixel SPX includes a pixel circuit 20 and a first light-emitting device 13a and a second light-emitting device 13b driven by the pixel circuit 20 to emit light of the corresponding color. The first light-emitting device 13a is used in the normal display mode (also known as the shared display mode), and the second light-emitting device 13b is used in the privacy display mode. This structure allows one pixel circuit to control two light-emitting devices simultaneously, achieving the integration of privacy functions without increasing the pixel circuit area.

[0046] Both the first light-emitting device 13a and the second light-emitting device 13b include a first electrode 131, a light-emitting layer 132, and a second electrode 133 stacked together. The first electrode 131 can be an anode, and the second electrode 133 can be a cathode. The light-emitting layer 132 can be made of organic light-emitting material to generate different colors of light. The first electrode 131 injects and transports holes into the central light-emitting layer 132, while the second electrode 133 injects and transports electrons into the light-emitting layer 132. The holes and electrons combine in the light-emitting layer 132 to form excitons, causing the organic light-emitting material to emit light, thus obtaining different colors of light. The first electrode 131 of each light-emitting device can be connected to a pixel circuit through vias, so that the pixel circuit drives each light-emitting device to emit light.

[0047] The first electrode 131 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metal with excellent light reflectivity. The conductive oxide layers can be formed, for example, using transparent conductive oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 133 is formed, for example, using a metallic material such as an alloy of magnesium and silver (MgAg).

[0048] The first light-emitting device 13a is used for light emission in normal display mode. In normal display mode, the first power signal line VSS1 provides a first level (i.e., low-level voltage), and the second power signal line VSS2 provides a second level (i.e., high-level voltage), so that the pixel circuit 20 drives the first light-emitting device 13a to emit light in a forward bias, while the second light-emitting device 13b is in a reverse bias or zero bias state and is thus turned off, achieving a normal display effect with a conventional wide viewing angle.

[0049] The second light-emitting device 13b is used for light emission in the privacy display mode. In the privacy display mode, the first power signal line VSS1 provides a second level and the second power signal line VSS2 provides a first level, causing the second light-emitting device 13b to emit light under forward bias, while the first light-emitting device 13a is in a reverse bias or zero bias state and is thus turned off, achieving a narrow viewing angle privacy display effect.

[0050] The display panel provided in this invention connects the first electrodes of a first light-emitting device and a second light-emitting device in the same sub-pixel to the same pixel circuit. Simultaneously, the second electrode of the first light-emitting device is connected to a first power signal line, and the second electrode of the second light-emitting device is connected to a second power signal line. Therefore, switching between normal display mode and privacy display mode can be achieved simply by changing the output voltage of the first and second power signal lines. This solution eliminates the need for additional transistors or scanning signal lines in the pixel circuit, effectively reducing the layout area of ​​the pixel circuit and facilitating higher pixel density. It can well meet the high-resolution display requirements of applications such as automotive, mobile phones, virtual reality (VR), and augmented reality (AR).

[0051] Figure 3 This is a partial cross-sectional view of a display panel provided in an embodiment of the present invention. For example... Figure 3As shown, the display panel also includes an array substrate 11 and an isolation structure 12; the isolation structure 12 is located on one side of the array substrate 11, and the isolation structure 12 includes a first isolation structure 12b1 and a second isolation structure 12b2, with the first isolation structure 12b1 and the second isolation structure 12b2 being insulated from each other.

[0052] The first isolation structure 12b1 encloses and forms a plurality of first isolation openings 12a1, and the second isolation structure 12b2 encloses and forms a plurality of second isolation openings 12a2; the second electrode 133 of the first light-emitting device 13a is located in the corresponding first isolation opening 12a1 and overlaps with the first isolation structure 12b1, and the second electrode 133 of the second light-emitting device 13b is located in the corresponding second isolation opening 12a2 and overlaps with the second isolation structure 12b2. The first power signal line VSS1 and the second power signal line VSS2 are disposed on the array substrate 11 and are electrically connected to the first isolation opening 12a1 and the second isolation opening 12a2, respectively.

[0053] Specifically, the array substrate 11 includes a substrate 111, a driving circuit layer 112, and a planarization layer 113. The substrate 111 can be a rigid substrate or a flexible substrate. The driving circuit layer 113 is disposed on one side of the substrate 111 and includes a plurality of pixel circuits 20. Each pixel circuit 20 includes at least one transistor, such as a driving transistor and a data writing transistor, for transmitting data voltage to the control terminal of the driving transistor under the control of a scan signal and generating a corresponding driving current. The planarization layer 113 is disposed on the side of the driving circuit layer 112 away from the substrate and is used to cover the transistors, capacitors, signal traces, and other structures in the driving circuit layer 112, providing a flat surface for the subsequent fabrication of film layers. A via is provided in the planarization layer 113, through which the first electrode 131 of the light-emitting device is electrically connected to the pixel circuit in the driving circuit layer 112. In the display panel, the isolation structure 12 is disposed on the side of the planarization layer 112 away from the substrate 111. The first electrode 131 of the light-emitting device is located between the planarization layer 113 and the isolation structure 12. The light-emitting layer 132 and the second electrode 133 of the light-emitting device are disposed within the isolation opening formed by the isolation structure 12. By integrating the pixel circuit 20 in the array substrate, a driving signal can be provided to the light-emitting device while supporting it, thereby realizing independent control of the light-emitting device.

[0054] Optionally, the first electrode 131 of the first light-emitting device 13a and the first electrode 131 of the second light-emitting device 13b are disposed on the same layer and electrically connected as one unit. The display panel also includes a first electrode layer, which is disposed on the side of the planarization layer 113 away from the substrate 111; the first electrode 131 of the first light-emitting device 13a and the second light-emitting device 13b are disposed on the first electrode layer.

[0055] In the above embodiments, by setting the isolation structure 12, the light-emitting devices of different colors can be fabricated separately and independently. Specifically, the continuous arrangement of the light-emitting layers 132 between adjacent light-emitting devices can cause lateral crosstalk, resulting in adjacent light-emitting devices emitting light erroneously, thus affecting the display quality. By setting each light-emitting device independently, the problem of lateral crosstalk between adjacent light-emitting devices can be improved, thereby enhancing the display quality of the display panel.

[0056] Since the isolation structure 12 is disposed on the array substrate 11, when the light-emitting layer 132 and the second electrode 133 are vapor-deposited, the light-emitting layer 132 forms a barrier at the isolation structure 12, so that adjacent light-emitting devices are independent of each other and crosstalk is avoided. Optionally, the second electrode 133 can overlap with the isolation structure 12, so that the second electrode 133 forms a whole-layer structure. Of course, the second electrode 133 can not overlap with the isolation structure 12, so that the second electrodes 133 are independent of each other.

[0057] When the display panel includes the isolation structure 12, each color of light-emitting device can be fabricated in a single layer before patterning, thus eliminating the need for a mask and reducing costs. Different colors of light-emitting devices are fabricated in different sequences. During the patterning process of the later-fabricated light-emitting devices, isolation can be achieved through the isolation structure 12, improving the yield of the patterning process and reducing the impact of patterning on the yield of the light-emitting devices.

[0058] In some embodiments, the first light-emitting device 13a is provided in a one-to-one correspondence with the first isolation opening 12a1, and the second light-emitting device 13b is provided in a one-to-one correspondence with the second isolation opening 12a2.

[0059] Optionally, the first power signal line VSS1 is electrically connected to the first isolation structure corresponding to the first isolation opening 12a1 through the first via 14. The second power signal line VSS2 is electrically connected to the second isolation structure corresponding to the second isolation opening 12a2 through the second via 15.

[0060] Optionally, the isolation structure includes a first isolation portion 121 and a second isolation portion 122 stacked sequentially, with the orthographic projection of the first isolation portion 121 onto the array substrate located within the orthographic projection of the second isolation portion 122 onto the array substrate. Thus, the two ends of the second isolation portion 122 protrude compared to the sides of the first isolation portion 121, and this shape of the isolation structure 12 is also referred to as a pendant shape. The first isolation portion 121 and the second isolation portion 122 are made of different materials, and the etching rate of the second isolation portion 122 is lower than that of the first isolation portion 121. The material of the first isolation portion 121 includes a conductive material, specifically including at least one of aluminum (Al), aluminum alloys, and aluminum alloys including at least one of aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The second isolation portion 122 can be a single-layer structure or a multi-layer structure. If the second isolation portion 122 is a single-layer structure, the material of the second isolation portion 122 can include at least one of titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy. When the second isolation portion 122 has a multi-layer structure, one layer of the second isolation portion 122 is made of at least one of titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy or molybdenum-niobium alloy, and the other layer of the second isolation portion 122 may be made of conductive oxide or inorganic insulating material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0061] Optionally, the second electrode 133 is electrically connected to the first isolation section 121. After the second electrode 133 is connected to the isolation structure, the second electrode 133 is electrically connected to the power signal line in the array substrate 11 through the isolation structure 12 and the via in sequence, thereby realizing the supply of cathode voltage.

[0062] Continue to refer to Figure 3 The display panel also includes a pixel definition layer 16 disposed on the array substrate, and an isolation structure 12 disposed on the side of the pixel definition layer 16 away from the array substrate 11; the pixel definition layer 16 is provided with a plurality of first pixel openings and a plurality of second pixel openings; the first pixel openings are connected to the corresponding first isolation openings, and the second pixel openings are connected to the corresponding second isolation openings.

[0063] Specifically, the first pixel opening corresponds one-to-one with the first isolation opening and is interconnected with each other, and the second pixel opening corresponds one-to-one with the second isolation opening and is interconnected with each other.

[0064] The areas of the orthographic projections of the first pixel opening and the second pixel opening onto the array substrate 11 may be the same or different. The shapes of the orthographic projections of the pixel opening and the corresponding isolation opening 12 onto the array substrate 11 may be the same or different. Optionally, the orthographic projection of the first isolation opening onto the array substrate covers the orthographic projection of the first pixel opening onto the array substrate, and the orthographic projection of the second isolation opening onto the array substrate covers the orthographic projection of the second pixel opening onto the array substrate. The pixel defining layer 16 is made of an inorganic material, such as at least one inorganic insulating material selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON).

[0065] In one embodiment, the pixel definition layer 16 includes a plurality of sub-layers, including a first sub-layer and a second sub-layer stacked sequentially along a direction away from the array substrate 11, that is, the pixel definition layer 16 can adopt a dual-layer design.

[0066] For example, the first sublayer exhibits better film-forming properties than the second sublayer. That is, under the same thickness conditions, the first sublayer can better cover the stepped structure formed by the first electrode compared to the second sublayer, without causing cracks. Conversely, to achieve the same stepped coverage effect, the thickness of the first sublayer needs to be thinner than that of the second sublayer, meaning the thickness requirement for the first sublayer is relatively low, which is beneficial for product thinning. Furthermore, better film-forming properties are reflected in the better coverage of the formed film, making it denser and more effective at isolating moisture.

[0067] For example, the second sublayer has better etching resistance than the first sublayer. Since the side of the pixel definition layer 16 facing away from the array substrate 11 will be etched during the display panel manufacturing process, by selecting a material with stronger etching resistance as the second sublayer, the etching resistance of the pixel definition layer 16 can be improved, further enhancing the reliability of the display panel.

[0068] For example, the first sublayer and the second sublayer are made of different materials. For instance, the first sublayer is made of silicon nitride, and the second sublayer is made of silicon oxide.

[0069] For example, the thickness of the first sublayer is greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms. For instance, the thickness of the first sublayer is 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, 5000 angstroms, etc.

[0070] For example, the thickness of the second sublayer is greater than or equal to 500 angstroms and less than or equal to 3000 angstroms. For instance, the thickness of the second sublayer is 500 angstroms, 1000 angstroms, 2000 angstroms, 3000 angstroms, etc.

[0071] Optionally, the first light-emitting device 13a and the second light-emitting device 13b further include a light-emitting layer 132; the light-emitting layer 132 of the first light-emitting device is disposed in the corresponding first pixel opening, and the light-emitting layer 132 of the second light-emitting device is disposed in the corresponding second pixel opening.

[0072] Specifically, a first electrode 131 is disposed on the array substrate 11, and a pixel definition layer 16 covers the end of the first electrode 131. A pixel opening is provided on the pixel definition layer 16, through which the first electrode 131 is exposed. The light-emitting layers 132 of the first light-emitting device 13a and the second light-emitting device 13b cover the sidewall of the pixel opening of the pixel definition layer 16 and the side of the pixel definition layer 16 facing away from the array substrate 11. Each light-emitting layer 132 is located within the pixel opening and is in contact with the first electrode 131.

[0073] Figure 4a This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 4b This is a partial cross-sectional view of another display panel provided in an embodiment of the present invention. (See reference) Figure 4a and Figure 4b Optionally, multiple subpixels are arranged in multiple pixel rows along the column direction in the display area AA of the display panel, and the multiple pixel rows include multiple odd rows and multiple even rows; The first light-emitting device 13a of the same sub-pixel is located in the corresponding odd-numbered row, and the second light-emitting device 13b is located in the even-numbered row adjacent to the odd-numbered row.

[0074] The second electrodes 133 of multiple first light-emitting devices 13a located in the same row are electrically connected, and the second electrodes 133 of multiple second light-emitting devices 13b located in the same row are electrically connected.

[0075] Specifically, in this embodiment, a complete sub-pixel is not located within a single row, but rather spans vertically across adjacent odd and even rows. Specifically, for the k-th sub-pixel (k=1,2,3…), its first light-emitting device 13a is located in row (2k-1) (odd row), and its second light-emitting device 13b is located in row 2k (even row). The two light-emitting devices of the same sub-pixel are vertically aligned in the column direction (i.e., located in the same column).

[0076] Within the same pair of odd and even rows (e.g., row 1 and row 2), multiple sub-pixels can be arranged along the row direction (horizontal direction), with each sub-pixel occupying a different column. For example, the first light-emitting device in row 1, column 1 and the second light-emitting device in row 2, column 1 together form the sub-pixel of column 1; the first light-emitting device in row 1, column 2 and the second light-emitting device in row 2, column 2 together form the sub-pixel of column 2, and so on. Therefore, the sub-pixel index is determined by the column coordinates, while the row coordinates are fixed to the pair of odd and even rows.

[0077] All first light-emitting devices 13a located in the same odd-numbered row have their second electrodes 133 located in corresponding first isolation openings 12a1 and connected to the first isolation structure 12b1, thereby achieving mutual electrical connection of all second electrodes within the row through the first isolation structure 12b1; the first isolation structure 12b1 is electrically connected to the first power signal line VSS1 disposed on the array substrate through the first via 14. Similarly, all second light-emitting devices 13b located in the same even-numbered row have their second electrodes 133 connected to the second isolation structure 12b2 to achieve intra-row communication, and are electrically connected to the second power signal line VSS2 through the second via 15.

[0078] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 5 As shown, optionally, the non-display area NAA includes a lower border area adjacent to the display area AA; the lower border area is provided with a first signal transmission line TS1 and a second signal transmission line TS2; The first power signal line VSS1 is electrically connected to the first signal transmission line TS1 in the lower frame area, and the first signal transmission line TS1 is electrically connected to the first power management module 17. The second power signal line VSS2 is electrically connected to the second signal transmission line TS2 in the lower frame area, and the second signal transmission line TS2 is electrically connected to the second power management module 18.

[0079] Optionally, continue to refer to Figure 5 The display area AA is provided with a first power signal line VSS1 and a second power signal line VSS2 in a mesh-like connection structure; The first power signal line VSS1 includes multiple first signal lines VSS11 extending along the first direction X and spaced apart along the second direction Y, and multiple second signal lines VSS12 extending along the second direction Y and spaced apart along the first direction X. The first signal lines VSS11 and the second signal lines VSS12 are electrically connected, and the first direction and the second direction intersect.

[0080] The second power signal line VSS2 includes multiple third signal lines VSS21 extending along the first direction X and spaced apart along the second direction Y, and multiple fourth signal lines VSS22 extending along the second direction Y and spaced apart along the first direction X. The third signal lines VSS21 and the fourth signal lines VSS22 are electrically connected.

[0081] Because the first power signal line VSS1 and the second power signal line VSS2 are connected in a mesh structure, the impedance of the first power signal line VSS1 and the second power signal line VSS2 in the display area AA is significantly reduced. This reduces the power consumption of the first power signal on the first power signal line VSS1 and the second power signal on the second power signal line VSS2 during transmission, further reducing the overall power consumption of the display panel. On the other hand, by reducing the impedance of the first power signal line VSS1 and the second power signal line VSS2 in the display area, the voltage difference between the first power signal and the second power signal in different areas of the display area can be reduced, resulting in more uniform brightness of the display panel and further improving the display quality.

[0082] Optionally, the first signal line VSS11 and the second signal line VSS12 are disposed on different conductive layers and electrically connected through a fourth via; the third signal line VSS21 and the fourth signal line VSS22 are disposed on different conductive layers and electrically connected through a fifth via; the first signal line VSS11 and the third signal line VSS21 are disposed on the same conductive layer or different conductive layers; the second signal line VSS12 and the fourth signal line VSS22 are disposed on the same conductive layer or different conductive layers.

[0083] Figure 6 This is a partial cross-sectional view of another display panel provided in an embodiment of the present invention. For example... Figure 6 As shown, optionally, the lower border area of ​​the display panel includes a virtual light-emitting area NAA1 and a dam area NAA2 that are adjacent to the display area AA, with the virtual light-emitting area located between the display area AA and the dam area.

[0084] The virtual light-emitting area NAA1 is provided with multiple virtual light-emitting devices 13c; each virtual light-emitting device 13c includes a virtual cathode 134; the isolation structure 12 also includes a third isolation structure 12b3, which encloses multiple third isolation openings 12a3, with the virtual cathode 134 located in the corresponding third isolation opening 12a3 and connected to the third isolation structure 12b3; the third isolation structure 12b3 is electrically connected to the second isolation structure 12b2 corresponding to the second light-emitting device located in the last row of the display area AA; the second signal transmission line TS2 is electrically connected to the third isolation structure 12b3 near the dam area, and provides voltage to the second electrode 133 of the second light-emitting device 13b through the third isolation structure 12b3.

[0085] Specifically, the virtual light-emitting device is located in the lower border area, and its structure is similar to that of the real light-emitting devices (i.e., the first light-emitting device 13a and the second light-emitting device 13b) in the display area, including at least one virtual cathode. However, the virtual light-emitting device 13c does not participate in the actual image display; its main function is to assist in achieving process uniformity and providing electrical connection paths.

[0086] The second signal transmission line TS2 is electrically connected to the third isolation structure 12b3 near the dam area, transmitting voltage (e.g., low or high level) to the virtual cathode 134 within the third isolation opening 12a3. Then, through the continuous conductivity of the third isolation structure 12b3, the voltage is sequentially transmitted inwards to other third isolation openings 12a3, ultimately reaching the second isolation opening 12a2 at the edge of the display area AA, thereby providing a cathode potential for the second light-emitting device 13b within the display area AA. This remote feeding method avoids the complex direct drilling connection between the signal transmission line and the interior of the display area AA, simplifying the wiring of the lower bezel.

[0087] Optionally, the second signal transmission line TS2 is electrically connected to the third isolation structure 12b3 near the dam area NAA2 through the third via 19; the virtual cathode 134 is disposed on the same layer as the second electrode 133.

[0088] Specifically, the second signal transmission line TS2 is disposed on the driving circuit layer 112 of the array substrate 11, while the third isolation opening 12a3 and the virtual cathode inside it are located on the light-emitting device layer above the array substrate 11. In order to achieve electrical connection, a third via 19 needs to be opened between the layers so that the second signal transmission line TS2 can be electrically connected to the third isolation structure 12b3 near the dam area NAA2 through the third via 19.

[0089] The virtual cathode and the second electrode 133 of the real light-emitting device in the display area AA are fabricated using the same photolithography or vapor deposition process and are located on the same film layer. With this setup, no additional mask or process steps are required, and the virtual cathode can be formed simultaneously with the second electrode, saving manufacturing costs.

[0090] Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 6 and Figure 7 As shown, optionally, the first signal transmission line TS1 includes a first transmission structure 31, and the second signal transmission line TS2 includes a second transmission structure 32; in the lower frame area, the second transmission structure 32 includes a plurality of first structures 321 arranged at intervals along the first direction X.

[0091] The first transmission structure 31 includes a second structure 311 and a plurality of third structures 312, wherein the third structure 312 is located between two adjacent first structures 321 in the first direction X. The first structure 321 is electrically connected to the third isolation opening 12a3 so that the first structure 321 is electrically connected to the second power signal line VSS2. The second structure 311 extends along the first direction X and is connected to the first power signal line VSS1 and the third structure 312; wherein the first direction X intersects with the direction perpendicular to the array substrate 11.

[0092] Specifically, the first transmission structure 31 is used to transmit the voltage provided by the first power management module 17 to the first power signal line VSS1 in the display area. The second transmission structure 32 is used to transmit the voltage provided by the second power management module 18 to the second power signal line VSS2 in the display area.

[0093] Multiple first structures 321 are arranged at certain intervals from left to right (or from right to left) within the lower border area. A second structure 311 is the main body of the first transmission structure 31, extending continuously along the first direction X, resembling a bus. A third structure 312 is a branch structure extending from the second structure 311 into the gaps between the first structures 321. Each third structure 312 is positioned precisely within the gap between two adjacent first structures 321. That is, the first structures 321 and third structures 312 are arranged alternately along the first direction X.

[0094] The first transmission structure 31 and the second transmission structure 32 are on different layers.

[0095] The third isolation structure 12b3 includes a fourth isolation structure 12b31 as a conductive line. The fourth isolation structure 12b31 has no isolation opening. The orthogonal projections of the first transmission structure 31 and the second transmission structure 32 on the substrate 111 are located within the orthogonal projection of the fourth isolation structure 12b31 on the substrate 111.

[0096] The width of the fourth isolation structure 12b31 is greater than the sum of the widths of the first transmission structure 31 and the second transmission structure 32. The orthographic projections of the first transmission structure 31 and the second transmission structure 32 on the substrate 111 do not overlap to reduce coupling effects.

[0097] Each of the first structures 321 is electrically connected to the fourth isolation structure 12b31. As mentioned above, the third isolation structure 12b3 is electrically connected to (or integrated with) the second isolation structure 12b2 corresponding to the second light-emitting device in the display area AA. Therefore, through the electrical connection between the first structure 321 and the fourth isolation structure 12b31, the voltage of the second transmission structure 32 can be transmitted to the entire second power signal line VSS2 via the fourth isolation structure 12b31, the third isolation structure 12b3, and the virtual cathode 134.

[0098] The second structure 311, acting as a bus, is designed in width and thickness to carry the total current of the first light-emitting devices 13a across the entire screen. Specifically, the width of the second structure 311 is greater than the line width of the first power signal line VSS1 to ensure lower resistance and sufficient current carrying capacity. Simultaneously, the width of the second structure 311 is less than the total width of the fourth isolation structure 12b31 to avoid unnecessary coupling with other structures or occupying excessive area. Multiple third structures 312 act as multiple parallel current injection points, evenly distributed horizontally, distributing current from the bus to different areas of the first power signal line VSS1 grid, thereby reducing in-plane voltage drop and ensuring consistent cathode potentials for the first light-emitting devices 13a on the left, center, and right sides of the display area.

[0099] Optionally, the first structure 321 includes a first part a1 and a second part a2. The first part a1 extends along a first direction X, and the second part a2 is disposed on the side of the first part a1 away from the second structure 311 and extends along a second direction Y.

[0100] In this embodiment, a one-to-one correspondence is established between odd-numbered columns of sub-pixels and the third structure 312, and between even-numbered columns of sub-pixels and the first structure 321. Specifically, the first third structure 312 corresponds one-to-one with the first column of sub-pixels from left to right, and provides a cathode voltage to the first light-emitting device 13a of the sub-pixels in that column through the first power signal line VSS1; the first first structure 321 corresponds one-to-one with the second column of sub-pixels, and provides a cathode voltage to the second light-emitting device 13b of the sub-pixels in that column through the second power signal line VSS2; the second third structure 312 corresponds one-to-one with the third column of sub-pixels; the second first structure 321 corresponds one-to-one with the fourth column of sub-pixels; and so on, until all sub-pixel columns are covered.

[0101] Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 8 As shown, optionally, the pixel circuit 20 includes a driving module 110, a data writing module 120, a coupling module 130, and a light emission control module 140; The first end of the data writing module 120 and the coupling module 130 are connected to the first node N1, and the second end of the coupling module 130 is connected to the control terminal of the drive module 110 to the second node N2. The data writing module 120 is used to transmit the data voltage Vdata to the first node N1 according to the signal on the second scan line, and write the voltage information associated with the data voltage Vdata to the control terminal of the drive module 110 through the coupling module 130. The first electrodes of the first light-emitting device 13a and the second light-emitting device 13b are connected to the third node N3; The driving module 110 and the light-emitting control module 140 are connected in series between the positive power signal line VDD and the third node N3. The light-emitting control module 140 is used to control the first light-emitting device 13a or the second light-emitting device 13b to emit light according to the driving current output by the driving module 110 based on the signal on the first light-emitting control signal line EM1.

[0102] Continue to refer to Figure 8 Optionally, the pixel circuit 20 further includes a compensation module 150, which is connected between the control terminal and the first terminal of the driving module 110. The compensation module 150 is used to compensate the threshold voltage of the driving module 110 according to the signal on the second scan line S2. Optionally, the pixel circuit 20 further includes a first initialization module 160, which is connected between the first initialization signal line Vref1 and the control terminal of the driving module 110. The first initialization module 160 is used to transmit the first initialization voltage on the first initialization line Vref1 to the control terminal of the driving module 110 according to the signal on the first scan line S1. Optionally, the pixel circuit 20 further includes a second initialization module 170, which is connected between the second initialization signal line Vref2 and the third node N3. The second initialization module 170 is used to transmit the second initialization voltage on the second initialization signal line Vref2 to the third node N3 according to the signal on the second light emission control signal line EM2.

[0103] Optionally, the pixel circuit 20 further includes a third initialization module 180, which is connected between the third initialization signal line Vref3 and the first node N1. The third initialization module 180 is used to transmit the third initialization voltage on the third initialization signal line Vref3 to the first node N1 according to the signal on the first light emission control signal line EM1.

[0104] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 9 As shown, optionally, the coupling module 130 includes a first capacitor C1 and a second capacitor C2; the first end of the first capacitor C1 serves as the first end of the coupling module 130, the second end of the first capacitor C1 and the first end of the second capacitor C2 are connected to the fourth node N4, and the second end of the second capacitor C2 serves as the second end of the coupling module 130.

[0105] Optionally, the pixel circuit 20 further includes a fourth initialization module 190, which is connected between the third initialization signal line Vref3 and the fourth node N4. The fourth initialization module 190 is used to transmit the third initialization voltage on the third initialization signal line Vref3 to the fourth node N4 according to the signal on the second light emission control signal line EM2. Optionally, the positive power signal line VDD is multiplexed as the third initialization signal line Vref3, and the positive power voltage transmitted on the positive power signal line VDD is multiplexed as the third initialization voltage.

[0106] Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 10 As shown, the driving module 110 includes a driving transistor DTFT, the data writing module 120 includes a data writing transistor M1, the light emission control module 140 includes a light emission control transistor M2, the compensation module 150 includes a compensation transistor M3, the first initialization module 160 includes a first initialization transistor M4, the second initialization module 170 includes a second initialization transistor M5, the third initialization module 180 includes a third initialization transistor M6, and the fourth initialization module 190 includes a fourth initialization transistor M7.

[0107] Optionally, the compensation transistor M3, the first initialization transistor M4, and the fourth initialization transistor M7 are all two transistors connected in series.

[0108] by Figure 10 Taking the structure shown as an example, the driving process of the pixel circuit 20 may include: In the first initialization stage, the signal on the first scan line S1 is at a low potential, which controls the first initialization transistor M4 to turn on, and provides the first initialization voltage on the first initialization signal line Vref1 to the gate of the driving transistor DTFT, thereby initializing the gate of the driving transistor DTFT.

[0109] During the data writing phase, the signal S2 on the second scan line S2 is at a low potential, which turns on both the control data writing transistor M2 and the compensation transistor M3. The data voltage Vdata is transmitted to the gate of the driving transistor DTFT through the data writing transistor M2, the driving transistor DTFT and the threshold compensation transistor M3 until the driving transistor DTFT is turned off, thus completing the data writing.

[0110] In the second initialization phase, the signal on the second light-emitting control signal line EM2 is at a low potential, controlling both the second initialization transistor M5 and the fourth initialization transistor M7 to conduct. The second initialization voltage on the second initialization signal line Vref2 is transmitted to the third node N3, realizing the initialization of the anode of the first light-emitting device 13a and the anode of the second light-emitting device 13b. Simultaneously, the third initialization voltage on the third initialization signal line Vref3 is transmitted to the fourth node N4, realizing the initialization of the fourth node N4. For example, this second initialization phase can be set at any time period before the light-emitting phase in the display frame.

[0111] During the light-emitting stage, the signal on the first light-emitting control signal line EM1 is at a low potential, and both the light-emitting control transistor M2 and the third initialization transistor M6 are turned on. The driving transistor DTFT generates a driving current according to the potential of its gate and provides it to the third node N3. In this stage, if the first power signal line VSS1 provides a first level and the second power signal line VSS2 provides a second level, the driving current can drive the first light-emitting device 13a to work, and the second light-emitting device 13b is turned off and does not emit light; if the first power signal line VSS1 provides a second level and the second power signal line VSS2 provides a first level, the driving current drives the second light-emitting device 13b to work, and the first light-emitting device 13a is turned off and does not emit light.

[0112] The display panel provided in this embodiment of the invention drives the first light-emitting device 13a and the second light-emitting device 13b in the same sub-pixel through the same pixel circuit 20. By simply changing the levels of the first power signal line VSS1 and the second power signal line VSS2, the normal display mode and the privacy display mode can be switched through timing selection, thereby achieving an active privacy effect. Since no additional transistors are needed in the pixel circuit, the layout area of ​​the pixel circuit is reduced, thus achieving a high pixel density active privacy display. Simultaneously, combined with the optimized signal transmission line layout and virtual light-emitting device design in the lower bezel area, the width of the lower bezel is effectively reduced, achieving a narrow bezel effect.

[0113] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention, which has corresponding beneficial effects.

[0114] The display devices in this application include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0115] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: A first power signal line, a second power signal line, and multiple sub-pixels; The sub-pixels are arranged in an array, and each sub-pixel includes a first light-emitting device and a second light-emitting device; The first electrodes of the first light-emitting device and the second light-emitting device of the same sub-pixel are electrically connected; The second electrode of the first light-emitting device is connected to the first power signal line, and the second electrode of the second light-emitting device is connected to the second power signal line. The first power signal line and the second power signal line are insulated from each other.

2. The display panel according to claim 1, characterized in that, It also includes an array substrate and an isolation structure; The isolation structure is located on one side of the array substrate. The isolation structure includes a first isolation structure and a second isolation structure, and the first isolation structure and the second isolation structure are insulated from each other. The first isolation structure encloses and forms a plurality of first isolation openings, and the second isolation structure encloses and forms a plurality of second isolation openings; The second electrode of the first light-emitting device is located in the corresponding first isolation opening and overlaps with the first isolation structure; the second electrode of the second light-emitting device is located in the corresponding second isolation opening and overlaps with the second isolation structure. The first power signal line and the second power signal line are disposed on the array substrate and are electrically connected to the first isolation opening and the second isolation opening, respectively. Preferably, the multiple sub-pixels are arranged in the column direction in the display area of ​​the display panel to form multiple pixel rows, and the multiple pixel rows include multiple odd-numbered rows and multiple even-numbered rows; The first light-emitting device of the same sub-pixel is located in the corresponding odd-numbered row, and the second light-emitting device is located in the even-numbered row adjacent to the odd-numbered row; Preferably, the second electrodes of a plurality of first light-emitting devices located in the same row are electrically connected, and the second electrodes of a plurality of second light-emitting devices located in the same row are electrically connected.

3. The display panel according to claim 1, characterized in that, The first electrode of the first light-emitting device and the first electrode of the second light-emitting device are disposed in the same layer and electrically connected as one unit; Preferably, the display panel further includes an array substrate, which includes a substrate, a driving circuit layer, and a planarization layer; The driving circuit layer is disposed on one side of the substrate; The planarization layer is disposed on the side of the driving circuit layer away from the substrate; The first power signal line and the second power signal line are disposed on the driving circuit layer; Preferably, the driving circuit layer includes multiple conductive layers, and the first power signal line and the second power signal line are disposed in at least one of the multiple conductive layers.

4. The display panel according to claim 1, characterized in that, The display panel further includes a display area and a lower border area adjacent to the display area; the lower border area is provided with a first signal transmission line and a second signal transmission line; The first power signal line is electrically connected to the first signal transmission line in the lower frame area, and the first signal transmission line is electrically connected to the first power management module. The second power signal line is electrically connected to the second signal transmission line in the lower frame area, and the second signal transmission line is electrically connected to the second power management module; Preferably, the lower border area of ​​the display panel includes a virtual light-emitting area and a dam area disposed adjacent to the display area; the virtual light-emitting area is located between the display area and the dam area; The virtual light-emitting area is provided with multiple virtual light-emitting devices; each virtual light-emitting device includes a virtual cathode; the isolation structure also includes a third isolation structure, which encloses and forms multiple third isolation openings, and the virtual cathode is located in the corresponding third isolation opening and overlaps with the third isolation structure. Preferably, the third isolation structure is electrically connected to the second isolation structure corresponding to the second light-emitting device located in the last row of the display area; the second signal transmission line is electrically connected to the third isolation structure near the dam area; 5. The display panel according to claim 2, characterized in that, The display panel further includes a pixel definition layer disposed on the array substrate, and the isolation structure is disposed on the side of the pixel definition layer away from the array substrate; The pixel definition layer is provided with multiple first pixel openings and multiple second pixel openings; The first pixel opening is connected to the corresponding first isolation opening, and the second pixel opening is connected to the corresponding second isolation opening; Preferably, the orthographic projection of the first isolation opening on the array substrate covers the orthographic projection of the first pixel opening on the array substrate, and the orthographic projection of the second isolation opening on the array substrate covers the orthographic projection of the second pixel opening on the array substrate; Preferably, the first light-emitting device and the second light-emitting device further include a light-emitting layer; The light-emitting layer of the first light-emitting device is disposed within the corresponding first pixel opening, and the light-emitting layer of the second light-emitting device is disposed within the corresponding second pixel opening.

6. The display panel according to claim 1, characterized in that, The display panel includes a display area, and the display area is provided with a first power signal line and a second power signal line in a mesh-like connection structure; The first power signal line includes a plurality of first signal lines extending along a first direction and spaced apart along a second direction, and a plurality of second signal lines extending along the second direction and spaced apart along the first direction. The first signal lines and the second signal lines are electrically connected, and the first direction and the second direction intersect. The second power signal line includes a plurality of third signal lines extending along a first direction and spaced apart along a second direction, and a plurality of fourth signal lines extending along the second direction and spaced apart along the first direction, wherein the third signal lines are electrically connected to the fourth signal lines. Preferably, the first signal line and the second signal line are disposed on different conductive layers and are electrically connected through a fourth via; Preferably, the third signal line and the fourth signal line are disposed on different conductive layers and are electrically connected through a fifth via; Preferably, the first signal line and the third signal line are disposed on the same conductive layer or on different conductive layers; Preferably, the second signal line and the fourth signal line are disposed on the same conductive layer or on different conductive layers; Preferably, the first direction is perpendicular to the second direction.

7. The display panel according to claim 1, characterized in that, The sub-pixel also includes a pixel circuit; The first electrodes of the first light-emitting device and the second light-emitting device corresponding to the same sub-pixel are electrically connected to the same pixel circuit; The pixel circuit includes a driving module, a data writing module, a coupling module, and a light emission control module; The data writing module is connected to the first end of the coupling module at the first node, and the second end of the coupling module is connected to the control terminal of the driving module at the second node; the data writing module is used to transmit data voltage to the first node according to the signal on the second scan line, and write voltage information associated with the data voltage to the control terminal of the driving module through the coupling module; The first electrodes of the first light-emitting device and the second light-emitting device are connected to the third node; The driving module and the light-emitting control module are connected in series between the positive power signal line and the third node. The light-emitting control module is used to control the first light-emitting device or the second light-emitting device to emit light according to the driving current output by the driving module based on the signal on the first light-emitting control signal line. Preferably, in normal display mode, the first power signal line provides a first level and the second power signal line provides a second level, so that the pixel circuit drives the first light-emitting device to emit light and turns off the second light-emitting device; In privacy display mode, the first power signal line provides the second level, and the second power signal line provides the first level, so that the pixel circuit drives the second light-emitting device to emit light and turns off the first light-emitting device.

8. The display panel according to claim 7, characterized in that, The pixel circuit also includes a compensation module, which is connected between the control terminal and the first terminal of the driving module. The compensation module is used to compensate the threshold voltage of the driving module according to the signal on the second scan line. The pixel circuit further includes a first initialization module, which is connected between the first initialization signal line and the control terminal of the driving module. The first initialization module is used to transmit the first initialization voltage on the first initialization line to the control terminal of the driving module according to the signal on the first scan line. Preferably, the pixel circuit further includes a second initialization module, which is connected between the second initialization signal line and the third node. The second initialization module is used to transmit the second initialization voltage on the second initialization signal line to the third node according to the signal on the second light emission control signal line. Preferably, the pixel circuit further includes a third initialization module, which is connected between the third initialization signal line and the first node. The third initialization module is used to transmit the third initialization voltage on the third initialization signal line to the first node according to the signal on the first light emission control signal line.

9. The display panel according to claim 7, characterized in that, The coupling module includes a first capacitor and a second capacitor; The first end of the first capacitor serves as the first end of the coupling module, the second end of the first capacitor is connected to the first end of the second capacitor at the fourth node, and the second end of the second capacitor serves as the second end of the coupling module. Preferably, the pixel circuit further includes a fourth initialization module, which is connected between the third initialization signal line and the fourth node. The fourth initialization module is used to transmit the third initialization voltage on the third initialization signal line to the fourth node according to the signal on the second light emission control signal line. Preferably, the positive power signal line is multiplexed as the third initialization signal line, and the positive power voltage transmitted on the positive power signal line is multiplexed as the third initialization voltage.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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