Display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device. The display panel comprises at least one pixel circuit, the pixel circuit comprising a first transistor connected with a first electrode of a light emitting device; the display panel further comprises a substrate, an active layer, a first conductive layer and a fifth conductive layer; the active layer is arranged on one side of the substrate, and the active layer comprises a first active region of the first transistor; the first conductive layer is arranged on a side of the active layer away from the substrate, and the first conductive layer comprises a first gate electrode, and a projection of the first gate electrode on the active layer at least partially covers the first active region; the fifth conductive layer is arranged on a side of the first conductive layer away from the substrate, and the fifth conductive layer comprises a first initialization signal line, and the first initialization signal line extends along a first direction; the first initialization signal line is connected with one end of the first active region; and the first direction is a column direction in which the pixel circuits are arranged. The PPI of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In existing technologies, the pixel density (Pixels Per Inch, PPI) of display panels is relatively low, which cannot meet the needs of users. Summary of the Invention

[0003] The present invention provides a display panel and a display device to improve the pixel density of the display panel.

[0004] According to one aspect of the present invention, a display panel is provided, comprising at least one pixel circuit, the pixel circuit including a first transistor connected to a first electrode of a light-emitting device; the display panel further comprising: Substrate; An active layer is disposed on one side of the substrate, and the active layer includes a first active region of the first transistor; A first conductive layer is disposed on the side of the active layer away from the substrate. The first conductive layer includes a first gate, and the orthogonal projection of the first gate onto the active layer at least partially covers the first active region. A fifth conductive layer is disposed on the side of the first conductive layer away from the substrate. The fifth conductive layer includes a first initialization signal line that extends along a first direction. The first initialization signal line is connected to one end of the first active region. The first direction is the column direction of the pixel circuit arrangement.

[0005] According to another aspect of the present invention, a display device is provided, comprising the display panel described in the first aspect.

[0006] The technical solution of this invention, by setting the first initialization signal line to extend along the first direction, can save the space occupied by the first initialization signal line along the second direction, thereby helping to improve the PPI of the display panel.

[0007] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of an active layer structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of an active layer and a first conductive layer provided in an embodiment of the present invention; Figure 4 A schematic diagram of an active layer, a first conductive layer, and a second conductive layer provided in an embodiment of the present invention; Figure 5 A schematic diagram of an active layer, a first conductive layer, a second conductive layer, and a third conductive layer provided in an embodiment of the present invention; Figure 6 A schematic diagram of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a first type of via provided for an embodiment of the present invention; Figure 7 A schematic diagram of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a first type of via, and a fourth conductive layer provided for an embodiment of the present invention; Figure 8 A schematic diagram of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a first type of via, a fourth conductive layer, and a second type of via provided for an embodiment of the present invention; Figure 9 A schematic diagram of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a first type of via, a fourth conductive layer, a second type of via, and a fifth conductive layer provided for an embodiment of the present invention; Figure 10 A partial schematic diagram of a display panel provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along AA' according to an embodiment of the present invention; Figure 12 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along BB' according to an embodiment of the present invention; Figure 13 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along CC' according to an embodiment of the present invention; Figure 14This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along DD' according to an embodiment of the present invention; Figure 15 This is a schematic diagram of an active layer, a fifth conductive layer, and a third type of via provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of an active layer, a fifth conductive layer, a third type of via, and an anode layer provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along EE' according to an embodiment of the present invention; Figure 18 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along FF' according to an embodiment of the present invention; Figure 19 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along JJ' according to an embodiment of the present invention; Figure 20 for Figure 5 A partially enlarged schematic diagram of one of the display panels is provided; Figure 21 A partially enlarged schematic diagram of another partial display panel provided in an embodiment of the present invention; Figure 22 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along GG' according to an embodiment of the present invention; Figure 23 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along HH' according to an embodiment of the present invention; Figure 24 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along II' according to an embodiment of the present invention; Figure 25 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0011] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0012] In existing technologies, the pixel circuitry within a display panel comprises multiple transistors, which require multiple scan signal lines to transmit different scan signals. This results in limited layout space on the display panel, making it impossible to achieve a high PPI.

[0013] To address the aforementioned technical problems, embodiments of the present invention provide a display panel. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of an active layer structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of an active layer and a first conductive layer provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of an active layer, a first conductive layer, and a second conductive layer provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of an active layer, a first conductive layer, a second conductive layer, and a third conductive layer provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a first type of via provided in an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a first type of via, and a fourth conductive layer provided in an embodiment of the present invention. Figure 8 This invention provides a schematic diagram of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a first type of via, a fourth conductive layer, and a second type of via, as provided in an embodiment of the invention. Figure 9 This is a schematic diagram of the structure of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a first type of via, a fourth conductive layer, a second type of via, and a fifth conductive layer provided in an embodiment of the present invention. Figure 10 This is a partial schematic diagram of a display panel provided in an embodiment of the present invention. Figures 1 to 10As shown, the display panel includes at least one pixel circuit 100, the pixel circuit 100 includes a first transistor T1, the first transistor T1 is connected to the first electrode A of the light-emitting device OLED; the display panel also includes a substrate ( Figures 1 to 10 (Not shown in the image), active layer 10, first conductive layer M1, and fifth conductive layer M5. Active layer 10 is disposed on one side of the substrate and includes a first active region 11 of a first transistor T1. First conductive layer M1 is disposed on the side of active layer 10 away from the substrate and includes a first gate M11. The orthogonal projection of the first gate M11 onto active layer 10 at least partially covers the first active region 11. Fifth conductive layer M5 is disposed on the side of first conductive layer M1 away from the substrate and includes a first initialization signal line VREF1 extending along a first direction Y. The first initialization signal line VREF1 is connected to one end of the first active region 11; the first direction Y is the column direction of the pixel circuit 100 arrangement.

[0014] Specifically, such as Figure 1 As shown, the first electrode A of the OLED can be the anode of the OLED. The first initialization signal line VREF1 can provide a first initialization signal. The first initialization signal is a signal with a fixed voltage. The material of the first active layer 10 can be low-temperature polysilicon (LTPS), and the first conductive layer M1 and the fifth conductive layer M5 can be metal layers, used to form devices in the pixel circuit 100 and the connection lines between devices. Each active region can include a source region, a channel region, and a drain region, with the channel region disposed between the source region and the drain region. The orthogonal projection of the gate of each transistor onto the substrate covers the corresponding channel region to form the transistor. In the display panel, the orthogonal projection of the first gate M11 onto the active layer 10 covers the channel region of the first active region 11 to form the first transistor T1. One end of the first active region 11 can be the first electrode of the first transistor T1. When the first initialization signal line VREF1 is connected to one end of the first active region 11, the first initialization signal can be provided to the first electrode of the first transistor T1. The other end of the first active region 11 can be the second electrode of the first transistor T1. The second electrode of the first transistor T1 is connected to the first electrode A of the OLED light-emitting device. During the initialization phase of the pixel circuit 100, the first transistor T1 is turned on. The first transistor T1 provides a first initialization signal to the first electrode A of the OLED, initializing the first electrode A of the OLED and improving the image retention phenomenon of the display panel. The first initialization signal line VREF1 extends along the first direction Y, which can save the space occupied by the first initialization signal line VREF1 along the second direction X (that is, the row direction of the pixel circuit 100), thereby helping to improve the PPI of the display panel.

[0015] The technical solution of this embodiment, by setting the first initialization signal line to extend along the first direction, can save the space occupied by the first initialization signal line along the second direction, thereby helping to improve the PPI of the display panel.

[0016] Continue to refer to Figures 1 to 10 The display panel includes a plurality of sub-pixel units 110 arranged along the second direction X. Each sub-pixel unit includes a first pixel circuit 101 and a second pixel circuit 102 arranged and adjacent to each other along the second direction X. The fifth conductive layer M5 is provided with at least two first initialization signal lines VREF1. Each first initialization signal line VREF1 is disposed between the first pixel circuit 101 and the second pixel circuit 102 in a sub-pixel unit 110. The second direction X is the row direction in which the pixel circuits 100 are arranged.

[0017] Specifically, a row of pixel circuits 100 can be divided into multiple sub-pixel units 110. Each sub-pixel unit 110 includes a first pixel circuit 101 and a second pixel circuit 102 arranged along the second direction X. The first pixel circuit 101 and the second pixel circuit 102 are arranged adjacent to each other. At the same time, the first pixel circuit 101 and the second pixel circuit 102 are arranged alternately along the second direction X. A first initialization signal line VREF1 is disposed between the first pixel circuit 101 and the second pixel circuit 102 within the same sub-pixel unit 110. The first pixel circuit 101 and the second pixel circuit 102 can share the same first initialization signal line VREF1, thereby reducing the number of first initialization signal lines VREF1 required and further saving the space occupied by the first initialization signal lines VREF1, which is beneficial to improving the PPI of the display panel. Moreover, at least two first initialization signal lines VREF1 are arranged along the second direction X. Each first initialization signal line VREF1 is set within a sub-pixel unit 110, which can improve the consistency of impedance voltage drop on different first initialization signal lines VREF1, thereby improving the consistency of the first initialization signal within different sub-pixel units 110.

[0018] Continue to refer to Figures 1 to 10 The first pixel circuit 101 and the second pixel circuit 102 are symmetrical about the first initialization signal line VREF1.

[0019] Specifically, the first pixel circuit 101 and the second pixel circuit 102 are symmetrical about the first initialization signal line VREF1, meaning the layout of the first pixel circuit 101 and the layout of the second pixel circuit 102 are symmetrical about the first initialization signal line VREF1. At this time, the layout of the first pixel circuit 101 and the layout of the second pixel circuit 102 are a left-right mirror structure. When the first initialization signal line VREF1 is positioned between the first pixel circuit 101 and the second pixel circuit 102, the connection lines between the first transistor T1 in the first pixel circuit 101 and the first transistor T1 in the second pixel circuit 102 and the first initialization signal line VREF1 can be simplified, which helps save layout space and thus improves the PPI of the display panel. For example, as shown... Figures 1 to 10 As shown, the first active region 11 in the first pixel circuit 101 and the first active region 11 in the second pixel circuit 102 are symmetrical about the first initialization signal line VREF1. At this time, one end of the first active region 11 in the first pixel circuit 101 and one end of the first active region 11 in the second pixel circuit 102 are connected in contact, and the area of ​​contact connection is designated as the first connection active region. The first initialization signal line VREF1 is connected to the first connection active region, allowing the first initialization signal line VREF1 to be connected to the first electrode of the first transistor T1 in the first pixel circuit 101 and the first electrode of the first transistor T1 in the second pixel circuit 102. This simplifies the connection line between the first initialization signal line VREF1 and the pixel circuit 100, saving layout space and thus improving the PPI of the display panel.

[0020] Continue to refer to Figures 1 to 10 The display panel also includes a third conductive layer M3, which is disposed between the first conductive layer M1 and the fifth conductive layer M5. The third conductive layer M3 includes a first initialization signal structure VR1, which is connected to the first initialization signal line VREF1.

[0021] Specifically, the third conductive layer M3 can be a metal layer. For example, when the display panel includes a low-temperature polycrystalline oxide (LTPO) array substrate, the third conductive layer M3 can be a GATO layer, disposed on the side of the oxide semiconductor layer away from the substrate. The first initialization signal structure VR1 is connected to the first initialization signal line VREF1, such that the first initialization signal structure VR1 is part of the first initialization signal line VREF1. The first initialization signal structure VR1 can be connected in parallel with the first initialization signal line VREF1, thereby reducing the impedance voltage drop of the first initialization signal and further improving the consistency of the first initialization signal received by different pixel circuits 100.

[0022] Continue to refer to Figures 1 to 10 The first initialization signal structure VR1 extends along the second direction X. When the first initialization signal structure VR1 is connected to the first initialization signal line VREF1, it is beneficial for the first initialization signal structure VR1 and the first initialization signal line VREF1 to form a mesh structure, thereby reducing the impedance voltage drop of the first initialization signal, improving the consistency of the first initialization signal received by different pixel circuits 100, and improving the display effect of the display panel.

[0023] Continue to refer to Figures 1 to 10 The first initialization signal structure VR1 is connected to each first initialization signal line VREF1, resulting in multiple connection points between VR1 and VREF1. When VR1 and VREF1 form a mesh structure, there can be multiple connection points within the mesh structure. Further increasing the parallel connection degree of VR1 and VREF1 reduces their equivalent impedance, thereby further reducing the impedance voltage drop of the first initialization signal and improving the consistency of the first initialization signal received by different pixel circuits 100.

[0024] In some embodiments, the display panel includes a plurality of first initialization signal structures VR1 arranged along a first direction Y, and each first initialization signal structure VR1 is connected to a first initialization signal line VREF1.

[0025] Specifically, Figures 5 to 10 The illustration exemplarily shows a first initialization signal structure VR1 arranged along a second direction X within a region of a row of pixel circuits 100. In the display panel, each region of a row of pixel circuits 100 has a first initialization signal structure VR1 arranged along the second direction X. Each first initialization signal structure VR1 is connected to all first initialization signals VREF1, forming a mesh structure for transmitting first initialization signals. In this mesh structure, along the first direction Y, each grid contains one pixel circuit 100. Along the second direction X, each grid contains two pixel circuits 100. The two pixel circuits 100 within a grid are adjacent first pixel circuits 101 and second pixel circuits 102, and the first pixel circuit 101 and second pixel circuit 102 are pixel circuits 100 within different sub-pixel circuits 110.

[0026] Continue to refer to Figures 1 to 10 Within sub-pixel unit 110, the first initialization signal structure VR1 is symmetrical about the first initialization signal line VREF1, which can improve the display panel's resolution. Figure 1Consistency is achieved, simplifying the manufacturing process of the display panel and improving its display effect.

[0027] Continue to refer to Figures 1 to 10 The display panel also includes a fourth conductive layer M4. The fourth conductive layer M4 is disposed between the first conductive layer M1 and the fifth conductive layer M5. The fourth conductive layer M4 includes a first connection structure L1, and a first initialization signal structure VR1 is connected to a first initialization signal line VREF1 through the first connection structure L1.

[0028] Specifically, along the thickness direction of the display panel, the first connection structure L1 is disposed between the first initialization signal structure VR1 and the first initialization signal line VREF1. Connecting the first initialization signal structure VR1 and the first initialization signal line VREF1 via the first connection structure L1 avoids the manufacturing difficulties caused by excessively deep vias when the first initialization signal line VREF1 and the first initialization signal structure VR1 are directly connected. This also improves the connection reliability between the first initialization signal line VREF1 and the first initialization signal structure VR1.

[0029] Continue to refer to Figures 1 to 10 The first connection structure L1 is disposed between adjacent pixel circuits 100 within the sub-pixel unit 110. The first pixel circuit 101 and the second pixel circuit 102 within the sub-pixel unit 110 can share a first connection structure L1 and be connected to the same first initialization signal line VREF1. That is, one end of the first active area 11 in the first pixel circuit 101 and one end of the first active area 11 in the second pixel circuit 102 are connected to the same first connection structure L1. This can reduce the number of first connection structures L1, which is beneficial to simplifying the layout design of the display panel and thus improving the PPI of the display panel.

[0030] Figure 11 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along AA', as provided in an embodiment of the present invention. Figures 1 to 11 As shown, the display panel also includes a first type of via ILD and a second type of via PLN. The first connection structure L1 is connected to the first initialization signal structure VR1 through the first first type of via ILD1, and the first connection structure L1 is connected to the first initialization signal line VREF1 through the first second type of via PLN1.

[0031] Specifically, the first type of via ILD may include a deep hole connecting the fourth conductive layer M4 to the active layer 10, the first conductive layer M1, and the third conductive layer M3. Multiple first type via ILDs are included. The display panel includes a first insulating layer 21. The first insulating layer 21 may be disposed between the third conductive layer M3 and the fourth conductive layer M4, and the first first type via ILD 1 penetrates the first insulating layer 21. Simultaneously, the orthographic projection of the first connection structure L1 on the substrate at least partially overlaps with the orthographic projection of the first first type via ILD 1 on the substrate, and the orthographic projection of the first first type via ILD 1 on the substrate at least partially overlaps with the orthographic projection of the first initialization signal structure VR1 on the substrate. When the first first type via ILD 1 contains conductive material, the first connection structure L1 can be connected to the first initialization signal structure VR1 through the first first type via ILD 1.

[0032] The second type of via PLN includes a via connecting the fifth conductive layer M5 to the fourth conductive layer M4. Multiple second type via PLNs are included. The display panel also includes a second insulating layer 22. The second insulating layer 22 is disposed between the fourth conductive layer M4 and the fifth conductive layer M5. The second type via PLN penetrates the second insulating layer 22. Simultaneously, the orthographic projection of the first connection structure L1 on the substrate at least partially overlaps with the orthographic projection of the first second type via PLN1 on the substrate, and the orthographic projection of the first connection structure L1 on the substrate at least partially overlaps with the orthographic projection of the first initialization signal line VREF1 on the substrate. When the first second type via PLN1 contains conductive material, the first connection structure L1 can be connected to the first initialization signal line VREF1 through the first second type via PLN1. Thus, the first initialization signal line VREF1 can be connected to the first initialization signal structure R1 through the first connection structure L1.

[0033] Continue to refer to Figure 11 The first connection structure L1 is connected to one end of the first active region 11 through the second first type via ILD2.

[0034] Specifically, when the display panel includes a second conductive layer M2, the second conductive layer M2 is disposed between the first conductive layer M1 and the third conductive layer M3. A first-type via ILD may include a deep hole with a fourth conductive layer M4 connecting to the active layer 10, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. The display panel also includes a third insulating layer 23, a fourth insulating layer 24, and a fifth insulating layer 25. The third insulating layer 23 is disposed between the active layer 10 and the first conductive layer M1. The fourth insulating layer 24 is disposed between the first conductive layer M1 and the second conductive layer. The fifth insulating layer 25 is disposed between the second conductive layer M2 and the third conductive layer M3. A second first-type via ILD2 penetrates the first insulating layer 21, the third insulating layer 23, the fourth insulating layer 24, and the fifth insulating layer 25. Simultaneously, the orthographic projection of the first connection structure L1 on the substrate at least partially overlaps with the orthographic projection of the second first-type via ILD2 on the substrate, and the orthographic projection of the second first-type via ILD2 on the substrate at least partially overlaps with the orthographic projection of the first connection active region on the substrate. When the second first-type via ILD2 contains conductive material, the first connection structure L1 can be connected to the first connection active region through the second first-type via ILD2. That is, the first connection structure L1 is connected to one end of the first active region 11 of the first pixel circuit 101, and at the same time, the first connection structure L1 is connected to one end of the first active region 11 of the second pixel circuit 102 within the same sub-pixel unit 110, so that the first initialization signal line VREF1 provides a first initialization signal to two adjacent pixel circuits 100 through the first connection structure L1. This also reduces the number of first-type via ILDs in the display panel, which is beneficial for improving the PPI of the display panel.

[0035] Continue to refer to Figures 1 to 10 The pixel circuit 100 further includes a second transistor T2 and a third transistor T3; the active layer 10 further includes a second active region 12 of the second transistor T2 and a third active region 13 of the third transistor T3; along the second direction X, at least a portion of the first active region 11, the second active region 12 and the third active region 13 are located on the same straight line; the first conductive layer M1 further includes a second gate M12 and a third gate M13; the orthographic projection of the second gate M12 on the active layer 10 at least partially covers the second active region 12, and the orthographic projection of the third gate M13 on the active layer 10 at least partially covers the third active region 13; along the second direction X, at least a portion of the first gate M11, the second gate M12 and the third gate M13 are located on the same straight line.

[0036] Specifically, the orthogonal projection of the second gate M12 onto the active layer 10 covers the channel region of the second active region 12 to form the second transistor T2. The orthogonal projection of the third gate M13 onto the active layer 10 covers the channel region of the third active region 13 to form the third transistor T3. Along the second direction X, the channel regions of the first active region 11, the second active region 12, and the third active region 13 can be located on the same straight line, and at least a portion of the first gate M11, the second gate M12, and the third gate M13 are located on the same straight line, such that the first transistor T1, the second transistor T2, and the third transistor T3 are arranged laterally. The first transistor T1, the second transistor T2, and the third transistor T3 can be controlled by the same scan signal line, reducing the number of scan signal lines required by the pixel circuit 100, thereby simplifying the layout of the display panel and improving the PPI of the display panel.

[0037] For example, the first conductive layer M1 further includes a first scan signal line S1, which is connected to the first gate M11, the second gate M12, and the third gate M13, and is used to control the first transistor T1, the second transistor T2, and the third transistor T3 to be simultaneously turned on or off. When the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, the second transistor T2 and the third transistor T3 initialize the gate G and the first node N of the driving transistor TD of the pixel circuit 100 in this row, respectively. At the same time, the first transistor T1 initializes the first electrode A of the light-emitting device OLED connected to the pixel circuit 100 in the previous row.

[0038] In some embodiments, the portion of the first scan signal line S1 that overlaps with the first active region 11 on the active layer 10 is multiplexed as the first gate M11, which can simplify the structure of the first conductive layer M1 and help improve the PPI of the display panel.

[0039] In some embodiments, the portion of the first scan signal line S1 that overlaps with the second active region 12 on the active layer 10 is multiplexed as the second gate M12, which can simplify the structure of the first conductive layer M1 and help improve the PPI of the display panel.

[0040] In some embodiments, the portion of the first scan signal line S1 that overlaps with the third active region 13 on the active layer 10 is multiplexed as the third gate M13, which can simplify the structure of the first conductive layer M1 and help improve the PPI of the display panel.

[0041] Continue to refer to Figures 1 to 10The first scan signal line S1 extends along the second direction X and is a straight line. By partially multiplexing the first scan signal line S1 into the first gate M11, the second gate M12, and the third gate M13, the layout space occupied by the first scan signal line S1 can be reduced, thereby further improving the PPI of the display panel.

[0042] Continue to refer to Figures 1 to 10 The second transistor T2 is a dual-gate transistor.

[0043] Specifically, such as Figure 1 As shown, the first terminal of the second transistor T2 is connected to the first node N, and the second terminal of the second transistor T2 is connected to the power signal line VDD. The power signal line VDD provides a power signal with a fixed potential. When the second transistor T2 is turned on, it can provide a power signal to the first node N to fix the potential of the first node N. The second transistor T2 is a dual-gate transistor, which can reduce the leakage current between the first node N and the second transistor T2, thereby increasing the maintenance time of the potential of the first node N and improving the display stability of the display panel.

[0044] Continue to refer to Figures 1 to 10 The second active region 12 includes a second active region A 121, a second active region B 122, and a second active region C 123 connected in sequence. The second active region A 121 and the second active region C 123 extend along a first direction Y, and the second active region B 122 extends along a second direction X. The second gate M12 extends along the second direction X, and the orthographic projection of the second gate M12 on the active layer 10 at least partially overlaps with the orthographic projection of the second active region A 121 on the substrate and the orthographic projection of the second active region C 123 on the substrate.

[0045] Specifically, the second transistor T2 includes a second A transistor T21 and a second B transistor T22. The overlapping portion of the orthogonal projection of the second gate M12 on the substrate and the orthogonal projection of the second A active region 121 on the substrate can form the second A transistor T21. The overlapping portion of the orthogonal projection of the second gate M12 on the substrate and the orthogonal projection of the second C active region 123 on the substrate can form the second B transistor T22. One end of the second A active region 121 is connected to one end of the second C active region 123 through the second B active region 122, that is, the first electrode of the second A transistor T21 is connected to the first electrode of the second B transistor T22 through the second B active region 122, forming a dual-gate structure second transistor T2.

[0046] Continue to refer to Figures 1 to 10 The orthographic projection of the first initialization signal structure VR1 on the substrate at least partially covers the orthographic projection of the second active region 122 on the substrate.

[0047] Specifically, the voltage on the first initialization signal structure VR1 is a fixed voltage of the first initialization signal. An insulating layer exists between the first initialization signal structure VR1 and the second active region 122 along the thickness direction of the display panel. When the first initialization signal structure VR1 at least partially covers the second active region 122, a capacitor is formed between the first initialization signal structure VR1 and the second active region 122. This reduces the leakage current of the first node N through the second transistor T2, increases the maintenance time of the potential of the first node N, improves the brightness stability of the display panel, and reduces screen flicker.

[0048] Continue to refer to Figures 1 to 10 The third transistor, T3, is a dual-gate transistor.

[0049] Specifically, such as Figure 1 As shown, the first terminal of the third transistor T3 is connected to the gate G of the driving transistor TD, and the second terminal of the third transistor T3 is connected to the second initialization signal line VREF2. The second initialization signal line VREF2 provides a second initialization signal with a fixed potential. When the third transistor T3 is turned on, it can provide the second initialization signal to the gate G of the driving transistor TD, thus initializing the gate G of the driving transistor TD. The third transistor T3 is a dual-gate transistor, which can reduce the leakage current between the gate G of the driving transistor TD and the third transistor T3, thereby increasing the potential maintenance time of the gate G of the driving transistor TD and improving the display stability of the display panel.

[0050] Continue to refer to Figures 1 to 10 The third active region 13 includes a third active region A 131, a third active region B 132, and a third active region C 133 connected in sequence. The third active region A 131 and the third active region C 133 extend along the first direction Y, and the third active region B 132 extends along the second direction X. The third gate M13 extends along the second direction Y, and the orthographic projection of the third gate M13 on the substrate at least partially overlaps with the orthographic projections of the third active region A 131 and the third active region C 133 on the substrate.

[0051] Specifically, the third transistor T3 includes a third A transistor T31 and a third B transistor T32. The overlapping portion of the orthogonal projection of the third gate M13 onto the substrate and the orthogonal projection of the third A active region 131 onto the substrate can form the third A transistor T31. The overlapping portion of the orthogonal projection of the third gate M13 onto the substrate and the orthogonal projection of the third C active region 133 onto the substrate can form the third B transistor T32. One end of the third A active region 131 is connected to one end of the third C active region 133 through the third B active region 132, that is, the first terminal of the third A transistor T31 is connected to the first terminal of the third B transistor T32 through the third B active region 132, forming a dual-gate structure third transistor T3.

[0052] Continue to refer to Figures 1 to 10 The orthographic projection of the first initialization signal structure VR1 on the substrate at least partially covers the orthographic projection of the third active region 132 on the substrate.

[0053] Specifically, the voltage on the first initialization signal structure VR1 is a fixed voltage of the first initialization signal. An insulating layer exists between the first initialization signal structure VR1 and the third active region 132 along the thickness direction of the display panel. When the first initialization signal structure VR1 at least partially covers the third active region 132, a capacitance is formed between the first initialization signal structure VR1 and the third active region 132. This reduces the leakage current of the gate G of the driving transistor TD through the third transistor T3, increases the potential maintenance time of the gate G of the driving transistor TD, improves the brightness stability of the display panel, and reduces screen flicker.

[0054] Continue to refer to Figures 1 to 10 The pixel circuit also includes a driving transistor TD; the active layer 10 also includes a driving active region 18 of the driving transistor TD, the first conductive layer M1 also includes a driving gate Md, the orthogonal projection of the driving gate Md on the active layer 10 at least partially covers the driving active region 18; the driving gate Md is connected to one end of the third active region 13.

[0055] Specifically, the orthogonal projection of the driving gate Md onto the active layer 10 covers the channel region of the driving active region 18 to form the driving transistor TD. One end of the third active region 13 is the first electrode of the third transistor T3. The driving gate Md is connected to one end of the third active region 13, which is the connection between the driving gate Md and the first electrode of the third transistor T3, so that the third transistor T3 can provide a second initialization signal to the driving gate Md to initialize the potential of the driving gate Md.

[0056] Continue to refer to Figures 1 to 10 The fourth conductive layer M4 also includes a second connection structure L2, through which the driving gate Md is connected to one end of the third active region 13.

[0057] Specifically, the equivalent resistance of the fourth conductive layer M4 is relatively small. The driving gate Md is connected to one end of the third active region 13 through the second connection structure L2, which can reduce the equivalent impedance between the driving gate Md and the third active region 13, improve the accuracy of the first initialization signal transmission to the gate G of the driving transistor TD, and thus improve the display accuracy of the display panel. Moreover, the second connection structure L2 is disposed on the fourth conductive layer M4, which can reduce the layout complexity of the first conductive layer M1, which is beneficial to improving the PPI of the display panel.

[0058] Figure 12 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along BB', as provided in an embodiment of the present invention. Figure 12 As shown, the second connection structure L2 is connected to one end of the third active region 13 through the third first type via ILD3, and the second connection structure L2 is connected to the driving gate Md through the fourth first type via ILD4.

[0059] Specifically, the third type-1 via ILD3 penetrates the first insulating layer 21, the third insulating layer 23, the fourth insulating layer 24, and the fifth insulating layer 25. Simultaneously, the orthographic projection of the second connection structure L2 onto the substrate partially overlaps with the orthographic projection of the third type-1 via ILD3 onto the substrate, and the orthographic projection of the third type-1 via ILD3 onto the substrate at least partially overlaps with the orthographic projection of one end of the third active region 13 onto the substrate. When conductive material is present within the third type-1 via ILD3, the second connection structure L2 can be connected to one end of the third active region 13 through the third type-1 via ILD3.

[0060] The fourth type-1 via ILD4 can penetrate the first insulating layer 21, the fourth insulating layer 24, and the fifth insulating layer 25. Simultaneously, the orthographic projection of the second connection structure L2 on the substrate partially overlaps with the orthographic projection of the fourth type-1 via ILD4 on the substrate, and the orthographic projection of the fourth type-1 via ILD4 on the substrate at least partially overlaps with the orthographic projection of the driving gate Md on the substrate. When the fourth type-1 via ILD4 contains conductive material, the second connection structure L2 can be connected to the driving gate Md through the fourth type-1 via ILD4. Thus, the driving gate Md is connected to one end of the third active region 13 through the second connection structure L2. At this time, the fourth type-1 via ILD4 corresponds to the first node N in the pixel circuit 100.

[0061] Continue to refer to Figures 1 to 10 Along the first direction Y, the first transistor T1, the second transistor T2 and the third transistor T3 are disposed on the same side of the driving transistor TD, which helps to improve the compactness of the layout of the pixel circuit 100, thereby improving the PPI of the display panel.

[0062] Continue to refer to Figures 1 to 10 The pixel circuit 100 also includes a first capacitor C1, which includes a first electrode C11, and the driving gate Md is multiplexed as the first electrode C11. This not only enables the first electrode C11 of the first capacitor C1 to be connected to the driving gate Md, but also simplifies the layout structure of the pixel circuit 100, which helps to reduce the layout space occupied by the pixel circuit 100 in the display panel and improves the PPI of the display panel.

[0063] Continue to refer to Figures 1 to 10 The display panel also includes: The second conductive layer M2 is disposed between the first conductive layer M1 and the third conductive layer M3; the second conductive layer M2 includes the second electrode C12 of the first capacitor C1, and the orthographic projection of the second electrode C12 on the substrate at least partially overlaps with the orthographic projection of the first electrode C11 on the substrate.

[0064] Specifically, the second conductive layer M2 can be a metal layer used to form devices in the pixel circuit and the connecting lines between devices. A fourth insulating layer 24 is provided between the second conductive layer M2 and the first conductive layer M1 to insulate them. The orthographic projection of the second electrode C12 onto the substrate at least partially overlaps with the orthographic projection of the first electrode C11 onto the substrate. The first electrode C11, the second electrode C12, and the fourth insulating layer 24 between them form a first capacitor.

[0065] Continue to refer to Figures 1 to 10 The third conductive layer M3 also includes a third electrode C13, the orthographic projection of the third electrode C13 on the substrate at least partially overlaps with the orthographic projection of the second electrode C12 on the substrate.

[0066] Specifically, a fifth insulating layer 25 is present between the second conductive layer M2 and the third conductive layer M3. The orthographic projection of the third electrode C13 onto the substrate at least partially overlaps with the orthographic projection of the second electrode C12 onto the substrate. The second electrode C12, the third electrode C13, and the fifth insulating layer 25 between them form a second capacitor C2. The second capacitor C2 shares the second electrode C12 with the first capacitor C1. Furthermore, the second capacitor C2 and the first capacitor C1 are connected in series, which can increase the capacitance value of the storage capacitor between the gate G of the driving transistor TD and the power signal line VDD, which helps to reduce crosstalk in the display panel and improves the PPI of the display panel.

[0067] Continue to refer to Figures 1 to 10The orthographic projection of the second electrode C12 onto the substrate covers the orthographic projection of the fourth type-1 via ILD4 onto the substrate. For example, the orthographic projection of the fourth type-1 via ILD4 onto the substrate can be located in the middle region of the orthographic projection of the second electrode C12 onto the substrate. The second electrode C12 can shield the coupling effect of other signals on the fourth type-1 via ILD4, that is, shield the coupling effect of other signals on the gate G of the driving transistor TD, thus improving the crosstalk phenomenon of the display panel.

[0068] Continue to refer to Figures 1 to 10 The orthographic projection of the third electrode plate C13 on the substrate covers the orthographic projection of the fourth type I via ILD4 on the substrate, which can also shield the coupling effect of other signals on the fourth type I via ILD4, that is, shield the coupling effect of other signals on the gate G of the driving transistor TD, thus improving the crosstalk phenomenon of the display panel.

[0069] Continue to refer to Figures 1 to 10 The fourth conductive layer M4 includes a second initialization signal line VREF2; the second initialization signal line VREF2 is connected to the other end of the third active region 13.

[0070] Specifically, the other end of the third active region 13 is the second terminal of the third transistor T3. The second initialization signal line VREF2 is connected to the other end of the third active region 13, that is, the second initialization signal line VREF2 is connected to the second terminal of the third transistor T3, providing a second initialization signal with a fixed potential to the second terminal of the third transistor T3.

[0071] Continue to refer to Figures 1 to 10 The second initialization signal line VREF2 includes multiple second initialization signal structures VR2 arranged along the second direction X; each second initialization signal structure VR2 is connected to the other end of the third active region 13 in two adjacent pixel circuits 100, and the two adjacent pixel circuits 100 are respectively the first pixel circuit 101 and the second pixel circuit 102 in a sub-pixel unit 110.

[0072] Specifically, each second initialization signal structure VR2 is disposed within the layout of a sub-pixel unit 110. Each second initialization signal structure VR2 extends along the second direction X and is connected to the other end of the third active region 13 of the two pixel circuits 100 within the sub-pixel unit 110, respectively. It can simultaneously provide the second initialization signal to the second pole of the third transistor T3 of the two pixel circuits 100 within the sub-pixel unit 110, which is beneficial to improving the layout compactness of the display panel and increasing the PPI of the display panel.

[0073] Continue to refer to Figures 1 to 10The second initialization signal structure VR2 is symmetrical about the first initialization signal line VREF1. When the second initialization signal structure VR2 is connected to the other end of the third active area 13 within the two adjacent pixel circuits 100, the connection lines can be simplified, improving the display panel layout. Figure 1 This consistency simplifies the manufacturing process of the display panel and improves its display effect.

[0074] Continue to refer to Figures 1 to 10 The second conductive layer M2 also includes a third initialization signal structure VR3, and adjacent second initialization signal structures VR2 are connected through a third initialization signal structure VR3.

[0075] Specifically, along the second direction X, the third initialization signal structure VR3 and the second initialization signal structure VR2 are alternately arranged and interconnected. The third initialization signal structure VR3 extends along the second direction X; at this time, the second initialization signal structure VR2 and the third initialization signal structure VR3 form a second initialization signal line VREF2 extending along the second direction X, which is used to provide second initialization signals for different pixel circuits 100.

[0076] Figure 13 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along CC', as provided in an embodiment of the present invention. Figure 13 As shown, the second initialization signal structure VR2 is connected to the third initialization signal structure VR3 through the fifth first type via ILD5.

[0077] Specifically, the fifth type-1 via ILD5 penetrates both the first insulating layer 21 and the fifth insulating layer 25. Simultaneously, the orthographic projection of the fifth type-1 via ILD5 onto the substrate at least partially overlaps with the orthographic projection of the second initialization signal structure VR2 onto the substrate, and the orthographic projection of the fifth type-1 via ILD5 onto the substrate at least partially overlaps with the orthographic projection of the third initialization signal structure VR3 onto the substrate. When conductive material is present within the fifth type-1 via ILD5, the second initialization signal structure VR2 is connected to the third initialization signal structure VR3 through the fifth type-1 via ILD5.

[0078] Continue to refer to Figure 13The display panel also includes a first type of via ILD, which penetrates an insulating layer 21, a third insulating layer 23, a fourth insulating layer 24, and a fifth insulating layer 25. Simultaneously, the orthographic projection of the second initialization signal structure VR2 onto the substrate at least partially overlaps with the orthographic projection of the first type of via ILD onto the substrate, and the orthographic projection of the other end of the third active region 13 onto the substrate at least partially overlaps with the orthographic projection of the first type of via ILD onto the substrate. When the first type of via ILD contains conductive material, the second initialization signal structure VR2 is connected to the other end of the third active region 13 through the first type of via ILD.

[0079] Continue to refer to Figures 1 to 10 The third initialization signal structure VR3 is symmetrical about the first initialization signal line VREF1, which can improve the display panel's resolution. Figure 1 Consistency is achieved, simplifying the manufacturing process of the display panel and improving its display effect.

[0080] Continue to refer to Figures 1 to 10 The pixel circuit 100 also includes a fourth transistor T4; the active layer 10 also includes a fourth active region 14 of the fourth transistor T4, and the first conductive layer M1 also includes a fourth gate M14 of the fourth transistor T4. The orthogonal projection of the fourth gate M14 on the active layer 10 at least partially covers the fourth active region 14; one end of the fourth active region 14 is connected to one end of the third active region 13, and the other end of the fourth active region 14 is connected to one end of the driving active region 18.

[0081] Specifically, the orthogonal projection of the fourth gate M14 onto the active layer 10 covers the channel region of the fourth active region 14 to form the fourth transistor T4. One end of the third active region 13 is the first electrode of the third transistor T3. One end of the fourth active region 14 and one end of the third active region 13 can be connected through the active layer 10. That is, there is a heavily doped active layer 10 between one end of the fourth active region 14 and one end of the third active region 13, and it is in contact with one end of the fourth active region 14 and one end of the third active region 13, respectively. At this time, the first electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3. When the driving gate Md is connected to one end of the third active region 13 through the second connection structure L2, one end of the fourth active region 14 is connected to the driving gate Md through the second connection structure L2. That is, the first electrode of the fourth transistor T4 is connected to the gate G of the driving transistor TD. Meanwhile, the other end of the fourth active region 14 can be connected to one end of the driving active region 18 through the active layer 10, that is, the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor TD. When the fourth transistor T4 is turned on, the driving transistor TD is connected in a diode configuration, which can achieve threshold compensation for the driving transistor TD.

[0082] Continue to refer to Figures 1 to 10One end of the third active region 13 has a third connecting active region, and the orthographic projection of the third initialization signal structure VR3 on the substrate at least partially covers the orthographic projection of the third connecting active region on the substrate.

[0083] Specifically, when one end of the third active region 13 is connected to one end of the fourth active region 14, the active layer 10 used for connection between the one end of the third active region 13 and the one end of the fourth active region 14 is the third connecting active region. An insulating layer exists between the third initialization signal structure VR3 and the third connecting active region along the thickness direction of the display panel. By setting the third initialization signal structure VR3 to at least partially cover the third connecting active region, a capacitor is formed between the third initialization signal structure VR3 and the third connecting active region, reducing the leakage current of the driving gate Md through the third transistor T3, increasing the potential maintenance time of the gate G of the driving transistor TD, improving the brightness stability of the display panel, and reducing screen flicker.

[0084] Continue to refer to Figures 1 to 10 The first conductive layer M1 also includes a second scan signal line S2, which is connected to the fourth gate M14 and is used to provide a scan signal to the gate of the fourth transistor T4 to control the turn-on and turn-off of the fourth transistor T4.

[0085] Continue to refer to Figures 1 to 10 The portion of the second scan signal line S2 that overlaps with the fourth active region 14 on the active layer 10 is multiplexed as the fourth gate M14, which can simplify the structure of the first conductive layer M1 and help improve the PPI of the display panel.

[0086] Continue to refer to Figures 1 to 10 The pixel circuit 100 also includes a fifth transistor T5; the active layer 10 also includes a fifth active region 15 of the fifth transistor T5, and the first conductive layer M1 also includes a fifth gate M15 of the fifth transistor T5. The orthogonal projection of the fifth gate M15 on the active layer 10 at least partially covers the fifth active region 15; one end of the fifth active region 15 is connected to one end of the second active region 12, one end of the fifth active region 15 is connected to the second electrode C12, and the other end of the fifth active region 15 is connected to the other end of the driving active region 18.

[0087] Specifically, the orthogonal projection of the fifth gate M15 onto the active layer 10 covers the channel region of the fifth active region 15 to form the fifth transistor T5. One end of the fifth active region 15 and one end of the second active region 12 can be connected through the active layer 10. That is, there is a heavily doped active layer 10 between one end of the fifth active region 15 and one end of the second active region 12, and it is in contact with one end of the fifth active region 15 and one end of the second active region 12, respectively. At this time, the first electrode of the fifth transistor T5 is connected to the first electrode of the second transistor T2. At the same time, one end of the fifth active region 15 is connected to the second electrode plate C12, so that the first electrode of the fifth transistor T5 and the first electrode of the second transistor T2 are both connected to the first node N. The second electrode of the fifth transistor T5 is connected to the power signal line VDD. When the fifth transistor T5 and the second transistor T2 are turned on in a time-division manner, the potential of the first node N can be fixed in a time-division manner. The other end of the fifth active region 15 and the other end of the driving active region 18 are connected through the active layer 10. When the other ends of the fifth active region 15 and the driving active region 18 are simultaneously connected to the power signal line VDD, the number of vias in the display panel can be reduced, the layout design in the display panel can be simplified, and the PPI of the display panel can be improved.

[0088] Continue to refer to Figures 1 to 10 One end of the second active region 12 has a second connecting active region, and the orthographic projection of the third initialization signal structure VR3 on the substrate at least partially covers the orthographic projection of the second connecting active region on the substrate.

[0089] Specifically, when one end of the second active region 12 is connected to one end of the fifth active region 15, the active layer 10 used for connection between one end of the second active region 12 and one end of the fifth active region 15 is the second connection active region. Along the thickness direction of the display panel, an insulating layer exists between the third initialization signal structure VR3 and the second connection active region. By setting the third initialization signal structure VR3 to at least partially cover the second connection active region, a capacitor is formed between the third initialization signal structure VR3 and the second connection active region, reducing the leakage current of the first node N through the second transistor T2, increasing the potential maintenance time of the first node N, improving the brightness stability of the display panel, and mitigating screen flicker.

[0090] Continue to refer to Figures 1 to 10The fourth conductive layer M4 also includes a third connection structure L3. One end of the fifth active region 15 is connected to the second electrode C12 through the third connection structure L3. This reduces the equivalent impedance between the fifth active region 15 and the second electrode C12, improving the accuracy of the power signal provided by the power signal line VDD to the first node N, thereby improving the display accuracy of the display panel. Furthermore, the third connection structure L3, located in the fourth conductive layer M4, reduces the layout complexity of the first conductive layer M1, which is beneficial for improving the PPI of the display panel.

[0091] Figure 14 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along DD', as provided in an embodiment of the present invention. Figure 14 As shown, the third connection structure L3 is connected to one end of the fifth active region 15 through the sixth first type via ILD6, and the third connection structure L3 is connected to the second electrode plate C12 through the seventh first type via ILD7.

[0092] Specifically, the sixth type-1 via ILD6 penetrates the first insulating layer 21, the third insulating layer 23, the fourth insulating layer 24, and the fifth insulating layer 25. Simultaneously, the orthographic projection of the third connection structure L3 on the substrate partially overlaps with the orthographic projection of the sixth type-1 via ILD6 on the substrate, and the orthographic projection of the sixth type-1 via ILD6 on the substrate at least partially overlaps with the orthographic projection of one end of the fifth active region 15 on the substrate. When conductive material is present within the sixth type-1 via ILD6, the third connection structure L3 can be connected to one end of the fifth active region 15 through the sixth type-1 via ILD6. The seventh type-1 via ILD7 penetrates the first insulating layer 21 and the fifth insulating layer 25. Simultaneously, the orthographic projection of the third connection structure L3 on the substrate partially overlaps with the orthographic projection of the seventh type-1 via ILD7 on the substrate, and the orthographic projection of the seventh type-1 via ILD7 on the substrate partially overlaps with the orthographic projection of the second electrode C12 on the substrate. When the seventh type I via ILD7 contains conductive material, the third connection structure L3 is connected to the second electrode C12 through the seventh type I via ILD7.

[0093] Continue to refer to Figures 1 to 10 The orthographic projection of the third electrode plate C13 onto the substrate covers the orthographic projection of the seventh type-1 via ILD7 onto the substrate. For example, the orthographic projection of the seventh type-1 via ILD7 onto the substrate can be located in the middle region of the orthographic projection of the third electrode plate C13 onto the substrate. The third electrode plate C13 can shield the coupling effect of other signals on the seventh type-1 via ILD7, that is, shield the coupling effect of other signals on the first node N, thus improving the crosstalk phenomenon of the display panel.

[0094] Continue to refer to Figures 1 to 10Along the second direction X, the fourth type-1 via ILD4 and the seventh type-1 via ILD7 are arranged adjacent to each other. This increases the distance from the fourth and seventh type-1 vias ILD4 and ILD7 to the sides of the capacitor plate. When a data signal line DATA is placed on one side of the capacitor plate, increasing the distance from the fourth and seventh type-1 vias ILD4 and ILD7 to the data signal line DATA reduces the coupling effect of the data signal provided by the data signal line DATA on the first node N and the gate G of the driving transistor TD, thus improving crosstalk in the display panel.

[0095] Continue to refer to Figures 1 to 10 The second scan signal line S2 is connected to the fifth gate M15 and is used to provide a scan signal to the fifth transistor T5 to control the turn-on or turn-off of the fifth transistor T5.

[0096] Continue to refer to Figures 1 to 10 The portion of the second scan signal line S2 that overlaps with the fifth active region 15 on the active layer 10 is multiplexed as the fifth gate M15, which can simplify the structure of the first conductive layer M1 and help improve the PPI of the display panel.

[0097] Continue to refer to Figures 1 to 10 The second scan signal line S2 extends along the second direction X.

[0098] Specifically, the fifth transistor T5 and the fourth transistor T4 are arranged along the second direction X. By setting the second scan signal line S2 to extend along the second direction X, the second scan signal line S2 can be multiplexed as the fourth gate M14 and the fifth gate M15, thereby reducing the layout space occupied by the second scan signal line S2 and further improving the PPI of the display panel.

[0099] Continue to refer to Figures 1 to 10 The fourth active region 14 and the fifth active region 15 are arranged along the second direction X, such that the fourth transistor T4 and the fifth transistor T5 are also arranged along the second direction X. The fourth transistor T4 and the fifth transistor T5 can be controlled by the same scan signal line, reducing the number of scan signal lines required by the pixel circuit 100, thereby simplifying the layout of the display panel and improving the PPI of the display panel.

[0100] Continue to refer to Figures 1 to 10 The fourth transistor, T4, is a dual-gate transistor.

[0101] Specifically, one end of the fourth active region 14 is connected to the driving gate Md. By setting the fourth transistor T4 as a dual-gate transistor, the leakage current from the gate G of the driving transistor TD to the fourth transistor T4 can be reduced, thereby increasing the potential maintenance time of the gate G of the driving transistor TD and improving the display stability of the display panel.

[0102] Continue to refer to Figures 1 to 10 The fourth active region 14 includes a fourth active region A 141 and a fourth active region B 142 connected together. The fourth active region A 141 extends along a first direction Y, and the fourth active region B 142 extends along a second direction X. The fourth gate M14 includes an integrated fourth sub-gate M141 and a fourth sub-gate M142. The fourth sub-gate M141 extends along the second direction X, and the fourth sub-gate M142 extends along the first direction Y. The orthographic projection of the fourth sub-gate M141 on the substrate at least partially overlaps with the orthographic projection of the fourth active region A 141 on the substrate. The orthographic projection of the fourth sub-gate M142 on the substrate at least partially overlaps with the orthographic projection of the fourth active region B 142 on the substrate.

[0103] Specifically, the fourth transistor T4 includes a fourth A transistor T41 and a fourth B transistor T42. The portion where the orthographic projection of the fourth A sub-gate M141 onto the substrate overlaps with the orthographic projection of the fourth A active region 141 onto the substrate forms the fourth A transistor T41. The portion where the orthographic projection of the fourth B sub-gate M142 onto the substrate overlaps with the orthographic projection of the fourth B active region 142 onto the substrate forms the fourth B transistor T42. One end of the fourth A active region 141 and one end of the fourth B active region 142 are connected, that is, the first electrode of the second A transistor T41 and the first electrode of the fourth B transistor T42 are connected, forming a dual-gate structure fourth transistor T4.

[0104] Continue to refer to Figures 1 to 10 The connection between the fourth active region 141 and the fourth active region 141 has a fourth connecting active region, and the orthographic projection of the first initialization signal structure VR1 on the substrate at least partially covers the orthographic projection of the fourth connecting active region on the substrate.

[0105] Specifically, the active layer 10 used for connection between one end of the fourth active region 141 and one end of the fourth active region 142 is the fourth connecting active region. An insulating layer exists between the first initialization signal structure VR1 and the fourth connecting active region along the thickness direction of the display panel. By setting the orthographic projection of the first initialization signal structure VR1 on the substrate to at least partially cover the orthographic projection of the fourth connecting active region on the substrate, a capacitor is formed between the first initialization signal structure VR1 and the fourth connecting active region. This reduces the leakage current of the driving gate Md through the fourth transistor T4, increases the potential maintenance time of the gate G of the driving transistor TD, improves the brightness stability of the display panel, and reduces screen flicker.

[0106] Continue to refer to Figures 1 to 10 The fifth transistor, T5, is a dual-gate transistor.

[0107] Specifically, one end of the fifth active region 15 is connected to the first node N. By setting the fifth transistor T5 as a dual-gate transistor, the leakage current from the first node N to the fifth transistor T5 can be reduced, thereby increasing the potential maintenance time of the first node N and improving the display stability of the display panel.

[0108] Continue to refer to Figures 1 to 10 The fifth active region 15 includes a fifth active region A 151 and a fifth active region B 152 connected together. The fifth active region A 151 extends along a first direction Y, and the fifth active region B 152 extends along a second direction X. The fifth gate M15 includes an integrated fifth sub-gate M151 and a fifth sub-gate M152. The fifth sub-gate M151 extends along the second direction X, and the fifth sub-gate M152 extends along the first direction Y. The orthographic projection of the fifth sub-gate M151 on the substrate at least partially overlaps with the orthographic projection of the fifth active region A 151 on the substrate. The orthographic projection of the fifth sub-gate M152 on the substrate at least partially overlaps with the orthographic projection of the fifth active region B 152 on the substrate.

[0109] Specifically, the fifth transistor T5 includes a fifth A transistor T51 and a fifth B transistor T52. The portion where the orthographic projection of the fifth A sub-gate M151 onto the substrate overlaps with the orthographic projection of the fifth A active region 151 onto the substrate forms the fifth A transistor T51. The portion where the orthographic projection of the fifth B sub-gate M152 onto the substrate overlaps with the orthographic projection of the fifth B active region 152 onto the substrate forms the fifth B transistor T52. One end of the fifth A active region 151 and one end of the fifth B active region 152 are connected, that is, the first electrode of the fifth A transistor T51 and the first electrode of the fifth B transistor T52 are connected, forming a dual-gate structure fifth transistor T5.

[0110] Continue to refer to Figures 1 to 10 Along the first direction Y, the fourth transistor T4 and the fifth transistor T5 are located on the same side of the driving transistor TD, which helps to improve the compactness of the pixel circuit 100 layout and thus improve the PPI of the display panel.

[0111] Continue to refer to Figures 1 to 10 Along the first direction Y, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are arranged on the same side of the driving transistor TD, which helps to improve the compactness of the layout of the pixel circuit 100, thereby improving the PPI of the display panel.

[0112] Continue to refer to Figures 1 to 10 Along the first direction Y, the second scan signal line S2 is located between the driving active area 18 and the first scan signal line S1, which simplifies the layout of the pixel circuit 100, improves the compactness of the layout of the pixel circuit 100, and helps to improve the PPI of the display panel.

[0113] Continue to refer to Figures 1 to 10 Along the first direction Y, the second initialization signal line VREF2 is located between the first scan signal line S1 and the second scan signal line S2, facilitating the connection between the second initialization signal line VREF2 and the second terminal of the third transistor T3. This simplifies the layout of the pixel circuit 100, improves the compactness of the pixel circuit 100 layout, and helps to improve the PPI of the display panel.

[0114] Continue to refer to Figures 1 to 10 Along the first direction Y, the first initialization signal structure VR1 is located on the side of the first scan signal line S1 away from the second scan signal line S2. It is used to cover the middle node of the second transistor T2 and the middle node of the third transistor T3, reduce the leakage current of the gate G of the driving transistor TD and the first node N, and improve the brightness stability of the display panel.

[0115] Figure 15 This is a schematic diagram of an active layer, a fifth conductive layer, and a third type of via provided in an embodiment of the present invention. Figure 16 This is a schematic diagram illustrating the structure of an active layer, a fifth conductive layer, a third type of via, and an anode layer, provided in an embodiment of the present invention. (Reference) Figures 1 to 10 , Figure 15 and Figure 16 The fifth conductive layer M5 also includes a power signal line VDD, which is connected to the third electrode plate C13, the other end of the driving active region 18, the other end of the second active region 12 and the other end of the fifth active region 15. It is used to provide power signals to the second electrode of the second capacitor C2, the second electrode of the driving transistor TD, the second electrode of the second transistor T2 and the second electrode of the fifth transistor T5, so as to ensure the normal operation of the pixel circuit 100.

[0116] For example, the fourth conductive layer M4 also includes a fourth connection structure L4 and a fifth connection structure L5. The third electrode plate C13 is connected to the other end of the fifth active region 15 and the other end of the second active region 12 through the fourth connection structure L4, and the third electrode plate C13 is connected to the power signal line VDD through the fifth connection structure L5.

[0117] Specifically, the other end of the fifth active region 15 is connected to the other end of the driving active region 18. When the third plate C13 is connected to the other end of the fifth active region 15 and the other end of the second active region 12 through the fourth connection structure L4, and the third plate C13 is connected to the other end of the driving active region 18 through the fourth connection structure L4, then the second terminal of the second capacitor C2 is connected to the second terminal of the fifth transistor T5, the second terminal of the second transistor T2, and the second terminal of the driving transistor TD. At the same time, the third plate C13 is connected to the power signal line VDD through the fifth connection structure L5. This is equivalent to the power signal line VDD being connected to the second terminal of the fifth transistor T5, the second terminal of the second transistor T2, and the second terminal of the driving transistor TD through the fifth connection structure L5 and the third plate C13, which is used to provide power signals to the second terminal of the second capacitor C2, the second terminal of the fifth transistor T5, the second terminal of the second transistor T2, and the second terminal of the driving transistor TD.

[0118] Figure 17 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along EE', as provided in an embodiment of the present invention. Figure 17 As shown, the fourth connection structure L4 is connected to the other end of the second active region 12 through the eighth first type via ILD8, the fourth connection structure L4 is connected to the other end of the driving active region 18 through the ninth first type via ILD9, and the fourth connection structure L4 is connected to the third electrode plate C13 through the tenth first type via ILD10.

[0119] Specifically, the eighth type-1 via ILD8 penetrates the first insulating layer 21, the third insulating layer 23, the fourth insulating layer 24, and the fifth insulating layer 25. Simultaneously, the orthographic projection of the fourth connection structure L4 on the substrate at least partially overlaps with the orthographic projection of the eighth type-1 via ILD8 on the substrate, and the orthographic projection of the eighth type-1 via ILD8 on the substrate at least partially overlaps with the orthographic projection of the other end of the second active region 12 on the substrate. When conductive material is present within the eighth type-1 via ILD8, the fourth connection structure L4 is connected to the other end of the second active region 12 through the eighth type-1 via ILD8. The ninth type-1 via ILD9 penetrates the first insulating layer 21, the third insulating layer 23, the fourth insulating layer 24, and the fifth insulating layer 25. Simultaneously, the orthographic projection of the fourth connection structure L4 on the substrate at least partially overlaps with the orthographic projection of the ninth type-1 via ILD9 on the substrate, and the orthographic projection of the ninth type-1 via ILD9 on the substrate at least partially overlaps with the orthographic projection of the other end of the driving active region 18 on the substrate. When the ninth type-1 via ILD9 contains conductive material, the fourth connection structure L4 is connected to the other end of the driving active region 18 through the ninth type-1 via ILD9, which is equivalent to being connected to the other end of the fifth active region 15. The tenth type-1 via ILD10 penetrates the first insulating layer 21. Simultaneously, the orthographic projection of the fourth connection structure L4 on the substrate at least partially overlaps with the orthographic projection of the tenth type-1 via ILD10 on the substrate, and the orthographic projection of the tenth type-1 via ILD10 on the substrate at least partially overlaps with the orthographic projection of the third electrode C13 on the substrate. When the tenth type-1 via ILD10 contains conductive material, the fourth connection structure L4 is connected to the third electrode C13.

[0120] Continue to refer to Figures 1 to 10 The fifth active region 151 and the fifth active region 152 are connected at the junction of the fifth active region 151 and the fifth active region 152. The orthographic projection of the fourth connection structure L4 on the substrate at least partially covers the orthographic projection of the fifth active region on the substrate.

[0121] Specifically, the active layer 10 used for connection between one end of the fifth active region 151 and one end of the fifth active region 152 is the fifth connecting active region. The signal on the fourth connecting structure L4 is a power signal with a fixed potential. An insulating layer is provided between the fourth connecting structure L4 and the fifth connecting active region along the thickness direction of the display panel. By setting the orthographic projection of the fourth connecting structure L4 on the substrate to at least partially cover the orthographic projection of the fifth connecting active region on the substrate, a capacitor is formed between the fourth connecting structure L4 and the fifth connecting active region. This reduces the leakage current of the first node through the fifth transistor T5, increases the potential maintenance time of the first node N, improves the brightness stability of the display panel, and reduces screen flicker.

[0122] Figure 18This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along FF', as provided in an embodiment of the present invention. Figure 18 As shown, the fifth connection structure L5 is connected to the third plate C13 through the eleventh first type via ILD11, and the fifth connection structure L5 is connected to the power signal line VDD through the second second type via PLN2.

[0123] Specifically, the eleventh type-1 via ILD11 penetrates the first insulating layer 21. Simultaneously, the orthographic projection of the fifth connection structure L5 on the substrate at least partially overlaps with the orthographic projection of the eleventh type-1 via ILD11 on the substrate, and the orthographic projection of the eleventh type-1 via ILD11 on the substrate partially overlaps with the orthographic projection of the third electrode C13 on the substrate. When conductive material is present within the eleventh type-1 via ILD11, the fifth connection structure L5 is connected to the third electrode C13. The orthographic projection of the fifth connection structure L5 on the substrate at least partially overlaps with the orthographic projection of the second type-2 via PLN2 on the substrate, and the orthographic projection of the second type-2 via PLN2 on the substrate at least partially overlaps with the orthographic projection of the power signal line VDD on the substrate. When conductive material is present within the second type-2 via PLN2, the fifth connection structure L5 is connected to the power signal line VDD.

[0124] Continue to refer to Figures 1 to 10 The orthographic projection of the power signal line VDD on the substrate covers the orthographic projection of the fourth type-1 via ILD4 on the substrate.

[0125] Specifically, the power signal line VDD has a fixed potential. When the power signal line VDD covers the fourth type-1 via ILD, it is equivalent to the power signal line VDD covering the gate G of the driving transistor TD. At this time, the power signal line VDD can shield the coupling effect of other signals on the gate G of the driving transistor TD, improve the potential stability of the gate G of the driving transistor TD, and improve the crosstalk phenomenon of the display panel.

[0126] Continue to refer to Figures 1 to 10 The orthographic projection of the power signal line VDD on the substrate covers the orthographic projection of the seventh type-1 via ILD7 on the substrate.

[0127] Specifically, when the power signal line VDD covers the seventh type-1 via ILD7, it is equivalent to the power signal line VDD covering the first node N. In this case, the power signal line VDD can shield the coupling effect of other signals on the first node N, improve the potential stability of the first node, and reduce crosstalk in the display panel.

[0128] Continue to refer to Figures 1 to 10The display panel includes multiple power signal lines VDD, which extend along the first direction Y and are arranged along the second direction X. This increases the power signal transmission channels, improves the consistency of power signal transmission to different pixel circuits 100, and improves the brightness consistency of the display panel.

[0129] Continue to refer to Figures 1 to 10 The fifth connection structure L5 is connected to the two adjacent power signal lines VDD. When the fifth connection structure L5 extends along the second direction X, the fifth connection structure L5 and the power signal line VDD can form a mesh structure, which can further reduce the impedance voltage drop on the power signal line VDD, improve the consistency of the power signal, and thus improve the brightness consistency of the display panel.

[0130] Continue to refer to Figures 1 to 10 The display panel includes multiple fifth connection structures L5 arranged along the second direction X. Each fifth connection structure L5 is connected to the third plate C13 in two adjacent pixel circuits 100. When the fifth connection structure L5 is connected to two adjacent power signal lines VDD, the path for the power signal to be transmitted to the two adjacent pixel circuits 100 is a mesh structure, which reduces the impedance voltage drop of the power signal and improves the brightness uniformity of the display panel.

[0131] Continue to refer to Figures 1 to 10 The fifth connection structure L5 is symmetrical about the first initialization signal line VREF1. When the fifth connection structure L5 is simultaneously connected to the third electrode plate C13 in two adjacent pixel circuits 100, the connection lines between the fifth connection structure L5 and the third electrode plate C13 can be simplified. This also improves the layout of the pixel circuit 100. Figure 1 Consistency is beneficial for improving the display effect of the display panel.

[0132] Continue to refer to Figures 1 to 10 The pixel circuit 100 also includes a sixth transistor T6; the active layer 10 also includes a sixth active region 16 of the sixth transistor T6, and the first conductive layer M1 also includes a sixth gate M16 of the sixth transistor T6; the orthogonal projection of the sixth gate M16 on the active layer 10 at least partially covers the sixth active region 16, and one end of the sixth active region 16 is connected to the second electrode plate C12.

[0133] Specifically, the orthogonal projection of the sixth gate M16 onto the active layer 10 covers the channel region of the sixth active region 16 to form the sixth transistor T6. One end of the sixth active region 16 is the first electrode of the sixth transistor T6. One end of the sixth active region 16 is connected to the second electrode plate C12, that is, the first electrode of the sixth transistor T6 is connected to the second electrode (first node N) of the first capacitor C1. The second electrode of the sixth transistor T6 is connected to the data signal line DATA. When the sixth transistor T6 is turned on, the data signal provided by the data signal line DATA is transmitted to the first node N through the sixth transistor T6. And through the coupling effect of the first capacitor C1, it is transmitted to the gate G of the driving transistor TD to realize the writing of the data signal.

[0134] Continue to refer to Figure 14 One end of the sixth active region 16 is connected to the third connection structure L3 through the twelfth first type via ILD12.

[0135] Specifically, the twelfth type-1 via ILD12 penetrates the first insulating layer 21, the third insulating layer 23, the fourth insulating layer 24, and the fifth insulating layer 25. Simultaneously, the orthographic projection of the third connection structure L3 on the substrate at least partially overlaps with the orthographic projection of the twelfth type-1 via ILD12 on the substrate, and the orthographic projection of the twelfth type-1 via ILD12 on the substrate at least partially overlaps with the orthographic projection of one end of the sixth active region 16 on the substrate. When a conductive layer connection is present within the twelfth type-1 via ILD12, one end of the sixth active region 16 is connected to the third connection structure L3. The third connection structure L3 is connected to the second electrode C12 through the seventh type-1 via ILD7, thereby allowing one end of the sixth active region 16 to be connected to the second electrode C12. This simplifies the connection line between the first electrode of the sixth transistor T6 and the first node N, which is beneficial for improving the PPI of the display panel.

[0136] Continue to refer to Figures 1 to 10 The fifth conductive layer M5 also includes a data signal line DATA, which is connected to the other end of the sixth active region 16 and is used to provide a data signal to the second electrode of the sixth transistor T6.

[0137] Continue to refer to Figures 1 to 10 The fourth conductive layer M4 also includes a sixth connection structure L6. The data signal line DATA is connected to the other end of the sixth active region 16 through the sixth connection structure L6, which avoids the process difficulty caused by excessive via depth when the data signal line DATA is directly connected to the other end of the sixth active region 16, and at the same time improves the connection reliability between the data signal line DATA and the other end of the sixth active region 16.

[0138] Figure 19 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along JJ', as provided in an embodiment of the present invention. Figure 19 As shown, the sixth connection structure L6 is connected to the other end of the sixth active region 16 through the thirteenth type I via ILD13, and the sixth connection structure L6 is connected to the data signal line DATA through the third type II via PLN3.

[0139] Specifically, the thirteenth type-1 via ILD13 penetrates the first insulating layer 21, the third insulating layer 23, the fourth insulating layer 24, and the fifth insulating layer 25. The orthographic projection of the sixth connection structure L6 on the substrate at least partially overlaps with the orthographic projection of the thirteenth type-1 via ILD13 on the substrate, and the orthographic projection of the thirteenth type-1 via ILD13 on the substrate at least partially overlaps with the orthographic projection of the other end of the sixth active region 16 on the substrate. When conductive material is present within the thirteenth type-1 via ILD13, the sixth connection structure L6 is connected to the other end of the sixth active region 16. The third type-2 via PLN3 penetrates the second insulating layer 22. The orthographic projection of the sixth connection structure L6 on the substrate at least partially overlaps with the orthographic projection of the third type-2 via PLN3 on the substrate, and the orthographic projection of the third type-2 via PLN3 on the substrate at least partially overlaps with the orthographic projection of the data signal line DATA on the substrate. When conductive material is present within the third type-2 via PLN3, the sixth connection structure L6 is connected to the data signal line DATA.

[0140] Continue to refer to Figures 1 to 10 Along the second direction X, the seventh type I via ILD7 is located between the data signal line DATA and the fourth type I via ILD4. This can reduce the coupling effect of the data signal line DATA on the gate G potential of the driving transistor TD, improve the stability of the gate G potential of the driving transistor TD, and improve the crosstalk phenomenon of the display panel.

[0141] Continue to refer to Figures 1 to 10 The third electrode plate C13 includes a first edge P1 and a second edge P2, which are disposed opposite to each other. Both the first edge P1 and the second edge P2 extend along the first direction Y. Along the second direction X, the distance from the first edge P1 to the data signal line DATA is less than the distance from the second edge P2 to the data signal line DATA. The distance from the seventh first type via ILD7 to the first edge P1 is greater than or equal to the distance from the seventh first type via ILD7 to the second edge P2.

[0142] Specifically, along the second direction X, the first edge P1 and the second edge P2 are the left and right edges of the third electrode plate C13. Simultaneously, the first edge P1 is close to the data signal line DATA. The seventh type-1 via ILD7 is located on the side of the third electrode plate C13 closest to the second edge P2. This allows the seventh type-1 via ILD7 to be moved away from the data signal line DATA along the second direction X, reducing the coupling effect of the data signal on the data signal line DATA on the potential of the first node N, improving the potential stability of the first node N, and mitigating crosstalk in the display panel.

[0143] For example, along the second direction X, the minimum distance between the data signal line DATA and the power signal line VDD is greater than or equal to 2.5µm.

[0144] Specifically, along the second direction X, the power signal line VDD has a raised or recessed area, meaning the edges of the power signal line VDD extending along the first direction Y are not on a straight line. Along the second direction X, the minimum distance between the data signal line DATA and the power signal line VDD is the straight-line distance between the raised areas of the data signal line DATA and the power signal line VDD along the second direction X. By setting the minimum distance between the data signal line DATA and the power signal line VDD to be greater than or equal to 2.5µm, the parasitic capacitance between the data signal line DATA and the power signal line VDD can be reduced, which helps to improve crosstalk in the display panel. For example, along the second direction X, the minimum distance between the data signal line DATA and the power signal line VDD is greater than or equal to 5µm.

[0145] Continue to refer to Figures 1 to 10 The sixth transistor, T6, is a dual-gate transistor.

[0146] Specifically, one end of the sixth active region 16 is connected to the first node N. By setting the sixth transistor T6 as a dual-gate transistor, the leakage current from the first node N to the sixth transistor T6 can be reduced, thereby increasing the potential maintenance time of the first node N and improving the display stability of the display panel.

[0147] Figure 20 for Figure 5 A partially enlarged schematic diagram of the display panel is provided. (For example...) Figure 20 As shown, the sixth active region 16 includes a sixth active region A 161, a sixth active region B 162, and a sixth active region C 163 connected in sequence. The sixth active region A 161 and the sixth active region C 163 extend along the first direction Y, and the sixth active region B 162 extends along the second direction X. The sixth gate M16 extends along the second direction X, and the orthographic projection of the sixth gate M16 on the substrate at least partially overlaps with the orthographic projections of the sixth active region A 161 and the sixth active region C 163 on the substrate.

[0148] Specifically, the sixth transistor T6 includes a sixth A transistor T61 and a sixth B transistor T62. The overlapping portion of the orthogonal projection of the sixth gate M16 onto the substrate and the orthogonal projection of the sixth A active region 161 onto the substrate can form the sixth A transistor T61. The overlapping portion of the orthogonal projection of the sixth gate M16 onto the substrate and the orthogonal projection of the sixth C active region 163 onto the substrate can form the sixth B transistor T62. One end of the sixth A active region 161 is connected to one end of the sixth C active region 163 through the sixth B active region 162, that is, the first electrode of the sixth A transistor T61 is connected to the first electrode of the sixth B transistor T62 through the sixth B active region 162, forming a double-gate structure sixth transistor T6.

[0149] Figure 21 This is a partially enlarged schematic diagram of another portion of the display panel provided in an embodiment of the present invention. For example... Figure 21 As shown, the sixth active region 16 includes a connected sixth active region 164 and a sixth active region 165. The sixth active region 164 extends along the first direction Y, and the sixth active region 165 extends along the second direction X. The sixth gate M16 includes an integrated sixth sub-gate M161 and a sixth sub-gate M162. The sixth sub-gate M161 extends along the second direction X, and the orthographic projection of the sixth sub-gate M161 on the substrate at least partially overlaps with the orthographic projection of the sixth active region 164 on the substrate. The sixth sub-gate M162 extends along the first direction Y, and the orthographic projection of the sixth sub-gate M162 on the substrate at least partially overlaps with the orthographic projection of the sixth active region 165 on the substrate.

[0150] Specifically, the sixth transistor T6 includes a sixth A transistor T61 and a sixth B transistor T62. The sixth A transistor T61 is formed by the overlap of the orthogonal projection of the sixth A sub-gate M161 onto the substrate and the orthogonal projection of the sixth D active region 164 onto the substrate. The sixth B sub-gate M162 extends along the first direction Y, and the sixth B transistor T62 is formed by the overlap of the orthogonal projection of the sixth B sub-gate M162 onto the substrate and the orthogonal projection of the sixth E active region 165 onto the substrate. One end of the sixth D active region 164 and one end of the sixth E active region 165 are connected, that is, the first electrode of the sixth A transistor T61 and the first electrode of the sixth B transistor T62 are connected, forming a dual-gate structure sixth transistor T6.

[0151] Continue to refer to Figure 20 and Figure 21The third conductive layer M3 also includes an electrostatic shielding structure DS, which is connected to the third electrode plate C13; the orthographic projection of the electrostatic shielding structure DS on the substrate covers the orthographic projection of the sixth active region 162 on the substrate; or, the connection between the sixth active region 164 and the sixth active region 165 has a sixth connecting active region; the orthographic projection of the electrostatic shielding structure DS on the substrate at least partially covers the orthographic projection of the sixth connecting active region on the substrate.

[0152] Specifically, the voltage on the third plate C13 is a power supply signal with a fixed potential. Connecting the electrostatic shielding structure DS to the third plate C13 allows the electrostatic shielding structure DS to have a fixed potential. Figure 21 In the middle, the electrostatic shielding structure DS covers the sixth active region 162, which is equivalent to the electrostatic shielding structure DS covering the middle node of the sixth transistor T6. This reduces the parasitic capacitance between the data signal line DATA and the first node N, reduces the coupling effect of the data signal on the potential of the first node N, improves the potential stability of the first node N, and improves the crosstalk phenomenon of the display panel.

[0153] Or, in Figure 21 In the diagram, the active layer 10 used for connection between one end of the sixth active region 164 and one end of the sixth active region 165 is the sixth connecting active region. The electrostatic shielding structure DS covers the sixth connecting active region, which is equivalent to the electrostatic shielding structure DS covering the middle node of the sixth transistor T6. This reduces the parasitic capacitance between the data signal line DATA and the first node N, reduces the coupling effect of the data signal on the potential of the first node N, improves the potential stability of the first node N, and improves the crosstalk phenomenon of the display panel.

[0154] Continue to refer to Figure 20 and Figure 21 The electrostatic shielding structure DS and the third electrode plate C13 are integrated into one structure, which can simplify the manufacturing process of the display panel.

[0155] Continue to refer to Figures 1 to 10 Along the first direction Y, the sixth transistor T6 and the first transistor T1 are located on opposite sides of the driving transistor TD, which can increase the distance between different scan signal lines and reduce mutual interference between different scan signals. At the same time, it helps to improve the compactness of the layout of the pixel circuit 100, thereby increasing the PPI of the display panel.

[0156] Continue to refer to Figures 1 to 10 The fourth conductive layer M4 also includes multiple third scan signal lines S3 arranged along the second direction X. Each third scan signal line S3 is connected to two adjacent sixth gates M16. The two adjacent sixth gates M16 are located in the same sub-pixel unit 110.

[0157] Specifically, each third scan signal line S3 is disposed within a sub-pixel unit 110. The third scan signal line S3 and the sixth gate M16 are alternately disposed along the second direction X and are interconnected. Thus, the third scan signal line S3 and the sixth gate M16 form a complete scan signal line, providing a third scan signal for a row of pixel circuits 100.

[0158] Continue to refer to Figures 1 to 10 In different sub-pixel units 110, two adjacent sixth gates M16 are connected, which allows the third scan signal line S3 and the sixth gate M16 to be interconnected along the second direction X, so as to provide a third scan signal for a row pixel circuit 100.

[0159] Figure 22 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along GG' according to an embodiment of the present invention. Figure 22 As shown, the third scan signal line S3 is connected to the two adjacent sixth gates M16 through a first type via ILD.

[0160] Specifically, the first type of via ILD penetrates the first insulating layer 21, the fourth insulating layer 24, and the fifth insulating layer 25. The orthographic projection of each first type of via ILD onto the substrate at least partially overlaps with the orthographic projection of the third scan signal line S3 and the sixth gate M16 onto the substrate. When there is conductive material within the first type of via ILD, the third scan signal line S3 is connected to the two sixth gates M16 respectively.

[0161] Continue to refer to Figures 1 to 10 The third scan signal line S3 is symmetrical about the first initialization signal line VREF1, which simplifies the wiring when connecting the third scan signal line S3 to the two sixth gates M16. It also improves the display panel's layout. Figure 1 This consistency simplifies the manufacturing process of the display panel and improves its display effect.

[0162] Continue to refer to Figures 1 to 10 The pixel circuit 100 also includes a seventh transistor T7; the active layer 10 also includes a seventh active region 17 of the seventh transistor T7, and the first conductive layer M1 also includes a seventh gate M17 of the seventh transistor T7; the orthogonal projection of the seventh gate M17 on the active layer 10 at least partially covers the seventh active region 17; one end of the seventh active region 17 is connected to one end of the driving active region 18.

[0163] Specifically, the orthogonal projection of the seventh gate M17 onto the active layer 10 covers the channel region of the seventh active region 17 to form the seventh transistor T7. One end of the seventh active region 17 can be connected to one end of the driving active region 18 through the heavily doped active layer 10, so that the first electrode of the seventh transistor T7 is connected to the first electrode of the driving transistor TD. The second electrode of the seventh transistor T7 is connected to the first electrode A of the OLED. During the light emission stage, the seventh transistor T7 is turned on, providing a driving current path for the OLED.

[0164] Continue to refer to Figures 1 to 10 Along the first direction Y, the seventh transistor T7 and the sixth transistor T6 are located on the same side of the driving transistor TD, which helps to improve the compactness of the layout of the pixel circuit 100, thereby increasing the PPI of the display panel.

[0165] Continue to refer to Figures 1 to 10 The first conductive layer M1 also includes a light-emitting control signal line EM, which is connected to the seventh gate M17 and is used to control the conduction or cutoff of the seventh transistor T7.

[0166] Continue to refer to Figures 1 to 10 The portion of the light-emitting control signal line EM projected onto the active layer 10 and overlapping with the seventh active region 17 is multiplexed as the seventh gate M17, which simplifies the structure of the first conductive layer M1 and helps to improve the PPI of the display panel.

[0167] Continue to refer to Figure 16 The display panel also includes an anode layer M6, which is disposed on the side of the fifth conductive layer M5 away from the fourth conductive layer M4; the anode layer M6 includes an anode An; the fourth conductive layer M4 also includes a seventh connection structure L7; the other end of the seventh active region 17 is connected to the anode An through the seventh connection structure L7.

[0168] Specifically, the anode An is the first electrode A of the OLED light-emitting device. The other end of the seventh active region 17 is connected to the anode An through the seventh connection structure L7. This avoids the process difficulty caused by excessive via depth when the anode An is directly connected to the other end of the seventh active region 17, and at the same time improves the connection reliability between the anode An and the other end of the seventh active region 17.

[0169] Figure 23 This is a schematic diagram of a cross-sectional structure of a display panel obtained by cutting along HH' according to an embodiment of the present invention. Figure 24 This is a schematic cross-sectional view of a display panel obtained by cutting along II', according to an embodiment of the present invention. (See reference) Figures 1 to 10 , Figure 15 , Figure 16 , Figures 23 to 24The display panel also includes a third type of via Q; the seventh connection structure L7 is connected to the other end of the seventh active region 17 through the fourteenth type of first via ILD14, and the seventh connection structure L7 is connected to the anode An through the fourth type of second via PLN4 and the third type of via Q.

[0170] Specifically, the fourteenth type-1 via ILD14 penetrates the first insulating layer 21, the third insulating layer 23, the fourth insulating layer 24, and the fifth insulating layer 25. The orthographic projection of the seventh connection structure L7 onto the substrate at least partially overlaps with the orthographic projection of the fourteenth type-1 via ILD14 onto the substrate, and the orthographic projection of the fourteenth type-1 via ILD14 onto the substrate at least partially overlaps with the orthographic projection of the other end of the seventh active region 17 onto the substrate. When conductive material is present within the fourteenth type-1 via ILD14, the seventh connection structure L7 is connected to the other end of the seventh active region 17.

[0171] A sixth insulating layer 26 is present between the fifth conductive layer M5 and the anode layer M6. The fifth conductive layer M5 includes an anode structure M51, and a second type via PLN4 penetrates the second insulating layer 22. The orthographic projection of the second type via PLN4 onto the substrate at least partially overlaps with the orthographic projection of the anode structure M51 onto the substrate, and the orthographic projection of the second type via PLN4 onto the substrate at least partially overlaps with the orthographic projection of the seventh connection structure L7 onto the substrate. The seventh connection structure L7 is connected to the anode structure M51. A third type via Q penetrates the sixth insulating layer 26, and the seventh connection structure L7 is connected to the anode An through the fourth second type via PLN4 and the third type via Q.

[0172] Continue to refer to Figures 1 to 10 as well as Figure 15 and Figure 16 The fourth conductive layer M4 also includes a first in-plane signal line FA1, which extends along the second direction X and is disposed on the side of the first initialization signal structure VR1 away from the first scan signal line S1.

[0173] Specifically, the first in-plane signal line FA1 is used to transmit data signals. A first initialization signal structure VR1 is inserted between the first in-plane signal line FA1 and the first scan signal line S1, making the first in-plane signal line FA1 away from the first scan signal line S1. Simultaneously, the first initialization signal structure VR1 has a first initialization signal with a fixed potential, which acts as a shield between the first in-plane signal line FA1 and the first scan signal line S1, reducing the parasitic capacitance between the data signal and the first scan signal line S1. This improves the mura phenomenon, such as slanted bright lines, on the display panel.

[0174] Continue to refer to Figures 1 to 10 as well as Figure 15 and Figure 16The fifth conductive layer M5 also includes a second in-plane signal line FA2, which extends along the first direction Y and is connected to the first in-plane signal line FA1 for transmitting data signals. The first in-plane signal line FA1 extends along the second direction X, and the second in-plane signal line FA2 extends along the first direction Y. The cooperation of the first in-plane signal line FA1 and the second in-plane signal line FA2 can distribute the data signals corresponding to different columns of pixel circuits 100 to different columns of pixel circuits 100, realizing the transmission of in-plane data signals, which helps to reduce the bottom bezel of the display panel. At this time, the first in-plane signal line FA1 and the second in-plane signal line FA2 form a mesh structure, which can reduce the impedance voltage drop of the data signal and help improve the brightness uniformity of the display panel.

[0175] Continue to refer to Figures 1 to 10 as well as Figure 15 and Figure 16 The second inner signal line FA2 is located on the side of the data signal line DATA that is away from the power signal line VDD. At this time, along the second direction X, the second inner signal line FA2 and the first initialization signal line VREF1 are respectively located on both sides of the pixel circuit 100, which is beneficial to improving the brightness uniformity of the display panel.

[0176] Continue to refer to Figures 1 to 10 as well as Figure 15 and Figure 16 The display panel includes multiple second-plane in-plane signal lines FA2 arranged along the second direction Y. Each second-plane in-plane signal line FA2 is connected to the first-plane in-plane signal line FA1 through a fifth second-type via PLN5.

[0177] Continue to refer to Figures 1 to 10 as well as Figure 15 and Figure 16 Along the second direction X, the second in-plane signal line FA2 is disposed between adjacent sub-pixel units 110, and is disposed on both sides of the same pixel circuit 100 as the first initialization signal line VREF1, which is beneficial to improving the brightness consistency of the display panel.

[0178] Continue to refer to Figures 1 to 10 as well as Figure 15 and Figure 16 The display panel includes multiple in-plane signal lines FA1 arranged along the first direction Y. Along the first direction Y, the in-plane signal lines FA1 are positioned between adjacent pixel circuits 100, away from the first scan signal line S1 or the light emission control signal line EM, and also away from the point connected to the anode An (a third-type via Q). This helps reduce the parasitic capacitance between the data signal on the in-plane signal line FA1 and the first scan signal line S1, the light emission control signal line EM, and the anode An, thus improving mura phenomena such as slanted bright lines on the display panel.

[0179] For example, along the first direction Y, the distance between the first in-plane signal line FA1 and the first scan signal line S1 in the next pixel circuit 100 is greater than or equal to 6um, which reduces the parasitic capacitance between the first in-plane signal line FA1 and the first scan signal line S1, and improves the mura phenomenon such as slanted bright lines on the display panel.

[0180] For example, along the first direction Y, the distance between the signal line FA1 in the first surface and the seventh connection structure L7 in the previous pixel circuit 100 is greater than or equal to 6um, which reduces the parasitic capacitance between the signal line FA1 in the first surface and the anode An, and improves the mura phenomenon such as slanted bright lines on the display panel.

[0181] In some embodiments, when setting the first in-plane signal line FA1 and anode An, the overlap area of ​​the first in-plane signal line FA1 and anode An can be reduced along the thickness direction of the display panel. This can also reduce the parasitic capacitance between the first in-plane signal line FA1 and anode An, thereby improving mura phenomena such as slanted bright lines on the display panel.

[0182] Continue to refer to Figures 1 to 10 as well as Figure 15 and Figure 16 The orthographic projection of the anode An onto the fifth conductive layer M5 is symmetrical about the first initialization signal line VREF1 or the second in-plane signal line FA2.

[0183] Specifically, such as Figure 16 As shown, the anode layer M6 includes a first anode An1 and a second anode An2. The orthographic projection of the first anode An1 onto the fifth conductive layer M5 is symmetrical about the first initialization signal line VREF1, and the orthographic projection of the first anode An1 onto the fifth conductive layer M5 is symmetrical about the second in-plane signal line FA2, which can improve the large viewing angle skew of the display panel.

[0184] This invention also provides a display device. Figure 25 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 25 As shown, the display device 2000 includes the display panel 1000 provided in any embodiment of the present invention. Since the display device 2000 includes the display panel 1000 provided in any embodiment of the present invention, it has the same beneficial effects as the display panel 1000 provided in any embodiment of the present invention, and will not be described again here. The display device 2000 can be, for example, any product or component with display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart wearable device, or information kiosks in public lobbies.

[0185] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0186] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, The display panel includes at least one pixel circuit, the pixel circuit including a first transistor connected to a first electrode of a light-emitting device; the display panel further includes: Substrate; An active layer is disposed on one side of the substrate, and the active layer includes a first active region of the first transistor; A first conductive layer is disposed on the side of the active layer away from the substrate. The first conductive layer includes a first gate, and the orthogonal projection of the first gate onto the active layer at least partially covers the first active region. A fifth conductive layer is disposed on the side of the first conductive layer away from the substrate. The fifth conductive layer includes a first initialization signal line that extends along a first direction. The first initialization signal line is connected to one end of the first active region. The first direction is the column direction of the pixel circuit arrangement.

2. The display panel according to claim 1, characterized in that, The display panel includes a plurality of sub-pixel units arranged along a second direction, and each sub-pixel unit includes a first pixel circuit and a second pixel circuit arranged adjacent to each other along the second direction. The fifth conductive layer is provided with at least two first initialization signal lines, each of which is disposed between the first pixel circuit and the second pixel circuit within a sub-pixel unit; the second direction is the row direction of the pixel circuit arrangement. Preferably, the first pixel circuit and the second pixel circuit are symmetrical about the first initialization signal line.

3. The display panel according to claim 2, characterized in that, The display panel also includes: A third conductive layer is disposed between the first conductive layer and the fifth conductive layer. The third conductive layer includes a first initialization signal structure, which is connected to the first initialization signal line. Preferably, the first initialization signal structure extends along the second direction; Preferably, the first initialization signal structure is connected to each of the first initialization signal lines; Preferably, within the sub-pixel unit, the structure of the first initialization signal is symmetrical about the first initialization signal line; Preferably, the display panel includes a plurality of first initialization signal structures arranged along the first direction, and each first initialization signal structure is connected to a first initialization signal line; Preferably, the display panel further includes: A fourth conductive layer is disposed between the first conductive layer and the fifth conductive layer. The fourth conductive layer includes a first connection structure, and the first initialization signal structure is connected to the first initialization signal line through the first connection structure. Preferably, the first connection structure is disposed between adjacent pixel circuits within the sub-pixel unit; Preferably, the display panel further includes a first type of via and a second type of via, the first connection structure is connected to the first initialization signal structure through the first first type of via, and the first connection structure is connected to the first initialization signal line through the first second type of via; Preferably, the first connection structure is connected to one end of the first active region through a second first-type via.

4. The display panel according to claim 3, characterized in that, The pixel circuit also includes a second transistor and a third transistor; The active layer further includes a second active region of the second transistor and a third active region of the third transistor; along the second direction, at least a portion of the first active region, the second active region, and the third active region are located on the same straight line; The first conductive layer further includes a second gate and a third gate; the orthographic projection of the second gate onto the active layer at least partially covers the second active region, and the orthographic projection of the third gate onto the active layer at least partially covers the third active region; Along the second direction, at least a portion of the first gate, the second gate, and the third gate are located on the same straight line; Preferably, the first conductive layer further includes a first scan signal line, which is connected to the first gate, the second gate, and the third gate; Preferably, the portion of the first scan signal line that overlaps with the first active region on the active layer is multiplexed as the first gate. Preferably, the portion of the first scan signal line that overlaps with the second active region on the orthographic projection of the first scan signal line on the active layer is multiplexed as the second gate. Preferably, the portion of the first scan signal line that overlaps with the third active region on the orthographic projection of the first scan signal line on the active layer is multiplexed as the third gate. Preferably, the first scan signal line extends along the second direction and is a straight line; Preferably, the second transistor is a dual-gate transistor; Preferably, the second active region includes a second active region A, a second active region B, and a second active region C connected in sequence, the second active region A and the second active region C extending along the first direction, and the second active region B extending along the second direction; the second gate extends along the second direction, and the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projections of the second active region A and the second active region C on the substrate; Preferably, the orthographic projection of the first initialization signal structure onto the substrate at least partially covers the orthographic projection of the second active region onto the substrate; Preferably, the third transistor is a dual-gate transistor; Preferably, the third active region includes a third active region A, a third active region B, and a third active region C connected in sequence, the third active region A and the third active region C extending along the first direction, and the third active region B extending along the second direction; the third gate extends along the second direction, and the orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projections of the third active region A and the third active region C on the substrate; Preferably, the orthographic projection of the first initialization signal structure on the substrate at least partially covers the orthographic projection of the third active region on the substrate; Preferably, the pixel circuit further includes a driving transistor; the active layer further includes a driving active region of the driving transistor, the first conductive layer further includes a driving gate, and the orthographic projection of the driving gate on the active layer at least partially covers the driving active region; the driving gate is connected to one end of the third active region. Preferably, the fourth conductive layer further includes a second connection structure, through which the driving gate is connected to one end of the third active region; Preferably, the second connection structure is connected to one end of the third active region through a third first-type via, and the second connection structure is connected to the driving gate through a fourth first-type via; Preferably, along the first direction, the first transistor, the second transistor, and the third transistor are disposed on the same side of the driving transistor; Preferably, the pixel circuit further includes a first capacitor, the first capacitor including a first electrode, and the driving gate is multiplexed as the first electrode; Preferably, the display panel further includes: A second conductive layer is disposed between the first conductive layer and the third conductive layer; The second conductive layer includes the second electrode of the first capacitor, wherein the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate; Preferably, the third conductive layer further includes a third electrode plate, the orthographic projection of the third electrode plate on the substrate at least partially overlapping the orthographic projection of the second electrode plate on the substrate; Preferably, the orthographic projection of the second electrode plate on the substrate covers the orthographic projection of the fourth type of via on the substrate; Preferably, the orthographic projection of the third electrode plate on the substrate covers the orthographic projection of the fourth first type of via on the substrate.

5. The display panel according to claim 4, characterized in that, The fourth conductive layer includes a second initialization signal line; the second initialization signal line is connected to the other end of the third active region. Preferably, the second initialization signal line includes a plurality of second initialization signal structures arranged along the second direction; each of the second initialization signal structures is connected to the other end of the third active region in two adjacent pixel circuits, and the two adjacent pixel circuits are respectively the first pixel circuit and the second pixel circuit in a sub-pixel unit; Preferably, the structure of the second initialization signal is symmetrical about the first initialization signal line; Preferably, the second conductive layer further includes a third initialization signal structure, and adjacent second initialization signal structures are connected through one of the third initialization signal structures; Preferably, the second initialization signal structure is connected to the third initialization signal structure through a fifth of the first type of via; Preferably, the third initialization signal structure extends along the second direction; Preferably, the third initialization signal structure is symmetrical about the first initialization signal line.

6. The display panel according to claim 4, characterized in that, The pixel circuit also includes a fourth transistor; The active layer further includes a fourth active region of the fourth transistor, and the first conductive layer further includes a fourth gate of the fourth transistor. The orthographic projection of the fourth gate onto the active layer at least partially covers the fourth active region. One end of the fourth active region is connected to one end of the third active region, and the other end of the fourth active region is connected to one end of the driving active region. Preferably, one end of the third active region has a third connecting active region, and the orthographic projection of the third initialization signal structure on the substrate at least partially covers the orthographic projection of the third connecting active region on the substrate; Preferably, the first conductive layer further includes a second scan signal line, which is connected to the fourth gate. Preferably, the portion of the second scan signal line that overlaps with the fourth active region on the active layer is multiplexed as the fourth gate. Preferably, the pixel circuit further includes a fifth transistor; The active layer further includes a fifth active region of the fifth transistor, and the first conductive layer further includes a fifth gate of the fifth transistor. The orthogonal projection of the fifth gate onto the active layer at least partially covers the fifth active region. One end of the fifth active region is connected to one end of the second active region, one end of the fifth active region is connected to the second electrode plate, and the other end of the fifth active region is connected to the other end of the driving active region. Preferably, one end of the second active region has a second connected active region, and the orthographic projection of the third initialization signal structure on the substrate at least partially covers the orthographic projection of the second connected active region on the substrate; Preferably, the fourth conductive layer further includes a third connection structure, and one end of the fifth active region is connected to the second electrode plate through the third connection structure; Preferably, the third connection structure is connected to one end of the fifth active region through the sixth first type of via, and the third connection structure is connected to the second electrode plate through the seventh first type of via; Preferably, the orthographic projection of the third electrode plate on the substrate covers the orthographic projection of the seventh type of via on the substrate; Preferably, along the second direction, the fourth and seventh first-type vias are arranged adjacent to each other; Preferably, the second scan signal line is connected to the fifth gate; Preferably, the portion of the second scan signal line that overlaps with the fifth active region on the active layer is multiplexed as the fifth gate. Preferably, the second scan signal line extends along the second direction; Preferably, the fourth active region and the fifth active region are arranged along the second direction; Preferably, the fourth transistor is a dual-gate transistor; Preferably, the fourth active region includes a fourth active region A and a fourth active region B connected together, the fourth active region A extending along the first direction and the fourth active region B extending along the second direction; the fourth gate includes an integrated fourth sub-gate A and a fourth sub-gate B, the fourth sub-gate A extending along the second direction and the fourth sub-gate B extending along the first direction; the orthographic projection of the fourth sub-gate A on the substrate at least partially overlaps with the orthographic projection of the fourth active region A on the substrate; the orthographic projection of the fourth sub-gate B on the substrate at least partially overlaps with the orthographic projection of the fourth active region B on the substrate; Preferably, the connection between the fourth active region A and the fourth active region B has a fourth connecting active region, and the orthographic projection of the first initialization signal structure on the substrate at least partially covers the orthographic projection of the fourth connecting active region on the substrate. Preferably, the fifth transistor is a dual-gate transistor; Preferably, the fifth active region includes a fifth active region A and a fifth active region B connected together, the fifth active region A extending along the first direction and the fifth active region B extending along the second direction; the fifth gate includes an integrated fifth sub-gate A and a fifth sub-gate B, the fifth sub-gate A extending along the second direction and the fifth sub-gate B extending along the first direction; the orthographic projection of the fifth sub-gate A on the substrate at least partially overlaps with the orthographic projection of the fifth active region A on the substrate; the orthographic projection of the fifth sub-gate B on the substrate at least partially overlaps with the orthographic projection of the fifth active region B on the substrate; Preferably, along the first direction, the fourth transistor and the fifth transistor are located on the same side of the driving transistor; Preferably, along the first direction, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are disposed on the same side of the driving transistor; Preferably, along the first direction, the second scan signal line is located between the driving active region and the first scan signal line; Preferably, along the first direction, the second initialization signal line is located between the first scan signal line and the second scan signal line; Preferably, along the first direction, the first initialization signal structure is located on the side of the first scan signal line away from the second scan signal line.

7. The display panel according to claim 6, characterized in that, The fifth conductive layer also includes a power signal line, which is connected to the third electrode plate, the other end of the driving active region, the other end of the second active region, and the other end of the fifth active region. Preferably, the fourth conductive layer further includes a fourth connection structure and a fifth connection structure, the third electrode plate is connected to the other end of the fifth active region and the other end of the second active region through the fourth connection structure, and the third electrode plate is connected to the power signal line through the fifth connection structure; Preferably, the fourth connection structure is connected to the other end of the second active region through the eighth first type via, the fourth connection structure is connected to the other end of the driving active region through the ninth first type via, and the fourth connection structure is connected to the third electrode plate through the tenth first type via. Preferably, the connection between the fifth active region A and the fifth active region B has a fifth connecting active region, and the orthographic projection of the fourth connecting structure on the substrate at least partially covers the orthographic projection of the fifth connecting active region on the substrate; Preferably, the fifth connection structure is connected to the third electrode plate through the eleventh first type via, and the fifth connection structure is connected to the power signal line through the second second type via; Preferably, the orthographic projection of the power signal line on the substrate covers the orthographic projection of the fourth type-1 via on the substrate; Preferably, the orthographic projection of the power signal line on the substrate covers the orthographic projection of the seventh type-1 via on the substrate; Preferably, the display panel includes a plurality of power signal lines, which extend along the first direction and are arranged along the second direction; Preferably, the display panel includes a plurality of fifth connection structures arranged along the second direction, each fifth connection structure being connected to a third plate in two adjacent pixel circuits; Preferably, the fifth connection structure is connected to two adjacent power signal lines; Preferably, the fifth connecting structure extends along the second direction; Preferably, the fifth connection structure is symmetrical about the first initialization signal line.

8. The display panel according to claim 6, characterized in that, The pixel circuit also includes a sixth transistor; The active layer further includes a sixth active region of the sixth transistor, and the first conductive layer further includes a sixth gate of the sixth transistor; the orthographic projection of the sixth gate on the active layer at least partially covers the sixth active region, and one end of the sixth active region is connected to the second electrode plate. Preferably, one end of the sixth active region is connected to the third connection structure through the twelfth first type of via; Preferably, the fifth conductive layer further includes a data signal line, which is connected to the other end of the sixth active region; Preferably, the fourth conductive layer further includes a sixth connection structure, through which the data signal line is connected to the other end of the sixth active region; Preferably, the sixth connection structure is connected to the other end of the sixth active region through a thirteenth first-type via, and the sixth connection structure is connected to the data signal line through a third second-type via; Preferably, along the second direction, the seventh of the first type of via is located between the data signal line and the fourth of the first type of via; Preferably, the third electrode plate includes a first edge and a second edge, the first edge and the second edge are disposed opposite to each other, and both the first edge and the second edge extend along the first direction; along the second direction, the distance from the first edge to the data signal line is less than the distance from the second edge to the data signal line; the distance from the seventh first type via to the first edge is greater than or equal to the distance from the seventh first type via to the second edge; Preferably, along the second direction, the minimum distance between the data signal line and the power signal line is greater than or equal to 2.5 μm; Preferably, along the second direction, the minimum distance between the data signal line and the power signal line is greater than or equal to 5 μm; Preferably, the sixth transistor is a dual-gate transistor; Preferably, the sixth active region includes a sixth active region A, a sixth active region B, and a sixth active region C connected in sequence, the sixth active region A and the sixth active region C extending along the first direction, and the sixth active region B extending along the second direction; the sixth gate extends along the second direction, and the orthographic projection of the sixth gate on the substrate at least partially overlaps with the orthographic projections of the sixth active region A and the sixth active region C on the substrate; Alternatively, the sixth active region includes a connected sixth active region D and a sixth active region E, the sixth active region D extending along the first direction, the sixth active region E extending along the second direction, and the sixth gate including an integrated sixth sub-gate A and a sixth sub-gate B, the sixth sub-gate A extending along the second direction, the orthographic projection of the sixth sub-gate A onto the substrate at least partially overlapping the orthographic projection of the sixth active region D onto the substrate; the sixth sub-gate B extending along the first direction, the orthographic projection of the sixth sub-gate B onto the substrate at least partially overlapping the orthographic projection of the sixth active region E onto the substrate; Preferably, the third conductive layer further includes an electrostatic shielding structure, which is connected to the third electrode plate; the orthographic projection of the electrostatic shielding structure on the substrate covers the orthographic projection of the sixth active region on the substrate. Alternatively, the connection between the sixth active region D and the sixth active region E has a sixth connecting active region; the orthographic projection of the electrostatic shielding structure on the substrate at least partially covers the orthographic projection of the sixth connecting active region on the substrate; Preferably, the electrostatic shielding structure and the third electrode plate are an integrated structure; Preferably, along the first direction, the sixth transistor and the first transistor are located on opposite sides of the driving transistor; Preferably, the fourth conductive layer further includes a plurality of third scan signal lines arranged along the second direction, each of the third scan signal lines being connected to two adjacent sixth gates; the two adjacent sixth gates are located within the same sub-pixel unit; Preferably, in different sub-pixel units, two adjacent sixth gates are connected; Preferably, the third scan signal line is connected to two adjacent sixth gates through a first type of via; Preferably, the third scan signal line is symmetrical about the first initialization signal line; Preferably, the pixel circuit further includes a seventh transistor; the active layer further includes a seventh active region of the seventh transistor, and the first conductive layer further includes a seventh gate of the seventh transistor; The orthogonal projection of the seventh gate onto the active layer at least partially covers the seventh active region; one end of the seventh active region is connected to one end of the driving active region; Preferably, along the first direction, the seventh transistor and the sixth transistor are located on the same side of the driving transistor; Preferably, the first conductive layer further includes a light-emitting control signal line, which is connected to the seventh gate. Preferably, the portion of the light-emitting control signal line whose orthogonal projection on the active layer overlaps with the seventh active region is multiplexed as the seventh gate. Preferably, the display panel further includes an anode layer disposed on the side of the fifth conductive layer away from the fourth conductive layer; the anode layer includes an anode; the fourth conductive layer further includes a seventh connection structure; the other end of the seventh active region is connected to the anode through the seventh connection structure; Preferably, the display panel further includes a third type of via; the seventh connection structure is connected to the other end of the seventh active region through the fourteenth first type of via, and the seventh connection structure is connected to the anode through the fourth second type of via and the third type of via.

9. The display panel according to claim 8, characterized in that, The fourth conductive layer further includes a first in-plane signal line, which extends along the second direction and is disposed on the side of the first initialization signal structure away from the first scan signal line. Preferably, the fifth conductive layer further includes a second in-plane signal line, the second in-plane signal line extending along the first direction, and the second in-plane signal line being connected to the first in-plane signal line; Preferably, the second in-plane signal line is located on the side of the data signal line away from the power signal line; Preferably, the display panel includes a plurality of second in-plane signal lines arranged along the second direction, and each second in-plane signal line is connected to the first in-plane signal line through a fifth second type of via; Preferably, along the second direction, the second in-plane signal line is disposed between adjacent sub-pixel units; Preferably, the display panel includes a plurality of first in-plane signal lines arranged along the first direction, and the first in-plane signal lines are disposed between adjacent pixel circuits along the first direction; Preferably, along the first direction, the distance between the signal line in the first plane and the first scan signal line in the next pixel circuit is greater than or equal to 6 μm; Preferably, along the first direction, the distance between the signal line in the first plane and the seventh connection structure in the previous pixel circuit is greater than or equal to 6 μm; Preferably, the orthographic projection of the anode onto the fifth conductive layer is symmetrical about the first initialization signal line or the second in-plane signal line.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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