A preparation process of a semiconductor refrigeration sheet

Abstract

A fabrication process for a semiconductor refrigeration chip includes the following steps: S1, wafer pretreatment: cleaning and pretreatment of bismuth telluride wafers to produce clean wafers; S2, wafer surface metallization and etching; S3, wafer-level array welding and dicing: P-type and N-type bismuth telluride wafers are stacked alternately and directly butt-welded to form a PN wafer array, and then the welded PN wafer array is diced to obtain the required die array units; S4, device assembly and packaging. This invention directly completes the welding and assembly of P- and N-type bismuth telluride wafers at the whole wafer level, significantly reducing assembly steps and saving manufacturing costs. The wafer-level metal butt welding ensures the uniformity and integrity of the contact surface, significantly reducing the conduction impedance between P-type and N-type bismuth telluride, thereby improving the thermoelectric conversion and cooling efficiency of the entire device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials and thermoelectric conversion device manufacturing technology, specifically to a wafer-level fabrication process for a semiconductor cooling chip (or thermoelectric conversion device). Background Technology

[0002] Bismuth telluride can be used to prepare thermoelectric power generation devices as well as refrigeration devices. Thermoelectric power generation is a way to convert heat energy (temperature difference) into electrical energy using semiconductor thermoelectric conversion materials. It is of great significance for alleviating and solving the current growing energy pressure and environmental pollution. Thermoelectric power generation systems have the characteristics of compact structure, reliable performance, no noise, no wear, no leakage, good mobility and suitable for low energy density recycling. Bismuth telluride is currently the best performing and most widely used thermoelectric refrigeration material near room temperature. Based on the Seebeck effect and Peltier effect, it realizes solid-state refrigeration / heating without moving parts. These devices are also commonly referred to as semiconductor refrigeration chips, TECs or thermoelectric coolers.

[0003] The current process flow for cooling chips is typically as follows: wafers are metallized into dies and then diced; a ceramic substrate is then metallized to fabricate electrodes; multiple PN wafer dies are then individually soldered into a cooling device; and finally, wire bonding is performed. In the current process, each die needs to be assembled and soldered onto a substrate to form a cooling device. The entire process is very complex, and the independent soldering of each die results in high contact resistance, affecting the cooling efficiency of the final device. Summary of the Invention

[0004] To address the shortcomings of existing technologies where single bismuth telluride (STM) chips are complex to weld onto a substrate to form a cooling device and suffer from high contact resistance, this invention provides a fabrication process for a semiconductor cooling chip. This process simplifies the manufacturing process by completing the welding and forming of a chip array at the wafer level, effectively reducing the contact resistance between P / N type STM chips and thus significantly improving cooling efficiency. To solve the above-mentioned technical problems, the specific technical solution adopted by the present invention is as follows: A process flow for fabricating a semiconductor cooling chip, the method comprising the following steps: S1. Wafer pretreatment: The bismuth telluride wafer is cleaned and pretreated to produce a clean wafer; S2. Wafer surface metallization and etching: The bismuth telluride wafer surface is metallized to form a metallized wafer. The excess metal layer on the wafer surface is removed by etching to form a preset electrode pattern. S3. Wafer-level array welding and cutting: P-type bismuth telluride wafers and N-type bismuth telluride wafers are stacked and arranged alternately, and directly welded together to form a PN wafer array. Then, the welded PN wafer array is cut to obtain the required grain array unit. S4. Device Assembly and Packaging: The cut die array is soldered into a cooling device as needed and then wire-packaged.

[0005] Preferably, the cleaning and pretreatment in step S1 specifically includes: degreasing: immersing the bismuth telluride wafer in a special degreasing powder solution at 60±5℃ for 8-10 minutes; Roughening: The wafer is treated with a roughening solution containing chromic acid and sulfuric acid (or pre-roughening with organic solvents) to form a porous structure on the surface of the bismuth telluride wafer, thereby increasing the adhesion of subsequent coatings. Neutralization and activation: The residual oxidant is neutralized using hydrochloric acid and sodium sulfite solution, followed by activation of the bismuth telluride wafer surface using colloidal palladium in preparation for electroless plating. Preferably, the metallization operation in step S2 specifically includes: performing electroless nickel plating and electroplating tin plating sequentially on the surface of the pre-cleaned bismuth telluride wafer.

[0006] Preferably, the thickness of the electroless nickel plating is 3 μm, and the thickness of the electroplated tin plating is 3.5 μm. Preferably, the welding method in step S3 is metal-to-metal bonding, that is, directly welding and bonding the metal layer on the surface of the P-type bismuth telluride wafer to the metal layer on the surface of the N-type bismuth telluride wafer.

[0007] Compared with existing technologies, the present invention has the following advantages: it breaks through the cumbersome process of cutting wafers into individual dies and then arranging and welding them to a ceramic substrate one by one. The present invention directly completes the welding and assembly of P-type and N-type bismuth telluride wafers at the whole wafer level, which greatly reduces the assembly steps and saves manufacturing costs; the wafer-level metal butt welding ensures the uniformity and integrity of the contact surface, avoids the interface defects caused by independent welding of individual dies, and significantly reduces the conduction resistance between P-type and N-type bismuth telluride, thereby improving the thermoelectric conversion and cooling efficiency of the entire device. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the metallization and etching process of a single bismuth telluride cooling grain in an embodiment of the present invention. Figure 2 This is a schematic diagram of a complete wafer after the metal plating and etching processes are completed in an embodiment of the present invention; Figure 3 for Figure 2 A magnified schematic diagram of a portion of the middle wafer; Figure 4This is a schematic cross-sectional view of multiple P-type and N-type wafers alternately welded together in an embodiment of the present invention; Figure 5 This is a schematic diagram of the connection structure of a single cooling PN grain array formed after the wafer is cut in an embodiment of the present invention. Detailed Implementation

[0009] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the core steps in the fabrication of the refrigeration device and the thermoelectric conversion device (power generation) are the same; this embodiment uses the fabrication of the refrigeration device as an example for illustration.

[0010] As described in the background art, the traditional process route is: wafer → metallization and dicing → metallization of ceramic substrate to form electrodes → PN die array arranged and soldered into a cooling device → wire packaging; The present invention provides an improved semiconductor cooling chip process flow, the core process route of which is: wafer → wafer-level metallization → PN wafer-level soldering into an array → dicing the soldered array → soldering the die array into a cooling device → wire packaging.

[0011] The specific steps are as follows: Step S1, wafer cleaning and pretreatment: The first step is to clean the surface of the bismuth telluride wafer, which includes the following sub-steps: 1) Degreasing: Use a special degreasing powder solution to soak for 8-10 minutes at a temperature of 60±5℃ to remove surface oil stains; 2) Roughening: The wafer surface is treated with a roughening solution containing chromic acid and sulfuric acid (or organic solvent pre-roughening) to form a micro-porous structure on the bismuth telluride surface, thereby greatly increasing the mechanical adhesion of the subsequent metal coating. 3) Neutralization and activation: Hydrochloric acid and sodium sulfite solution are used to neutralize the residual oxidant on the surface, and then colloidal palladium solution is used to activate the surface, providing a catalytic core for the subsequent electroless plating process.

[0012] Step S2, wafer surface metallization and etching, such as Figure 1 As shown, taking a bismuth telluride unit region with a size of 5mm x 5mm as an example, after cleaning pretreatment, nickel (Ni) is first plated on both sides of the wafer, with the plating thickness controlled at approximately 3µm; then tin (Sn) is plated on it, with the plating thickness controlled at approximately 3.5µm. After the metal plating is completed, excess metal needs to be removed through etching to form the correct series electrode structure. Specifically, a portion of the nickel (Ni) and tin (Sn) plating is removed from both the front and back sides (specifically, a 5mm x 3mm area is removed), leaving a 5mm x 2mm metal contact area. To achieve series connectivity between adjacent dies, an alternating etching method is used, removing the lower edge from the front side and the upper edge from the back side, to complete the electrode fabrication of the cooling dies on the wafer. Figure 2 and Figure 3 The image shows the complete wafer after the metallization and etching processes are completed, along with a magnified view of its local structure. The yellow area in the image represents the portion of the retained metal coating.

[0013] Step S3, Wafer-level Array Welding and Cutting: P-type and N-type bismuth telluride wafer-level welding. This is a key step in this invention. After the above preparation is completed, instead of cutting, the P-type bismuth telluride wafers and N-type bismuth telluride wafers are directly laminated at the wafer level in a staggered manner. During welding, it is ensured that the reserved metal areas on the surfaces of the P-type and N-type bismuth telluride wafers are precisely aligned and fused together; for example... Figure 4 As shown, four bismuth telluride wafers can be welded together in this metal-to-metal manner to form a large-area PN wafer array entity, with two P-type and two N-type bismuth telluride wafers, which are alternately butted together in sequence. The aforementioned firmly soldered PN wafer array is then cut to the size of a single die (5mm*5mm). Since the P-type and N-type bismuth telluride elements have already formed a reliable physical and electrical connection through the internal metal layer before cutting, the resulting wafers are directly obtained after cutting. Figure 5 The cooling grain array structure shown in the figure (blue represents P-type, red represents N-type, yellow represents the metal layer connecting them, and each grain array also has four bismuth telluride units).

[0014] Step S4, Device Assembly and Packaging: These formed die arrays are soldered onto the ceramic substrate as needed to form a cooling device, and the final lead-packaged test is completed.

[0015] In summary, this invention directly completes the welding and assembly of P-type and N-type bismuth telluride wafers at the whole wafer level, which greatly reduces assembly steps and saves manufacturing costs. The wafer-level metal butt welding ensures the uniformity and integrity of the contact surface, significantly reduces the conduction resistance between P-type and N-type bismuth telluride, thereby improving the thermoelectric conversion and cooling efficiency of the entire device.

[0016] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A process flow for fabricating a semiconductor cooling chip, the method comprising the following steps: S1. Wafer pretreatment: The bismuth telluride wafer is cleaned and pretreated to produce a clean wafer; S2. Wafer surface metallization and etching: The bismuth telluride wafer surface is metallized to form a metallized wafer. The excess metal layer on the wafer surface is removed by etching to form a preset electrode pattern. S3. Wafer-level array welding and cutting: P-type bismuth telluride wafers and N-type bismuth telluride wafers are stacked and arranged alternately, and directly welded together to form a PN wafer array. Then, the welded PN wafer array is cut to obtain the required grain array unit. S4. Device Assembly and Packaging: The cut die array is soldered into a cooling device as needed and then wire-packaged.

2. The fabrication process of a semiconductor cooling chip according to claim 1, characterized in that, The cleaning and pretreatment in step S1 specifically includes: degreasing: immersing the bismuth telluride wafer in a special degreasing powder solution at 60±5℃ for 8-10 minutes; Roughening: A roughening solution containing chromic acid and sulfuric acid is used to treat the bismuth telluride wafer surface to form a porous structure, which increases the adhesion of subsequent coatings. Neutralization and activation: The residual oxidant is neutralized using hydrochloric acid and sodium sulfite solution, followed by activation of the bismuth telluride wafer surface using colloidal palladium in preparation for electroless plating.

3. The fabrication process of a semiconductor cooling chip according to claim 1, characterized in that, The metallization operation in step S2 specifically includes: sequentially plating nickel and tin on the surface of the pre-cleaned bismuth telluride wafer.

4. The fabrication process of a semiconductor cooling chip according to claim 3, characterized in that, The nickel plating thickness is 3µm, and the tin plating thickness is 3.5µm.

5. The fabrication process of a semiconductor cooling chip according to claim 1, characterized in that, The welding method in step S3 is metal-to-metal bonding, that is, directly welding and bonding the metal layer on the surface of the P-type bismuth telluride wafer to the metal layer on the surface of the N-type bismuth telluride wafer.

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