Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the structure comprising: a substrate, a lower metal layer is formed in the substrate, and the substrate exposes a top surface of the lower metal layer, the substrate comprises a first region, the first region is used for forming a memory device; a bottom electrode layer, extending along a longitudinal direction and standing on the lower metal layer of the first region, and directly contacting with the lower metal layer for electrical connection, wherein the longitudinal direction is a direction perpendicular to the surface of the substrate; a resistive switching layer, conformally covering the sidewall and the top surface of the bottom electrode layer, and extending to cover the substrate on both sides of the bottom electrode layer; a top electrode layer, conformally covering the resistive switching layer; and an upper metal layer, located on the top electrode layer and directly contacting with the top electrode layer for electrical connection. The present disclosure is conducive to achieving the goal of compatibility of memory cells and logic processes.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of semiconductor technology, memory devices are playing an increasingly important role in integrated circuits. Among the many new non-volatile memory technologies, resistive random access memory (RRAM) has attracted widespread attention in the industry due to its advantages such as simple structure, small footprint, fast read / write speed, and low power consumption.

[0003] A typical RRAM device structure usually includes a bottom electrode, a resistive switching layer, and a top electrode. The bottom and top electrodes are typically made of conductive materials such as titanium nitride (TiN), while the resistive switching layer is made of a metal oxide material with resistive switching properties (such as hafnium oxide or tantalum oxide). This device is generally integrated between metal interconnect layers, with its bottom and top electrodes connected via lower metal interconnects and upper vias, respectively, thus achieving electrical connection to external circuits.

[0004] However, as semiconductor process nodes continue to shrink, integrated circuits are placing increasingly higher demands on the size and integration density of RRAM devices. Summary of the Invention

[0005] The problem addressed by the embodiments of this disclosure is to provide a semiconductor structure and a method for forming the same, which is beneficial for achieving the goal of compatibility between memory cells and logic processes.

[0006] To address the aforementioned problems, this disclosure provides a semiconductor structure comprising: a substrate having a lower metal layer formed therein, with the substrate exposing the top surface of the lower metal layer; the substrate including a first region for forming a memory device; a bottom electrode layer extending longitudinally and protruding from the lower metal layer in the first region, and directly contacting the lower metal layer for electrical connection, wherein the longitudinal direction is perpendicular to the substrate surface; a resistive switching layer conformally covering the sidewalls and top surface of the bottom electrode layer, and extending to cover the substrate on both sides of the bottom electrode layer; a top electrode layer conformally covering the resistive switching layer; and an upper metal layer located on the top electrode layer and directly contacting the top electrode layer for electrical connection.

[0007] Optionally, the substrate further includes a second region for forming interconnect wires; the semiconductor structure further includes: an interconnect via structure extending longitudinally and protruding from the lower metal layer of the second region, and in direct contact with the lower metal layer for electrical connection; an upper metal layer is also located on the interconnect via structure and in direct contact with the interconnect via structure for electrical connection.

[0008] Optionally, the memory cell consisting of the bottom electrode layer, resistive switching layer, and top electrode layer is on the same layer as the interconnect via structure.

[0009] Optionally, the semiconductor structure further includes: an isolation layer covering the substrate on both sides of the bottom electrode layer; and a resistive switching layer extending to cover the isolation layer on both sides of the bottom electrode layer.

[0010] Optionally, the top electrode layer conformally covers the resistive switching layer, so that the top electrode layer has a shape that protrudes from the center to both sides; the semiconductor structure also includes: a mask layer located on the top electrode layer on both sides of the protruding top electrode layer, and covering the sidewalls of the top electrode layer.

[0011] Optionally, the semiconductor structure may also include a protective layer that covers the sidewalls of the mask layer and extends longitudinally to cover the ends of the top electrode layer and the resistive switching layer.

[0012] Optionally, the upper metal layer also covers the top of the mask layer; the protective layer also extends longitudinally to cover the sidewalls of the upper metal layer.

[0013] This disclosure also provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a lower metal layer is formed in the substrate and the substrate exposes the top surface of the lower metal layer, the substrate including a first region for forming a memory device; forming a bottom electrode layer extending longitudinally and protruding from the lower metal layer in the first region, the bottom electrode layer being in direct contact with the lower metal layer for electrical connection, wherein the longitudinal direction is perpendicular to the surface of the substrate; forming a resistive switching layer conformally covering the sidewalls and top surface of the bottom electrode layer and extending to cover the substrate on both sides of the bottom electrode layer; forming a top electrode layer conformally covering the resistive switching layer; removing portions of the top electrode layer, resistive switching layer and bottom electrode layer on the substrate on both sides of the bottom electrode layer, retaining the remaining top electrode layer, resistive switching layer and bottom electrode layer to form a memory cell; and forming an upper metal layer on the top electrode layer, the upper metal layer being in direct contact with the top electrode layer for electrical connection.

[0014] Optionally, in the step of providing a substrate, the substrate further includes a second region for forming interconnect wires; in the step of forming an upper metal layer on the top electrode layer, the upper metal layer being in direct contact with the top electrode layer for electrical connection, the step further includes: forming an interconnect via structure extending longitudinally and protruding on a lower metal layer in the second region, and an upper metal layer located on the interconnect via structure, the interconnect via structure being in direct contact with the lower metal layer for electrical connection.

[0015] Optionally, in the step of forming a via structure extending longitudinally and protruding on the lower metal layer of the second region, and an upper metal layer located on the via structure, the memory cell composed of the bottom electrode layer, the resistive switching layer, and the top electrode layer is on the same layer as the via structure.

[0016] Optionally, the step of forming a bottom electrode layer that extends longitudinally and protrudes from the lower metal layer of the first region includes: forming an isolation layer covering the substrate; forming a via that penetrates the isolation layer and exposes the top surface of the lower metal layer of the first region; and filling the via to form the bottom electrode layer.

[0017] Optionally, before forming a resistive switching layer that conformally covers the sidewalls and top surface of the bottom electrode layer and extends to cover the substrates on both sides of the bottom electrode layer, the method further includes: removing a portion of the thickness of the isolation layer; in the step of forming a resistive switching layer that conformally covers the sidewalls and top surface of the bottom electrode layer and extends to cover the substrates on both sides of the bottom electrode layer, the resistive switching layer extends to cover the remaining thickness of the isolation layer on both sides of the bottom electrode layer.

[0018] Optionally, in the step of forming a top electrode layer that conformally covers the resistive switching layer, the top electrode layer has a shape that protrudes from the center to both sides; the step of removing portions of the top electrode layer, resistive switching layer, and bottom electrode layer on the substrates on both sides of the bottom electrode layer includes: forming a mask layer that covers the top surface and sidewalls of the protruding top electrode layer and covers the top surface of the portions of the top electrode layer on both sides of the protruding top electrode layer; removing the exposed top electrode layer, resistive switching layer, and bottom electrode layer along the mask layer; the step of forming an upper metal layer on the top electrode layer includes: removing the mask layer on the top surface of the top electrode layer to form a first opening; filling the first opening to form an upper metal layer.

[0019] Optionally, after removing the exposed top electrode layer, resistive switching layer, and bottom electrode layer along the mask layer, and before forming the upper metal layer on the top electrode layer, the method further includes: forming a protective layer that covers the sidewalls of the mask layer and extends longitudinally to cover the ends of both sides of the top electrode layer and the resistive switching layer; in the step of removing the mask layer on the top surface of the top electrode layer to form the first opening, the first opening is surrounded by the protective layers on both sides.

[0020] Compared with the prior art, the technical solution of the present disclosure has the following advantages: In the semiconductor structure provided in this embodiment, the bottom electrode layer protrudes from the lower metal layer. A protruding bottom electrode layer is used, which is then conformally covered by a resistive switching layer and a top electrode layer. This completely preserves the protruding bottom electrode layer to form the memory cell. The area of ​​the resistive switching layer conformally covering the bottom electrode layer is the effective area of ​​the memory cell. Therefore, the ends formed by etching the resistive switching layer on both sides of the substrate on the bottom electrode layer are not part of the effective area of ​​the memory cell. This effectively avoids the impact of end damage from resistive switching layer etching on the memory cell, which is beneficial for ensuring the performance of the memory cell device. Furthermore, the bottom electrode layer is in direct contact with the lower metal layer, and the top electrode layer is in direct contact with the upper metal layer. In other words, utilizing the lower metal layer and the upper metal layer... The existing spacing between metal layers can form a memory cell consisting of a top electrode layer, a resistive switching layer, and a bottom electrode layer. This allows for the integration of memory cells without increasing the height of the interconnect layer formed by the lower and upper metal layers. As a result, memory cells can be integrated into the interconnect layer without increasing the overall height of the semiconductor structure, improving the integration density of the semiconductor structure. At the same time, without increasing the height of the interconnect layer formed by the lower and upper metal layers, the capacitance and resistance of the original interconnect layer are not changed. This avoids altering the parasitic capacitance and resistance of the original logic process, which helps reduce the risk and difficulty of the logic process and thus facilitates the achievement of the goal of compatibility between memory cells and logic processes. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of one embodiment of the semiconductor structure disclosed herein; Figures 2 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure disclosed herein; in, Figure 2 This is a schematic diagram of the structure corresponding to the step of providing a substrate in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 3 This is a schematic diagram of the structure corresponding to the step of forming a through hole in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 4 This is a schematic diagram of the structure corresponding to the step of forming the bottom electrode layer in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 5 This is a schematic diagram of the structure corresponding to the step of removing a partial thickness of the isolation layer in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 6 This is a schematic diagram of the structure corresponding to the steps of forming a resistive switching layer and a top electrode layer in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 7 This is a schematic diagram of the structure corresponding to the step of forming a mask layer in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 8This is a schematic diagram of the structure corresponding to the steps of constituting a memory cell in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 9 This is a schematic diagram of the structure corresponding to the step of forming a protective layer in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 10 This is a schematic diagram of the structure corresponding to the step of forming a dielectric layer in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 11 This is a schematic diagram of the structure corresponding to the step of forming the first opening in one embodiment of the method for forming the semiconductor structure disclosed herein; Figure 12 This is a schematic diagram of the structure corresponding to the step of forming the upper metal layer in one embodiment of the method for forming a semiconductor structure disclosed herein. Detailed Implementation

[0022] As can be seen from the background technology, with the continuous miniaturization of semiconductor process nodes, the reduction in RRAM device size and the increase in integration density have become the main trends in its development.

[0023] To address the aforementioned technical problems, this disclosure provides a semiconductor structure comprising: a substrate having a lower metal layer formed therein, with the substrate exposing the top surface of the lower metal layer; the substrate including a first region for forming a memory device; a bottom electrode layer extending longitudinally and protruding from the lower metal layer in the first region, and directly contacting the lower metal layer for electrical connection, wherein the longitudinal direction is perpendicular to the surface of the substrate; a resistive switching layer conformally covering the sidewalls and top surface of the bottom electrode layer, and extending to cover the substrate on both sides of the bottom electrode layer; a top electrode layer conformally covering the resistive switching layer; and an upper metal layer located on the top electrode layer and directly contacting the top electrode layer for electrical connection.

[0024] In the semiconductor structure provided in this embodiment, the bottom electrode layer protrudes from the lower metal layer. A protruding bottom electrode layer is used, which is then conformally covered by a resistive switching layer and a top electrode layer. This completely preserves the protruding bottom electrode layer to form the memory cell. The area of ​​the resistive switching layer conformally covering the bottom electrode layer is the effective area of ​​the memory cell. Therefore, the ends formed by etching the resistive switching layer on both sides of the substrate on the bottom electrode layer are not part of the effective area of ​​the memory cell. This effectively avoids the impact of end damage from resistive switching layer etching on the memory cell, which is beneficial for ensuring the performance of the memory cell device. Furthermore, the bottom electrode layer is in direct contact with the lower metal layer, and the top electrode layer is in direct contact with the upper metal layer. In other words, utilizing the lower metal layer and the upper metal layer... The existing spacing between metal layers can form a memory cell consisting of a top electrode layer, a resistive switching layer, and a bottom electrode layer. This allows for the integration of memory cells without increasing the height of the interconnect layer formed by the lower and upper metal layers. As a result, memory cells can be integrated into the interconnect layer without increasing the overall height of the semiconductor structure, improving the integration density of the semiconductor structure. At the same time, without increasing the height of the interconnect layer formed by the lower and upper metal layers, the capacitance and resistance of the original interconnect layer are not changed. This avoids altering the parasitic capacitance and resistance of the original logic process, which helps reduce the risk and difficulty of the logic process and thus facilitates the achievement of the goal of compatibility between memory cells and logic processes.

[0025] To make the above-mentioned objects, features and advantages of the embodiments of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of the first embodiment of the semiconductor structure disclosed herein.

[0027] refer to Figure 1 The semiconductor structure includes: a substrate 100, in which a lower metal layer 110 is formed, and the top surface of the lower metal layer 110 is exposed; the substrate 100 includes a first region 100a for forming a memory device; and a bottom electrode layer 200, which extends longitudinally (e.g., along the top surface of the lower metal layer 110). Figure 1 The upper metal layer 610 extends and protrudes from the lower metal layer 110 of the first region 100a (as shown in the Z direction) and is in direct contact with the lower metal layer 110 for electrical connection. The longitudinal direction is perpendicular to the surface of the substrate 100. The resistive switching layer 300 conformally covers the sidewalls and top surface of the bottom electrode layer 200 and extends to cover the substrate 100 on both sides of the bottom electrode layer 200. The top electrode layer 400 conformally covers the resistive switching layer 300. The upper metal layer 610 is located on the top electrode layer 400 and is in direct contact with the top electrode layer 400 for electrical connection.

[0028] Substrate 100 is used to provide a process operation platform for the fabrication of semiconductor structures.

[0029] In some embodiments, the substrate 100 includes a first region 100a for forming a memory device.

[0030] The first region 100a is used to form a storage device. For example, the first region 100a is used to form a storage cell to integrate the storage cell between the interconnect layer formed by the upper metal layer 610 and the lower metal layer 110.

[0031] In some embodiments, the substrate 100 further includes a second region 100b for forming interconnect wires.

[0032] The second region 100b is used to form interconnect wires; for example, stacked interconnect layers are formed in the second region 100b.

[0033] In some embodiments, a lower metal layer 110 is formed in the substrate 100, and the top surface of the lower metal layer 110 is exposed in the substrate 100.

[0034] The lower metal layer 110 of the first region 100a is used to electrically connect with the bottom electrode layer 200 to load an electrical signal onto the bottom electrode layer 200.

[0035] The lower metal layer 110 of the second region 100b is used to interconnect with the upper metal layer 610 to form a stacked interconnect layer.

[0036] The bottom electrode layer 200 is used as the bottom electrode of the semiconductor structure memory cell, providing electrical contact with the resistive switching layer 300.

[0037] In some embodiments, the bottom electrode layer 200 can be a single-layer structure or a multi-layer structure. As an example, in this embodiment, the bottom electrode layer 200 is a single-layer structure that protrudes from the lower metal layer 110 of the first region 100a. In other embodiments, the bottom electrode layer may also include a protruding first electrode layer and a second electrode layer that conformally covers the first electrode layer.

[0038] In some embodiments, the material of the bottom electrode layer 200 includes one or more of TaN, TiN, Ru, Pt, Pd, Ta, Ti, and W.

[0039] As the core functional layer of the semiconductor structure memory cell, the resistive switching layer 300 undergoes migration and redistribution of oxygen vacancies under the action of an external electric field, forming or breaking conductive filaments, thereby realizing reversible switching between different resistance states. For example, it realizes reversible switching between the high resistance state (HRS) and the low resistance state (LRS) to complete data storage.

[0040] Accordingly, in some embodiments, the resistive switching layer 300 conformally covers the bottom electrode layer 200 and the substrates 100 on both sides of the bottom electrode layer 200, such that the resistive switching layer 300 has a shape in which the middle protrudes from both sides.

[0041] In some embodiments, the resistive switching layer 300 includes an oxide layer 310 and a buffer layer 320 located on the oxide layer 310, wherein the oxide layer 310 conformally covers the bottom electrode layer 200 and the buffer layer 320 conformally covers the oxide layer 310.

[0042] As the core layer for the resistive switching function of the resistive switching layer 300, the oxide layer 310 undergoes migration, aggregation and redistribution of oxygen vacancies under the drive of an external electric field, forming or breaking conductive filaments, thereby realizing reversible switching between different resistive states.

[0043] In some embodiments, the oxide layer 310 may be formed as a single-layer structure or a multi-layer structure according to actual needs.

[0044] In some embodiments, the material of the oxide layer 310 includes HfO. x TaO x One or more of TiO2, ZrO2, NiO and Al2O3.

[0045] The buffer layer 320 is used to supply oxygen to the oxide layer 310 and also to regulate the concentration of oxygen vacancies at the interface, thereby optimizing the resistive switching behavior of the resistive switching layer 300.

[0046] In some embodiments, the buffer layer 320 may be formed as a single-layer structure or a multi-layer structure according to actual needs.

[0047] In some embodiments, the material of the buffer layer 320 includes Ti, Ta, Al, and TiO. x and AlO x One or more of them.

[0048] The top electrode layer 400 is used as the top electrode of the memory cell in the semiconductor structure, and works with the bottom electrode layer 200 to apply an operating voltage.

[0049] Accordingly, in some embodiments, the top electrode layer 400 conformally covers the resistive switching layer 300, such that the top electrode layer 400 has a shape in which the center protrudes from both sides.

[0050] In some embodiments, the material of the top electrode layer 400 includes TiN or W.

[0051] The upper metal layer 610 of the first region 100a is used to load electrical signals onto the top electrode layer 400.

[0052] In some embodiments, the bottom electrode layer 200 protrudes from the lower metal layer 110. A protruding bottom electrode layer 200 is used, which is then conformally covered by the resistive switching layer 300 and the top electrode layer 400. This means the protruding bottom electrode layer 200 is fully preserved to form a memory cell. The area of ​​the resistive switching layer 300 conformally covering the bottom electrode layer 200 is the effective area of ​​the memory cell. Therefore, the ends formed by etching the resistive switching layer 300 on the substrates 100 on both sides of the bottom electrode layer 200 are not part of the effective area of ​​the memory cell. This effectively avoids the impact of end damage from the etching of the resistive switching layer 300 on the memory cell, which is beneficial for ensuring the performance of the memory cell device. Furthermore, the bottom electrode layer 200 is in direct contact with the lower metal layer 110, and the top electrode layer 400 is in direct contact with the upper metal layer 610. In other words, the lower metal layer 110 is utilized to form a memory cell. The existing spacing between metal layer 110 and upper metal layer 610 can form a memory cell consisting of top electrode layer 400, resistive switching layer 300 and bottom electrode layer 200. This allows for the integration of memory cells without increasing the height of the interconnect layer formed by lower metal layer 110 and upper metal layer 610. Thus, memory cells can be integrated into the interconnect layer without increasing the overall height of the semiconductor structure, improving the integration density of the semiconductor structure. At the same time, without increasing the height of the interconnect layer formed by lower metal layer 110 and upper metal layer 610, the capacitance and resistance of the original interconnect layer are not changed. Therefore, the parasitic capacitance and resistance of the original logic process are not changed, which helps to reduce the risk and difficulty of the logic process and thus helps to achieve the goal of compatibility between memory cells and logic process.

[0053] In some embodiments, the semiconductor structure further includes: an interconnect via structure 620, which extends longitudinally and protrudes from the lower metal layer 110 of the second region 100b, and is in direct contact with the lower metal layer 110 for electrical connection.

[0054] The interconnect via structure 620 is used to electrically connect the upper metal layer 610 and the lower metal layer 110 of the second region 100b.

[0055] Accordingly, in some embodiments, the upper metal layer 610 is also located on the interconnect via structure 620 and is in direct contact with the interconnect via structure 620 for electrical connection.

[0056] In some embodiments, the memory cell formed by the bottom electrode layer 200, the resistive switching layer 300, and the top electrode layer 400 is on the same layer as the interconnect via structure 620.

[0057] The memory cell formed by the bottom electrode layer 200, resistive switching layer 300, and top electrode layer 400 in the first region 100a is on the same layer as the interconnect via structure 620 in the second region 100b. In other words, by utilizing the vertical space of the original interconnect via structure 620, a memory cell formed by the bottom electrode layer 200, resistive switching layer 300, and top electrode layer 400 is formed in the first region 100a. This allows the memory cell to be integrated without increasing the total height of the semiconductor structure, thereby improving the integration density of the semiconductor structure. Furthermore, it does not increase the height of the interconnect layer formed by the lower metal layer 110 and the upper metal layer 610, i.e., it does not change the capacitance and resistance of the original interconnect layer. Therefore, it does not change the parasitic capacitance and resistance of the original logic process, which helps to reduce the logic process risk and difficulty when integrating memory cells, and thus helps to achieve the goal of compatibility between memory cells and logic processes.

[0058] In some embodiments, the semiconductor structure further includes: a dielectric layer 600 covering the substrate 100, wherein in the first region 100a, an upper metal layer 610 penetrates the dielectric layer 600 on the top electrode layer 400, and in the second region 100b, an interconnect via structure 620 and an upper metal layer 610 on the interconnect via structure 620 penetrate the dielectric layer 600 on the lower metal layer 110.

[0059] The dielectric layer 600 provides a process platform for forming the upper metal layer 610 and the interconnect via structure 620.

[0060] In some embodiments, the semiconductor structure further includes an isolation layer 120 covering the substrate 100 on both sides of the bottom electrode layer 200.

[0061] The isolation layer 120 is used to isolate the resistive switching layer 300 and the substrate 100 on both sides of the bottom electrode layer 200.

[0062] Accordingly, in some embodiments, the resistive switching layer 300 extends over the isolation layer 120 on both sides of the bottom electrode layer 200.

[0063] The resistive switching layer 300 extends and covers the isolation layers 120 on both sides of the bottom electrode layer 200, so that the resistive switching layer 300 is isolated from the lower metal layer 110 below through the isolation layers 120, so as to ensure the basic function of the memory cell composed of the bottom electrode layer 200, the resistive switching layer 300 and the top electrode layer 400.

[0064] In some embodiments, the semiconductor structure further includes a mask layer 500 located on the top electrode layer 400 on both sides of the protruding top electrode layer 400 and covering the sidewalls of the top electrode layer 400.

[0065] The sidewall of the top electrode layer 400 refers to the sidewall of the top electrode layer 400 that protrudes in the middle.

[0066] The mask layer 500 is used as an etching mask to form the final morphology of the bottom electrode layer 200, the resistive switching layer 300 and the top electrode layer 400.

[0067] Accordingly, in some embodiments, the sidewalls of the mask layer 500 are flush with the ends of the resistive switching layer 300 and the top electrode layer 400.

[0068] The term "end of resistive switching layer 300" refers to the sidewalls of resistive switching layer 300 on the conformal covering substrate 100 on both sides of the protruding resistive switching layer 300, and the term "end of top electrode layer 400" refers to the sidewalls of top electrode layer 400 on the conformal covering substrate 100 on both sides of the protruding top electrode layer 400.

[0069] In semiconductor manufacturing, the resistive switching layer 300 and the top electrode layer 400 are patterned along the sidewall of the mask layer 500. Therefore, the sidewall of the mask layer 500 is flush with the ends of the resistive switching layer 300 and the top electrode layer 400.

[0070] In some embodiments, the material of the mask layer 500 includes silicon nitride.

[0071] In some embodiments, the upper metal layer 610 also covers the top of the mask layer 500.

[0072] In other words, the upper metal layer 610 extends horizontally to cover the top of the mask layer 500 on both sides of the top electrode layer 400, which helps to completely cover the top surface of the top electrode layer 400 and makes the contact window between the upper metal layer 610 and the top electrode layer 400 larger, thereby improving the electrical contact performance between the upper metal layer 610 and the top electrode layer 400.

[0073] In some embodiments, the semiconductor structure further includes a protective layer 510 that covers the sidewalls of the mask layer 500 and extends longitudinally to cover the ends of the top electrode layer 400 and the resistive switching layer 300 on both sides.

[0074] The protective layer 510 is used to protect the ends of the top electrode layer 400 and the resistive switching layer 300 on both sides, so as to reduce the impact of other processes on the memory cell composed of the bottom electrode layer 200, the resistive switching layer 300 and the top electrode layer 400, and ensure the performance of the memory cell.

[0075] In some embodiments, the protective layer 510 also extends longitudinally to cover the sidewalls of the upper metal layer 610.

[0076] In semiconductor manufacturing, the protective layer 510 can also form a space on the top electrode layer 400 to form the upper metal layer 610, reducing the process difficulty of forming the upper metal layer 610 and simplifying the manufacturing process of the upper metal layer 610. Consequently, the protective layer 510 also extends longitudinally to cover the sidewalls of the upper metal layer 610.

[0077] Accordingly, this disclosure also provides a method for forming a semiconductor structure.

[0078] Figures 2 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure disclosed herein.

[0079] refer to Figure 2 A substrate 100 is provided, in which a lower metal layer 110 is formed, and the top surface of the lower metal layer 110 is exposed. The substrate 100 includes a first region 100a, which is used to form a memory device.

[0080] Substrate 100 is used to provide a process operation platform for the fabrication of semiconductor structures.

[0081] In some embodiments, the substrate 100 includes a first region 100a for forming a memory device.

[0082] The first region 100a is used to form a storage device. For example, the first region 100a is used to form a storage cell to integrate the storage cell between the interconnect layer formed by the upper metal layer and the lower metal layer 110.

[0083] In some embodiments, during the step of providing substrate 100, substrate 100 further includes a second region 100b, which is used to form interconnect wires.

[0084] The second region 100b is used to form interconnect wires; for example, stacked interconnect layers are formed in the second region 100b.

[0085] In some embodiments, a lower metal layer 110 is formed in the substrate 100, and the top surface of the lower metal layer 110 is exposed in the substrate 100.

[0086] The lower metal layer 110 of the first region 100a is used to electrically connect with the subsequently formed bottom electrode layer to load an electrical signal onto the bottom electrode layer.

[0087] The lower metal layer 110 of the second region 100b is used to interconnect with the subsequently formed upper metal layer to form a stacked interconnect layer.

[0088] Reference Figures 2 to 4 Forming along the longitudinal direction (e.g.) Figure 3 The bottom electrode layer 200 extends and protrudes from the lower metal layer 110 of the first region 100a (as shown in the Z direction). The bottom electrode layer 200 is in direct contact with the lower metal layer 110 for electrical connection. The longitudinal direction is perpendicular to the surface of the substrate 100.

[0089] The bottom electrode layer 200 is used as the bottom electrode of the semiconductor structure memory cell, providing electrical contact with the resistive switching layer.

[0090] In some embodiments, the bottom electrode layer 200 can be a single-layer structure or a multi-layer structure. As an example, in this embodiment, the bottom electrode layer 200 is a single-layer structure that protrudes from the lower metal layer 110 of the first region 100a. In other embodiments, the bottom electrode layer may also include a protruding first electrode layer and a second electrode layer that conformally covers the first electrode layer.

[0091] In some embodiments, the material of the bottom electrode layer 200 includes one or more of TaN, TiN, Ru, Pt, Pd, Ta, Ti, and W.

[0092] Specifically, refer to Figure 2 The step of forming a bottom electrode layer 200 extending longitudinally and protruding on the lower metal layer 110 of the first region 100a includes forming an isolation layer 120 covering the substrate 100.

[0093] The isolation layer 120 is used to provide a process operation platform for forming the bottom electrode layer 200, and the isolation layer 120 is also used to isolate the subsequently formed resistive switching layer from the underlying lower metal layer 110.

[0094] In some embodiments, in the step of forming an isolation layer 120 covering the substrate 100, the isolation layer 120 includes a first isolation layer 130 and a second isolation layer 140 located on the first isolation layer 130.

[0095] Subsequently, a portion of the isolation layer 120 needs to be removed, which can then be achieved by removing the second isolation layer 140. By selecting the materials of the first isolation layer 130 and the second isolation layer 140, an etching selectivity ratio can be achieved between the first isolation layer 130 and the second isolation layer 140, making it easier to remove the second isolation layer 140 and reducing damage to the first isolation layer 130. Furthermore, by selecting the material of the first isolation layer 130, it can effectively block the diffusion of metal ions from the lower metal layer 110 in the substrate 100.

[0096] refer to Figure 3 A through-hole 150 is formed, penetrating the isolation layer 120 and exposing the top surface of the lower metal layer 110 of the first region 100a.

[0097] The via 150 provides space for the formation of the bottom electrode layer 200, and the via 150 exposes the top surface of the lower metal layer 110 of the first region 100a, so that the bottom electrode layer 200 subsequently formed in the via 150 comes into contact with the lower metal layer 110 for electrical connection.

[0098] refer to Figure 4 The bottom electrode layer 200 is formed by filling the through-hole 150.

[0099] The via 150 is filled to form a bottom electrode layer 200 that extends longitudinally and protrudes from the lower metal layer 110.

[0100] refer to Figure 5 Before the subsequent formation of the conformal covering of the sidewalls and top surface of the bottom electrode layer 200 and the extension of the resistive switching layer covering the substrate 100 on both sides of the bottom electrode layer 200, the method further includes: removing a portion of the thickness of the isolation layer 120.

[0101] Remove part of the isolation layer 120, leaving the remaining thickness of the isolation layer 120 to isolate the resistive switching layer subsequently formed on the substrate 100 from the underlying lower metal layer 110.

[0102] Specifically, in some embodiments, removing a portion of the thickness of the isolation layer 120 includes removing the second isolation layer 140 while retaining the first isolation layer 130.

[0103] By selecting the materials of the first isolation layer 130 and the second isolation layer 140, the first isolation layer 130 and the second isolation layer 140 have an etching selectivity ratio, making it easy to remove the second isolation layer 140 and better retain the first isolation layer 130. This makes it easy to remove part of the thickness of the isolation layer 120 and retain the remaining thickness of the isolation layer 120, reducing the difficulty of the process.

[0104] refer to Figure 6 The resistive switching layer 300 forms a conformal covering of the sidewalls and top surface of the bottom electrode layer 200 and extends to cover the substrate 100 on both sides of the bottom electrode layer 200.

[0105] As the core functional layer of the semiconductor structure memory cell, the resistive switching layer 300 undergoes migration and redistribution of oxygen vacancies under the action of an external electric field, forming or breaking conductive filaments, thereby realizing reversible switching between different resistance states. For example, it realizes reversible switching between the high resistance state (HRS) and the low resistance state (LRS) to complete data storage.

[0106] Accordingly, in some embodiments, in the step of forming a resistive switching layer 300 that conformally covers the sidewalls and top surface of the bottom electrode layer 200 and extends to cover the substrate 100 on both sides of the bottom electrode layer 200, the resistive switching layer 300 extends to cover the remaining thickness of the isolation layer 120 on both sides of the bottom electrode layer 200.

[0107] The resistive switching layer 300 extends and covers the remaining thickness of the isolation layer 120 on both sides of the bottom electrode layer 200, so that the resistive switching layer 300 is isolated from the lower metal layer 110 below through the isolation layer 120, so as to ensure the basic function of the memory cell composed of the bottom electrode layer 200, the resistive switching layer 300 and the top electrode layer.

[0108] Accordingly, in some embodiments, in the step of forming a resistive switching layer 300 that conformally covers the sidewalls and top surface of the bottom electrode layer 200 and extends to cover the substrates 100 on both sides of the bottom electrode layer 200, the resistive switching layer 300 conformally covers the bottom electrode layer 200 and covers the substrates 100 on both sides of the bottom electrode layer 200, such that the resistive switching layer 300 has a shape in the middle protruding from both sides.

[0109] Specifically, in some embodiments, the step of forming a resistive switching layer 300 that conformally covers the sidewalls and top surface of the bottom electrode layer 200 and extends to cover the substrate 100 on both sides of the bottom electrode layer 200 includes: forming an oxide layer 310 that conformally covers the sidewalls and top surface of the bottom electrode layer 200 and extends to cover the substrate 100 on both sides of the bottom electrode layer 200; and forming a buffer layer 320 that conformally covers the oxide layer 310.

[0110] As the core layer for the resistive switching function of the resistive switching layer 300, the oxide layer 310 undergoes migration, aggregation and redistribution of oxygen vacancies under the drive of an external electric field, forming or breaking conductive filaments, thereby realizing reversible switching between different resistive states.

[0111] In some embodiments, the oxide layer 310 may be formed as a single-layer structure or a multi-layer structure according to actual needs.

[0112] In some embodiments, the material of the oxide layer 310 includes HfO. x TaO x One or more of TiO2, ZrO2, NiO and Al2O3.

[0113] The buffer layer 320 is used to supply oxygen to the oxide layer 310 and also to regulate the concentration of oxygen vacancies at the interface, thereby optimizing the resistive switching behavior of the resistive switching layer 300.

[0114] In some embodiments, the buffer layer 320 may be formed as a single-layer structure or a multi-layer structure according to actual needs.

[0115] In some embodiments, the material of the buffer layer 320 includes Ti, Ta, Al, and TiO. x and AlO x One or more of them.

[0116] Continue to refer to Figure 6 A top electrode layer 400 is formed by conformally covering the resistive switching layer 300.

[0117] The top electrode layer 400 is used as the top electrode of the memory cell in the semiconductor structure, and works with the bottom electrode layer 200 to apply an operating voltage.

[0118] Accordingly, in some embodiments, in the step of forming a top electrode layer 400 that conformally covers the resistive switching layer 300, the top electrode layer 400 conformally covers the resistive switching layer 300, such that the top electrode layer 400 has a shape in which the center protrudes from both sides.

[0119] In some embodiments, the material of the top electrode layer 400 includes TiN or W.

[0120] Reference Figures 7 to 8 Part of the top electrode layer 400, resistive switching layer 300 and bottom electrode layer 200 on the substrate 100 on both sides of the bottom electrode layer 200 are removed, and the remaining top electrode layer 400, resistive switching layer 300 and bottom electrode layer 200 are retained to form a memory cell.

[0121] Specifically, refer to Figure 7 The step of removing portions of the top electrode layer 400, resistive switching layer 300 and bottom electrode layer 200 on the substrate 100 on both sides of the bottom electrode layer 200 includes: forming a mask layer 500 that covers the top surface and sidewalls of the protruding top electrode layer 400 and covers the top surface of portions of the top electrode layer 400 on both sides of the protruding top electrode layer 400.

[0122] The top surface of the top electrode layer 400 refers to the top surface of the top electrode layer 400 that protrudes in the middle, and the side wall of the top electrode layer 400 refers to the side wall of the top electrode layer 400 that protrudes in the middle.

[0123] The mask layer 500 is used as an etching mask for removing portions of the top electrode layer 400, resistive switching layer 300 and bottom electrode layer 200 on the substrate 100 on both sides of the bottom electrode layer 200.

[0124] In some embodiments, in the step of forming a mask layer 500 that covers the top surface and sidewalls of the protruding top electrode layer 400 and covers the top surface of the top electrode layer 400 on both sides of the protruding top electrode layer 400, the width of the mask layer 500 is greater than the width of the top surface of the top electrode layer 400.

[0125] The width of the mask layer 500 is greater than the width of the top surface of the top electrode layer 400, ensuring that the mask layer 500 can completely cover the top surface and sidewalls of the top electrode layer 400. This ensures that when the top electrode layer 400 and the resistive switching layer 300 are etched along the mask layer 500, there is sufficient coverage of the resistive switching layer 300 and the top electrode layer 400 of the bottom electrode layer 200, so as to ensure the basic function of the memory cell.

[0126] In some embodiments, the material of the mask layer 500 includes silicon nitride.

[0127] refer to Figure 8 The top electrode layer 400, resistive switching layer 300, and bottom electrode layer 200 exposed by the mask layer 500 are removed along the mask layer 500.

[0128] Accordingly, in some embodiments, in the step of removing the top electrode layer 400, resistive switching layer 300 and bottom electrode layer 200 exposed along the mask layer 500, the sidewall of the mask layer 500 is flush with the ends of the resistive switching layer 300 and the top electrode layer 400.

[0129] The term "end of resistive switching layer 300" refers to the sidewalls of resistive switching layer 300 on the conformal covering substrate 100 on both sides of the protruding resistive switching layer 300, and the term "end of top electrode layer 400" refers to the sidewalls of top electrode layer 400 on the conformal covering substrate 100 on both sides of the protruding top electrode layer 400.

[0130] refer to Figure 9 After removing the top electrode layer 400, resistive switching layer 300 and bottom electrode layer 200 exposed by the mask layer 500, before forming an upper metal layer on the top electrode layer 400, the method further includes: forming a protective layer 510 that covers the sidewalls of the mask layer 500 and extends longitudinally to cover the ends of the top electrode layer 400 and the resistive switching layer 300 on both sides.

[0131] The protective layer 510 is used to protect the ends of the top electrode layer 400 and the resistive switching layer 300 on both sides, so as to reduce the impact of other processes on the memory cell composed of the bottom electrode layer 200, the resistive switching layer 300 and the top electrode layer 400, and ensure the performance of the memory cell.

[0132] refer to Figure 10 A dielectric layer 600 is formed covering a substrate 100, a bottom electrode layer 200, a resistive switching layer 300, a top electrode layer 400 on the substrate 100, and a mask layer 500 and a protective layer 510 on the substrate 100.

[0133] The dielectric layer 600 provides a process platform for the subsequent formation of interconnect via structures and upper metal layers.

[0134] In some embodiments, the material of the dielectric layer 600 includes silicon oxide.

[0135] Reference Figure 11 and Figure 12 An upper metal layer 610 is formed on the top electrode layer 400, and the upper metal layer 610 is in direct contact with the top electrode layer 400 for electrical connection.

[0136] The upper metal layer 610 of the first region 100a is used to load electrical signals onto the top electrode layer 400.

[0137] In some embodiments, the bottom electrode layer 200 protrudes from the lower metal layer 110. A protruding bottom electrode layer 200 is used, which is then conformally covered by the resistive switching layer 300 and the top electrode layer 400. This means the protruding bottom electrode layer 200 is fully preserved to form a memory cell. The area of ​​the resistive switching layer 300 conformally covering the bottom electrode layer 200 is the effective area of ​​the memory cell. Therefore, the ends formed by etching the resistive switching layer 300 on the substrates 100 on both sides of the bottom electrode layer 200 are not part of the effective area of ​​the memory cell. This effectively avoids the impact of end damage from the etching of the resistive switching layer 300 on the memory cell, which is beneficial for ensuring the performance of the memory cell device. Furthermore, the bottom electrode layer 200 is in direct contact with the lower metal layer 110, and the top electrode layer 400 is in direct contact with the upper metal layer 610. In other words, the lower metal layer 110 is utilized to form a memory cell. The existing spacing between metal layer 110 and upper metal layer 610 can form a memory cell consisting of top electrode layer 400, resistive switching layer 300 and bottom electrode layer 200. This allows for the integration of memory cells without increasing the height of the interconnect layer formed by lower metal layer 110 and upper metal layer 610. Thus, memory cells can be integrated into the interconnect layer without increasing the overall height of the semiconductor structure, improving the integration density of the semiconductor structure. At the same time, without increasing the height of the interconnect layer formed by lower metal layer 110 and upper metal layer 610, the capacitance and resistance of the original interconnect layer are not changed. Therefore, the parasitic capacitance and resistance of the original logic process are not changed, which helps to reduce the risk and difficulty of the logic process and thus helps to achieve the goal of compatibility between memory cells and logic process.

[0138] In some embodiments, the step of forming an upper metal layer 610 on the top electrode layer 400, wherein the upper metal layer 610 is in direct contact with the top electrode layer 400 for electrical connection, further includes: forming an interconnect via structure 620 extending longitudinally and protruding on the lower metal layer 110 of the second region 100b, and an upper metal layer 610 located on the interconnect via structure 620, wherein the interconnect via structure 620 is in direct contact with the lower metal layer 110 for electrical connection.

[0139] The interconnect via structure 620 is used to electrically connect the upper metal layer 610 and the lower metal layer 110 of the second region 100b.

[0140] In some embodiments, in the step of forming an interconnect via structure 620 extending longitudinally and protruding on a lower metal layer 110 of a second region 100b, and an upper metal layer 610 located on the interconnect via structure 620, the memory cell composed of a bottom electrode layer 200, a resistive switching layer 300, and a top electrode layer 400 is on the same layer as the interconnect via structure 620.

[0141] The memory cell formed by the bottom electrode layer 200, resistive switching layer 300, and top electrode layer 400 in the first region 100a is on the same layer as the interconnect via structure 620 in the second region 100b. In other words, by utilizing the vertical space of the original interconnect via structure 620, a memory cell formed by the bottom electrode layer 200, resistive switching layer 300, and top electrode layer 400 is formed in the first region 100a. This allows the memory cell to be integrated without increasing the total height of the semiconductor structure, thereby improving the integration density of the semiconductor structure. Furthermore, it does not increase the height of the interconnect layer formed by the lower metal layer 110 and the upper metal layer 610, i.e., it does not change the capacitance and resistance of the original interconnect layer. Therefore, it does not change the parasitic capacitance and resistance of the original logic process, which helps to reduce the logic process risk and difficulty when integrating memory cells, and thus helps to achieve the goal of compatibility between memory cells and logic processes.

[0142] Specifically, refer to Figure 11 The step of forming an upper metal layer 610 on the top electrode layer 400 includes: removing the mask layer 500 on the top surface of the top electrode layer 400 to form a first opening 630.

[0143] The first opening 630 provides a spatial location for forming the upper metal layer 610 that contacts the top electrode layer 400.

[0144] In some embodiments, the mask layer 500 above the top surface of the top electrode layer 400 is removed, so that the first opening 630 exposes the complete top surface of the top electrode layer 400, and the remaining mask layer 500 is located on the top electrode layers 400 on both sides of the protruding top electrode layer 400 and covers the sidewalls of the top electrode layer 400. That is, the first opening 630 also exposes the top surface of the remaining mask layer 500 on the top electrode layers 400 on both sides of the protruding top electrode layer 400 in the horizontal direction, thereby making the process window for forming the upper metal layer 610 larger, which is beneficial to ensuring the electrical connection performance between the upper metal layer 610 and the top electrode layer 400.

[0145] Accordingly, in some embodiments, in the step of removing the mask layer 500 on the top surface of the top electrode layer 400 to form the first opening 630, the first opening 630 is surrounded by protective layers 510 on both sides.

[0146] By selecting the materials of the mask layer 500 and the protective layer 510, the mask layer 500 and the protective layer 510 can have an etching selectivity ratio, which makes it easier to remove the mask layer 500 on the top surface of the top electrode layer 400 and reduces damage to the protective layer 510, thereby forming the first opening 630 surrounded by the protective layers 510 on both sides and reducing the process difficulty of forming the first opening 630.

[0147] In some embodiments, the forming method further includes: forming a second opening 640 that penetrates the dielectric layer 600 above the lower metal layer 110 and is interconnected with it in the second region 100b, and a third opening 650 located above the second opening 640.

[0148] The second opening 640 is used to provide space for the subsequent formation of interconnect via structures, and the third opening 650 is used to provide space for the subsequent formation of the upper metal layer 610.

[0149] refer to Figure 12 The first opening 630 is filled to form the upper metal layer 610.

[0150] Specifically, in some embodiments, in the step of filling the first opening 630 to form the upper metal layer 610, the upper metal layer 610 also covers the top of the mask layer 500, so that the upper metal layer 610 completely covers the top surface of the top electrode layer 400, and makes the contact window between the upper metal layer 610 and the top electrode layer 400 larger, thereby improving the electrical contact performance between the upper metal layer 610 and the top electrode layer 400.

[0151] Accordingly, in some embodiments, during the step of filling the first opening 630 to form the upper metal layer 610, the protective layer 510 also extends longitudinally to cover the sidewall of the upper metal layer 610.

[0152] In some embodiments, the forming method further includes: filling a second opening 640 to form an interconnect via structure 620 that is in contact with and electrically connected to the lower metal layer 110; and filling a third opening 650 to form an upper metal layer 610 that is in contact with and electrically connected to the interconnect via structure 620.

[0153] The interconnect via structure 620 is used to electrically connect the upper metal layer 610 and the lower metal layer 110 of the second region 100b.

[0154] It should be noted that in the first region 100a, the upper metal layer 610 is directly in contact with the top electrode layer 400 for electrical connection. In the second region 100b, an interconnect via structure 620 is formed between the upper metal layer 610 and the lower metal layer 110. That is, the memory cell composed of the top electrode layer 400, the resistive switching layer 300, and the bottom electrode layer 200 is formed using the same layer space of the interconnect via structure 620. This allows the memory cell structure to be integrated without increasing the total height of the semiconductor structure, without changing the parasitic capacitance and resistance of the original logic process, and reducing the risk and difficulty of the logic process.

[0155] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a lower metal layer formed therein, and the substrate exposing the top surface of the lower metal layer, the substrate including a first region for forming a memory device; A bottom electrode layer extends longitudinally and protrudes from the lower metal layer of the first region, and is in direct contact with the lower metal layer for electrical connection, wherein the longitudinal direction is perpendicular to the surface of the substrate; A resistive switching layer conformally covers the sidewalls and top surface of the bottom electrode layer and extends to cover the substrates on both sides of the bottom electrode layer, such that the resistive switching layer has a shape in the middle protruding from both sides. The top electrode layer is conformally covered on the resistive switching layer, such that the top electrode layer has a shape in which the middle protrudes from both sides. The upper metal layer is located on the top electrode layer and is in direct contact with the top electrode layer for electrical connection; The substrate further includes a second region for forming interconnect wires; The semiconductor structure further includes: an interconnect via structure extending along the longitudinal direction and protruding from the lower metal layer of the second region, and in direct contact with the lower metal layer for electrical connection; The upper metal layer is also located on the interconnect via structure and is in direct contact with the interconnect via structure for electrical connection. The memory cell, consisting of the bottom electrode layer, resistive switching layer, and top electrode layer, is on the same layer as the interconnect via structure.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an isolation layer covering the substrate on both sides of the bottom electrode layer; The resistive switching layer extends and covers the isolation layers on both sides of the bottom electrode layer.

3. The semiconductor structure as described in claim 1, characterized in that, The top electrode layer conformally covers the resistive switching layer, such that the top electrode layer has a shape in which the center protrudes from both sides. The semiconductor structure further includes a mask layer located on the top electrode layers on both sides of the protruding top electrode layer, and covering the sidewalls of the top electrode layer.

4. The semiconductor structure as described in claim 3, characterized in that, The semiconductor structure further includes a protective layer that covers the sidewalls of the mask layer and extends longitudinally to cover the ends of the top electrode layer and the resistive switching layer on both sides.

5. The semiconductor structure as described in claim 4, characterized in that, The upper metal layer also covers the top of the mask layer; The protective layer also extends longitudinally to cover the sidewalls of the upper metal layer.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided in which a lower metal layer is formed and the substrate exposes the top surface of the lower metal layer. The substrate includes a first region for forming a memory device. A bottom electrode layer is formed that extends longitudinally and protrudes from the lower metal layer in the first region. The bottom electrode layer is in direct contact with the lower metal layer for electrical connection. The longitudinal direction is perpendicular to the surface of the substrate. A resistive switching layer is formed to conformally cover the sidewalls and top surface of the bottom electrode layer and extend to cover the substrates on both sides of the bottom electrode layer, such that the resistive switching layer has a shape in the middle protruding from both sides. A top electrode layer is formed to conformally cover the resistive switching layer, such that the top electrode layer has a shape in which the center protrudes from both sides. Remove portions of the top electrode layer, resistive switching layer, and bottom electrode layer from the substrates on both sides of the bottom electrode layer, and retain the remaining top electrode layer, resistive switching layer, and bottom electrode layer to form a memory cell; An upper metal layer is formed on the top electrode layer, and the upper metal layer is in direct contact with the top electrode layer for electrical connection. In the step of providing the substrate, the substrate further includes a second region for forming interconnect wires; The step of forming an upper metal layer on the top electrode layer, wherein the upper metal layer is in direct contact with the top electrode layer for electrical connection, further includes: forming an interconnect via structure that extends longitudinally and protrudes from the lower metal layer in the second region, and an upper metal layer located on the interconnect via structure, wherein the interconnect via structure is in direct contact with the lower metal layer for electrical connection. In the steps of forming a longitudinally extending, protruding interconnect via structure on a lower metal layer in the second region, and an upper metal layer on the interconnect via structure, the memory cell composed of the bottom electrode layer, the resistive switching layer, and the top electrode layer is on the same layer as the interconnect via structure.

7. The forming method as described in claim 6, characterized in that, The step of forming a bottom electrode layer that extends longitudinally and protrudes from the lower metal layer in the first region includes: forming an isolation layer covering the substrate; A through-hole is formed that penetrates the isolation layer and exposes the top surface of the lower metal layer in the first region; The through-hole is filled to form the bottom electrode layer.

8. The forming method as described in claim 7, characterized in that, Before forming a resistive switching layer that conformally covers the sidewalls and top surface of the bottom electrode layer and extends to cover the substrate on both sides of the bottom electrode layer, the method further includes: removing a portion of the thickness of the isolation layer; In the step of forming a resistive switching layer that conformally covers the sidewalls and top surface of the bottom electrode layer and extends to cover the substrates on both sides of the bottom electrode layer, the resistive switching layer extends to cover the remaining thickness of the isolation layer on both sides of the bottom electrode layer.

9. The forming method as described in claim 6, characterized in that, In the step of forming a top electrode layer that conformally covers the resistive switching layer, the top electrode layer has a shape in which the center protrudes from both sides. The step of removing portions of the top electrode layer, resistive switching layer, and bottom electrode layer from the substrates on both sides of the bottom electrode layer includes: forming a mask layer that covers the protruding top surface and sidewalls of the top electrode layer and covers portions of the top surface of the top electrode layer on both sides of the protruding top electrode layer; Remove the top electrode layer, resistive switching layer, and bottom electrode layer exposed along the mask layer; The step of forming an upper metal layer on the top electrode layer includes: removing the mask layer on the top surface of the top electrode layer to form a first opening; The first opening is filled to form the upper metal layer.

10. The forming method as described in claim 9, characterized in that, After removing the exposed top electrode layer, resistive switching layer and bottom electrode layer along the mask layer, and before forming an upper metal layer on the top electrode layer, the method further includes: forming a protective layer that covers the sidewalls of the mask layer and extends longitudinally to cover the ends of the top electrode layer and the resistive switching layer on both sides. In the step of removing the mask layer on the top surface of the top electrode layer to form the first opening, the first opening is surrounded by the protective layers on both sides.

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