An oxide transistor active layer structure and method of fabrication

Abstract

This application discloses an active layer structure and fabrication method for an oxide transistor, relating to the semiconductor field. The fabrication method for the oxide transistor active layer structure proposed in this application includes: providing a substrate; depositing a wetting layer on the substrate, the wetting layer containing anions, said anions including at least nitrogen ions, or fluorine ions, or hydrogen ions, the material of the wetting layer being an insulating material or a semiconductor material; and depositing an active channel layer on the wetting layer, the material of the active channel layer being a material with a mobility greater than 30 cm⁻¹. 2 The oxide semiconductor material has a strength of / (V·s). During the growth of the active channel layer, defects in the active channel layer are repaired, allowing anions in the wetting layer to recombine with oxygen vacancies in the active channel layer. This application also proposes an oxide transistor active layer structure prepared using the above method. The oxide transistor active layer structure and preparation method proposed in this application can improve threshold voltage negative drift and suppress cation interdiffusion.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to an active layer structure and fabrication method for an oxide transistor. Background Technology

[0002] Amorphous oxide semiconductors (AOS) are characterized by their high carrier mobility and extremely low off-state current (Io). off Its excellent optical transparency and low fabrication temperature have made it a core candidate material for high-performance semiconductor technology, especially in the field of thin-film transistors (TFTs). With the acceleration of global digitalization, emerging industries such as advanced displays, 5G communications, artificial intelligence (AI), augmented reality (AR), and virtual reality (VR) are placing increasingly stringent demands on display driving and logic processing capabilities. Therefore, researchers need to develop semiconductor devices with high mobility and high stability. However, the mobility of amorphous indium gallium zinc oxide (IGZO) TFTs, which are currently widely used in industry, is typically maintained at around 10 cm⁻¹. 2 The voltage is around / (V·s), which is insufficient to support the future demands of high-frequency, high-resolution display technologies. Furthermore, using oxide semiconductor materials with high mobility results in a large oxygen vacancy concentration, leading to severe negative threshold voltage drift and making the device difficult to turn off.

[0003] Altering the proportions of elements such as indium (In), gallium (Ga), and zinc (Zn) makes it difficult to overcome the limitations of the "mobility-stability trade-off." For example, while increasing the indium content can improve mobility, it can lead to excessively high carrier concentration and deterioration of device stability; while increasing the gallium content can improve stability, it can significantly reduce mobility.

[0004] Existing bilayer oxide active layer schemes are prone to cation interdiffusion during subsequent thermal processes, leading to fuzzy interfacial band structures. Therefore, how to achieve precise, gradual, and in-situ control of oxygen vacancies without sacrificing stability, while simultaneously preventing cation interdiffusion, has become a pressing technical challenge. Summary of the Invention

[0005] This application discloses a method for fabricating an active layer structure of an oxide transistor, characterized by the following steps: providing a substrate; depositing an impregnation layer over the substrate, the impregnation layer containing anions, the anions including at least nitrogen ions, or fluorine ions, or hydrogen ions, the material of the impregnation layer being an insulating material or a semiconductor material; depositing an active channel layer over the impregnation layer, the material of the active channel layer being a material with a mobility greater than 30 cm⁻¹. 2 / (V·s) oxide semiconductor material; during the growth of the active channel layer, defect repair is performed on the active channel layer so that the anions in the wetting layer recombine with the oxygen vacancies in the active channel layer; and the process temperature of the above steps does not exceed 400℃.

[0006] In particular, the preparation method proposed in this application is characterized by further including plasma treatment on the surface of the impregnated layer to perform anion doping.

[0007] In particular, the preparation method proposed in this application is characterized in that the preparation process of the wetting layer is sputter deposition, and the process gas is a mixture of argon and nitrogen, or a mixture of argon and fluorine, or a mixture of argon and hydrogen.

[0008] In particular, the preparation method proposed in this application is characterized in that the preparation process of the wetting layer is atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD), and the introduced precursor or reactant contains nitrogen ions, or fluorine ions, or hydrogen ions.

[0009] In particular, the preparation method proposed in this application is characterized in that the plasma treatment includes nitrogen plasma treatment, or fluorine plasma treatment, or hydrogen plasma treatment.

[0010] In particular, the preparation method proposed in this application is characterized in that the temperature is between 100℃ and 400℃ during the deposition of the active channel layer.

[0011] In particular, the preparation method proposed in this application is characterized in that the material of the wetting layer is alumina, silicon dioxide, hafnium oxide, indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, or inorganic ceramic material.

[0012] In particular, the preparation method proposed in this application is characterized in that the material of the active channel layer is indium zinc oxide, indium trioxide, or indium tin oxide.

[0013] This application also proposes an active layer structure for an oxide transistor prepared by the above method, characterized in that it includes a substrate, a wetting layer, and an active channel layer in contact with the substrate, wherein the material of the wetting layer is an insulating material or a semiconductor material, the wetting layer contains anions, and the anions include at least nitrogen ions, or fluorine ions, or hydrogen ions, and the material of the active channel layer has a mobility greater than 30 cm⁻¹. 2 Oxide semiconductor material with a strength of / (V·s).

[0014] In particular, the active layer structure of the oxide transistor proposed in this application is characterized in that the anion is a nitrogen ion, or a fluoride ion, or a hydrogen ion, or a combination of nitrogen ions, fluoride ions, and hydrogen ions, or a combination of any two of nitrogen ions, fluoride ions, and hydrogen ions.

[0015] The active layer structure proposed in this application improves the situation where a high concentration of oxygen vacancies in materials with high mobility leads to negative threshold voltage drift by recombination of oxygen vacancies with anions. The active layer structure preparation method proposed in this application employs a low-temperature process not exceeding 400℃ to suppress cation interdiffusion. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an oxide transistor active layer structure according to an embodiment of this application; Figure 2 This is a flowchart of a method for fabricating an active layer structure of an oxide transistor according to an embodiment of this application; Figure 3 This is a schematic diagram of the fabrication process of an oxide transistor active layer structure according to an embodiment of this application; Figure 4 This is a schematic diagram of the impregnation layer preparation process according to an embodiment of this application; Figure 5 This is a schematic diagram of a plasma processing procedure according to an embodiment of this application; Figure 6 This is a schematic diagram of oxygen vacancy recombination according to an embodiment of this application; Figure 7 This is a schematic diagram showing the relationship between the position and anion content in the active layer structure of an oxide transistor according to an embodiment of this application; Figure 8 This is a schematic diagram showing the relationship between the position and zinc ion content in the active layer structure of an oxide transistor according to an embodiment of this application; Figure 9 This is a schematic diagram showing the relationship between the position and oxygen vacancy content in the active layer structure of an oxide transistor according to an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0019] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0020] A transistor can refer to any type of transistor, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). When a transistor is a field-effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low-temperature polycrystalline silicon, organic transistors, etc. Based on whether the charge carriers are electrons or holes, they can be divided into N-type transistors and P-type transistors. The gate of a field-effect transistor is its control electrode; the first electrode can be the drain or source, and the corresponding second electrode can be the source or drain. The gate or control electrode can be the control electrode. When a transistor is a bipolar junction transistor (BJT), the base is its control electrode; the first electrode can be the collector or emitter, and the corresponding second electrode can be the emitter or collector. The base or control electrode can be the control electrode. Transistors can be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS, or CMOS processes.

[0021] Figure 1 This is a schematic diagram of the active layer structure of an oxide transistor according to an embodiment of this application.

[0022] According to one embodiment, such as Figure 1 As shown, the active layer structure of the oxide transistor can be located above the substrate 103.

[0023] According to one embodiment, the active layer structure of the oxide transistor may include a wetting layer 102 located above the substrate 103. According to one embodiment, the raw material of the wetting layer 102 may include an insulating material, such as alumina (Al2O3), silicon dioxide (SiO2), or hafnium oxide (HfO2). The material of the wetting layer 102 may also include a semiconductor material, such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), or indium zinc oxide (IZO). The material of the wetting layer 102 may also include organic polymer materials or inorganic ceramic materials.

[0024] According to one embodiment, the wetting layer 102 contains anions prior to the defect repair process. According to one embodiment, the anions can be introduced into the wetting layer 102 by sputter deposition or plasma treatment. According to one embodiment, the anions in the wetting layer 102 can be nitrogen ions, fluoride ions, hydrogen ions, or a combination of these three anions, or a combination of any two of these three anions.

[0025] According to one embodiment, the oxide transistor active layer structure may further include an active channel layer 101 located above the impregnation layer 102. According to one embodiment, the raw material of the active channel layer 101 may include a high-mobility oxide semiconductor material with a mobility greater than 30 cm⁻¹. 2 / (V·s), such as indium zinc oxide (IZO), indium trioxide (In2O3), and indium tin oxide (ITO).

[0026] According to one embodiment, the active channel layer 101 includes oxygen vacancies prior to the defect repair process. According to one embodiment, oxygen vacancies are vacancies formed by the absence of oxygen atoms in the crystal lattice and are widely present in oxide semiconductors.

[0027] According to one embodiment, after the defect repair process, oxygen vacancies in the active channel layer 101 recombine with at least some or all of the anions in the impregnation layer 102.

[0028] According to one embodiment, charge carriers are transported only in the active channel layer 101, and the impregnation layer 102 does not participate in charge carrier transport.

[0029] According to one embodiment, the wetting layer 102 can also serve as a buffer layer or a gate dielectric layer.

[0030] According to one embodiment, Figure 1The active layer structure shown was prepared at temperatures not exceeding 400°C in all processes. The anions in the active layer structure exist in a free state, making them easier to diffuse. Cations, on the other hand, have greater migration energies and are more difficult to move. Furthermore, temperatures not exceeding 400°C are significantly lower than the temperatures at which cations diffuse considerably. Therefore, this application employs a process temperature not exceeding 400°C to suppress cation interdiffusion.

[0031] Figure 2 This is a flowchart of a method for fabricating an active layer structure of an oxide transistor according to an embodiment of this application. Figure 3 This is a schematic diagram of the fabrication process of an oxide transistor active layer structure according to an embodiment of this application. Figure 4 This is a schematic diagram of the impregnation layer preparation process according to an embodiment of this application. Figure 5 This is a schematic diagram of a plasma processing procedure according to an embodiment of this application.

[0032] Step 201: As Figure 3 As shown in (a), a substrate 103 is provided.

[0033] Step 202: As Figure 3 As shown in (b), an anion-containing wetting layer 102 is deposited over a substrate 103. According to one embodiment, the material of the wetting layer 102 may include an insulating material, such as alumina (Al2O3), silicon dioxide (SiO2), or hafnium oxide (HfO2). The material of the wetting layer 102 may also include a semiconductor material, such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), or indium zinc oxide (IZO). The material of the wetting layer 102 may also include organic polymer materials or inorganic ceramic materials. According to one embodiment, the wetting layer 102 may be prepared using a sputtering deposition process. According to one embodiment, during the preparation of the wetting layer 102 using a sputtering deposition process, the process gas introduced may be a mixture of argon (Ar) and nitrogen (N2), or a mixture of argon (Ar) and fluorine (F2), or a mixture of argon and hydrogen (H2).

[0034] According to one embodiment, the process of preparing the wetting layer 102 using a sputtering deposition process is as follows: Figure 4 As shown, argon ions 402 bombard the target 401, causing metal oxide particles 403 to detach from the target and be transported to the substrate, forming a wetting layer 102 on the upper surface of the substrate. During this process, anions 406 originate from the introduced process gas.

[0035] According to one embodiment, the wetting layer 102 can also be prepared using atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD). During the preparation of the wetting layer 102 using ALD or PECVD, a precursor or reactant containing nitrogen ions, fluoride ions, or hydrogen ions can be introduced as a source of anions.

[0036] According to one embodiment, alternatively, such as Figure 3 As shown in (c), the surface of the wetting layer 102 is subjected to plasma treatment to perform anion doping. The plasma treatment may include nitrogen plasma treatment, fluorine plasma treatment, or hydrogen plasma treatment. The plasma treatment causes anions 406 to accumulate at the surface of the wetting layer 102, such as... Figure 5 As shown. According to one embodiment, the anions introduced during the plasma treatment process and the anions introduced during the deposition of the wetting layer 102 can be the same type of anion or different anions.

[0037] According to one embodiment, the prepared impregnation layer 102 contains an excess of anions, such as nitrogen ions (N). 3- ) or fluoride ions (F - ) or hydrogen ions (H - ).

[0038] According to one embodiment, in step 202, if the method for preparing the wetting layer 102 is sputter deposition, or ALD, or PECVD, then subsequent plasma treatment may or may not be performed.

[0039] According to another embodiment, in step 202, if plasma treatment is selected, the method for preparing the wetting layer 102 can be any method.

[0040] Step 203: As Figure 3 As shown in (d), an active channel layer 101 is deposited over the wetting layer 102. According to one embodiment, the material of the active channel layer 101 may include a high-mobility oxide semiconductor material with a mobility greater than 30 cm⁻¹. 2 / (V·s), such as indium zinc oxide (IZO), indium trioxide (In2O3), and indium tin oxide (ITO). During the deposition of the active channel layer 101, the temperature is between 100°C and 400°C. According to one embodiment, the material of the wetting layer 102 itself hardly reacts with the anions introduced therein, and the wetting layer 102 has a weak binding force on the anions, therefore, as Figure 6 As shown, during the deposition of the active channel layer 101, under the combined effect of temperature and concentration gradient, excess anions 406 in the wetting layer 102 diffuse into the active channel layer 101 and recombine with oxygen vacancies 601 in the active channel layer 101.

[0041] According to one embodiment, in the above preparation process, all process temperatures do not exceed 400°C. Anions in the active layer structure exist in a free state and are more easily diffused. Cations, on the other hand, have greater migration energies and are more difficult to move. Furthermore, a temperature not exceeding 400°C is far below the temperature at which significant cation diffusion occurs. Therefore, this application uses a process temperature not exceeding 400°C to suppress cation interdiffusion.

[0042] Figure 7 This is a schematic diagram showing the relationship between the position and anion content in the active layer structure of an oxide transistor according to an embodiment of this application. Figure 9 This is a schematic diagram showing the relationship between the position and oxygen vacancy content in the active layer structure of an oxide transistor according to an embodiment of this application.

[0043] According to one embodiment, such as Figure 7 As shown, the horizontal axis represents the anion content, and the vertical axis represents the location, i.e., the distance from the interface. In the active channel layer 101, the closer the location is to the interface, the higher the anion content. The farther the location is from the interface, the lower the anion content. For example, Figure 7 Compared to point B, point A is farther from the interface, so the anion content at point A is lower than that at point B.

[0044] According to one embodiment, such as Figure 9 As shown, the horizontal axis represents the oxygen vacancy content, and the vertical axis represents the location, i.e., the distance from the interface. In the active channel layer 101, the farther the location is from the interface, the higher the oxygen vacancy content. For example, Figure 9 Compared to point E, point D is farther from the interface, so the oxygen vacancy content at point D is greater than that at point E.

[0045] According to one embodiment, Figure 7 The changes in anion content shown and Figure 9 The changes in oxygen vacancy content shown exhibit an opposite trend: locations with high anion content have low oxygen vacancy content. This phenomenon indicates that anions have a passivating effect on oxygen vacancies.

[0046] Figure 8 This is a schematic diagram showing the relationship between the position and zinc ion content in the active layer structure of an oxide transistor according to an embodiment of this application.

[0047] According to one embodiment, Figure 8 Taking an active layer structure where the wetting layer 102 is made of indium zinc oxide (IZO) and the active channel layer 101 is made of indium trioxide (In2O3) as an example. According to one embodiment, such as... Figure 8As shown, the horizontal axis represents the zinc ion content, and the vertical axis represents the location, i.e., the distance from the interface. Zinc ions are present only in the wetting layer 102 and not in the active channel layer 101. For example, Figure 8 At point C in the active channel layer 101, the zinc ion content is 0. This indicates that the interdiffusion of cations is effectively suppressed.

[0048] The active layer structure proposed in this application improves the negative threshold voltage drift caused by the high oxygen vacancy concentration in materials with high mobility through the recombination of anions with oxygen vacancies, and also enhances stability. The active layer structure preparation method proposed in this application employs a low-temperature process not exceeding 400℃ to suppress the interdiffusion of cations.

[0049] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. A method for fabricating an active layer structure of an oxide transistor, characterized in that, Includes the following steps: Provide substrate; An impregnation layer is deposited over the substrate, the impregnation layer containing anions, the anions including at least nitrogen ions, or fluorine ions, or hydrogen ions, and the material of the impregnation layer is an insulating material or a semiconductor material; An active channel layer is deposited above the wetting layer, the material of which has a mobility greater than 30 cm⁻¹. 2 Oxide semiconductor materials with a strength of / (V·s); During the growth of the active channel layer, defects in the active channel layer are repaired, allowing anions in the wetting layer to recombine with oxygen vacancies in the active channel layer. Furthermore, the process temperature for all the above steps does not exceed 400℃.

2. The preparation method according to claim 1, characterized in that, It also includes plasma treatment on the surface of the impregnated layer to perform anion doping.

3. The preparation method according to claim 1 or 2, characterized in that, The preparation process of the wetting layer is sputter deposition, and the process gas is a mixture of argon and nitrogen, or a mixture of argon and fluorine, or a mixture of argon and hydrogen.

4. The preparation method according to claim 1 or 2, characterized in that, The preparation process of the wetting layer is atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD), and the introduced precursor or reactant contains nitrogen ions, fluoride ions, or hydrogen ions.

5. The preparation method according to claim 2, characterized in that, The plasma treatment includes nitrogen plasma treatment, or fluorine plasma treatment, or hydrogen plasma treatment.

6. The preparation method according to claim 1, characterized in that, During the deposition of the active channel layer, the temperature is between 100℃ and 400℃.

7. The preparation method according to claim 1, characterized in that, The material of the wetting layer is aluminum oxide, silicon dioxide, hafnium oxide, indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, or inorganic ceramic material.

8. The preparation method according to claim 1, characterized in that, The active channel layer is made of indium zinc oxide, indium trioxide, or indium tin oxide.

9. An oxide transistor active layer structure prepared by the method according to any one of claims 1-8, characterized in that, The system includes a substrate, a wetting layer, and an active channel layer in contact with it. The wetting layer is made of an insulating or semiconductor material and contains anions, including at least nitrogen ions, fluorine ions, or hydrogen ions. The active channel layer is made of a material with a mobility greater than 30 cm⁻¹. 2 Oxide semiconductor material with a strength of / (V·s).

10. The oxide transistor active layer structure according to claim 9, characterized in that, The anion is a nitrogen ion, or a fluoride ion, or a hydrogen ion, or a combination of nitrogen ions, fluoride ions, and hydrogen ions, or a combination of any two of nitrogen ions, fluoride ions, and hydrogen ions.

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