Wafer thinning process method
Patent Information
- Application Number
- CN202610578578.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-28
- Publication Date
- 2026-08-18
AI Technical Summary
[0014] This invention provides a wafer thinning process method that, for wafer thinning processes including wet etching, adds a planarization process before the wet etching process. This process removes mechanical damage to the wafer surface caused by previous grinding processes, removes the damaged layer, repairs the wafer surface morphology, restores planarization, and then performs the wet etching thinning process. This improves the defects of silicon holes formed by excessive etching due to pits carrying the chemical solution on the wafer surface, thereby improving the stability of the wafer thinning process and the reliability of the device.
Smart Images
Figure CN122602792A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device manufacturing, and in particular to a wafer thinning process method for a back-illuminated image sensor (BSI). Background Technology
[0002] Backside illumination (BSI) image sensors are sensors that "reverse" the design of the photosensitive layer and the circuit layer in traditional image sensors. The core of this design is to move the circuit layer (including transistors, metal wiring, etc.) that was originally located in front of the photosensitive layer to behind the photosensitive layer.
[0003] Back-illuminated image sensors are widely used in consumer electronics, security, and automotive fields due to their higher quantum efficiency. Typically, products with a pixel pitch of 1.12μm or less are manufactured using the BSI process. Thanks to deep trench isolation (DTI) and metal grid processes, the performance of BSI products is greatly improved.
[0004] Back-illuminated image sensors are made by thinning the silicon substrate of a CIS wafer and then building a color filter and a microlens on the back of the photodiode. Light enters from the back, increasing the photosensitive area of the photoelectric element and reducing light loss during wiring, which can significantly improve the light sensitivity of CIS in low-light environments.
[0005] Backside Integral (BSI) process involves bonding two wafers together. The top wafer is the device wafer, and the bottom wafer is the carrier wafer. To meet subsequent process requirements, the device wafer is thinned to 2.5–3 μm. The BSI thinning cycle combines multiple processes, including grinding, wet thinning, SI CMP, and TMAH ET, to progressively reduce the device wafer thickness and improve its in-plane uniformity.
[0006] For example, a BSI wafer fabrication process includes: ①Grinding: This process reduces the wafer thickness from 775 μm to 26 μm. The heat and debris generated during this process can easily cause Si damage. Figure 1 As shown; ②Wet thinning: Using chemical solutions to reduce the wafer thickness from 26 μm to 4.4 μm, the residual chemical solution in the pits on the wafer surface can cause prolonged substrate damage and increase Si damage. Figure 2 As shown; ③SI CMP: The wafer is thinned from 4.4 μm to 3.6 μm, which exposes Si holes and reveals the FSI pattern; ④TMAH ET: Utilizing the TMAH chemical solution ET along the crystal orientation to create defects that expose copper at the top of the wafer, such as... Figure 3 As shown. Summary of the Invention
[0007] The technical problem to be solved by the present invention is to provide a wafer thinning process method to reduce wafer surface defects formed in the wafer thinning process.
[0008] The wafer thinning process described in this invention first performs a surface grinding and planarization process to repair the wafer surface before performing the wet etching thinning process.
[0009] Furthermore, the process method includes: The first step is to perform grinding, which thins the wafer to a certain thickness. The second step is to perform the Si CMP-1 polishing process to remove the polishing damage layer on the wafer surface; The third step is to continue thinning the wafer using a wet etching thinning process. The fourth step is to continue with a second grinding of Si CMP-2; The fifth step involves the TMAH etching process (TMAH ET) to further thin the wafer until it reaches the target thickness.
[0010] Furthermore, in the first step, after grinding, the wafer surface has mechanical damage including scratches and pits.
[0011] Furthermore, in the second step, after Si CMP-1 polishing, the thickness removed by polishing needs to remove the mechanical damage defects on the wafer surface, so that the wafer surface is restored to planarity.
[0012] Furthermore, in the third step, the wet etching thinning process, since the wafer surface has been planarized, based on the isotropic nature of wet etching, the overall etching rate of the wafer surface remains consistent, eliminating void defects on the wafer surface.
[0013] Furthermore, the wafer is a wafer used to fabricate a back-illuminated image sensor (BSI).
[0014] This invention provides a wafer thinning process method that, for wafer thinning processes including wet etching, adds a planarization process before the wet etching process. This process removes mechanical damage to the wafer surface caused by previous grinding processes, removes the damaged layer, repairs the wafer surface morphology, restores planarization, and then performs the wet etching thinning process. This improves the defects of silicon holes formed by excessive etching due to pits carrying the chemical solution on the wafer surface, thereby improving the stability of the wafer thinning process and the reliability of the device. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the grinding process in wafer thinning.
[0016] Figure 2 This is a schematic diagram of wet etching thinning in wafer thinning processes.
[0017] Figure 3 This is a schematic diagram illustrating the Si CMP and TMAH ET processes performed during wafer thinning.
[0018] Figure 4 This is a schematic diagram of the wafer thinning process of the present invention. Detailed Implementation
[0019] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] This invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0021] This invention discloses a wafer thinning process method that reduces device defects caused by silicon damage during the process.
[0022] Taking a back-illuminated image sensor (BSI) as an example, this invention improves the BSI thinning process to a five-step process, adding a Si CMP process after grinding. The improved BSI thinning process is: Grinding, Si CMP-1, Wetthinning, Si CMP-2, and TMAH ET.
[0023] For details, please refer to the following: Figure 4 A schematic diagram of the process steps, in an embodiment of a BSI thinning process, includes: The first step is to perform grinding, which reduces the thickness of the device wafer from 775μm to 26μm. After this grinding step, the surface of the device wafer may have some mechanical damage, resulting in defects such as pits and scratches.
[0024] The second step involves a Si CMP-1 polishing process to reduce the thickness of the device wafer from 26 μm to 20 μm. This is roughly a coarse polishing process of 4.5 PSI for 360 seconds. This polishing process removes the damaged layer on the device wafer surface caused by the mechanical polishing in the first step, eliminating defects such as pits and scratches. This restores the flattened surface of the device wafer, eliminating these defects.
[0025] The third step involves further thinning the device wafer using a wet etching process, reducing its thickness from 20 μm to 4.4 μm. Wet thinning, a chemical process, is isotropic and prone to leaving residues in pits, causing continuous corrosion of the wafer. Therefore, the Si CMP-1 polishing process added after the mechanical grinding process in this invention can planarize the wafer surface, remove previously formed pits, reduce the processing time of the wet etching step, and prevent the chemical residues from remaining inside the pits for extended periods, which could worsen minor Si damage defects and lead to Si holes.
[0026] The fourth step involves continuing with the standard process, a second CMP polishing using Si CMP-2. This step reduces the device wafer thickness from 4.4 μm to 3.6 μm.
[0027] The fifth step involves the TMAH etching process. This process reduces the thickness of the device wafer from 3.6 μm to 2.7 μm, achieving the target thickness reduction.
[0028] This invention removes the mask-induced damage layer on the wafer surface by adding a Si CMP process after grinding, restoring the wafer surface to planarity. Then, a wet thinning process is performed to avoid the deterioration of previously formed Si damage and the formation of Si holes. This not only improves the yield and reliability of CIS devices, but also effectively avoids the contamination of the fab production line caused by exposed copper due to Si holes.
[0029] The above embodiments only take the thinning process of back-illuminated image sensors (BSI) as an example. When similar technical problems are involved, the technical methods of this invention can also be used for implementation.
[0030] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A wafer thinning process, characterized in that: When performing wafer thinning, before performing wet etching thinning, a surface grinding and planarization process is first performed to repair the wafer surface, and then the wet etching thinning process is performed.
2. The wafer thinning process method of claim 1, wherein: The process method includes: The first step is to perform grinding, which thins the wafer to a certain thickness. The second step is to perform the Si CMP-1 polishing process to remove the polishing damage layer on the wafer surface; The third step is to continue thinning the wafer using a wet etching thinning process. The fourth step is to continue with a second grinding of Si CMP-2; The fifth step involves the TMAH etching process (TMAH ET) to further thin the wafer until it reaches the target thickness.
3. The wafer thinning process method of claim 1, wherein: In the first step, after grinding, the wafer surface has mechanical damage including scratches and pits.
4. The wafer thinning process method of claim 1, wherein: The second step, after Si CMP-1 polishing, is to remove the mechanical damage defects on the wafer surface by polishing to restore the wafer surface to planarity.
5. The wafer thinning process method of claim 1, wherein: In the third step, during the wet etching thinning process, since the wafer surface has been planarized, based on the isotropic nature of wet etching, the overall etching rate of the wafer surface remains consistent, eliminating void defects on the wafer surface.
6. The wafer thinning process method according to any one of claims 1 to 5, characterized in that: The wafer in question is a wafer used to fabricate a back-illuminated image sensor (BSI).
7. The wafer thinning process method as described in claim 6, characterized in that: The wafer mentioned includes a silicon wafer.