A method for removing layers of a small size chip package

Abstract

The present application belongs to the technical field of chip analysis, and relates to a layer removing method for small-size chip packaging bodies, which comprises the following steps: S1: providing a chip packaging body to be processed, the packaging body containing a chip die; S2: mechanically grinding the chip packaging body until the surface of the chip die; S3: applying an acidic reagent for selective corrosion to completely expose the surface of the chip die; S4: dry etching the exposed surface of the chip die until a first metal layer is exposed; S5: removing the metal pads on the surface of the chip die by a wet etching process, and continuously removing the first metal layer by the wet etching process; S6: continuously removing a first titanium nitride layer under the first metal layer by grinding; and S7: repeating the steps of S4-S6 to remove a second metal layer and a second titanium nitride layer. The present application retains the packaging body throughout the process, does not remove the chip die, avoids cracks, fragmentation and grinding rolling deviation caused by mechanical clamping from the root, and guarantees smooth analysis.

Description

Technical Field

[0001] This invention belongs to the field of chip analysis technology, and specifically relates to a method for removing layers from a small-sized chip package. Background Technology

[0002] Semiconductor chip failure analysis is a key technology for locating defects, optimizing processes, and improving yield in the R&D and mass production stages of integrated circuits. Delayering, as a core process of failure analysis, can directly expose internal structural defects of the chip by gradually peeling off the chip's encapsulation colloid, passivation layer, metal interconnect layer, and dielectric layer, providing direct evidence for fault tracing. With the continuous increase in demand for miniaturization, ultrathinness, and high density of chips in consumer electronics and portable devices, chip die sizes are constantly shrinking, with many die sizes now below 1000μm×1000μm (1mm×1mm). At the same time, to meet the requirements of high conductivity and low impedance, silver-copper alloy pads are increasingly widely used in precision integrated circuits, posing a severe challenge to traditional delayering processes.

[0003] Currently, the mainstream delamination process in the industry adopts the technical route of "first removing the die, then delaminating layer by layer." That is, the die is first separated from the package through chemical capping, mechanical disassembly, etc., and then the individual die is subjected to grinding, etching, and other operations to complete the delamination. This process is mature in the analysis of conventionally sized dies (≥1mm×1mm), but it has insurmountable technical bottlenecks in the processing of small-sized dies and alloy pad samples.

[0004] For small grains smaller than 1mm×1mm, which are lightweight, small in size and fragile in structure, mechanical gripping during grain removal can easily cause cracks or even breakage at the grain edges, and liquid impact during chemical opening can easily cause grains to fall off and be lost. Even if the grains are successfully removed, small grains are very prone to rolling and shifting during subsequent grinding, resulting in uneven grinding surfaces, incomplete exposure of layer structures, and generally low delamination yield. A large number of samples cannot be analyzed due to grain damage and grinding failure.

[0005] For silver-copper alloy pad samples, the defects of traditional processes are even more prominent. The silver and copper metals in the alloy pads are highly reactive, and the acidic solutions encountered during grain removal can cause severe over-corrosion of the pads, resulting in large-area loss of the alloy layer and leaving only the underlying titanium nitride (TiN) structure. This not only destroys the original morphology of the pads, but also causes uncontrolled surface flatness and uneven etching of the metal layer during subsequent layer-by-layer removal, resulting in a high failure rate of the pads. This directly leads to the inability to carry out failure analysis or the distortion of the results.

[0006] While some existing technologies attempt to optimize the fixation of small dies or the protection of pads, none of them deviate from the core process of "removing dies first." For example, fixing small dies with a film to reduce rolling or covering pads with protective adhesive to reduce corrosion can only alleviate local problems. These solutions cannot fundamentally solve the core contradictions of die detachment, breakage, and excessive corrosion of alloy pads. Furthermore, they suffer from problems such as residual protective materials, complex operation, and poor adaptability.

[0007] In summary, existing delamination processes can no longer meet the needs of efficient and low-damage analysis of small-sized grains and alloy pad samples. The industry urgently needs an innovative technical solution that can complete the entire delamination process directly on the package without removing the grain, in order to solve the current technical bottleneck and improve the delamination yield and analysis reliability of special samples.

[0008] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0009] The purpose of this invention is to provide a method for removing layers from a small-sized chip package, thereby overcoming the defects in the prior art.

[0010] To achieve the above objectives, the present invention provides a method for delamination of a small-size chip package, comprising the following steps: S1: Provide a chip package to be processed, wherein the package contains a chip die; S2: Mechanically grind the chip package until it is close to the chip die surface; S3: Apply acidic reagents for selective etching to fully expose the chip die surface; S4: Dry etch the exposed grain surface until the first metal layer is exposed; S5: Remove the metal pads on the chip die surface by wet etching process, and continue to remove the first metal layer by wet etching process; S6: Continue grinding to remove the first titanium nitride layer beneath the first metal layer; S7: Repeat steps S4-S6 to remove the second metal layer and the second titanium nitride layer.

[0011] Preferably, the size of the chip die is ≤1mm×1mm.

[0012] Preferably, the encapsulated body is made of epoxy resin, and the grinding in step S2 is done using diamond sandpaper.

[0013] Preferably, in step S2, the chip die surface is ground until the lead outline is clearly visible.

[0014] Preferably, step S3 is performed by applying a single drop, with a single drop volume ≤ 0.05 ml.

[0015] Preferably, after corrosion in step S3, the sample is immediately rinsed with deionized water to remove residual acid.

[0016] Preferably, the metal pads on the surface of the chip die are silver-copper alloy pads.

[0017] Preferably, both the first metal layer and the second metal layer are aluminum interconnect layers.

[0018] Preferably, the dry etching in step S4 is performed using reactive ion etching, and the etching gas is a fluorine-based gas.

[0019] Compared with the prior art, one aspect of the present invention has the following beneficial effects: This invention preserves the package and does not remove the die throughout the process, thus avoiding the problems of cracks, breakage and grinding roll displacement caused by mechanical clamping. It solves the defects of small die shedding and uneven grinding in traditional processes, significantly improves the delamination yield of dies smaller than 1mm×1mm, and ensures smooth analysis. This invention uses only trace amounts of controlled acid etching, avoiding excessive etching of silver-copper alloy pads by strong acid during traditional open-shell crystal removal, reducing alloy layer loss and pad morphology damage, lowering the risk of pad failure, and ensuring a smooth and uniform surface after subsequent delamination. This invention eliminates complex steps such as die removal, die fixing, and pad protection, and directly completes the entire process of grinding, etching, and engraving on the package, reducing problems such as residual protective material and cumbersome operation. It has strong adaptability and is suitable for various small-sized and alloy pad samples.

[0020] This invention can be extended to ESD chips, ultra-thin precision ICs, small-sized chips below 1mm, and special samples with non-removable dies, filling a technological gap in the industry, avoiding the distortion of traditional process analysis, and improving the accuracy of failure analysis and the customer's sample processing capabilities. Attached Figure Description

[0021] Figure 1 This is a process flow diagram of a delamination method for a small-sized chip package according to the present invention; Figure 2 This is a schematic diagram of the sample after step S1 in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the sample after step S2 in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the sample after step S3 in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the sample after processing in step S6 of Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the sample after processing in step S7 of Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the sample after delamination using existing technology in Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the sample after delamination in Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of the sample after delamination using existing technology in Embodiment 2 of the present invention.

[0022] Figure 10 This is a schematic diagram of the layered structure of the chip die of the present invention; Reference numerals: 1-substrate, 2-second titanium nitride layer, 3-second metal layer, 4-first titanium nitride layer, 5-first metal layer, 6-metal pad, 7-lead, 8-epoxy resin encapsulation. Detailed Implementation

[0023] The specific embodiments of the present invention will be described in detail below, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0024] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0025] Example 1:

[0026] The chip package contains a chip die, which includes a substrate 1. On the substrate 1, a second titanium nitride layer 2, a second metal layer 3, a first titanium nitride layer 4, a first metal layer 5, and metal pads 6 are sequentially disposed. The first metal layer 5 and the metal pads 6 are connected by leads 7. The package is an epoxy resin package 8. Figure 10 As shown, semiconductor chip failure analysis is a key technology for locating defects, optimizing processes, and improving yield in the R&D and mass production stages of integrated circuits, and layer-by-layer delayering is the core process of failure analysis.

[0027] This embodiment provides a method for removing layers from a small-sized chip package, including the following steps: S1: Provide a chip package to be processed, the package containing a chip die, such as... Figure 2 As shown, the encapsulation body is an epoxy resin encapsulation body, and the size of the chip die is ≤1mm×1mm; S2: Mechanically grind the chip package until it is close to the chip die surface, such as... Figure 3As shown, the outline of the lead wires on the surface of the chip die is clearly visible. Diamond sandpaper was used for polishing during the process. The lead wires are conductors that connect the first metal layer and the metal pads. S3: Apply an acidic reagent for selective etching to completely expose the chip die surface, such as... Figure 4 As shown, the leads and metal pads on the chip die surface are completely exposed. The metal pads are silver-copper alloy pads. When applying the acidic reagent, a single droplet application method is used, with a single droplet volume ≤0.05ml. The etching time is approximately 3-10s. The acidic reagent is hydrofluoric acid or a fluorine-containing mixed acid with a concentration of approximately 10wt%-15wt%. After etching, the chip is immediately rinsed with deionized water to remove residual acid. S4: Dry etching is performed on the exposed grain surface until the first metal layer is exposed. The dry etching uses reactive ion etching and the etching gas is a fluorine-based gas. S5: Remove the metal pads on the chip die surface by wet etching process, and continue to remove the first metal layer by wet etching process, wherein the time for wet etching to remove the first metal layer is 2-8 seconds; S6: Continue grinding to remove the first titanium nitride layer beneath the first metal layer, such as... Figure 5 As shown, diamond sandpaper is used for grinding in the same way; S7: Repeat steps S4-S6 to remove the second metal layer and the second titanium nitride layer. Figure 6 As shown, the first metal layer and the second metal layer are both aluminum interconnect layers, and the first titanium nitride layer and the second titanium nitride layer are barrier layers.

[0028] In this case, using existing technology, the first step is to separate the die from the package through chemical decapsulation or mechanical disassembly. Then, the individual die is subjected to grinding, etching, and corroding operations to remove the layers, resulting in a sample as shown below. Figure 7 As shown, cracks and fragmentation are more obvious at the edges.

[0029] Example 2:

[0030] For conventional samples with chip die sizes > 1mm × 1mm, the above-described delamination process is used to remove the second metal layer and the second titanium nitride layer. The resulting sample is shown below. Figure 8 As shown.

[0031] For standard samples of the same specifications, existing technology is used, which involves first separating the die from the package through chemical decapsulation and mechanical disassembly, and then performing operations such as grinding, etching, and corroding on the individual die to remove the layers. The sample after removing the second metal layer and the second titanium nitride layer is as follows: Figure 9 As shown, the chip die damage is quite severe.

[0032] While the above-mentioned delamination process involves the use of acid, which carries the risk of damaging the chip die, the damage is significantly reduced compared to the process of removing the die first and then delaminating.

[0033] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A method for removing layers from a small-sized chip package, characterized in that, Includes the following steps: S1: Provide a chip package to be processed, wherein the package contains a chip die; S2: Mechanically grind the chip package until it is close to the chip die surface; S3: Apply acidic reagents for selective etching to fully expose the chip die surface; S4: Dry etch the exposed grain surface until the first metal layer is exposed; S5: Remove the metal pads on the chip die surface by wet etching process, and continue to remove the first metal layer by wet etching process; S6: Continue grinding to remove the first titanium nitride layer beneath the first metal layer; S7: Repeat steps S4-S6 to remove the second metal layer and the second titanium nitride layer.

2. The method for removing layers from a small-sized chip package according to claim 1, characterized in that, The size of the chip die is ≤1mm×1mm.

3. The method for removing layers from a small-sized chip package according to claim 1, characterized in that, The object is an epoxy resin encapsulated body, and the grinding in step S2 is done using diamond sandpaper.

4. The method for removing layers from a small-sized chip package according to claim 3, characterized in that, In step S2, the chip die surface is ground until the lead outline is clearly visible.

5. The method for removing layers from a small-sized chip package according to claim 1, characterized in that, Step S3 is performed by applying a single drop, with a single drop volume ≤ 0.05 ml.

6. The method for removing layers from a small-sized chip package according to claim 5, characterized in that, Immediately after corrosion in step S3, rinse with deionized water to remove residual acid.

7. The method for removing layers from a small-sized chip package according to claim 1, characterized in that, The metal pads on the surface of the chip die are silver-copper alloy pads.

8. The method for removing layers from a small-sized chip package according to claim 1, characterized in that, Both the first metal layer and the second metal layer are aluminum interconnect layers.

9. The method for removing layers from a small-sized chip package according to claim 1, characterized in that, The dry etching step S4 uses reactive ion etching, and the etching gas is a fluorine-based gas.

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