Method for increasing pin alignment accuracy of a power semiconductor module

Abstract

A method for increasing the overall pin alignment accuracy of a power semiconductor module having a plurality of pins includes attaching the plurality of pins and one or more power semiconductor dies to a first side of a substrate to form a power semiconductor subassembly; using a jig to align a distal end of each pin with an alignment feature of an electrically insulating housing; and after alignment, attaching the housing to the power semiconductor subassembly. The housing is attached to the subassembly such that the housing and the substrate together define an interior space in which the pins and the one or more power semiconductor dies are disposed. The pins extend out of the housing.

Description

Technical Field

[0001] This disclosure relates generally to power semiconductor modules, and particularly to increasing the pin alignment accuracy of power semiconductor modules. Background Technology

[0002] The demand for electronic modules (often referred to as power semiconductor modules) for power applications continues to grow rapidly across a wide range of industries, including automotive, consumer electronics, renewable energy, manufacturing, and medical. Advances in semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have enabled the manufacture of such power semiconductor modules with advantageous features, such as smaller footprint, higher voltage and current capabilities, and faster switching speeds. Many applications have specific dimensional requirements and tolerances for the features of power semiconductor modules used to assemble and / or interface them with other components. During the assembly of power semiconductor modules and components, modules that do not meet these requirements and tolerances may require manual handling or may even be deemed unusable for a given application.

[0003] Therefore, a solution is needed to improve the alignment accuracy of the features of power semiconductor modules interfacing with other components. Summary of the Invention

[0004] According to an embodiment of a method for increasing the overall pin alignment accuracy of a power semiconductor module having multiple pins, the method includes: attaching a plurality of pins and one or more power semiconductor dies to a first side of a substrate to form a power semiconductor subassembly; aligning the distal end of each pin with alignment features of an electrically insulating housing using a jig; and after alignment, attaching the housing to the power semiconductor subassembly such that the housing and the substrate together define an internal space in which the pins and one or more power semiconductor dies are disposed, wherein the pins extend beyond the housing.

[0005] According to an embodiment of a method for forming a power semiconductor module having multiple pins, the method includes: attaching a plurality of pins and one or more power semiconductor dies to a first side of a substrate to form a power semiconductor subassembly; aligning the distal end of each pin with alignment features of an electrically insulating housing using a jig; and after alignment, attaching a housing to the power semiconductor subassembly such that the housing and the substrate together define an internal space in which the pins and one or more power semiconductor dies are disposed, wherein the pins extend beyond the housing, wherein the alignment includes: placing the housing on the jig such that alignment features of the housing mate with a first alignment feature of the jig; and placing the power semiconductor subassembly on the housing such that the distal end of each pin in a subset of the pins mates with a second alignment feature of the jig.

[0006] After reading the following detailed description and reviewing the accompanying drawings, those skilled in the art will recognize the additional features and advantages. Attached Figure Description

[0007] The elements in the accompanying drawings are not necessarily drawn to scale relative to each other. The same reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. These embodiments are depicted in the accompanying drawings and are described in detail in the following description.

[0008] Figure 1A and Figure 1B A method for attaching a plurality of pins and one or more power semiconductor dies to a substrate to form a power semiconductor subassembly, according to an embodiment, is illustrated.

[0009] Figure 2A-2C A method for placing an electrically insulating housing on a clamp according to an embodiment is shown.

[0010] Figures 3A-3C A method according to an embodiment is shown for aligning the distal end of each of a plurality of pins of a power semiconductor sub-assembly with alignment features of an electrically insulating housing using a clamp and attaching the electrically insulating housing to the power semiconductor sub-assembly.

[0011] Figure 4A and Figure 4B A top plan view of a power semiconductor module according to an embodiment is shown.

[0012] Figure 5A and Figure 5B A perspective view of a power semiconductor module according to an embodiment is shown.

[0013] Figure 6 An assembly of a power semiconductor module and component according to an embodiment is shown. Detailed Implementation

[0014] This document describes a method for forming a power semiconductor module comprising multiple pins. The pins are configured to interface with external components of an application (e.g., a printed circuit board (PCB)) and provide an electrical interface for the power semiconductor module. Some portions of the assembly process between the power semiconductor module and the external component of the application can be automated. Automated assembly processes can use external features of the power semiconductor module (e.g., features of the housing, surfaces, etc.) as a reference system for aligning the power semiconductor module with the component of the application. Misalignment of the pins relative to this reference system can increase the complexity of the process of assembling the power semiconductor module with the component, as misaligned pins may not properly mate with corresponding openings in the component and may require manual intervention to form a proper interface. In some cases, pin misalignment exceeding specific tolerances of the application may render the power semiconductor module unusable for that application.

[0015] According to the embodiments described herein, a jig is used to align each pin with the alignment features of the housing before attaching the housing to a power semiconductor sub-assembly comprising pins and one or more power semiconductor dies attached to a substrate. In some examples, aligning the pins with the housing when forming a power semiconductor module according to the methods described herein can increase the likelihood of proper mating of the pins with components (e.g., PCBs) when integrating the power semiconductor module into a target application. Such improved alignment of the pins can even enable this part of the assembly process of the power semiconductor module with external components to be performed using an automated process. Specifically, sufficiently precise alignment of the pins with the housing can enable the use of an automated assembly system to assemble the power semiconductor module and components, the automated assembly system being configured to pick up the power semiconductor module by clamping the housing, align the pins with the receiving holes of the component using the housing as a position reference point, and insert the pins into the receiving holes of the component. This automated process can provide a simpler and more cost-effective process for manufacturing power semiconductor modules.

[0016] An exemplary embodiment of a method for increasing overall pin alignment accuracy when forming a power semiconductor module will now be described with reference to the accompanying drawings.

[0017] Figure 1A and Figure 1B A method for attaching a plurality of pins 140 and one or more power semiconductor dies 120 to a substrate 110 to form a power semiconductor subassembly 105 is shown according to an embodiment.

[0018] Examples of substrate 110 include DCB (Direct Copper Bond) or AMB (Active Metal Brazing) substrates, printed circuit boards (PCBs), lead frames, or other substrates such as insulated metal substrates (IMS). Substrate 110 may include one or more insulating layers and / or metallization layers. Insulating layers may include ceramics, polymers such as polyimide, etc. Metallization layers may include copper, aluminum, alloys, etc., and may include one or more traces and / or one or more contact pads. Figure 1A and Figure 1B The substrate 110 includes a first side 110 of the substrate 110. S1 Metallization layer 112 on top.

[0019] Each power semiconductor die 120 may include one or more devices, such as one or more transistors, diodes, resistors, capacitors, and / or other types of active or passive devices. One or more power semiconductor dies 120 may be vertical power semiconductor dies (e.g., vertical power transistor dies). For a vertical power transistor die, the main current flow path is between the front and rear sides of the power semiconductor die 120 (along the z-direction in FIG. 1). In one embodiment, one or more power semiconductor dies 120 are SiC transistor dies, such as SiC power MOSFETs (metal-oxide-semiconductor field-effect transistors). One or more power semiconductor dies 120 may be Si power MOSFET dies, HEMT (high electron mobility transistor) dies, IGBT (insulated-gate bipolar transistor) dies, JFET (junction field-effect transistor) dies, etc. In examples where more than one power semiconductor die 120 is attached to the substrate 110, the power semiconductor dies 120 may all have similar or identical designs (e.g., device type, structure, material, size, etc.), or some power semiconductor dies 120 or each power semiconductor die 120 may have different designs. Various arrangements of the power semiconductor dies 120 on the substrate 110 are contemplated. For example, one or more power semiconductor dies 120 may be arranged on the substrate 110 to form all or part of the circuitry of a power semiconductor module, such as a DC / AC inverter, DC / DC converter, AC / DC converter, DC / AC converter, AC / AC converter, multiphase inverter, H-bridge, motor driver, etc. In some examples, the circuitry including one or more power semiconductor dies 120 is a half-bridge or full-bridge circuit.

[0020] Pins 140 may be formed of copper, aluminum, an alloy (e.g., a nickel-tin alloy), or other conductive materials. As previously described, pins 140 provide an electrical interface for the power semiconductor module, wherein each pin 140 is configured to interface with a component (e.g., a PCB) to which the power semiconductor module will be integrated. Each pin 140 may have a diameter d, which is a longitudinal extension perpendicular to the pin 140 (e.g., perpendicular to...). Figure 1A and Figure 1B The diameter d of each pin 140 is less than 1 mm. In some examples, the diameter d of each pin 140 is less than 1 mm. In this example, the distal end 140 of each pin 140... DE It is a press-fit end, comprising a tip portion 141 and a deformable portion 142 adjacent to the tip portion 141. In this configuration, the tip portion 141 of the pin 140 can be inserted into a hole in a PCB or other type of substrate, and the deformable portion 142 can undergo plastic and / or elastic deformation when pressed against the wall of the hole, thereby securing the pin 140 to the substrate. Other configurations of the pin 140 and means of mating the pin 140 to components are envisioned. For example, the distal end 140 of the pin 140... DE It can be soldered to components such as PCBs.

[0021] exist Figure 1A and Figure 1B In the example, multiple sleeves 130 are attached to the first side 110 of the substrate 110. S1 Sleeve 130 may be formed of a metal or metal alloy such as copper or aluminum. In some examples, one or more sleeves 130 include an electrically insulating covering or coating. In this embodiment, sleeve 130 is attached to metallization layer 112, but one or more sleeves 130 may be attached to different metallization layers or other portions of substrate 110. Sleeve 130 may be attached to substrate 110 (e.g., metallization layer 112 or other metallization layers) by soldering (e.g., using soft solder, using solder paste), adhesion, fusion welding, etc. Each sleeve 130 is configured to receive pin 140 and may electrically couple the received pin 140 to one or more power semiconductor dies 120 (e.g., through metallization layer 112), but other means (e.g., soldering) are contemplated for attaching pin 140 to substrate 110 and electrically coupling pin 140 to one or more power semiconductor dies 120 without using sleeve 130. That is, sleeve 130 in the embodiments herein is optional and not necessary for the disclosed methods.

[0022] Figure 1B This illustrates attaching pin 140 and one or more power semiconductor dies 120 to a first side 110 of substrate 110. S1To form a power semiconductor sub-assembly 105. In this example, one or more power semiconductor dies 120 are attached to the metallization layer 112, but one or more power semiconductor dies 120 may be attached to different metallization layers or other portions of the substrate 110. One or more power semiconductor dies 120 may be attached to the substrate 110 (e.g., metallization layer 112 or other metallization layers) by soldering, diffusion soldering, brazing, adhesion, etc.

[0023] By using each pin 140 (e.g., the proximal end 140 of each pin 140) PE The pin 140 is inserted into the corresponding sleeve 130 attached to the substrate 110. The proximal end 140 of the corresponding pin 140... PE It can be press-fitted into the corresponding sleeve 130. In some examples, the proximal end 140 of a given pin 140 PE Weld to the corresponding sleeve 130.

[0024] The remainder of this disclosure describes a method for increasing the alignment accuracy of pin 140 when forming a power semiconductor module. Specifically, the method disclosed herein includes attaching an electrically insulating housing to... Figure 1A and Figure 1B Before the power semiconductor sub-assembly 105, a clamp is used to hold the distal end 140 of each pin 140. DE Align with the alignment features of the electrically insulating housing.

[0025] Figure 2A-2C A method for placing an electrically insulating housing 150 on a clamp 200 according to an embodiment is shown.

[0026] The housing 150 may comprise one or more pieces of metal, plastic, composite material, and / or other suitable material. The housing 150 has a length L and a width W. In some examples, the length L of the housing 150 is less than 100 mm. In some examples, the width W of the housing 150 is less than 100 mm.

[0027] The housing 150 can be a molded shell (e.g., a frame) formed from a molding compound. The molding compound is a plastic encapsulant typically formed from an organic resin such as epoxy resin. The plastic encapsulant may include fillers such as non-melting inorganic materials. A catalyst may be used to accelerate the curing reaction of the organic resin. Depending on the application, other materials (such as flame retardants, adhesion promoters, ion traps, stress relievers, colorants, etc.) may be added to the plastic encapsulant. The molding compound can be formed through injection molding, compression molding, film-assisted molding (FAM), reaction injection molding (RIM), resin transfer molding (RTM), blow molding, etc.

[0028] According to an embodiment, the housing 150 includes alignment features 155. In this example, the alignment features 155 include at least two apertures 155 formed in the housing 150. The apertures 155 extend from the outer surface 150. S Extending into housing 150. In the following text, the terms “alignment feature 155” and “orifice 155” may be used interchangeably as appropriate; however, this is merely an example and other embodiments of alignment feature 155 (e.g., a post) are contemplated.

[0029] The clamp 200 can be formed from any suitable material (e.g., metal, plastic, ceramic, etc.). The clamp 200 includes a cavity 205, which is formed by an opening 205. P Base 205 B Side wall 205 SW and from the base 205 B and sidewall 205 SW The extension is defined by at least two sidewall features 215. Figure 2A The clamp 200 includes four sidewall features 215, one of which is located at each corner of the cavity 205. Each sidewall feature 215 includes features relative to the opening 205. P Recessed exterior facing surface 215 S Opening 205 P The outer peripheral surface 200 of the fixture 200 S Overlapping, and formed by the outer peripheral surface 200 of the clamp 200 S Lateral encirclement.

[0030] According to an embodiment, the clamp 200 includes a first alignment feature 210 and a second alignment feature 220. The first alignment feature 210 of the clamp 200 is disposed on the outer peripheral surface 200. S Above. In this example, the first alignment feature 210 of the clamp 200 includes two posts 210, but other embodiments of the first alignment feature 210 are contemplated (e.g., more than two posts 210, orifices). In the following text, the terms "first alignment feature 210" and "post 210" may be used interchangeably as appropriate. Figure 2A In the example of clamp 200, the post 210 is tapered, although this is not necessary, and other geometries for the post 210 are envisioned. A second alignment feature 220 of clamp 200 is disposed in cavity 205. In this example, the second alignment feature 220 of clamp 200 includes an outwardly facing surface 215 formed in each sidewall feature 215. S The aperture 220 is specified, but other locations for the second alignment feature 220 are contemplated. In the following text, the terms "second alignment feature 220" and "aperture 220" may be used interchangeably as appropriate.

[0031] Figure 2B and Figure 2C The image shows the housing 150 placed on the clamp 200. The outer surface 150 of the housing is shown. S The outer peripheral surface 200 of the fixture 200 S The housing 150 is placed on the clamp 200 in a manner that includes inserting each post 210 of the clamp 200 into a corresponding opening 155 of the housing 150. That is, the housing 150 is placed on the clamp 200 such that the alignment feature 155 of the housing 150 engages with the first alignment feature 210 of the clamp 200. With the alignment feature 155 of the housing 150 engaging with the first alignment feature 210 of the clamp 200, the second alignment feature 220 of the clamp 200 is aligned with the alignment feature 155 of the housing 150 in both the x and y directions.

[0032] Figures 3A-3C The illustration shows a method for using a clamp 200 to hold the distal end 140 of each of a plurality of pins 140 of a power semiconductor subassembly 105. DE A method of aligning the housing 150 with the alignment feature 155 and attaching the housing 150 to the power semiconductor subassembly 105.

[0033] Figure 3A A subset of pin 140 is shown. S 140 for each pin S Aligned perpendicularly with the corresponding aperture 220 of the fixture 200 (e.g., along the z-direction). In this example, a subset 140 of the pins 140 S Includes four corner pins 140 attached to substrate 110. S Each of them.

[0034] Figure 3B and Figure 3C This illustrates placing a power semiconductor sub-assembly 105 on a housing 150, which includes a subset 140 of pins 140. S The far end of each pin 140 in DE Insert it into the corresponding opening 220 of the clamp 200. That is, place the power semiconductor sub-assembly 105 on the housing 150, such that a subset 140 of the pins 140... S The far end of each pin 140 in DE It mates with the second alignment feature 220 of the clamp 200. For example... Figure 3CAs shown, the aperture 220 of the clamp 200 may be tapered to facilitate the positioning of pins 140 in the x and y directions when the power semiconductor sub-assembly 105 is placed on the housing 150. When the power semiconductor sub-assembly 105 is placed on the housing 150, a subset 140 not included in the pins 140... S Each pin 140 is received by cavity 205 of fixture 200.

[0035] The alignment feature 155 of the housing 150 mates with the first alignment feature 210 of the clamp 200 and the subset 140 of the pins 140 S The far end of each pin 140 in DE When engaged with the second alignment feature 220 of the clamp 200, the pin 140 is aligned with the alignment feature 155 of the housing 150 in both the x and y directions. After the pin 140 is aligned with the alignment feature 155 of the housing 150, the housing 150 is attached (e.g., by gluing) to the power semiconductor subassembly 105. Figure 3B and Figure 3C In the example, the housing 150 is attached to the first side 110 of the substrate 110. S1 .

[0036] Figure 4A and Figure 4B A top plan view of a power semiconductor module 100 according to an embodiment is shown. The power semiconductor module 100 is capable of using the present disclosure. Figure 1A-3C As shown and referred to in this disclosure Figure 1A-3C An example of a power semiconductor module formed by the described steps. The power semiconductor module 100 includes a housing 150 attached to a power semiconductor sub-assembly 105, wherein, according to... Figure 2A-3C As shown and referenced Figure 2A-3C The method described involves aligning pin 140 with alignment feature 155 of the housing.

[0037] Figure 4A The target position p of pin 140 is shown. T and final position p F For example, where Δp represents the final position p of pin 140. F Target position p of pin 140 T The deviation (e.g., in the x and y directions). Each pin 140 of the power semiconductor module 100 has a target position p T Final position p F And deviation Δp. In Figure 4A The axis in the diagram shows the deviation Δp of each pin 140 of the power semiconductor module 100 in the x and y directions.

[0038] The target position p of each pin 140 can be measured relative to a reference system. T And the target position p for each pin is 140. T This can correspond to the target location of pin 140 for a given application of the power semiconductor module. The reference system may include features of the housing 150, including alignment features 155, edges / surfaces / corners of the housing 150, screw holes of the housing 150, etc., and can be used to achieve alignment purposes (e.g., clamping the housing, aligning the housing 150 with the components) when assembling the power semiconductor module 100 with components for the target application. Therefore, aligning pin 140 with the housing 150 using the method disclosed herein ensures that pin 140 is also aligned with the reference system, potentially facilitating the assembly of the power semiconductor module 100 with components for the target application. By aligning pin 140 with the alignment features 155 of the housing 150 according to the method disclosed herein, the final position p of each pin 140 is... F Its corresponding target position p T The deviation Δp can be less than, for example, 0.4 mm in both the x-direction (also referred to herein as the first direction) and the y-direction (also referred to herein as the second direction) relative to the reference system. In other words, the maximum value of the deviation Δp among all pins 140 of the power semiconductor module 100 (given by...) Figure 4A Δp on the axis max (This indicates that) it can be less than, for example, 0.4 mm.

[0039] Figure 4B The housing 150 of the power semiconductor module 100 is shown to include an outer surface feature 150 at each corner. E Examples. Figure 4B External surface features 150 E This is an example of an outer surface feature of a reference system used for alignment purposes during the assembly of the power semiconductor module 100 with components of a target application. For example, during the assembly of the power semiconductor module 100 with components of a target application, Figure 4B External surface features 150 E This can be used as a clamping surface for (e.g., using an automated assembly system) picking up the power semiconductor module 100. By aligning the pins 140 with the alignment feature 155 of the housing 150 according to the method disclosed herein, the pins 140 also align with the outer surface feature 150 of the housing 150. E Alignment facilitates the insertion of pin 140 into the receiving hole of the component (e.g., a hole in the PCB).

[0040] Figure 5A and Figure 5BA perspective view of a power semiconductor module 100 according to an embodiment is shown. Alignment features 155 are used to align pins 140 with housing 150, and housing 150 is attached to the power semiconductor sub-assembly 105 (e.g., attached to a first side 110 of a substrate). S1 Subsequently, housing 150 and substrate 110 together define internal space 102, within which pins 140 and one or more power semiconductor dies 120 are disposed. Pins 140 extend beyond housing 150 (e.g., beyond outer surface 150). S This provides a means for mating pin 140 with components of a target application. When integrating the power semiconductor module 100 into a target application, aligning pin 140 with alignment features 155 of housing 150 according to the methods disclosed herein facilitates insertion of pin 140 into receiving holes (e.g., holes in a PCB) of components.

[0041] Figure 5B An example is shown in which the methods disclosed herein also include attaching a cover 160 to a housing 150. Alternatively, the cover 160 may be attached to a power semiconductor subassembly 105. The cover 160 also defines an internal space 102 in which pins 140 and one or more power semiconductor dies 120 are disposed. Each pin 140 extends out of the housing 150 through an opening 162 in the cover 160.

[0042] Figure 6 An assembly of a power semiconductor module 100 and component 300 according to an embodiment is shown. Component 300 (such as a PCB) includes an opening 310 corresponding to the target locations of pins 140 of the power semiconductor module 100. The distal end 140 of each pin 140 is... DE The power semiconductor module 100 and component 300 are assembled by inserting them into the corresponding opening 310 of component 300. Although Figure 6 As shown Figure 1A As shown and referenced Figure 1A The press-fit pin 140 is described, but pin 140 can be assembled with component 300 by other means (e.g., soldering).

[0043] Precise alignment of pin 140 with housing 150 ensures that pin 140 can be properly inserted into opening 310 during the assembly of power semiconductor module 100 and component 300. As previously stated, if pin 140 is adequately aligned with a reference system including features of housing 150 within acceptable tolerances, the assembly process can potentially be automated. Therefore, forming power semiconductor module 100 according to the methods disclosed herein ensures sufficiently precise alignment of pin 140 relative to housing 150 to enable automated assembly of power semiconductor module 100 and component 300, thereby potentially providing a more cost-effective manufacturing process.

[0044] Although this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0045] Example 1: A method for increasing the overall pin alignment accuracy of a power semiconductor module having multiple pins, the method comprising: attaching a plurality of pins and one or more power semiconductor dies to a first side of a substrate to form a power semiconductor subassembly; aligning the distal end of each of the pins with alignment features of an electrically insulating housing using a jig; and, after alignment, attaching the housing to the power semiconductor subassembly such that the housing and the substrate together define an internal space in which the pins and one or more power semiconductor dies are disposed, wherein the pins extend beyond the housing.

[0046] Example 2: According to the method of Example 1, wherein the alignment includes: placing the housing on the fixture such that an alignment feature of the housing mates with a first alignment feature of the fixture; and placing the power semiconductor subassembly on the housing such that the distal end of each pin in a subset of the pins mates with a second alignment feature of the fixture.

[0047] Example 3: According to the method of Example 2, wherein the clamp includes an outer peripheral surface that coincides with the opening of the cavity of the clamp and laterally surrounds the opening of the cavity of the clamp, wherein the first alignment feature of the clamp is disposed on the outer peripheral surface, and wherein the second alignment feature of the clamp is disposed in the cavity of the clamp.

[0048] Example 4: The method according to Example 2 or 3, wherein the alignment feature of the housing includes at least two orifices formed in the housing, wherein the first alignment feature of the clamp includes at least two posts, and wherein placing the housing on the clamp includes: inserting each of the at least two posts of the clamp into a corresponding orifice of the at least two orifices of the housing.

[0049] Example 5: The method according to Example 4, wherein the at least two pillars of the clamp are tapered.

[0050] Example 6: The method according to any one of Examples 2 to 5, wherein the second alignment feature of the fixture includes an aperture formed in each of at least two sidewall features of the fixture, and wherein placing the power semiconductor subassembly on the housing includes: inserting the distal end of each pin in the subset of the pins into the corresponding aperture formed in the at least two sidewall features of the fixture.

[0051] Example 7: The method according to Example 6, wherein the at least two sidewall features of the fixture partially define the cavity of the fixture, and wherein, when the power semiconductor sub-assembly is placed on the housing, each pin not included in the subset of pins is received by the cavity of the fixture.

[0052] Example 8: According to the method of Example 7, wherein the cavity of the clamp is further defined by a base and a sidewall, and wherein each of the at least two sidewall features of the clamp extends from the base and the sidewall.

[0053] Example 9: The method according to Example 7 or 8, wherein the cavity of the clamp is further defined by an opening that coincides with and is laterally surrounded by the outer peripheral surface of the clamp, wherein an orifice formed in each of at least two sidewall features of the clamp is formed in the outward-facing surface of the sidewall feature, and wherein the outward-facing surface of each of the at least two sidewall features is recessed relative to the opening.

[0054] Example 10: The method according to any one of Examples 6 to 9, wherein the orifice formed in the at least two sidewall features of the fixture is tapered.

[0055] Example 11: The method according to any one of Examples 1 to 10, wherein attaching the housing to the power semiconductor sub-assembly includes gluing.

[0056] Example 12: The method according to any one of Examples 1 to 11 further includes attaching a cover to the housing and / or power semiconductor sub-assembly, wherein the cover further defines an internal space in which pins and one or more power semiconductor dies are disposed, and wherein each of the pins extends out of the housing through an opening in the cover.

[0057] Example 13: The method according to any one of Examples 1 to 12, wherein after attaching the housing to the power semiconductor sub-assembly, the final position of each pin deviates from the target position by less than 0.4 mm in both the first and second directions relative to the reference system.

[0058] Example 14: The method according to any one of Examples 1 to 13, wherein at least one of the length or width of the housing in a dimension substantially parallel to the substrate is less than 100 mm.

[0059] Example 15: The method described in any of Examples 1 to 14, wherein the diameter of each pin is less than 1 mm.

[0060] Example 16: A method for forming a power semiconductor module having a plurality of pins, the method comprising: attaching the plurality of pins and one or more power semiconductor dies to a first side of a substrate to form a power semiconductor subassembly; aligning the distal end of each of the pins with alignment features of an electrically insulating housing using a jig; and, after the alignment, attaching the housing to the power semiconductor subassembly such that the housing and the substrate together define an internal space in which the pins and the one or more power semiconductor dies are disposed, wherein the pins extend beyond the housing, wherein the alignment comprises: placing the housing on the jig such that the alignment features of the housing engage with a first alignment feature of the jig; and placing the power semiconductor subassembly on the housing such that the distal end of each pin in a subset of the pins engages with a second alignment feature of the jig.

[0061] Example 17: The method according to Example 16, wherein the clamp includes an outer peripheral surface that coincides with the opening of a cavity of the clamp and laterally surrounds the opening of the cavity of the clamp, wherein a first alignment feature of the clamp is disposed on the outer peripheral surface, and wherein a second alignment feature of the clamp is disposed in the cavity of the clamp.

[0062] Example 18: The method according to Example 16 or 17, wherein, after attaching the housing to the power semiconductor sub-assembly, the final position of each pin deviates from the target position by less than 0.4 mm in both the first and second directions relative to the reference system.

[0063] Example 19: The method according to any one of Examples 16 to 18, wherein at least one of the length or width of the housing in a dimension substantially parallel to the substrate is less than 100 mm.

[0064] Example 20: The method described in any of Examples 16 to 19, wherein the diameter of each pin is less than 1 mm.

[0065] Terms such as "first," "second," etc., are used to describe various elements, areas, parts, etc., and are not intended to be limiting. Throughout the specification, the same term refers to the same element.

[0066] As used herein, the terms “having,” “comprising,” “including,” “containing,” etc., are open-ended terms that indicate the presence of the said element or feature but do not exclude additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0067] Unless otherwise expressly stated, the expression “and / or” shall be interpreted to include all possible parallel and alternative combinations. For example, the expression “A and / or B” shall be interpreted to mean A but not B, B but not A, or both A and B. Unless otherwise expressly stated, the expression “at least one of…” shall be interpreted in the same manner as “and / or”. For example, the expression “at least one of A and B” shall be interpreted to mean A but not B, B but not A, or both A and B.

[0068] It should be understood that, unless otherwise specifically stated, the features of the various embodiments described herein can be combined with each other.

[0069] Although specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be used instead of the specific embodiments shown and described without departing from the scope of this disclosure. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A method for increasing the overall pin alignment accuracy of a power semiconductor module having multiple pins, the method comprising: The plurality of pins and one or more power semiconductor dies are attached to a first side of the substrate to form a power semiconductor subassembly; Use a clamp to align the distal end of each of the pins with the alignment features of the electrically insulating housing; as well as After the alignment, the housing is attached to the power semiconductor sub-assembly such that the housing and the substrate together define an internal space in which the pins and the one or more power semiconductor dies are disposed. The pin extends outside the housing.

2. The method according to claim 1, wherein, The alignment includes: The housing is placed on the clamp such that the alignment feature of the housing mates with the first alignment feature of the clamp; and The power semiconductor subassembly is placed on the housing such that the distal end of each pin in a subset of the pins mates with a second alignment feature of the clamp.

3. The method according to claim 2, in, The clamp includes an outer peripheral surface that coincides with the opening of the clamp's cavity and laterally surrounds the opening of the clamp's cavity. The first alignment feature of the clamp is disposed on the outer peripheral surface, and The second alignment feature of the clamp is disposed in the cavity of the clamp.

4. The method according to claim 2, wherein, The alignment feature of the housing includes at least two orifices formed in the housing, wherein the first alignment feature of the clamp includes at least two posts, and wherein placing the housing on the clamp includes: inserting each of the at least two posts of the clamp into a corresponding orifice among the at least two orifices of the housing.

5. The method according to claim 4, wherein, The at least two posts of the clamp are tapered.

6. The method according to claim 2, wherein, The second alignment feature of the clamp includes an aperture formed in each of at least two sidewall features of the clamp, and wherein placing the power semiconductor subassembly on the housing includes inserting the distal end of each pin in the subset of the pins into the corresponding aperture formed in the at least two sidewall features of the clamp.

7. The method according to claim 6, wherein, The at least two sidewall features of the clamp partially define the cavity of the clamp, and wherein, when the power semiconductor subassembly is placed on the housing, each pin not included in the subset of pins is received by the cavity of the clamp.

8. The method according to claim 7, wherein, The cavity of the clamp is further defined by a base and a sidewall, wherein each of the at least two sidewall features of the clamp extends from the base and the sidewall.

9. The method according to claim 7, in, The cavity of the clamp is further defined by an opening that coincides with and is laterally surrounded by the outer peripheral surface of the clamp. Wherein, the orifice formed in each of the at least two sidewall features of the fixture is formed in the outward-facing surface of the sidewall feature, and Wherein, the outward-facing surface of each of the at least two sidewall features is recessed relative to the opening.

10. The method according to claim 6, wherein, The orifices formed in the at least two sidewall features of the fixture are tapered.

11. The method according to claim 1, wherein, Attaching the housing to the power semiconductor sub-assembly includes gluing.

12. The method according to claim 1, further comprising: The cover is attached to the housing and / or the power semiconductor sub-assembly, wherein the cover further defines the internal space in which the pins and the one or more power semiconductor dies are disposed, and wherein each of the pins extends out of the housing through an opening in the cover.

13. The method according to claim 1, wherein, After the housing is attached to the power semiconductor sub-assembly, the final position of each pin deviates from the target position by less than 0.4 mm in both the first and second directions relative to the reference system.

14. The method according to claim 1, wherein, The housing has a length or width of at least 100 mm in a dimension substantially parallel to the substrate.

15. The method according to claim 1, wherein, Each of the pins has a diameter of less than 1 millimeter.

16. A method for forming a power semiconductor module having a plurality of pins, the method comprising: The plurality of pins and one or more power semiconductor dies are attached to a first side of the substrate to form a power semiconductor subassembly; Use a clamp to align the distal end of each of the pins with the alignment features of the electrically insulating housing; as well as After the alignment, the housing is attached to the power semiconductor sub-assembly such that the housing and the substrate together define an internal space in which the pins and the one or more power semiconductor dies are disposed. The pins extend beyond the housing. The alignment includes: The housing is placed on the clamp such that the alignment feature of the housing mates with the first alignment feature of the clamp; and The power semiconductor subassembly is placed on the housing such that the distal end of each pin in a subset of the pins mates with a second alignment feature of the clamp.

17. The method of claim 16, in, The clamp includes an outer peripheral surface that coincides with the opening of the clamp's cavity and laterally surrounds the opening of the clamp's cavity. The first alignment feature of the clamp is disposed on the outer peripheral surface, and The second alignment feature of the clamp is disposed in the cavity of the clamp.

18. The method according to claim 16, wherein, After the housing is attached to the power semiconductor sub-assembly, the final position of each pin deviates from the target position by less than 0.4 mm in both the first and second directions relative to the reference system.

19. The method of claim 16, wherein, The housing has a length or width of at least 100 mm in a dimension substantially parallel to the substrate.

20. The method of claim 16, wherein, Each of the pins has a diameter of less than 1 millimeter.

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