Method of forming shallow trench isolation structure
Patent Information
- Application Number
- CN202610492786.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-14
- Publication Date
- 2026-08-18
AI Technical Summary
由于干法蚀刻过程中会产生氟（F）离子残留，且干法蚀刻工序与STI完全淀积工序之间存在不可避免的时间间隔，因此，在干法刻蚀工序完成后，残留的氟离子会暴露于空气环境中，与空气中的水汽发生化学反应生成具有强腐蚀性的氢氟酸（HF），氢氟酸会缓慢侵蚀STI结构中的隔离介质，导致STI结构内部形成空隙（Void）缺陷，从而会破坏存储单元的电学隔离效果，引发漏电、信号串扰等问题，最终导致芯片功能失效，大幅降低产品良率与生产效益
[0020] This application employs a combined process of "partial deposition - dry etching - wet cleaning - complete deposition." First, a first isolation dielectric layer is formed on the exposed surfaces of the trench, pad oxide layer, and hard mask layer. The first isolation dielectric layer fills the trench and forms an opening above the trench. Then, the first isolation dielectric layer is dry etched to thin it while increasing the width and angle of the opening. Next, wet cleaning is used to remove fluoride ions remaining in the first isolation dielectric layer due to dry etching, preventing the formation of hydrofluoric acid at its source. Finally, a second isolation dielectric layer is formed on the surface of the first isolation dielectric layer, filling the opening. This process helps avoid the formation of voids in the STI structure, improves the integrity of the STI structure, and thus enhances the yield and reliability of the chip product.
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Figure CN122602844A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for forming a shallow trench isolation structure. Background Technology
[0002] In the field of semiconductor device manufacturing, shallow trench isolation (STI) is the key to achieving electrical isolation between semiconductor devices. Taking memory devices as an example, the integrity of the STI structure is one of the determining factors of the leakage current level and signal crosstalk characteristics of memory chips, and significantly affects chip yield and reliability.
[0003] In the STI structure provided by related technologies, taking 48-nanometer (nm) NOR flash memory as an example, its STI structure is usually fabricated using a combination of "partial deposition - dry etching - full deposition". Because residual fluoride (F) ions are generated during the dry etching process, and there is an unavoidable time interval between the dry etching process and the STI full deposition process, the residual fluoride ions are exposed to the air after the dry etching process is completed. They react chemically with moisture in the air to generate highly corrosive hydrofluoric acid (HF). Hydrofluoric acid slowly erodes the isolation medium in the STI structure, causing void defects inside the STI structure. This damages the electrical isolation effect of the memory cells, leading to leakage, signal crosstalk, and ultimately chip malfunction, significantly reducing product yield and production efficiency. Summary of the Invention
[0004] This application provides a method for forming a shallow trench isolation structure, which helps to avoid the formation of voids in the STI structure and improve the integrity of the STI structure.
[0005] In view of this, this application provides a method for forming a shallow trench isolation structure, comprising:
[0006] A substrate with trenches is provided, the trenches isolating the active region of the substrate, and a pad oxide layer and a hard mask layer are formed sequentially from bottom to top on the substrate between the trenches;
[0007] A first isolation medium layer is formed on the exposed surfaces of the trench, the padding oxide layer, and the hard mask layer. The first isolation medium layer fills the trench and forms an opening above the trench.
[0008] Dry etching is performed on the first isolation dielectric layer, which thins the first isolation dielectric layer while increasing the width of the opening and the angle of the opening.
[0009] The first isolation dielectric layer is wet-cleaned to remove the fluoride ions remaining in the first isolation dielectric layer after dry etching.
[0010] A second isolation medium layer is formed on the surface of the first isolation medium layer, and the second isolation medium layer fills the opening.
[0011] Optionally, the cleaning solution used in the wet cleaning process includes an aqueous solution containing ammonium hydroxide and hydrogen peroxide.
[0012] Optionally, the mass ratio of ammonium hydroxide, hydrogen peroxide, and water in the cleaning solution is from 1:2.5:100 to 1:1.5:60.
[0013] Optionally, the wet cleaning process takes 10-20 seconds.
[0014] Optionally, after dry etching of the first isolation dielectric layer, the sidewall slope of the opening is greater than the sidewall slope of the trench.
[0015] Optionally, after dry etching of the first isolation dielectric layer, the cross-sectional profile of the opening is V-shaped.
[0016] Optionally, the material of the first insulating dielectric layer includes at least one of silicon oxide, silicon oxynitride, and silicon carbide.
[0017] Optionally, the material of the second insulating dielectric layer includes at least one of silicon oxide, silicon oxynitride, and silicon carbide.
[0018] Optionally, the dry etching process includes a dry etching process with a pre-cleaning step.
[0019] The technical solution of this application has at least the following advantages:
[0020] This application employs a combined process of "partial deposition - dry etching - wet cleaning - complete deposition." First, a first isolation dielectric layer is formed on the exposed surfaces of the trench, pad oxide layer, and hard mask layer. The first isolation dielectric layer fills the trench and forms an opening above the trench. Then, the first isolation dielectric layer is dry etched to thin it while increasing the width and angle of the opening. Next, wet cleaning is used to remove fluoride ions remaining in the first isolation dielectric layer due to dry etching, preventing the formation of hydrofluoric acid at its source. Finally, a second isolation dielectric layer is formed on the surface of the first isolation dielectric layer, filling the opening. This process helps avoid the formation of voids in the STI structure, improves the integrity of the STI structure, and thus enhances the yield and reliability of the chip product. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0022] Figure 1 This is a scanning electron microscope (SEM) image of a shallow trench isolation structure formed in related technologies;
[0023] Figure 2 This is a process flow diagram of a method for forming a shallow trench isolation structure provided in an exemplary embodiment of this application;
[0024] Figure 3 This is a cross-sectional schematic diagram of a trenched substrate provided in a method for forming a shallow trench isolation structure according to an exemplary embodiment of this application.
[0025] Figure 4 This is a cross-sectional schematic diagram of the first isolation medium layer after its formation in a method for forming a shallow trench isolation structure provided in an exemplary embodiment of this application;
[0026] Figure 5 This is a schematic cross-sectional view after dry etching in a method for forming a shallow trench isolation structure provided in an exemplary embodiment of this application;
[0027] Figure 6 This is a cross-sectional schematic diagram of the second isolation medium layer after its formation in a method for forming a shallow trench isolation structure provided in an exemplary embodiment of this application;
[0028] Figure 7 This is a SEM image of the second isolation medium layer after its formation in a method for forming a shallow trench isolation structure provided in an exemplary embodiment of this application;
[0029] Figure 8 This is a profile analysis (FA) diagram of the first isolation medium layer after its formation in a method for forming a shallow trench isolation structure provided in an exemplary embodiment of this application.
[0030] Figure 9 This is a diagram of the first isolation medium layer after dry etching in a method for forming a shallow trench isolation structure provided in an exemplary embodiment of this application.
[0031] Figure 10 This is a diagram of the first isolation medium layer after its formation in a method for forming a shallow trench isolation structure provided in another exemplary embodiment of this application;
[0032] Figure 11 This is a diagram of the first isolation medium layer after wet cleaning in a method for forming a shallow trench isolation structure provided in another exemplary embodiment of this application;
[0033] The numbers in the diagram represent:
[0034] 100, Substrate; 110, Trench; 120, Pad oxide layer; 130, Hard mask layer
[0035] 200, First isolation medium layer; 210, Opening;
[0036] 300. Second isolation medium layer; Detailed Implementation
[0037] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0038] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0039] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0040] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0041] The following is combined with Figures 1 to 11 This describes an embodiment of the present application.
[0042] refer to Figure 2 The illustration shows an embodiment of this application, providing a method for forming a shallow trench isolation structure, comprising:
[0043] S1, a substrate 100 with trenches 110 is provided, the trenches 110 isolate the active regions of the substrate 100, and a pad oxide layer 120 and a hard mask layer 130 are formed sequentially from bottom to top on the substrate 100 between the trenches 110.
[0044] Exemplarily, the substrate 100 can be a silicon substrate 100, a germanium (Ge) substrate 100, a gallium arsenide (GaAs) substrate 100, or other materials suitable for semiconductor device manufacturing. The pad oxide layer 120 includes a silicon oxide layer, and the hard mask layer 130 includes a silicon nitride layer. The formation of trenches 110 in the substrate 100 and the formation of the pad oxide layer 120 and the hard mask layer 130 on the substrate 100 between the trenches 110 are typically achieved through a combination of thermal oxidation, deposition, photolithography, and etching processes. For example, the pad oxide layer 120 is first formed on the substrate 100 by thermal oxidation, then a nitride layer is deposited on the coupling oxide layer 120 by chemical vapor deposition (CVD), then the pattern is transferred to the nitride layer by photolithography etching to form the hard mask layer 130, and then the trenches 110 are formed by etching using the hard mask layer 130 as a mask.
[0045] S2, a first isolation medium layer 200 is formed on the exposed surfaces of the trench 110, the pad oxide and the hard mask layer 130, the first isolation medium layer 200 fills the trench 110 and forms an opening 210 above the trench 110.
[0046] For example, the first isolation dielectric layer 200 is typically formed on the surfaces exposed by the trench 110, the pad oxide layer 120, and the hard mask layer 130 by a deposition process (e.g., CVD).
[0047] In some embodiments, the material of the first insulating dielectric layer 200 includes at least one of silicon oxide (SiO2), silicon oxynitride (SiON), and silicon carbide (SiC).
[0048] In some embodiments, the thickness of the formed first insulating dielectric layer 200 is 80 Å to 100 Å, for example, 80 Å, 90 Å, 100 Å, etc.; the width of the opening 210 is 80 nm to 100 nm, for example, 80 nm, 90 nm, 100 nm, etc.; and the depth of the opening 210 is 1200 Å to 1600 Å, for example, 1200 Å, 1400 Å, 1600 Å, etc.
[0049] For example, SEM is typically used for cross-sectional analysis and to measure the thickness of the isolation medium layer 200, the width and depth of the opening 210.
[0050] S3, dry etching is performed on the first isolation dielectric layer 200. While the first isolation dielectric layer 200 is thinned, the width of the opening 210 increases and the angle of the opening 210 becomes larger.
[0051] It should be noted that the angle of opening 210 refers to the degree measure of the angle formed by the cross-section of the opening sidewall.
[0052] In some embodiments, after dry etching of the first isolation dielectric layer 200, the sidewall slope of the opening 210 is greater than that of the trench 110, resulting in a larger opening angle. This morphology facilitates the full filling of the opening 210 by the subsequent second isolation dielectric, thereby helping to avoid the formation of voids in the STI structure.
[0053] In some embodiments, after dry etching of the first isolation dielectric layer 200, the cross-sectional profile of the opening 210 is V-shaped.
[0054] It should be noted that "the cross-sectional profile of opening 210 is V-shaped" is a general description of the shape of opening 210, which is wider at the top and narrower at the bottom. This shape can specifically represent a standard V-shape, an inverted trapezoid, or other irregular shapes that conform to the characteristics of being wider at the top and narrower at the bottom.
[0055] In some embodiments, the dry etching process includes a pre-cleaning step (i.e., pre-cleaning is performed before dry etching).
[0056] For example, the dry etching process in the pre-cleaning step is a silicon cobalt nickel (SiCoNi) etching process. By using the SiCoNi etching process to dry etch the first isolation dielectric layer 200, the thickness of the first isolation dielectric layer 200 and the morphology of the opening 210 can be precisely controlled, ensuring the quality of the subsequent filling of the second isolation dielectric.
[0057] In some embodiments, after dry etching of the first isolation dielectric layer 200, the thickness of the first isolation dielectric layer 200 is 60 Å - 85 Å, the width of the opening 210 is 82 nm - 110 nm, and the depth of the opening 210 is 1220 Å - 1900 Å.
[0058] For example, the thickness of the first insulating dielectric layer 200 can be 60 Å, 65 Å, 70 Å, 75 Å, 80 Å, 85 Å, etc., the width of the opening 210 can be 82 nm, 85 nm, 90 nm, 100 nm, 110 nm, etc., and the depth of the opening 210 can be 1220 Å, 1300 Å, 1400 Å, 1500 Å, 1600 Å, etc.
[0059] For example, the FA results after the formation of the first isolation dielectric layer 200 are shown in [reference]. Figure 8 The thickness of the first isolation dielectric silicon oxide on the silicon nitride hard mask is 94 Å, the width of the opening 210 is 85.1 nm, and the depth of the opening 210 is 1498 Å; the FA results after dry etching of the first isolation dielectric layer 200 are shown in [reference]. Figure 9 The first isolation dielectric silicon oxide on the silicon nitride hard mask has a thickness of 71 Å, an opening 210 with a width of 89.6 nm, and an opening 210 with a depth of 1522 Å.
[0060] S4, perform wet cleaning on the first isolation dielectric layer 200 to remove fluoride ions remaining in the first isolation dielectric layer 200 after dry etching.
[0061] In some embodiments, the cleaning solution used in wet cleaning includes an aqueous solution containing ammonium hydroxide and hydrogen peroxide.
[0062] Aqueous solutions of ammonium hydroxide (NH4OH) and hydrogen peroxide are alkaline, and fluoride ions (F⁻) can react with them to form ammonium fluoride (NH4F), which is easily soluble in water and can be effectively washed away. Using this cleaning solution to perform wet cleaning of the first isolation medium helps to prevent fluoride ions remaining in the first isolation medium layer 200 after dry etching from combining with water vapor in the air to form hydrofluoric acid and corroding the isolation medium in the STI structure.
[0063] Understandably, wet cleaning is usually carried out at room temperature, which refers to a temperature range of 15℃-35℃.
[0064] In some embodiments, the mass ratio of ammonium hydroxide, hydrogen peroxide, and water in the cleaning solution is from 1:2.5:100 to 1:1.5:60.
[0065] The inventors discovered in their research that when the concentrations of ammonia hydroxide and hydrogen peroxide in the cleaning solution are too high, the corrosion rate of the first isolation medium is too fast. This leads to a significant reduction in the thickness of the first isolation medium layer 200 and a significant deterioration in its surface morphology, affecting the filling quality of subsequent isolation media and thus impacting the integrity of the STI structure. Conversely, when the concentrations of ammonia hydroxide and hydrogen peroxide in the cleaning solution are too low, the cleaning efficiency is too low, making it difficult to effectively remove fluoride ions remaining in the first isolation medium layer 200. To ensure the cleaning solution's effectiveness in removing fluoride ions remaining from dry etching while minimizing damage to the first isolation medium layer 200, the mass ratio of ammonia hydroxide, hydrogen peroxide, and water in the cleaning solution is between 1:2.5:100 and 1:1.5:60.
[0066] For example, the mass ratio of ammonia hydroxide, hydrogen peroxide, and water in the cleaning solution can be 1:2.5:100, 1:2:80, 1:1.5:60, etc., which can be set according to the actual application scenario.
[0067] In some embodiments, the wet cleaning process takes 10-20 seconds.
[0068] The inventors discovered in their research that if the wet cleaning process takes too long, the cleaning solution will cause significant damage to the first isolation dielectric layer 200, thus affecting the integrity of the STI structure. If the wet cleaning process is too short, the fluoride ions remaining in the first isolation dielectric layer 200 will be difficult to remove effectively. In order to ensure the cleaning solution's removal effect on the residual fluoride ions from the dry etching process, while minimizing damage to the first isolation dielectric layer 200, the wet cleaning process time is set at 10-20 seconds.
[0069] For example, the processing time for wet cleaning can be 10s, 15s, 20s, etc., and can be set according to the actual application scenario.
[0070] In some embodiments, after wet cleaning of the first isolation medium layer 200, the thickness of the first isolation medium layer 200 is 60Å-85Å, the width of the opening 210 is 82nm-110nm, and the depth of the opening 210 is 1220Å-1900Å.
[0071] For example, the thickness of the first insulating dielectric layer 200 can be 60 Å, 65 Å, 70 Å, 75 Å, 80 Å, 85 Å, etc., the width of the opening 210 can be 82 nm, 85 nm, 90 nm, 100 nm, 110 nm, etc., and the depth of the opening 210 can be 1220 Å, 1300 Å, 1400 Å, 1500 Å, 1600 Å, etc.
[0072] For example, the FA result after the formation of the first isolation dielectric layer 200 is shown in the figure. Figure 10The thickness of the first isolation dielectric silicon oxide on the silicon nitride hard mask is 89 Å, the width of the opening 210 is 83.8 nm, and the depth of the opening 210 is 1432 Å. When the mass ratio of ammonium hydroxide, hydrogen peroxide, and water in the cleaning solution used for wet cleaning is 1:2:80, and the wet cleaning time is 15 s, the FA results after wet cleaning of the first isolation dielectric layer 200 are shown in the figure. Figure 11 The first isolation dielectric silicon oxide on the silicon nitride hard mask has a thickness of 71 Å, an opening 210 with a width of 87.6 nm, and an opening 210 with a depth of 1494 Å.
[0073] S5, a second isolation medium layer 300 is formed on the surface of the first isolation medium layer 200, and the second isolation medium layer 300 fills the opening 210.
[0074] For example, the second isolation medium layer 300 is typically formed on the surface of the first isolation medium layer 200 by a deposition process, such as physical vapor deposition (PVD).
[0075] In some embodiments, the material of the second insulating dielectric layer 300 includes at least one of silicon oxide, silicon oxynitride, and silicon carbide.
[0076] For example, after the second isolation dielectric layer 300 is formed, see Figure 7 There are no gaps in the STI structure.
[0077] In the STI structures provided by related technologies, taking 48-nanometer (nm) NOR flash memory as an example, its STI structure is typically fabricated using a combination of processes: partial deposition, dry etching, and full deposition. See also... Figure 1 Because fluoride (F) ions are generated during the dry etching process, and there is an unavoidable time interval between the dry etching process and the STI full deposition process, the residual fluoride ions will be exposed to the air environment after the dry etching process is completed. They will react with the moisture in the air to generate highly corrosive hydrofluoric acid (HF). Hydrofluoric acid will slowly erode the isolation medium in the STI structure, causing void defects to form inside the STI structure. This will destroy the electrical isolation effect of the memory cell, causing problems such as leakage and signal crosstalk, and ultimately leading to chip failure, which will significantly reduce product yield and production efficiency.
[0078] This application employs a combined process of "partial deposition - dry etching - wet cleaning - complete deposition." First, a first isolation dielectric layer 200 is formed on the exposed surfaces of the trench 110, the pad oxide layer 120, and the hard mask layer 130. The first isolation dielectric layer 200 fills the trench 110 and forms an opening 210 above the trench 110. Then, the first isolation dielectric layer 200 is dry etched to thin it while increasing the width and angle of the opening 210. Next, wet cleaning is used to remove fluoride ions remaining in the first isolation dielectric layer 200 due to dry etching, preventing the formation of hydrofluoric acid at its source. Finally, a second isolation dielectric layer 300 is formed on the surface of the first isolation dielectric layer 200, filling the opening 210. This process helps to avoid the formation of voids in the STI structure, improves the integrity of the STI structure, and thus improves the yield and reliability of the chip product.
[0079] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for forming a shallow trench isolation structure, characterized in that, include: A substrate with trenches is provided, the trenches isolating the active region of the substrate, and a pad oxide layer and a hard mask layer are formed sequentially from bottom to top on the substrate between the trenches; A first isolation medium layer is formed on the exposed surfaces of the trench, the padding oxide layer, and the hard mask layer. The first isolation medium layer fills the trench and forms an opening above the trench. Dry etching is performed on the first isolation dielectric layer, which thins the first isolation dielectric layer while increasing the width of the opening and the angle of the opening. The first isolation dielectric layer is wet-cleaned to remove the fluoride ions remaining in the first isolation dielectric layer after dry etching. A second isolation medium layer is formed on the surface of the first isolation medium layer, and the second isolation medium layer fills the opening.
2. The method according to claim 1, characterized in that, The cleaning solution used in the wet cleaning process includes an aqueous solution containing ammonium hydroxide and hydrogen peroxide.
3. The method according to claim 2, characterized in that, The mass ratio of ammonia hydroxide, hydrogen peroxide, and water in the cleaning solution is from 1:2.5:100 to 1:1.5:
60.
4. The method according to claim 1, characterized in that, The wet cleaning process takes 10-20 seconds.
5. The method according to any one of claims 1, characterized in that, After dry etching of the first isolation dielectric layer, the sidewall slope of the opening is greater than the sidewall slope of the trench.
6. The method according to any one of claims 1, characterized in that, After dry etching of the first isolation dielectric layer, the cross-sectional profile of the opening is V-shaped.
7. The method according to any one of claims 1-6, characterized in that, The material of the first insulating dielectric layer includes at least one of silicon oxide, silicon oxynitride, and silicon carbide.
8. The method according to any one of claims 1-6, characterized in that, The material of the second insulating dielectric layer includes at least one of silicon oxide, silicon oxynitride, and silicon carbide.
9. The method according to any one of claims 1-6, characterized in that, The dry etching process includes a pre-cleaning step.