Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method. When a shallow trench isolation material layer with a certain thickness is left in the recess at the wafer edge, the residual shallow trench isolation material layer in the recess at the wafer edge is removed by second zero-layer etching to expose the bare wafer, then a metal silicide layer is deposited on the side wall and bottom wall of the recess at the wafer edge, and then a metal barrier layer is deposited on the surface of the metal silicide layer. The film layer stack structure in the recess at the wafer edge is optimized, so that the metal barrier layer in the edge recess of the wafer directly contacts the metal silicide layer, thereby solving the problems of metal material peeling (the metal barrier layer peels off from the recess position) and bulging / bubble defects of the metal material surface at the wafer edge, and improving the device yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for preparing a semiconductor device. Background Technology

[0002] In semiconductor manufacturing processes, as design dimensions decrease and performance requirements increase, the tolerance for defects generated during the process becomes increasingly lower. In advanced wafer fab processes, during the deposition of a barrier layer to prevent the diffusion of metal ions in contact holes, the metal ion barrier layer in the recesses of the wafer edge region (similar to the contact holes in the non-edge region of the wafer) is prone to peeling defects. These peeling defects located at the wafer edge can enter the effective die of the wafer during the process, thereby affecting the wafer yield.

[0003] Based on data from multiple rounds of experiments and wafer slicing, it was found that in the recesses at the edges of wafers with metal ion barrier layer peeling defects, after filling the main metal material layer, bulges / bubbles are easily generated on the surface of the main metal material layer in the recesses, which in turn form defects that affect semiconductor products. Therefore, it is crucial to improve the bulges / bubbles at the wafer edges. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor device, which can solve the problems of metal material peeling defects at the edge of traditional semiconductor devices and bulging / bubble defects on the surface of the metal material at the edge of the wafer, which affect the effective die of the wafer.

[0005] This application provides a method for fabricating a semiconductor device, including: A wafer is provided, and a first zero-layer etching is performed on the wafer to form at least one alignment mark on the wafer surface, wherein, during the first zero-layer etching process, the edge of the wafer will form a depression due to edge washing of the photolithography process and the etching process; A shallow trench isolation material layer is formed, which fills the depression; After forming a gate oxide layer and a gate material layer on the wafer surface away from the edge of the wafer, a portion of the gate material layer and a portion of the gate oxide layer are etched to form a gate structure. At the same time, a shallow trench isolation material layer of a first thickness in the recess at the edge of the wafer is etched away. After forming a silicide barrier layer on the wafer surface away from the edge of the wafer, the gate structure surface, and the shallow trench isolation material layer surface at the edge of the wafer, a portion of the silicide barrier layer is etched to expose a portion of the surface of the gate structure. At the same time, the silicide barrier layer and a second-thickness shallow trench isolation material layer in the recess at the edge of the wafer are etched away. A second zero-layer etching is performed on the wafer to remove the remaining thickness of the shallow trench isolation material layer in the recesses at the edge of the wafer; A metal silicide layer is formed at the recessed location; After forming an interlayer dielectric layer on the wafer away from the edge of the wafer and on the gate structure, the interlayer dielectric layer is etched to form a plurality of contact holes on the wafer surface and the gate structure surface. At the same time, a portion of the thickness of the metal silicide layer in the recess at the edge of the wafer is etched. A metal barrier layer is formed on the surface of the metal silicide layer and on the inner wall of the contact hole.

[0006] Optionally, in the method for fabricating the semiconductor device, the metal silicide layer is made of nickel silicide.

[0007] Optionally, in the method for fabricating the semiconductor device, after etching the interlayer dielectric layer to form a plurality of contact holes on the wafer surface and the gate structure surface, and simultaneously etching a portion of the thickness of the metal silicide layer in the recess at the edge of the wafer, the thickness of the metal silicide layer is 100 angstroms to 150 angstroms.

[0008] Optionally, in the method for fabricating the semiconductor device, during the second zero-layer etching of the wafer to remove the remaining thickness of the shallow trench isolation material layer in the recess at the edge of the wafer, the thickness of the shallow trench isolation material layer removed by etching is 4000 angstroms to 6000 angstroms.

[0009] Optionally, in the method for fabricating the semiconductor device, the thickness of the metal barrier layer is 90 angstroms to 110 angstroms.

[0010] Optionally, in the method for fabricating the semiconductor device, the metal barrier layer is made of titanium nitride.

[0011] Optionally, in the method for fabricating the semiconductor device, the shallow trench isolation material layer is made of silicon dioxide.

[0012] Optionally, in the method for fabricating the semiconductor device, after forming the metal barrier layer on the surface of the metal silicide layer on the inner wall of the recess and the inner wall of the contact hole, the method for fabricating the semiconductor device further includes: forming a metal material layer, the metal material layer filling the recess of the contact hole and the edge of the wafer.

[0013] Optionally, in the method for fabricating the semiconductor device, the wafer is a silicon substrate.

[0014] The technical solution of this application has at least the following advantages: In the semiconductor device fabrication method provided in this application, due to the poor adhesion between the shallow trench isolation material layer (silicon dioxide) and the subsequently deposited metal barrier layer (titanium nitride), peeling is prone to occur. Therefore, when a certain thickness of shallow trench isolation material layer remains in the recess of the wafer edge, this application removes the remaining shallow trench isolation material layer in the recess of the wafer edge through a second zero-layer etching to expose the bare wafer. Subsequently, a metal silicide layer is deposited on the sidewall and bottom wall (bare wafer) of the recess of the wafer edge. Then, a metal barrier layer is deposited on the surface of the metal silicide layer. This optimizes the film layer stacking structure in the recess of the wafer edge, allowing the metal barrier layer in the recess of the wafer edge to directly contact the metal silicide layer, thereby solving the problems of metal material peeling (metal barrier layer peeling off from the recess) defects in the recess of the wafer edge and bulging / bubble defects on the surface of the metal material in the wafer edge, and improving the device yield. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figures 2-9 This is a schematic diagram of the semiconductor structure in each process step of the semiconductor device fabrication according to an embodiment of the present invention; The reference numerals in the attached figures are explained as follows: 10-Substrate, 11-Recess, 20-Shallow trench isolation material layer, 21-Shallow trench isolation material layer of remaining thickness, 30-Metal silicide layer, 40-Metal barrier layer, 50-Metal material layer. Detailed Implementation

[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] This application provides a method for fabricating a semiconductor device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The method for fabricating the semiconductor device includes: First, perform step S1: Refer to Figure 2 , Figure 2 These are a top view and a cross-sectional view of a partial region of the semiconductor structure after the edge region of the wafer is recessed, according to an embodiment of this application. A wafer 10 is provided, and a first zero-layer etching is performed on the wafer 10 to form at least one alignment mark on the surface of the wafer 10. During the first zero-layer etching process, the wafer 10 undergoes edge washing, edge cleaning, and other processes, and a recess 11 is formed at the edge of the wafer 10.

[0022] In this embodiment, the wafer 10 is a silicon substrate, that is, the wafer 10 is a bare wafer.

[0023] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a cross-sectional view of the edge region of the semiconductor structure after the formation of the shallow trench isolation material layer according to an embodiment of this application, wherein the shallow trench isolation material layer 20 is formed and the shallow trench isolation material layer 20 fills the recess 11.

[0024] In this embodiment, the shallow trench isolation material layer 20 is made of silicon dioxide.

[0025] The shallow trench isolation material layer 20 is mainly used to fill multiple shallow trenches in the wafer to form different devices on the isolated wafer.

[0026] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a cross-sectional view of the semiconductor structure edge region after etching away a shallow trench isolation material layer of a first thickness in the recess of the edge of the wafer according to an embodiment of this application. After forming a gate oxide layer and a gate material layer on the surface of the wafer 10 away from the edge of the wafer 10, a portion of the gate material layer and a portion of the gate oxide layer are etched to form the gate structure of the semiconductor device. At the same time, the shallow trench isolation material layer 20 of a first thickness in the recess 11 of the edge of the wafer 10 is etched away.

[0027] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a cross-sectional view of the semiconductor structure edge region after etching away the silicide barrier layer and the second thickness of the shallow trench isolation material layer in the recess of the wafer edge according to an embodiment of this application. After forming a silicide barrier layer (not shown) on the surface of wafer 10 away from the edge of wafer 10, the surface of the gate structure, and the surface of the shallow trench isolation material layer at the edge of the wafer, a portion of the silicide barrier layer is etched to expose a portion of the surface of the gate structure. At the same time, the silicide barrier layer and the second thickness of the shallow trench isolation material layer 20 in the recess 11 at the edge of wafer 10 are etched away.

[0028] In this embodiment, the silicide barrier layer is made of silicon dioxide.

[0029] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6 This is a cross-sectional view of the semiconductor structure edge region after the wafer has undergone a second zero-layer etching according to an embodiment of this application. The wafer 10 is subjected to a second zero-layer etching to remove the remaining thickness of the shallow trench isolation material layer 21 in the recess 11 at the edge of the wafer 10.

[0030] During the second zero-layer etching of the wafer to remove the remaining thickness of the shallow trench isolation material layer in the recess at the edge of the wafer, the thickness of the shallow trench isolation material layer removed by etching is 4000 angstroms to 6000 angstroms.

[0031] Further, proceed to step S6: Refer to Figure 7 , Figure 7This is a cross-sectional view of the semiconductor structure edge region after a metal silicide layer is formed on the inner wall of the recess and the exposed surface of the gate structure according to an embodiment of this application. A metal silicide layer 30 is formed at the location of the recess 11.

[0032] In this embodiment, the metal silicide layer 30 is made of nickel silicide.

[0033] Preferably, a metal silicide layer 30 is formed on the inner wall of the recess 11 and on the exposed surface of the gate structure using a PVD (chemical vapor deposition) process.

[0034] Next, proceed to step S7: (Refer to...) Figure 8 , Figure 8 This is a cross-sectional view of the semiconductor structure edge region after etching a portion of the metal silicide layer in the recess of the edge of the wafer according to an embodiment of this application. After forming an interlayer dielectric layer on the wafer 10 away from the edge of the wafer 10 and on the gate structure, the interlayer dielectric layer is etched to form a plurality of contact holes on the wafer surface and the gate structure surface. At the same time, the metal silicide layer 30 with a portion of the thickness in the recess 11 of the edge of the wafer 10 is etched.

[0035] Wherein, after etching the interlayer dielectric layer to form a plurality of contact holes on the surface of the wafer 10 and the surface of the gate structure, and simultaneously etching a portion of the thickness of the metal silicide layer 30 in the recess 11 at the edge of the wafer 10, the thickness of the metal silicide layer 30 is 100 angstroms to 150 angstroms.

[0036] Finally, proceed to step S8: (Refer to...) Figure 9 , Figure 9 This is a cross-sectional view of the edge region of the semiconductor structure after a metal barrier layer is formed on the surface of the metal silicide layer 30 on the inner wall of the recess and on the inner wall of the contact hole, according to an embodiment of this application. A metal barrier layer 40 is formed on the surface of the metal silicide layer 30 and on the inner wall of the contact hole.

[0037] Preferably, the thickness of the metal barrier layer 40 is 90 angstroms to 110 angstroms.

[0038] Preferably, the metal barrier layer 40 is made of titanium nitride.

[0039] Furthermore, after the metal barrier layer 40 is formed on the surface of the metal silicide layer 30 on the inner wall of the recess 11 and on the inner wall of the contact hole, the method for fabricating the semiconductor device further includes: forming a metal material layer 50, the metal material layer 50 filling the recess 11 of the contact hole and the edge of the wafer.

[0040] In this application, due to the poor adhesion between the shallow trench isolation material layer (silicon dioxide) and the subsequently deposited metal barrier layer (titanium nitride), peeling is prone to occur. Therefore, when a certain thickness of shallow trench isolation material layer remains in the recess of the wafer edge, the remaining shallow trench isolation material layer in the recess of the wafer edge is removed by a second zero-layer etching to expose the bare wafer. Subsequently, a metal silicide layer is deposited on the sidewall and bottom wall (bare wafer) of the recess of the wafer edge. Then, a metal barrier layer is deposited on the surface of the metal silicide layer. This optimizes the film layer stacking structure in the recess of the wafer edge, so that the metal barrier layer in the recess of the wafer edge directly contacts the metal silicide layer, thereby solving the problems of metal material peeling (metal barrier layer peeling off from the recess) defects in the recess of the wafer edge and the bulging / bubble defects on the surface of the metal material in the wafer edge, and improving the device yield.

[0041] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A wafer is provided, and a first zero-layer etching is performed on the wafer to form at least one alignment mark on the wafer surface, wherein, during the first zero-layer etching process, the edge of the wafer will form a depression due to edge washing of the photolithography process and the etching process; A shallow trench isolation material layer is formed, which fills the depression; After forming a gate oxide layer and a gate material layer on the wafer surface away from the edge of the wafer, a portion of the gate material layer and a portion of the gate oxide layer are etched to form a gate structure. At the same time, a shallow trench isolation material layer of a first thickness in the recess at the edge of the wafer is etched away. After forming a silicide barrier layer on the wafer surface away from the edge of the wafer, the gate structure surface, and the shallow trench isolation material layer surface at the edge of the wafer, a portion of the silicide barrier layer is etched to expose a portion of the surface of the gate structure. At the same time, the silicide barrier layer and a second-thickness shallow trench isolation material layer in the recess at the edge of the wafer are etched away. A second zero-layer etching is performed on the wafer to remove the remaining thickness of the shallow trench isolation material layer in the recesses at the edge of the wafer; A metal silicide layer is formed at the recessed location; After forming an interlayer dielectric layer on the wafer away from the edge of the wafer and on the gate structure, the interlayer dielectric layer is etched to form a plurality of contact holes on the wafer surface and the gate structure surface. At the same time, a portion of the thickness of the metal silicide layer in the recess at the edge of the wafer is etched. A metal barrier layer is formed on the surface of the metal silicide layer and on the inner wall of the contact hole.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The metal silicide layer is made of nickel silicide.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After etching the interlayer dielectric layer to form a plurality of contact holes on the wafer surface and the gate structure surface, and simultaneously etching a portion of the thickness of the metal silicide layer in the recesses at the edge of the wafer, the thickness of the metal silicide layer is 100 angstroms to 150 angstroms.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, During the second zero-layer etching of the wafer to remove the remaining thickness of the shallow trench isolation material layer in the recess at the edge of the wafer, the thickness of the shallow trench isolation material layer removed by etching is 4000 angstroms to 6000 angstroms.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the metal barrier layer is 90 angstroms to 110 angstroms.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The metal barrier layer is made of titanium nitride.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The shallow trench isolation material layer is made of silicon dioxide.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the metal barrier layer on the surface of the metal silicide layer on the inner wall of the recess and on the inner wall of the contact hole, the method for fabricating the semiconductor device further includes: forming a metal material layer that fills the recess of the contact hole and the edge of the wafer.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The wafer is a silicon substrate.

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