Method of forming contact holes
Patent Information
- Application Number
- CN202610589638.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-29
- Publication Date
- 2026-08-18
AI Technical Summary
[0026]This application first performs a first dry etching process, stopping at the etching stop layer to form a groove. Then, an insulating sidewall is formed on the inner surface of the groove. A second dry etching process is then performed to remove the etching stop layer below the groove. Compared to a single etching process, this application uses two dry etching processes to form contact holes, which helps to avoid problems such as insufficient etching, over-etching, or sidewall damage. By forming an insulating sidewall between the two etching steps, not only can the thickness of the insulating dielectric layer between contact holes and between contact holes and the control gate be increased, but sidewall defects of the contact holes can also be filled, and their sidewall profile can be optimized. This is beneficial for the dispersion of the electric field on the insulating dielectric layer, improving the insulation reliability and breakdown resistance of the dielectric layer between contact holes and between contact holes and the control gate. This helps to reduce the risk of dielectric breakdown during device operation and improve the reliability of the device.
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Figure CN122602848A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for forming a contact hole. Background Technology
[0002] In semiconductor device manufacturing, contact holes (CTs) serve as critical vertical channels connecting the control gate (CG), source / drain regions, and upper metal circuitry, and their performance directly affects the electrical characteristics and reliability of the device.
[0003] In related technologies, taking NOR (Not-Or) flash memory as an example, after forming an interlayer dielectric layer on the surface of the NOR flash memory cell, a single etching process is typically used to form contact holes and fill them with metal to form metal plugs. As device dimensions shrink, the critical dimension (CD) of the contact holes continues to decrease, and the space between contact holes and the distance between the contact hole and the control gate also decreases accordingly. This process for forming contact holes has significant limitations: as the critical dimension of the contact holes shrinks, the etching process window narrows continuously, making a single etching process prone to problems such as insufficient etching, over-etching, or sidewall damage. Simultaneously, the narrow spacing between contact holes and between the contact hole and the gate leads to an increase in the electric field strength at the interface between the metal plug and the gate / dielectric layer, making dielectric breakdown highly likely during device operation. Figure 1 and Figure 2 As shown, this can cause device failure, affecting the device's reliability and lifespan. Summary of the Invention
[0004] This application provides a method for forming contact holes, which is beneficial to improving the dielectric breakdown resistance between contact holes and between contact holes and the control gate.
[0005] In view of this, this application provides a method for forming a contact hole, comprising:
[0006] S1, a substrate is provided, on which semiconductor device units are formed, and a silicide layer is formed on the substrate between adjacent semiconductor device units;
[0007] S2, forming an etch stop layer on the exposed surfaces of the semiconductor device unit and the substrate;
[0008] S3, an interlayer dielectric layer is formed on the surface exposed by the etch stop layer;
[0009] S4, photolithography forms a photoresist pattern, defines the target formation area of the groove, and exposes the interlayer dielectric layer of the area;
[0010] S5, using the photoresist pattern as a mask, perform the first dry etching, and stop the etching at the etching stop layer to form a groove on the interlayer dielectric layer;
[0011] S6, forming an insulating sidewall on the inner surface of the groove;
[0012] S7, a second dry etching is performed, the etching stop layer below the groove is removed, and a contact hole connected to the silicide layer is formed on the interlayer dielectric layer.
[0013] Optionally, the insulating sidewall includes a nitrided layer.
[0014] Optionally, the method for forming the interlayer dielectric layer includes:
[0015] S31, a first dielectric layer is formed in the isolation gap between adjacent semiconductor device units, and an opening is formed on the top of the first dielectric layer;
[0016] S32, dry etching is performed on the first dielectric layer, and the width of the opening is increased while the first dielectric layer is thinned;
[0017] S33, a second dielectric layer is formed on the surface of the first dielectric layer, and the second dielectric layer fills the opening and the isolation gap.
[0018] Optionally, the method for forming the interlayer dielectric layer further includes the step of forming a third dielectric layer on the surface of the second dielectric layer.
[0019] Optionally, the third dielectric layer includes a tetraethyl orthosilicate layer.
[0020] Optionally, before performing step S4, a step of planarizing the interlayer dielectric layer is also included.
[0021] Optionally, the etch stop layer includes a silicon oxynitride layer.
[0022] Optionally, the interlayer dielectric layer includes a silicon oxide layer.
[0023] Optionally, the semiconductor device unit includes a flash memory unit.
[0024] Optionally, the method, when used in a chip manufacturing process, further includes the step of forming a metal contact plug within a contact hole.
[0025] The technical solution of this application has at least the following advantages:
[0026] This application first performs a first dry etching process, stopping at the etching stop layer to form a groove. Then, an insulating sidewall is formed on the inner surface of the groove. A second dry etching process is then performed to remove the etching stop layer below the groove. Compared to a single etching process, this application uses two dry etching processes to form contact holes, which helps to avoid problems such as insufficient etching, over-etching, or sidewall damage. By forming an insulating sidewall between the two etching steps, not only can the thickness of the insulating dielectric layer between contact holes and between contact holes and the control gate be increased, but sidewall defects of the contact holes can also be filled, and their sidewall profile can be optimized. This is beneficial for the dispersion of the electric field on the insulating dielectric layer, improving the insulation reliability and breakdown resistance of the dielectric layer between contact holes and between contact holes and the control gate. This helps to reduce the risk of dielectric breakdown during device operation and improve the reliability of the device. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0028] Figure 1 This is a cross-sectional transmission electron microscope (TEM) image of a section after dielectric breakdown occurs between the contact hole and the control gate in the relevant technology.
[0029] Figure 2 This is a cross-sectional TEM image of a contact hole after dielectric breakdown occurs between them in the relevant technology.
[0030] Figure 3 This is a process flow diagram of a method for forming a contact hole provided in an exemplary embodiment of this application;
[0031] Figure 4 This is a schematic cross-sectional view of a substrate on which semiconductor device units are formed, provided in a method for forming contact holes according to an exemplary embodiment of this application.
[0032] Figure 5 This is a cross-sectional schematic diagram of the contact hole formation method provided in an exemplary embodiment of this application after the formation of an etch stop layer;
[0033] Figure 6 This is a schematic cross-sectional view of the method for forming a contact hole provided in an exemplary embodiment of this application after forming an interlayer dielectric layer;
[0034] Figure 7This is a schematic cross-sectional view of the contact hole forming method provided in an exemplary embodiment of this application after the groove has been formed;
[0035] Figure 8 This is a schematic cross-sectional view of the contact hole forming method provided in an exemplary embodiment of this application after forming an insulating sidewall;
[0036] Figure 9 This is a cross-sectional schematic diagram of the contact hole after it has been formed in a method for forming a contact hole according to an exemplary embodiment of this application;
[0037] Figure 10 This is a schematic cross-sectional view of the metal contact plug formed in a method for forming a contact hole according to an exemplary embodiment of this application.
[0038] Figure label:
[0039] 10. Substrate; 11. Semiconductor device unit; 12. Silicification layer; 13. Etch stop layer; 14. Isolation gap
[0040] 20. Interlayer dielectric layer; 21. Groove; 22. Insulating sidewall; 23. Contact hole; 24. Metal contact plug Detailed Implementation
[0041] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0042] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0043] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0044] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0045] The following is combined Figures 3 to 10 This describes an embodiment of the present application.
[0046] refer to Figure 1 The illustration shows an embodiment of this application, providing a method for forming a contact hole, comprising:
[0047] S1, a substrate 10 is provided, on which semiconductor device units 11 are formed, and a silicide layer 12 is formed on the substrate between adjacent semiconductor device units.
[0048] For example, the substrate 10 can be made of silicon, germanium (Ge), gallium arsenide (GaAs), or other materials suitable for semiconductor device manufacturing. The silicide layer 12 is located on the upper surface of the active region of the substrate. The silicide layer 12 can be a metal silicide layer, such as a nickel silicide (NiSi) layer, a cobalt silicide (CoSi2) layer, a titanium silicide (TiSi2) layer, etc. Typically, a silicide layer 12 can be formed on the substrate between adjacent semiconductor device units using a silicide process. For example, first, metal is deposited on the exposed surfaces of the semiconductor device units and the substrate. Then, a rapid annealing process is used to react the metal with silicon to form a metal silicide layer on the top of the control gate of the semiconductor device unit and on the substrate between adjacent semiconductor device units. Finally, the metal that has not reacted with silicon is removed.
[0049] In some embodiments, the semiconductor device unit 11 formed on the substrate 10 may be selected from at least one of memory device units (e.g., NOR flash memory units) and logic device units (e.g., MOS transistors).
[0050] For example, see Figure 4 The semiconductor device unit 11 formed on the substrate 10 includes a NOR flash memory unit, which includes a stacked gate structure and sidewalls located on the periphery of the gate structure.
[0051] S2, an etch stop layer 13 is formed on the exposed surfaces of the semiconductor device unit 11 and the substrate 10.
[0052] In some embodiments, the etch stop layer 13 includes a silicon oxynitride (SiON) layer.
[0053] For example, silicon oxynitride can be deposited on the exposed surfaces of the semiconductor device unit 11 and the substrate 10 using chemical vapor deposition (CVD) to form an etch stop layer 13.
[0054] S3, an interlayer dielectric layer 20 is formed on the surface exposed by the etch stop layer 13.
[0055] In some embodiments, the method for forming the interlayer dielectric layer 20 includes:
[0056] S31, a first dielectric layer is formed in the isolation gap between adjacent semiconductor device units 11, and an opening is formed on the top of the first dielectric layer;
[0057] S32, dry etching is performed on the first dielectric layer, and the width of the opening is increased while the first dielectric layer is thinned;
[0058] S33, a second dielectric layer is formed on the surface of the first dielectric layer, and the second dielectric layer fills the opening and the isolation gap.
[0059] The interlayer dielectric layer 20 is formed by a combination of "partial deposition - dry etching - complete deposition", which helps to avoid the formation of voids in the structure of the interlayer dielectric layer 20 and optimizes the integrity of the structure of the interlayer dielectric layer 20.
[0060] For example, the formation of the first dielectric layer within the isolation gap and the formation of the second dielectric layer on the surface of the first dielectric layer can both be achieved using a high aspect ratio process (HARP) deposition.
[0061] For example, both the first dielectric layer and the second dielectric layer include a silicon oxide (SiO2) layer.
[0062] In related technologies, high-density plasma (HDP) deposition and high-aspect-ratio process (HARP) deposition are commonly used to form the interlayer dielectric layer 20. However, HDP plasma can damage the structure in the semiconductor device cell 11. By using a combination of HARP partial deposition, dry etching, and HARP complete deposition, the influence of HDP plasma on the semiconductor device cell 11 can be avoided, which is beneficial to improving the reliability of the semiconductor device cell 11.
[0063] In some embodiments, the method for forming the interlayer dielectric layer 20 further includes the step of forming a third dielectric layer on the surface of the second dielectric layer.
[0064] For example, forming a third dielectric layer on the surface of the second dielectric layer can be achieved by chemical vapor deposition (CVD), and the third dielectric layer includes a tetraethyl orthosilicate layer.
[0065] In some embodiments, after forming the interlayer dielectric layer 20, a step of planarizing the interlayer dielectric layer 20 is further included.
[0066] For example, chemical mechanical polishing (CMP) is typically used to planarize the interlayer dielectric layer 20.
[0067] S4, photolithography forms a photoresist pattern, defines the target formation area of the groove, and exposes the interlayer dielectric layer 20 in that area.
[0068] S5, using the photoresist pattern as a mask, perform the first dry etching, and stop the etching at the etching stop layer 13, forming a groove 21 on the interlayer dielectric layer 20.
[0069] S6, forming an insulating sidewall 22 on the inner surface of the groove 21.
[0070] For example, forming an insulating sidewall 22 on the inner surface of the groove 21 can be achieved using atomic layer deposition (ALD).
[0071] The critical dimensions of the contact hole can be adjusted by controlling the thickness of the insulating sidewall 22.
[0072] In some embodiments, the insulating sidewall 22 includes a nitrided layer.
[0073] For example, the nitride layer includes silicon nitride.
[0074] Silicon nitride has a higher dielectric constant than general interlayer dielectric materials, which can withstand higher electric field strengths. This is beneficial to further improve the insulation reliability and breakdown resistance of the dielectric layer between contact holes and between contact holes and the control gate, thereby further reducing the risk of dielectric breakdown during device operation and improving device reliability.
[0075] S7, a second dry etching is performed, the etching stop layer 13 below the groove 21 is removed, and a contact hole 23 connected to the silicide layer is formed on the interlayer dielectric layer 20.
[0076] In some embodiments, the method of forming the contact hole 23 is used in the chip manufacturing process, and further includes the step of forming a metal contact plug 24 in the contact hole 23.
[0077] In related technologies, taking NOR flash memory as an example, after forming an interlayer dielectric layer 20 on the surface of the NOR flash memory cell, a single etching process is typically used to form contact holes 23 and fill them with metal to form metal plugs. As device dimensions shrink, the critical dimension (CD) of the contact holes 23 continues to decrease, and the spacing between contact holes 23 and between the contact holes 23 and the control gate also decreases accordingly. This process for forming contact holes 23 has significant limitations: as the critical dimension of the contact holes 23 shrinks, the etching process window for the contact holes 23 becomes increasingly narrow. A single etching process is prone to problems such as insufficient etching, over-etching, or sidewall damage. Simultaneously, the narrow spacing between contact holes 23 and between the contact holes 23 and the gate leads to an increase in the electric field strength at the interface between the metal plug and the gate / dielectric layer. During device operation, dielectric breakdown is highly likely to occur, such as... Figure 1 and Figure 2 As shown, this can cause device failure, affecting the device's reliability and lifespan.
[0078] This application first performs a first dry etching process, stopping at the etching stop layer 13 to form a groove 21. Then, an insulating sidewall 22 is formed on the inner surface of the groove 21. A second dry etching process is then performed to remove the etching stop layer 13 below the groove 21. Compared to a single etching process, this application uses two dry etching processes to form the contact hole 23, which helps to avoid problems such as insufficient etching, over-etching, or sidewall damage. By forming the insulating sidewall 22 between the two etching steps, the thickness of the insulating dielectric layer between the contact holes 23 and between the contact holes 23 and the control gate can be increased. It can also fill the sidewall defects of the contact holes 23, optimize their sidewall profile, and facilitate the dispersion of the electric field on the insulating dielectric layer. This improves the insulation reliability and breakdown resistance of the dielectric layer between the contact holes 23 and between the contact holes 23 and the control gate, thereby reducing the risk of dielectric breakdown during device operation and improving device reliability.
[0079] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for forming a contact hole, characterized in that, include: S1, a substrate is provided, on which semiconductor device units are formed, and a silicide layer is formed on the substrate between adjacent semiconductor device units; S2, forming an etch stop layer on the exposed surfaces of the semiconductor device unit and the substrate; S3, an interlayer dielectric layer is formed on the surface exposed by the etch stop layer; S4, photolithography forms a photoresist pattern, defines the target formation area of the groove, and exposes the interlayer dielectric layer of the area; S5, using the photoresist pattern as a mask, perform the first dry etching, and stop the etching at the etching stop layer to form a groove on the interlayer dielectric layer; S6, forming an insulating sidewall on the inner surface of the groove; S7, a second dry etching is performed, the etching stop layer below the groove is removed, and a contact hole connected to the silicide layer is formed on the interlayer dielectric layer.
2. The method according to claim 1, characterized in that, The insulating sidewall includes a nitrided layer.
3. The method according to claim 1, characterized in that, The method for forming the interlayer dielectric layer includes: S31, a first dielectric layer is formed in the isolation gap between adjacent semiconductor device units, and an opening is formed on the top of the first dielectric layer; S32, dry etching is performed on the first dielectric layer, and the width of the opening is increased while the first dielectric layer is thinned; S33, a second dielectric layer is formed on the surface of the first dielectric layer, and the second dielectric layer fills the opening and the isolation gap.
4. The method according to claim 3, characterized in that, It also includes the step of forming a third dielectric layer on the surface of the second dielectric layer.
5. The method according to claim 4, characterized in that, The third dielectric layer includes a tetraethyl orthosilicate layer.
6. The method according to claim 1, characterized in that, Before performing step S4, a step of planarizing the interlayer dielectric layer is also included.
7. The method according to any one of claims 1-6, characterized in that, The etching stop layer includes a silicon oxynitride layer.
8. The method according to any one of claims 1-6, characterized in that, The interlayer dielectric layer includes a silicon oxide layer.
9. The method according to any one of claims 1-6, characterized in that, The semiconductor device unit includes a flash memory unit.
10. The method according to any one of claims 1-6, characterized in that, The method is used in the chip manufacturing process and also includes the step of forming a metal contact plug inside the contact hole.