Chip package structure with glass via interconnect structure and method of making the same

Abstract

This application relates to a chip packaging structure with a glass through-hole interconnect (GTE) structure and its fabrication method. The fabrication method of the chip packaging structure with the GTE structure includes: fabricating the GTE structure; providing a temporary substrate and a first chip; mounting the GTE structure and the first chip on the same side of the temporary substrate; forming a first molding compound on one side of the temporary substrate, and forming a first redistribution layer on the side of the first molding compound away from the temporary substrate; bonding a second chip on the side of the first redistribution layer away from the first molding compound; removing the temporary substrate and exposing the GTE structure; forming a second redistribution layer on the side of the first molding compound away from the first redistribution layer; and forming a solder ball structure on the side of the second redistribution layer away from the first molding compound. The conductive pillars in the GTE structure of this application do not exhibit voids or collapse, significantly improving the warpage problem of the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure with a glass through-hole interconnect structure and its fabrication method. Background Technology

[0002] In existing chip packaging structures, a molding layer (such as epoxy molding compound, EMC, epoxy molding compound layer) with multiple conductive pillars (such as copper pillars) is generally required as an intermediate interconnect structure.

[0003] As interconnect density increases, the resulting conductive pillars need to possess characteristics such as high aspect ratio and high-density arrangement. This necessitates smaller photolithography and electroplating process windows, posing a significant challenge to existing photolithography processes. Simultaneously, the resulting high aspect ratio conductive pillars also carry risks such as voids and collapse. Furthermore, as the functionality of silicon bridging dies increases, the die thickness gradually increases, requiring a thicker molding layer. This leads to noticeable warpage issues after the chip packaging structure is formed. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip packaging structure with a glass through-hole interconnect structure and its fabrication method to address the technical problems mentioned above.

[0005] In a first aspect, this application provides a method for fabricating a chip package structure with a glass through-hole interconnect structure, the method comprising:

[0006] Fabrication of glass through-hole interconnect structures;

[0007] Provide a temporary substrate and a first chip;

[0008] The glass via interconnect structure and the first chip are mounted on the same side of the temporary substrate;

[0009] A first molding layer is formed on one side of the temporary substrate, and the first molding layer molds the glass via interconnect structure and the first chip.

[0010] A first redistribution layer is formed on the side of the first molding layer away from the temporary substrate, and the first redistribution layer is electrically connected to both the first chip and the glass via interconnect structure.

[0011] A second chip is bonded to the side of the first multi-wire layer away from the first molding layer, and the second chip is electrically connected to the first multi-wire layer.

[0012] Remove the temporary substrate to expose the glass via interconnect structure;

[0013] A second wiring layer is formed on the side of the first molding layer away from the first wiring layer, and the second wiring layer is electrically connected to the glass via interconnect structure;

[0014] A solder ball structure is formed on the side of the second wiring layer away from the first molding layer, and the solder ball structure is electrically connected to the second wiring layer.

[0015] In the above-mentioned method for fabricating a chip packaging structure with a glass through-hole interconnect structure, conductive pillars with high aspect ratio and high density can be easily fabricated by fabricating the glass through-hole interconnect structure; the conductive pillars in the glass through-hole interconnect structure will not have the problems of voids and collapse; and by fabricating the glass through-hole interconnect structure, the use of molding compound is greatly reduced, the coefficient of thermal expansion of glass is significantly smaller than that of molding compound, and within a certain range, the warpage problem of the chip packaging structure can be significantly improved by selecting glass with different coefficients of thermal expansion.

[0016] In some embodiments, the glass through-hole interconnect structure is fabricated, including:

[0017] Provide a transparent glass substrate;

[0018] The transparent glass substrate is locally modified to form multiple modified regions within the transparent glass substrate, the modified regions defining the shape and location of interconnect vias;

[0019] The modified region is wet-etched using a wet etching process to form interconnect vias;

[0020] Conductive pillars are formed within the interconnecting vias.

[0021] In some embodiments, before mounting the glass via interconnect structure and the first chip on the same side of the temporary substrate, the method further includes: forming a release layer on one side surface of the temporary substrate; the glass via interconnect structure and the first chip are both mounted on the surface of the release layer away from the temporary substrate;

[0022] After bonding the second chip to the side of the first redistribution layer away from the first molding compound layer, the method further includes: forming a second molding compound layer on the side of the first redistribution layer away from the first molding compound layer, and molding the second chip with the second molding compound layer.

[0023] In some embodiments, after forming a release layer on one side surface of the temporary substrate and before mounting the glass via interconnect structure and the first chip on the same side of the temporary substrate, the method further includes:

[0024] Multiple positioning blocks are formed on the surface of the release layer away from the temporary substrate, and the multiple positioning blocks are arranged at intervals; the first chip is mounted between adjacent positioning blocks.

[0025] In some embodiments, the height of the positioning block is less than the height of the glass via interconnect structure and the height of the first chip.

[0026] In some embodiments, the first chip is mounted face-up on one side of the temporary substrate, and a first pad is provided on the front side of the first chip; a first molding compound is formed on one side of the temporary substrate, comprising:

[0027] A first molding compound layer is formed on one side of the temporary substrate, the first molding compound layer covering the first chip and the glass via interconnect structure;

[0028] A grinding process is used to remove part of the first molding compound layer until the glass via interconnect structure and the first pad are exposed to obtain the first molding compound layer.

[0029] Secondly, this application also provides a chip packaging structure with a glass through-hole interconnect structure, the chip packaging structure with the glass through-hole interconnect structure including:

[0030] The first rewiring layer includes a first side and a second side opposite to each other;

[0031] A glass via interconnect structure is located on the first side of the first rewiring layer and is electrically connected to the first rewiring layer.

[0032] The first chip is located on the first side of the first wiring layer and is electrically connected to the first wiring layer.

[0033] A first molding layer is located on the first side of the first redistribution layer, molding the glass via interconnect structure and the first chip;

[0034] The second chip is located on the second side of the first wiring layer and is electrically connected to the first wiring layer;

[0035] The second wiring layer is located on the side of the first molding layer away from the first wiring layer, and is electrically connected to the glass via interconnect structure and the internal TSV structure of the first chip.

[0036] The solder ball structure is located on the side of the second rewiring layer away from the first molding layer and is electrically connected to the second rewiring layer.

[0037] In the aforementioned chip packaging structure with glass through-hole interconnects, high aspect ratio and high density conductive pillars can be easily fabricated by setting the glass through-hole interconnect structure; the conductive pillars in the glass through-hole interconnect structure will not have voids or collapse problems; furthermore, by setting the glass through-hole interconnect structure, the use of molding compound is greatly reduced, the coefficient of thermal expansion of glass is significantly less than that of molding compound, and within a certain range, the warpage problem of the chip packaging structure can be significantly improved by selecting glass with different coefficients of thermal expansion.

[0038] In some embodiments, the chip package structure with glass through-hole interconnect structure further includes:

[0039] The second molding layer is located on the second side of the first redistribution layer and molds the second chip.

[0040] In some embodiments, the chip package structure with glass through-hole interconnect structure further includes:

[0041] Multiple positioning blocks are located within the first molding layer and between the first chip and the glass via interconnect structure, with a spacing between them.

[0042] In some embodiments, the height of the positioning block is less than the height of the glass via interconnect structure and the height of the first chip. Attached Figure Description

[0043] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0044] Figure 1 This is a flowchart illustrating a method for fabricating a chip packaging structure with a glass through-hole interconnect structure, as provided in one embodiment of this application.

[0045] Figure 2 This is a flowchart illustrating the fabrication of a glass through-hole interconnect structure in a method for fabricating a chip packaging structure with a glass through-hole interconnect structure, as provided in one embodiment of this application.

[0046] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S111 of the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0047] Figure 4This is a cross-sectional schematic diagram of the structure obtained in step S112 of the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in an embodiment of this application.

[0048] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S113 of the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0049] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S114 of the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0050] Figure 7 This is a schematic cross-sectional view of the structure obtained after thinning the chip packaging structure with glass through-hole interconnect structure provided in one embodiment of this application.

[0051] Figure 8 This is a cross-sectional schematic diagram of the chip packaging structure with glass through-hole interconnect structure provided in one embodiment of this application, in which the obtained structure is placed on a dicing film for dicing.

[0052] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming a release layer and a positioning block in the preparation method of a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0053] Figure 10 This is a cross-sectional schematic diagram of the structure obtained in step S13 of the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in an embodiment of this application.

[0054] Figure 11 This is a schematic cross-sectional view of the structure obtained after forming the first molding compound layer in the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0055] Figure 12 This is a cross-sectional schematic diagram of the structure obtained in step S14 of the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0056] Figure 13 This is a cross-sectional schematic diagram of the structure obtained in step S15 of the method for fabricating a chip package structure with a glass through-hole interconnect structure provided in another embodiment of this application.

[0057] Figure 14 This is a schematic cross-sectional view of the structure obtained in step S16 of the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0058] Figure 15 This is a schematic cross-sectional view of the structure obtained after forming the second molding layer in the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0059] Figure 16 This is a schematic cross-sectional view of the structure obtained in step S17 of the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment.

[0060] Figure 17 This is a schematic cross-sectional view of the structure obtained after removing the first and second adhesion layers in the method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment of this application.

[0061] Figure 18 This is a schematic cross-sectional view of the structure obtained after forming the solder ball structure in the fabrication method of the chip packaging structure with glass through-hole interconnect structure provided in one embodiment.

[0062] Figure 19 This is a schematic cross-sectional view of the structure obtained after thinning the second molding layer in a method for fabricating a chip packaging structure with a glass through-hole interconnect structure provided in one embodiment.

[0063] Explanation of reference numerals in the attached figures:

[0064] 10. Glass via interconnect structure; 101. Transparent glass substrate; 1011. Modified region; 102. Interconnect via; 103. Conductive pillar; 11. Dicing film; 12. Temporary substrate; 13. First chip; 131. First chip body; 132. First pad; 14. First molding compound layer; 141. First molding compound material layer; 15. First redistribution layer; 151. First dielectric layer; 152. First metal wiring layer; 16. Second chip; 161. Second chip body; 162. Second pad; 17. Bonding ball; 18. Underfill layer; 19. Second molding compound layer; 20. Second redistribution layer; 201. Second dielectric layer; 202. Second metal wiring layer; 21. Bonding ball structure; 22. Release layer; 23. Positioning block; 24. First adhesion layer; 25. Second adhesion layer. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0067] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0068] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0070] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.

[0071] In one embodiment, see Figure 1 This application provides a method for fabricating a chip package structure with a glass through-hole interconnect structure. The method for fabricating a chip package structure with a glass through-hole interconnect structure may include the following steps: S11~S19.

[0072] S11: Fabrication of glass through-hole interconnect structure.

[0073] S12: Provides a temporary substrate and a first chip.

[0074] S13: Mount the glass via interconnect structure and the first chip on the same side of the temporary substrate.

[0075] S14: A first molding layer is formed on one side of a temporary substrate, and the first molding layer molds the glass through-hole interconnect structure and the first chip.

[0076] S15: A first redistribution layer is formed on the side of the first molding layer away from the temporary substrate. The first redistribution layer is electrically connected to the first chip and the glass via interconnect structure.

[0077] S16: The second chip is bonded to the side of the first wiring layer away from the first molding layer, and the second chip is electrically connected to the first wiring layer.

[0078] S17: Remove the temporary substrate and expose the glass via interconnect structure.

[0079] S18: A second wiring layer is formed on the side of the first encapsulation layer away from the first wiring layer, and the second wiring layer is electrically connected to the glass via interconnect structure.

[0080] S19: A solder ball structure is formed on the side of the second wiring layer away from the first molding layer, and the solder ball structure is electrically connected to the second wiring layer.

[0081] In the above-mentioned method for fabricating a chip package structure with a glass through-hole interconnect structure, conductive pillars with high aspect ratio and high density can be easily fabricated by fabricating the glass through-hole interconnect structure; the conductive pillars in the glass through-hole interconnect structure will not have the problems of voids and collapse; and by fabricating the glass through-hole interconnect structure, the use of molding compound is greatly reduced. The coefficient of thermal expansion (CTE) of glass is significantly smaller than that of molding compound, and within a certain range, it can be adjusted by selecting glass with different coefficients of thermal expansion, which can significantly improve the warpage problem of the chip package structure.

[0082] For example, please refer to Figure 2 In step S11, the glass through-hole interconnect structure is prepared, which may include the following steps: S111~S114.

[0083] S111: Provides a transparent glass substrate.

[0084] S112: Locally modify the transparent glass substrate to form multiple modified regions within the transparent glass substrate, wherein the modified regions define the shape and location of interconnect vias.

[0085] S113: The modified area is etched using a wet etching process to form interconnect vias.

[0086] S114: A conductive pillar is formed within the interconnect via.

[0087] As an example, before mounting the glass via interconnect structure and the first chip on the same side of the temporary substrate, the method further includes: forming a release layer on one side surface of the temporary substrate; both the glass via interconnect structure and the first chip are mounted on the surface of the release layer away from the temporary substrate.

[0088] As an example, after bonding the second chip on the side of the first wiring layer away from the first molding compound, the method further includes: forming a second molding compound on the side of the first wiring layer away from the first molding compound, and molding the second chip with the second molding compound.

[0089] As an example, after forming a release layer on one side surface of the temporary substrate, and before mounting the glass via interconnect structure and the first chip on the same side of the temporary substrate, the method further includes:

[0090] Multiple positioning blocks are formed on the surface of the release layer away from the temporary substrate, and the multiple positioning blocks are arranged at intervals; the first chip is mounted between adjacent positioning blocks.

[0091] As an example, the height of the positioning block can be much smaller than the height of the glass via interconnect structure and the height of the first chip.

[0092] As an example, the first chip is mounted on one side of the temporary substrate, and the front side of the first chip is provided with a first pad; in step S14, a first molding compound is formed on one side of the temporary substrate, including the following steps: S141~S142.

[0093] S141: A first molding compound layer is formed on one side of a temporary substrate, the first molding compound layer covering the first chip and the glass via interconnect structure.

[0094] S142: A grinding process is used to remove part of the first molding compound layer until the glass via interconnect structure and the first pad are exposed to obtain the first molding compound layer.

[0095] As an example, please combine Figure 2 See Figure 3 The transparent glass substrate 101 provided in step S111 may include an inorganic transparent glass substrate, such as a sodium-calcium-silicon glass substrate, a tempered glass substrate, a borosilicate glass substrate, a quartz glass substrate, a borate glass substrate, a phosphate glass substrate, or a silicon dioxide-based glass substrate, etc.

[0096] As an example, after step S111, a pretreatment step of the transparent glass substrate 101 may be included. Specifically, firstly, the surface of the transparent glass substrate 101 may be polished to remove surface impurities and scratches; secondly, the polished transparent glass substrate 101 may be annealed; and finally, the annealed transparent glass substrate 101 may be plasma cleaned. By performing the above pretreatment on the transparent glass substrate 101, the stability of the interaction between the transparent glass substrate 101 and the femtosecond laser can be improved in the subsequent step S112, thereby ensuring the uniformity of the modification treatment in step S112.

[0097] As an example, please combine Figure 2 See Figure 4 In step S112, a femtosecond laser (not shown) can be used to emit laser pulses to irradiate the transparent glass substrate 101, thereby achieving local modification of the transparent glass substrate 101. After the femtosecond laser pulse is incident on the interior of the transparent glass substrate 101, it will interact with the transparent glass substrate 101 to form local, fine modification channels (i.e., modification regions 1011) within the transparent glass substrate 101.

[0098] As an example, in step S112, multiple modified regions 1011 can be formed within the transparent glass substrate 101. Each modified region 1011 is a region that penetrates the transparent glass substrate 101 along the thickness direction, such as... Figure 4 As shown. The cross-sectional shape of each modified region 1011 can be circular, rectangular, elliptical, etc.

[0099] As an example, the multiple modified regions 1011 formed in step S112 can be arranged in parallel intervals within the transparent glass substrate 101. The multiple modified regions 1011 can be arranged at equal intervals within the transparent glass substrate 101; the multiple modified regions 1011 can also be arranged at non-equal intervals. For example, in some regions, the modified regions 1011 can be arranged at equal intervals, while in other regions, they can be arranged at non-equal intervals; alternatively, the transparent glass substrate 101 can have multiple regions, with the modified regions 1011 in each region arranged at equal intervals, but the distribution density of the modified regions 1011 in different regions is not entirely the same.

[0100] As an example, in step S112, the femtosecond laser pulse can be a laser pulse after shaping. Specifically, it can be a Gaussian laser pulse shaped into a flat-top pulse by a spatial light modulator, so that the laser energy is evenly distributed in the focusing area, thereby avoiding the modification difference caused by uneven laser energy distribution.

[0101] As an example, please combine Figure 2 See Figure 5 In step S113, a suitable wet etching solution can be selected based on the specific material of the transparent glass substrate 101 and the properties of the modified region 1011 to perform wet etching on the modified region 1011 to form interconnect vias 102. The wet etching solution needs to have a fast etching removal rate on the modified region 1011, while having a very low etching removal rate on other regions of the transparent glass substrate 101 outside the modified region 1011, or even not etching away other regions of the transparent glass substrate 101 outside the modified region 1011. After the wet etching process, the material of the modified region 1011 is removed, thereby forming interconnect vias 102 in the transparent glass substrate 101.

[0102] As an example, please combine Figure 2 See Figure 6 Electroplating processes can be used, but are not limited to, electroplating metal materials into the interconnect vias 102 to form conductive pillars 103. Specifically, the conductive pillars 103 can completely fill the interconnect vias 102 without gaps.

[0103] As an example, after forming the conductive pillars 103, if the transparent glass substrate 101 is relatively thick, the structure formed in step S114 can be thinned using a grinding process. After thinning, both the thickness of the transparent glass substrate 101 and the length of the retained conductive pillars 103 are reduced. Figure 7 As shown.

[0104] As an example, if the size of the transparent glass substrate 101 is relatively large, and the size of the glass through-hole interconnect structure 10 required in the actual chip packaging process is relatively small, the structure obtained in step S114 or the structure obtained after the thinning process can be as follows: Figure 8 The sample is placed on a dicing film 11 and diced to obtain a multi-glass through-hole interconnect structure 10.

[0105] As an example, please combine Figure 1 See Figure 9 The release layer 22 formed on one side surface of the temporary substrate before step S13 can be any film structure that is easy to remove by subsequent removal methods such as laser or high temperature to remove the temporary substrate 12.

[0106] As an example, please combine Figure 1 See Figure 9 The multiple positioning blocks 23 formed on the surface of the release layer 22 away from the temporary substrate 12 may all include copper pillars. The positioning blocks 23 can be used for rapid and accurate positioning of the subsequent first chip mounting and glass via interconnect structure mounting. The number of positioning blocks 23 can be set according to actual needs and is not specifically limited here; however, it should be noted that the first chip must have at least one positioning block 23 on at least two opposite sides.

[0107] As an example, please combine Figure 1 See Figure 10 In step S13, the first chip 13 can be mounted on one side of the temporary substrate 12 via the first adhesive layer 24, and the glass via interconnect structure 10 can be mounted on the side of the temporary substrate 12 on which the first chip 13 is mounted via the second adhesive layer 25. The first adhesive layer 24 can be the same as or different from the second adhesive layer 25.

[0108] It should be noted that when the release layer 22 is provided on the surface of the temporary substrate 12, the first adhesive layer 24 and the second adhesive layer 25 are both attached to the surface of the release layer 22 away from the temporary substrate 12.

[0109] As an example, the back side of the first chip 13 is in contact with the surface of the first adhesive layer 24 away from the temporary substrate 12.

[0110] As an example, please continue reading Figure 10The first chip 13 may include a first chip body 131 and a first pad 132; the first pad 132 is located on the front side of the first chip 13 (i.e., the surface of the first chip body 131 away from the first adhesion layer 24). Functional devices (not shown) and through-silicon vias (TSVs) (not shown) may be formed in the first chip body 131. The first pad 132 can be electrically connected to the functional devices, and the subsequently formed second redistribution layer 20 can be electrically connected to the through-silicon vias.

[0111] As an example, when a positioning block 23 is formed on the surface of the release layer 22 away from the temporary substrate 12, the height of the positioning block 23 can be less than the height of the first chip 13 and less than the height of the glass via interconnect structure 10. Compared with the prior art scheme where the positioning block and the conductive pillar for forming the interconnect structure are formed simultaneously, this application uses the glass via interconnect structure 10, and the height of the positioning block 23 can be set according to actual needs. The positioning block 23 can be set to a relatively small height, thereby reducing the process difficulty, and the positioning block 23 will not have the problem of collapsing due to excessive height.

[0112] As an example, please continue reading Figure 10 The glass via interconnect structure 10 can be located on the side of the positioning block 23 away from the first chip 13, and has a gap with the positioning block 23.

[0113] For example, please refer to Figure 11 In step S141, the thickness of the first molding compound layer 141 formed can be greater than the sum of the heights of the positioning block 23, the first chip 13, the first pad 132, and the first adhesive layer 24, and the sum of the thicknesses of the glass via interconnect structure 10 and the second adhesive layer 25; at this time, the upper surface of the first molding compound layer 141 (i.e., Figure 11 The first molding compound layer 141 (the surface of which is far from the release layer 22) is higher than the upper surface of the first chip 13 and the upper surface of the glass via interconnect structure 10.

[0114] As an example, the material of the first molding compound layer 141 may include, but is not limited to, epoxy molding compound.

[0115] For example, please refer to Figure 12 In step S142, a chemical mechanical polishing (CMP) process may be used, but is not limited to, to remove part of the first molding compound layer 141 to obtain the first molding compound layer 14.

[0116] It should be noted that since the height of the glass via interconnect structure 10 is greater than the height of the first chip 13, step S142 involves not only removing part of the first molding compound layer 141, but also removing part of the glass via interconnect structure 10. Because the glass via interconnect structure 10 involves both glass and metal materials, which are different from the materials of the first molding compound layer 141, different grinding processes need to be selected in step S142 depending on the material being removed. Specifically, the grinding wheel can be selected based on the material being ground. When the main material of the grinding surface is EMC, a grinding wheel specifically designed for cutting EMC is selected. When the grinding surface is a complex surface consisting of glass + EMC + Cu, a specific grinding wheel is selected for cutting. During the grinding process, different wheel feed speeds and chuck speeds need to be set according to the structure of the grinding surface. After grinding to the target thickness (or close to the target thickness), CMP technology can be used to obtain a smoother grinding surface, reducing the impact of grinding marks on electrical connections.

[0117] As an example, please combine Figure 1 See Figure 13 In step S15, multiple layers of first dielectric layer 151 and first metal wiring layer 152 can be alternately formed to serve as the first rewiring layer 15. The number of first dielectric layer 151 and the number of first metal wiring layer 152 can be set according to actual needs and are not specifically limited here. However, the upper surface of the top first dielectric layer needs to have a first metal wiring layer 152 formed thereon to facilitate electrical connection between the first rewiring layer 15 and other structures. The first metal wiring layers 152 on adjacent sides are electrically connected.

[0118] As an example, the first dielectric layer 151 may include, but is not limited to, polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO), or other suitable polymer-based dielectric materials. The material of the first metal wiring layer 152 may include one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN.

[0119] As an example, please combine Figure 1 See Figure 14 In step S16, the second chip 16 may include a second chip body 161 and a second pad 162; the second chip 16 may be bonded to the side of the first redistribution layer 15 away from the first molding compound layer 14 via bonding balls 17. The second chip 16 may be the same type of chip as the first chip 13, or it may be a different type of chip from the first chip 13.

[0120] As an example, in step S16, the number of second chips 16 bonded can be set according to actual needs. Figure 14The example shown is of bonding two second chips 16. In actual embodiments, the number of second chips 16 bonded is not limited to this.

[0121] As an example, the material of the bonding ball 17 may include, but is not limited to, tin.

[0122] As an example, the second chip 16 is flip-bonded to the side of the first redistribution layer 15 away from the first molding compound layer 14.

[0123] As an example, please continue reading Figure 15 After bonding the second chip 16, the process also includes forming an underfill layer 18 between the second chip 16 and the first redistribution layer 15.

[0124] As an example, the material of the underfill layer 18 may include, but is not limited to, capillary underfill (CUF), no-flow underfill (NUF), wafer-level underfill (WLUF), or molded underfill (MUF).

[0125] As an example, please continue reading Figure 15 After forming the bottom fill layer 18, the process may further include forming a second molding compound 19 on the side of the first redistribution layer 15 away from the first molding compound 14, wherein the second molding compound 19 molds the second chip 16. The material of the second molding compound 19 may be the same as the material of the first molding compound 14.

[0126] As an example, please combine Figure 1 See Figure 16 The temporary substrate 12 can be removed by removing the release layer 22; specifically, a peeling process can be used to remove the release layer 22 and the temporary substrate 12. A cross-sectional schematic diagram of the structure obtained after removing the temporary substrate 12 is shown below. Figure 16 As shown.

[0127] For example, please refer to Figure 17 After step S17, the following may also be included: removing the first adhesive layer 24, the second adhesive layer 25, a portion of the first molding compound 14, and a portion of the positioning block 23; specifically, chemical mechanical polishing (CMP) may be used, but is not limited to, to remove the first adhesive layer 24, the second adhesive layer 25, a portion of the first molding compound 14, and a portion of the positioning block 23. After removing the first adhesive layer 24, the second adhesive layer 25, a portion of the first molding compound 14, and a portion of the positioning block 23, the surfaces of the remaining positioning block 23 and the remaining first molding compound 14 that are away from the first redistribution layer 15 are flush with the surface of the glass via interconnect structure 10 that is away from the first redistribution layer 15, such as... Figure 17 As shown, the through-silicon vias in the first chip body 131 are exposed.

[0128] As an example, please combine Figure 1 See Figure 18 The second wiring layer 20 formed in step S18 may include a second dielectric layer 201 and a second metal wiring layer 202. The second dielectric layer 201 and the second metal wiring layer 202 can be set according to actual needs. The multiple second metal wiring layers 202 are arranged at intervals along the thickness direction in the stacked structure formed by the multiple second dielectric layers 201. The adjacent second metal wiring layers 202 can be electrically connected through metal plugs (not shown).

[0129] As an example, the material of the second dielectric layer 201 can be the same as the material of the first dielectric layer 151, and the material of the second metal wiring layer 202 can be the same as the material of the first metal wiring layer 152.

[0130] As an example, please combine Figure 1 Continue reading Figure 18 The solder ball structure 21 formed in step S19 may include, but is not limited to, solder balls.

[0131] As an example, after step S19, a step of thinning the second molding compound 19 may also be included, wherein the surface of the thinned second molding compound 19 away from the first redistribution layer 15 is flush with the back surface of the second chip 16, such as... Figure 19 As shown.

[0132] As an example, in the chip package structure with glass through-hole interconnect structure obtained in this application, the multiple glass through-hole interconnect structures 10 can be glass through-hole interconnect structures 10 with the same size of conductive pillars 103 and the same arrangement of conductive pillars 103; of course, in other examples, the multiple glass through-hole interconnect structures 10 can also be glass through-hole interconnect structures 10 with at least one of the size of conductive pillars 103 and the arrangement of conductive pillars 103 being different. Similarly, when the chip package structure with glass through-hole interconnect structure encapsulates multiple first chips 13, the multiple first chips 13 can be chips of the same type or chips of different types.

[0133] Unless otherwise expressly stated herein, the execution order of these steps in the method for fabricating a chip package structure with a glass through-hole interconnect structure in the above embodiments is not strictly limited, and these steps can be executed in other orders. Moreover, at least some steps in the method may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0134] The fabrication method of the chip package structure with glass through-hole interconnect structure in the above embodiments is intended to illustrate the formation principle of the chip package structure with glass through-hole interconnect structure in the embodiments of this application, and is not intended to limit the chip package structure with glass through-hole interconnect structure in the embodiments of this application. Other fabrication methods can also be used to fabricate the chip package structure with glass through-hole interconnect structure in the embodiments of this application.

[0135] In another embodiment, please refer to Figures 1 to 18 Continue reading Figure 19 This application also provides a chip package structure with a glass through-hole interconnect structure. The chip package structure with the glass through-hole interconnect structure may include: a first redistribution layer 15, which may include a first side and a second side; a glass through-hole interconnect structure 10, which may be located on the first side of the first redistribution layer 15 and electrically connected to the first redistribution layer 15; a first chip 13, which may be located on the first side of the first redistribution layer 15 and electrically connected to the first redistribution layer 15; and a first molding compound layer 14. A molding compound 14 is located on the first side of the first rewiring layer 15, molding the glass via interconnect structure 10 and the first chip 13; a second chip 16 is located on the second side of the first rewiring layer 15 and is electrically connected to the first rewiring layer 15; a second rewiring layer 20 is located on the side of the first molding compound 14 away from the first rewiring layer 15 and is electrically connected to the glass via interconnect structure 10; and a solder ball structure 21 is located on the side of the second rewiring layer 20 away from the first molding compound 14 and is electrically connected to the second rewiring layer 20.

[0136] In the chip packaging structure with glass through-hole interconnect structure described above, by setting the glass through-hole interconnect structure 10, conductive pillars 103 with high aspect ratio and high density arrangement can be easily fabricated; the conductive pillars 103 in the glass through-hole interconnect structure 10 will not have voids or collapse problems; and by setting the glass through-hole interconnect structure 10, the use of molding compound is greatly reduced. The coefficient of thermal expansion of glass is significantly less than that of molding compound such as EMC, and within a certain range, it can be adjusted by selecting glass with different coefficients of thermal expansion, which can significantly improve the warpage problem of chip packaging structure.

[0137] The chip encapsulation structure with glass through-hole interconnect structure in this embodiment can be adopted as follows: Figures 1 to 19 The chip encapsulation structure with glass through-hole interconnect structure in the corresponding embodiment is prepared by the same method.

[0138] As an example, a chip package structure with a glass through-hole interconnect structure may further include: a second molding layer 19, which is located on the second side of the first redistribution layer 15, and molds the second chip 16.

[0139] As an example, a chip package structure with a glass through-hole interconnect structure may further include: a plurality of positioning blocks 23, which are located within the first molding layer 14 and between the first chip 13 and the glass through-hole interconnect structure 10, and have a spacing between them and both the first chip 13 and the glass through-hole interconnect structure 10.

[0140] As an example, the height of the positioning block 23 can be much smaller than the height of the glass through-hole interconnect structure 10 and the height of the first chip 13.

[0141] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0142] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a chip packaging structure with a glass through-hole interconnect structure, characterized in that, include: Fabrication of glass through-hole interconnect structures; Provide a temporary substrate and a first chip; The glass via interconnect structure and the first chip are mounted on the same side of the temporary substrate; A first molding layer is formed on one side of the temporary substrate, and the first molding layer molds the glass via interconnect structure and the first chip. A first redistribution layer is formed on the side of the first molding layer away from the temporary substrate, and the first redistribution layer is electrically connected to both the first chip and the glass via interconnect structure. A second chip is bonded to the side of the first multi-wire layer away from the first molding layer, and the second chip is electrically connected to the first multi-wire layer. Remove the temporary substrate to expose the glass via interconnect structure; A second wiring layer is formed on the side of the first molding layer away from the first wiring layer, and the second wiring layer is electrically connected to the glass via interconnect structure; A solder ball structure is formed on the side of the second wiring layer away from the first molding layer, and the solder ball structure is electrically connected to the second wiring layer.

2. The method for fabricating a chip packaging structure with a glass through-hole interconnect structure according to claim 1, characterized in that, Fabricating glass through-hole interconnect structures, including: Provide a transparent glass substrate; The transparent glass substrate is locally modified to form multiple modified regions within the transparent glass substrate, the modified regions defining the shape and location of interconnect vias; The modified region is wet-etched using a wet etching process to form interconnect vias; Conductive pillars are formed within the interconnecting vias.

3. The method for fabricating a chip packaging structure with a glass through-hole interconnect structure according to claim 1, characterized in that, Before mounting the glass via interconnect structure and the first chip on the same side of the temporary substrate, the method further includes: forming a release layer on one side surface of the temporary substrate; both the glass via interconnect structure and the first chip are mounted on the surface of the release layer away from the temporary substrate. After bonding the second chip to the side of the first redistribution layer away from the first molding compound layer, the method further includes: forming a second molding compound layer on the side of the first redistribution layer away from the first molding compound layer, and molding the second chip with the second molding compound layer.

4. The method for fabricating a chip packaging structure with a glass through-hole interconnect structure according to claim 3, characterized in that, After forming a release layer on one side surface of the temporary substrate, and before mounting the glass via interconnect structure and the first chip on the same side of the temporary substrate, the method further includes: Multiple positioning blocks are formed on the surface of the release layer away from the temporary substrate, and the multiple positioning blocks are arranged at intervals; the first chip is mounted between adjacent positioning blocks.

5. The method for fabricating a chip packaging structure with a glass through-hole interconnect structure according to claim 4, characterized in that, The height of the positioning block can be much smaller than the height of the glass through-hole interconnect structure and the height of the first chip.

6. The method for fabricating a chip packaging structure with a glass through-hole interconnect structure according to claim 1, characterized in that, The first chip is mounted upright on one side of the temporary substrate, and a first pad is provided on the front side of the first chip; a first molding compound layer is formed on one side of the temporary substrate, comprising: A first molding compound layer is formed on one side of the temporary substrate, the first molding compound layer covering the first chip and the glass via interconnect structure; A grinding process is used to remove part of the first molding compound layer until the glass via interconnect structure and the first pad are exposed to obtain the first molding compound layer.

7. A chip packaging structure with a glass through-hole interconnect structure, characterized in that, include: The first rewiring layer includes a first side and a second side opposite to each other; A glass via interconnect structure is located on the first side of the first rewiring layer and is electrically connected to the first rewiring layer. The first chip is located on the first side of the first wiring layer and is electrically connected to the first wiring layer. A first molding layer is located on the first side of the first redistribution layer, molding the glass via interconnect structure and the first chip; The second chip is located on the second side of the first wiring layer and is electrically connected to the first wiring layer; The second wiring layer is located on the side of the first molding layer away from the first wiring layer and is electrically connected to the glass via interconnect structure. The solder ball structure is located on the side of the second rewiring layer away from the first molding layer and is electrically connected to the second rewiring layer.

8. The chip packaging structure with glass through-hole interconnect structure according to claim 7, characterized in that, Also includes: The second molding layer is located on the second side of the first redistribution layer and molds the second chip.

9. The chip packaging structure with glass through-hole interconnect structure according to claim 7, characterized in that, Also includes: Multiple positioning blocks are located within the first molding layer and between the first chip and the glass via interconnect structure, with a spacing between them.

10. The chip packaging structure with glass through-hole interconnect structure according to claim 9, characterized in that, The height of the positioning block can be much smaller than the height of the glass through-hole interconnect structure and the height of the first chip.

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