A via manufacturing method and semiconductor structure

Abstract

The embodiment of the present application provides a via manufacturing method and a semiconductor structure, the via manufacturing method comprises the following steps: providing a semiconductor device substrate; depositing a first dielectric layer on the semiconductor device substrate; etching the first dielectric layer to obtain a through-hole in the first dielectric layer; filling a sacrificial layer in the through-hole; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer to obtain a via hole; the projection of the through-hole on the second dielectric layer covers the via hole; removing the sacrificial layer; and filling metal in the via hole and the through-hole to obtain a via. The via manufacturing method provided by the embodiment of the present application can improve the yield of wafer dies.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a through-hole manufacturing method and a semiconductor structure. Background Technology

[0002] In the process of fabricating vias using related technologies, if overlay misalignment occurs (referring to the overall or partial positional shift of the upper layer pattern relative to the lower layer pattern, which is a type of photolithography overlay error and directly affects the overlap quality between the via and the upper and lower metal layers), it will cause via misalignment, which in turn will lead to a decrease in wafer die yield. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a through-hole manufacturing method and a semiconductor structure to improve wafer yield.

[0004] In a first aspect, embodiments of the present invention provide a method for manufacturing through holes, comprising: Provides semiconductor device substrates; A first dielectric layer is deposited on the semiconductor device substrate; Etch the first dielectric layer to obtain communication holes in the first dielectric layer; A sacrificial layer is filled into the communication cavity; Deposit a second dielectric layer on the first dielectric layer; The second dielectric layer is etched to obtain a through-hole cavity; the projection of the through-hole cavity onto the second dielectric layer covers the through-hole cavity. Remove the sacrificial layer; Metal is filled into the through hole and the communication hole to obtain a through hole.

[0005] In a second aspect, embodiments of the present invention provide a semiconductor structure, including: a semiconductor device substrate; A via is located above the semiconductor device substrate. The via includes a communication via penetrating a first dielectric layer on the semiconductor device substrate and a first via penetrating a second dielectric layer on the first dielectric layer. The projection of the communication via onto the second dielectric layer covers the first via.

[0006] This invention provides a method for manufacturing vias, comprising: providing a semiconductor device substrate; depositing a first dielectric layer on the semiconductor device substrate; etching the first dielectric layer to obtain a communication cavity in the first dielectric layer; filling the communication cavity with a sacrificial layer; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer to obtain a via cavity; the projection of the communication cavity onto the second dielectric layer covering the via cavity; removing the sacrificial layer; and filling the via cavity and the communication cavity with metal to obtain a via.

[0007] In the via fabrication method provided in this embodiment of the invention, a semiconductor device substrate is first provided. A first dielectric layer is deposited on the semiconductor device substrate, and the first dielectric layer is etched to form a communication cavity in the first dielectric layer. A sacrificial layer is filled in the communication cavity. A second dielectric layer is deposited on the first dielectric layer. The second dielectric layer is etched to obtain a via cavity. The projection of the communication cavity onto the second dielectric layer covers the via cavity. The sacrificial layer is removed. Metal is filled into the via cavity and the communication cavity to obtain a via. After the via cavity and the communication cavity are filled with metal, if an overlay misalignment occurs between the via and the semiconductor device substrate, since the projection of the communication cavity onto the second dielectric layer covers the via cavity located on the semiconductor device substrate, the communication via obtained by filling the communication cavity with metal can electrically connect the first via and the semiconductor device substrate. This reduces the probability of an overlay misalignment between the semiconductor device substrate and the first via, improving the yield of the wafer.

[0008] In addition, in this embodiment of the invention, a sacrificial layer is filled into the communication cavity of the first dielectric layer before the second dielectric layer is deposited. This can prevent the second dielectric layer from being deposited in the communication cavity, which would affect the subsequent removal of the sacrificial layer. Due to the presence of the second dielectric layer, the sacrificial layer cannot be completely removed, which would affect the effect of subsequent metal filling and further improve the yield of the wafer. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0010] Figure 1 This is a schematic flowchart of the through-hole manufacturing method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a semiconductor device substrate provided in an embodiment of the present invention; Figure 3Provided for embodiments of the present invention, in Figure 2 A schematic diagram of the first structure obtained after depositing the first dielectric layer 201 on the semiconductor device substrate 200; Figure 4 Provided for embodiments of the present invention, for Figure 3 A schematic diagram of the second structure obtained by etching the first dielectric layer 201 in the first structure; Figure 5 Provided for embodiments of the present invention, in Figure 4 A schematic diagram of the third structure obtained by filling the communication cavity 202 of the second structure with a sacrificial layer; Figure 6 Provided for embodiments of the present invention, in Figure 5 A schematic diagram of the fourth structure obtained by depositing a second dielectric layer 204 on the first dielectric layer 201 in the third structure; Figure 7 Provided for embodiments of the present invention, for Figure 6 A schematic diagram of the fifth structure obtained by etching the second dielectric layer 204 in the fourth structure; Figure 8 Provided for embodiments of the present invention, removing Figure 7 A schematic diagram of the sixth structure obtained from the sacrificial layer 203 in the fifth structure; Figure 9 Provided for embodiments of the present invention, removing Figure 7 Another structural diagram of the sixth structure is obtained from the sacrificial layer 203 in the fifth structure. Figure 10 In order to be in Figure 8 A schematic diagram of a semiconductor structure obtained by filling the through-hole 205 and the communication hole 202 in the sixth structure with metal; Figure 11 Provided for embodiments of the present invention, for Figure 3 Another schematic diagram of the second structure obtained by etching the first dielectric layer 201 in the first structure; Figure 12 Provided for embodiments of the present invention, removing Figure 7 The sacrificial layer 203 in the fifth structure is used to obtain another structural diagram of the sixth structure. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] In the process of fabricating vias using related technologies, if overlayer shift occurs (referring to the overall or partial positional shift of the upper layer pattern relative to the lower layer pattern, which is a type of photolithography overlay error and directly affects the bonding quality between the via and the upper and lower metal layers), it will lead to via offset (referring to the offset between the semiconductor device substrate and the via), which in turn will reduce the die yield.

[0013] Furthermore, as the critical dimensions of bare wafers become smaller, the risk of via misalignment gradually increases, affecting the performance of devices within the bare wafer.

[0014] To address the aforementioned problems, embodiments of the present invention provide a method for manufacturing through-holes, the process of which is illustrated in the following diagram. Figure 1 As shown, Figure 1 This is a schematic flowchart of a through-hole manufacturing method provided in an embodiment of the present invention.

[0015] Please refer to Figure 1 ,include: Step S101: Provide a semiconductor device substrate.

[0016] The semiconductor device substrate may include, for example, device structures such as transistors, capacitors, and resistors.

[0017] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a semiconductor device substrate provided in an embodiment of the present invention. The semiconductor device substrate 200 provided in step S101 can be as follows: Figure 2 As shown.

[0018] Step S102: Deposit a first dielectric layer on the semiconductor device substrate.

[0019] Please refer to Figure 3 , Figure 3 Provided for embodiments of the present invention, in Figure 2 A schematic diagram of the first structure obtained after depositing the first dielectric layer 201 on the semiconductor device substrate 200.

[0020] Step S103: Etch the first dielectric layer to obtain communication cavities in the first dielectric layer.

[0021] Please refer to Figure 4 , Figure 4 Provided for embodiments of the present invention, for Figure 3 A schematic diagram of the second structure obtained by etching the first dielectric layer 201 in the first structure, wherein there are communication holes 202 in the first dielectric layer 201.

[0022] Step S104: Fill the communication cavity with a sacrificial layer.

[0023] Please refer to Figure 5 , Figure 5 Provided for embodiments of the present invention, in Figure 4 A schematic diagram of the third structure is obtained by filling the communication cavity 202 of the second structure with a sacrificial layer. Figure 5 In the middle, we can see that, Figure 4 The sacrificial layer 203 is obtained by filling the communication cavity 202 in the middle.

[0024] Step S105: Deposit a second dielectric layer on the first dielectric layer.

[0025] Please refer to Figure 6 , Figure 6 Provided for embodiments of the present invention, in Figure 5 A schematic diagram of the fourth structure obtained by depositing a second dielectric layer 204 on the first dielectric layer 201 in the third structure is shown. Figure 6 As can be seen, the second dielectric layer 204 is deposited on the first dielectric layer 201.

[0026] Step S106: Etch the second dielectric layer to obtain a through-hole cavity.

[0027] Please refer to Figure 7 , Figure 7 Provided for embodiments of the present invention, for Figure 6 A schematic diagram of the fifth structure is obtained by etching the second dielectric layer 204 in the fourth structure. Figure 7 As can be seen, the through hole 205 is located in the second medium layer 204.

[0028] Step S107: Remove the sacrificial layer.

[0029] Please refer to Figure 8 , Figure 8 Provided for embodiments of the present invention, removing Figure 7 A schematic diagram of the sixth structure obtained from the sacrificial layer 203 in the fifth structure is shown below. Figure 8 As can be seen from bottom to top, there are communication holes 202 penetrating the first dielectric layer 201 and through holes 205 penetrating the second dielectric layer 204. The projection of the communication holes 202 onto the second dielectric layer 204 covers the through holes 205.

[0030] It can be seen that, Figure 8 In the process, the critical dimension (CD) of the connecting hole 202 is larger than the critical dimension of the through hole 205, and in Figure 8In this embodiment, the through-hole 205 is centered at the exact center of the communication hole 202. However, it is understood that in this embodiment, the positional relationship between the communication hole 202 and the through-hole 205 is such that the projection of the communication hole 202 onto the second dielectric layer 204 covers the through-hole 205. That is, the through-hole 205 does not necessarily need to be centered at the exact center of the communication hole 202; it can be slightly offset, as long as the projection of the communication hole 202 onto the second dielectric layer 204 covers the through-hole 205. Please refer to... Figure 9 , Figure 9 Provided for embodiments of the present invention, removing Figure 7 The sacrificial layer 203 in the fifth structure, and another structural diagram of the sixth structure, show that in Figure 9 In this embodiment, the through hole 205' is not centered on the communication hole 202'. Therefore, provided that the projection of the communication hole 202 on the second dielectric layer 204 covers the through hole 205, this embodiment does not limit whether the communication hole 202 and the through hole 205 are directly opposite each other (the through hole 205 is centered on the communication hole 202).

[0031] Step S108: Fill the through hole and the communication hole with metal to obtain a through hole.

[0032] Please refer to Figure 10 , Figure 10 In order to be in Figure 8 A schematic diagram of the semiconductor structure obtained by filling the through-hole 205 and the communication hole 202 in the sixth structure with metal can be seen. Figure 10 In the middle, the through hole 206 includes: a first through hole 2060 and a connecting through hole 2061.

[0033] It is known that the positional relationship between the first through hole 2060 and the connecting through hole 2061 is consistent with the positional relationship between the through hole cavity 205 and the connecting cavity 202.

[0034] The via type described in this embodiment of the invention can be, for example, a metal-to-metal via (Via) in the mid-process of a semiconductor chip. The Via is a vertical conductive structure that connects two metal layers. Its critical size is extremely small (nanometer level) and it is extremely sensitive to overlay shift errors.

[0035] In the via fabrication method provided in this embodiment of the invention, a semiconductor device substrate is first provided. A first dielectric layer is deposited on the semiconductor device substrate, and the first dielectric layer is etched to form a communication cavity in the first dielectric layer. A sacrificial layer is filled in the communication cavity. A second dielectric layer is deposited on the first dielectric layer. The second dielectric layer is etched to obtain a via cavity. The projection of the communication cavity onto the second dielectric layer covers the via cavity. The sacrificial layer is removed. Metal is filled into the via cavity and the communication cavity to obtain a via. After the via cavity and the communication cavity are filled with metal, if an overlay misalignment occurs between the via and the semiconductor device substrate, since the projection of the communication cavity onto the second dielectric layer covers the via cavity located on the semiconductor device substrate, the communication via obtained by filling the communication cavity with metal can electrically connect the first via and the semiconductor device substrate. This reduces the probability of an overlay misalignment between the semiconductor device substrate and the first via, improving the yield of the wafer.

[0036] In addition, in this embodiment of the invention, a sacrificial layer is filled into the communication cavity of the first dielectric layer before the second dielectric layer is deposited. This can prevent the second dielectric layer from being deposited in the communication cavity, which would affect the subsequent removal of the sacrificial layer. Due to the presence of the second dielectric layer, the sacrificial layer cannot be completely removed, which would affect the effect of subsequent metal filling and further improve the yield of the wafer.

[0037] In one embodiment, the first dielectric layer is a single layer (as described above). Figures 1-10 (as shown), or, the first dielectric layer may be two layers.

[0038] When the first dielectric layer has two layers, the etching of the first dielectric layer to obtain communication holes in the first dielectric layer includes: The second material layer in the first dielectric layer is etched to form the second communication cavity, and the first material layer in the first dielectric layer is etched to obtain the first communication cavity.

[0039] The etching of the second material layer and the etching of the first material layer, as described above, can be performed in the same step or in different steps.

[0040] The first communication hole is located on the semiconductor device substrate, and the projection of the second communication hole onto the first material layer covers the first communication hole.

[0041] In the case where there are two layers of the first dielectric layer, the projection of the communication hole onto the second dielectric layer covering the through hole means that the projection of the second communication hole onto the second dielectric layer covers the second through hole.

[0042] When the first dielectric layer has two layers, please refer to... Figure 11 , Figure 11 Provided for embodiments of the present invention, for Figure 3 Another schematic diagram of the second structure obtained by etching the first dielectric layer 201 in the first structure is shown below. Figure 11 The device includes: a semiconductor device substrate 200, a first material layer 2010 deposited on the semiconductor device 200, a second material layer 2011 deposited on the first material layer 2010, a first communication cavity 2020 formed by etching the first material layer 2010, and a second communication cavity 2021 formed by etching the second material layer 2011.

[0043] At the same time, it can be seen that, Figure 11 In this configuration, the first communication hole 2020 is centered at the exact center of the second communication hole 2021. The first communication hole 2020 may not be centered at the exact center of the second communication hole 2021, as long as the projection of the second communication hole 2021 onto the first material layer 2010 covers the first communication hole 2020.

[0044] Please refer to Figure 12 , Figure 12 Provided for embodiments of the present invention, removing Figure 7 The sacrificial layer 203 in the fifth structure, and the resulting schematic diagram of the sixth structure, are shown in the diagram. Figure 2 In the middle, from top to bottom, it includes: through hole 205, second communication hole 2021, and first communication hole 2020.

[0045] Based on the above discussion, the positional relationship between the first communication hole 2020, the second communication hole 2021, and the through hole 205 may include the following situations: In scenario 1, the first communication hole 2020 is centered at the exact center of the second communication hole 2021, and the through hole 205 is centered at the exact center of the second communication hole 2021.

[0046] In scenario 2, the first communication hole 2020 is centered at the exact center of the second communication hole 2021, and the through hole 205 is located slightly to the left of the exact center of the second communication hole 2021.

[0047] In scenario 3, the first communication hole 2020 is centered at the exact center of the second communication hole 2021, and the through hole 205 is located slightly to the right of the exact center of the second communication hole 2021.

[0048] Case 4: The first communication hole 2020 is located slightly to the left of the center of the second communication hole 2021, and the through hole 205 is located in the center of the second communication hole 2021.

[0049] Case 5: The first communication hole 2020 is located slightly to the right of the center of the second communication hole 2021, and the through hole 205 is centered at the center of the second communication hole 2021.

[0050] Case 6: The first communication hole 2020 is located slightly to the left of the center of the second communication hole 2021, and the through hole 205 is located slightly to the left of the center of the second communication hole 2021.

[0051] Case 7: The first communication hole 2020 is located slightly to the left of the center of the second communication hole 2021, and the through hole 205 is located slightly to the right of the center of the second communication hole 2021.

[0052] In scenario 8, the first communication hole 2020 is located slightly to the right of the center of the second communication hole 2021, and the through hole 205 is located slightly to the left of the center of the second communication hole 2021.

[0053] Case 9: The first communication hole 2020 is located slightly to the right of the center of the second communication hole 2021, and the through hole 205 is located slightly to the right of the center of the second communication hole 2021.

[0054] Based on the above discussion, and Figures 11-12 It can be seen that the projection of the second communication cavity 2021 onto the first material layer 2010 covers the first communication cavity 2020, and the projection of the second communication cavity 2021 onto the second dielectric layer 204 covers the through cavity 205. This means that the critical dimension of the second communication cavity 2021 is greater than or equal to the critical dimension of the first communication cavity 2020, and the critical dimension of the second communication cavity 2021 is greater than the critical dimension of the through cavity 205.

[0055] In one embodiment, the critical size of the second communication cavity is less than or equal to three times the critical size of the first communication cavity.

[0056] Please continue to refer to this. Figures 11-12 It can be seen that in Figures 11-12 In this context, the critical dimension of the second communication hole 2021 is more than one time and less than three times that of the first communication hole 2020. However, it is known that the critical dimension of the second communication hole 2021 should be more than one time greater than or equal to the critical dimension of the first communication hole 2020, and more than one time greater than or equal to the critical dimension of the through hole 205, while being less than or equal to three times the critical dimension of the first communication hole 2020. Therefore, it can be seen that... Figures 11-12In this embodiment, the ratio between the key dimensions of the second communication hole 2021, the first communication hole 2020, and the through hole 205 is only one example and does not imply a limitation on the proportional relationship between the key dimensions of the first communication hole 2020, the through hole 205, and the second communication hole 2021 in this embodiment.

[0057] This allows the solution described in the embodiments of the present invention to be implemented without occupying the area used in the semiconductor device substrate, thereby improving the yield of bare wafers.

[0058] In one embodiment, etching the first dielectric layer to obtain communication cavities in the first dielectric layer includes: A first etching method is used to etch the first dielectric layer to obtain an initial cavity; the initial cavity penetrates the first dielectric layer.

[0059] In the case where the first dielectric layer consists of two layers, the initial cavity has the same CD in both the first and second material layers.

[0060] The initial cavity is etched using a pre-defined second etching method to obtain the communication cavity.

[0061] In one embodiment, the preset first etching method may include, for example, a dry etching method; the preset second etching method may include, for example, a dry etching method and a wet etching method.

[0062] Dry etching refers to an etching method that uses plasma / high-energy ions to physically bombard and chemically react thin films in a gaseous environment without liquid chemical etchants. It is the mainstream etching process for semiconductor wafers. In this embodiment of the invention, dry etching is used to form initial cavities (CD) with the same shape in both the first and second dielectric layers.

[0063] Wet etching refers to immersing a wafer in a liquid chemical etching solution, relying on a pure chemical reaction to remove the thin film material. The entire process involves no plasma or ion bombardment, relying entirely on chemical etching.

[0064] Wherein, when the preset second etching method is a wet etching method, the etching rate of the wet etching method on the first material layer is less than the etching rate of the wet etching method on the second material layer.

[0065] The etching rate refers to the thickness of the medium layer that is etched away per unit time. The etching rate of the wet etching method on the first material layer is less than the etching rate of the wet etching method on the second material layer, meaning that the thickness of the medium layer etched away by the wet etching method on the first material layer is less than the thickness of the medium layer etched away by the wet etching method on the second material layer per unit time.

[0066] Specifically, if the etching rate of the wet etching method on the first material layer is less than the etching rate of the wet etching method on the second material layer, then the materials of the first and second material layers provided in this embodiment of the invention can be, for example, oxide layers, and the density of the first material layer is higher than that of the second material layer. This allows the etching rate of the wet etching method on the first material layer to be less than the etching rate of the wet etching method on the second material layer.

[0067] Breaking an etching step into two steps shortens the etching time per cycle, reduces process intensity, and minimizes erosion and pattern shift of the photomask. This ensures the positional accuracy of vias, reduces process defects, and effectively improves product yield.

[0068] In one embodiment, the etching selectivity ratio of the sacrificial layer material relative to the first dielectric layer is greater than 1; the material of the sacrificial layer includes polycrystalline silicon.

[0069] The etching selectivity ratio of the sacrificial layer material relative to the first dielectric layer can be, for example, the etching rate of the sacrificial layer material divided by the etching rate of the first dielectric layer material under the same etching method. A etching selectivity ratio greater than 1 means that, under the same etching method, such as wet etching, the etching rate of the sacrificial layer material divided by the etching rate of the first dielectric layer material is greater than 1, i.e., the etching rate of the sacrificial layer material is greater than the etching rate of the first dielectric layer material. This makes it easier to remove the sacrificial layer material during subsequent etching, as the etching rate of the sacrificial layer material is greater than that of the first dielectric layer material, thus reducing the etching of the first dielectric layer while removing the sacrificial layer.

[0070] Therefore, in a subsequent process, in step S107, in one embodiment, the sacrificial layer is removed, for example, by a wet process; the wet process uses low-concentration ammonia water to remove the sacrificial layer.

[0071] The materials of the second dielectric layer include borosilicate glass and fluorosilicone glass.

[0072] Since the aforementioned limitation on the association between the sacrificial layer material and the first dielectric layer material is to reduce the etching of the first dielectric layer when the sacrificial layer is removed later, and the association with the second dielectric layer is not significant when the sacrificial layer is removed later, the embodiments of the present invention do not limit the association between the material of the second dielectric layer and the material of the sacrificial layer, nor do they limit the association between the material of the first dielectric layer and the material of the third dielectric layer, as long as the respective process requirements are met.

[0073] In one embodiment, after the sacrificial layer is filled into the communication cavity and before the second dielectric layer is deposited on the first dielectric layer, the method further includes: The top of the sacrificial layer is planarized to be flush with the top of the second dielectric layer through a preset planarization process.

[0074] This allows for a flat bottom surface of the second dielectric layer deposited on the first dielectric layer. A flat bottom surface of the second dielectric layer optimizes photolithography focusing and depth of focus, effectively reduces overlay misalignment, avoids via alignment deviations, and improves photolithography yield. It also results in a more uniform dielectric etching rate, regular via etching depth and morphology, and more stable contact resistance. Simultaneously, it improves metal step coverage and via filling quality, reduces void defects, and lowers the risk of electromigration. Furthermore, it suppresses the accumulation of interlayer morphology errors, ensures the stability of multilayer metal interconnect processes, weakens local electric field concentration, reduces leakage current, improves IR (Integrated Resistance) voltage drop and timing performance, and enhances overall device yield and long-term reliability.

[0075] In one embodiment, the preset planarization process may include, for example, chemical mechanical polishing and etch-back.

[0076] Chemical mechanical polishing (CMP) is the only core process in semiconductor manufacturing that can achieve global wafer planarization. By combining chemical softening and mechanical polishing, nanoscale ultra-flat surfaces can be obtained.

[0077] Etch Back refers to first depositing a thin film across the entire surface to fill trenches / vias, then using dry / wet etching to uniformly remove a layer from the surface backwards, retaining only the material in the trenches and removing excess top film layer, achieving global planarity and local film retention. Corresponding to the via manufacturing method provided in this embodiment of the invention, a sacrificial layer is first filled into the first dielectric layer, then dry / wet etching is used to uniformly remove a layer from the surface backwards, retaining only the sacrificial layer in the first dielectric layer that connects to the vias. In other words, the top surface of the sacrificial layer is flush with the top surface of the first dielectric layer.

[0078] In one embodiment, after depositing a first dielectric layer on the semiconductor device substrate and before etching the first dielectric layer using a preset first etching method to obtain the initial cavity, the method further includes: Photolithography is performed on the first dielectric layer based on a pre-selected first photomask; After depositing the second dielectric layer on the first dielectric layer and before etching the second dielectric layer to obtain the via cavity, the method further includes: The second dielectric layer is photolithographically ...

[0079] In one embodiment, the first photomask and the second photomask are the same photomask, or the first photomask and the second photomask are different photomasks.

[0080] When the first and second photomasks mentioned above are the same photomask, resource consumption can be reduced.

[0081] Based on the same inventive concept, this invention also provides a semiconductor structure, please refer to... Figure 10 The semiconductor structure includes: a semiconductor device substrate 200; A via 206 is located above the semiconductor device substrate 200. The via 206 includes a communication via 2061 penetrating a first dielectric layer 201 on the semiconductor device substrate 200, and a first via 2060 penetrating a second dielectric layer 204 on the first dielectric layer 201. The projection of the communication via 2061 onto the second dielectric layer 204 covers the first via 2060.

[0082] Based on the above discussion, it can be seen that the semiconductor structure provided in the embodiments of the present invention is manufactured by the aforementioned through-hole manufacturing method. In the through-hole manufacturing method provided in the embodiments of the present invention, a semiconductor device substrate 200 is first provided, a first dielectric layer 201 is deposited on the semiconductor device substrate 200, and the first dielectric layer 201 is etched to form a communication cavity in the first dielectric layer 201, and a sacrificial layer is filled in the communication cavity; a second dielectric layer 204 is deposited on the first dielectric layer 201; the second dielectric layer 204 is etched to obtain a through-hole cavity; the projection of the communication cavity on the second dielectric layer 204 covers the through-hole cavity; the sacrificial layer is removed; and metal is filled in the through-hole cavity and the communication cavity to obtain a through-hole 206. After the vias and the communication holes are filled with metal, if an overlay misalignment occurs between the via 206 and the semiconductor device substrate 200, since the projection of the communication hole on the second dielectric layer 204 covers the via on the semiconductor device substrate 200, the communication via 2061 obtained by filling the communication hole with metal can electrically connect the first via 2060 and the semiconductor device substrate 200, thereby reducing the probability of an overlay misalignment between the semiconductor device substrate 200 and the first via 2060 and improving the yield of the wafer.

[0083] In addition, in this embodiment of the invention, a sacrificial layer is filled into the communication cavity of the first dielectric layer before the second dielectric layer is deposited. This can prevent the second dielectric layer from being deposited in the communication cavity, which would affect the subsequent removal of the sacrificial layer. Due to the presence of the second dielectric layer, the sacrificial layer cannot be completely removed, which would affect the effect of subsequent metal filling and further improve the yield of the wafer.

[0084] In one embodiment, the semiconductor device substrate includes a substrate, or the semiconductor device substrate includes a substrate and a gate structure.

[0085] This means that the via can be located on the substrate or on the gate structure. Of course, the via locations in the embodiments of the present invention are not limited to the gate structure and the substrate; the semiconductor structure manufacturing method provided in the embodiments of the present invention can be applied to any structure where vias need to be set.

[0086] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0087] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing through holes, characterized in that, include: Provides semiconductor device substrates; A first dielectric layer is deposited on the semiconductor device substrate; Etch the first dielectric layer to obtain communication holes in the first dielectric layer; A sacrificial layer is filled into the communication cavity; Deposit a second dielectric layer on the first dielectric layer; The second dielectric layer is etched to obtain a through-hole cavity; the projection of the through-hole cavity onto the second dielectric layer covers the through-hole cavity. Remove the sacrificial layer; Metal is filled into the through hole and the communication hole to obtain a through hole.

2. The through-hole manufacturing method as described in claim 1, characterized in that, The first dielectric layer is one layer, or the first dielectric layer is two layers; When the first dielectric layer has two layers, the etching of the first dielectric layer to obtain communication holes in the first dielectric layer includes: The second material layer in the first dielectric layer is etched to form the second communication cavity, and the first material layer in the first dielectric layer is etched to obtain the first communication cavity; The first communication cavity is located on the semiconductor device substrate, and the projection of the second communication cavity onto the first material layer covers the first communication cavity; The projection of the second communication cavity onto the second dielectric layer covers the second through-hole cavity.

3. The through-hole manufacturing method as described in claim 2, characterized in that, The critical dimension of the second communication hole is less than or equal to three times the critical dimension of the first communication hole.

4. The through-hole manufacturing method as described in claim 2, characterized in that, The etching of the first dielectric layer to obtain communication cavities in the first dielectric layer includes: A first etching method is used to etch the first dielectric layer to obtain an initial cavity; the initial cavity penetrates the first dielectric layer. The initial cavity is etched using a pre-defined second etching method to obtain the communication cavity.

5. The through-hole manufacturing method as described in claim 4, characterized in that, The preset first etching method includes a dry etching method; the preset second etching method includes a dry etching method and a wet etching method. Wherein, when the preset second etching method is a wet etching method, the etching rate of the wet etching method on the first material layer is less than the etching rate of the wet etching method on the second material layer.

6. The through-hole manufacturing method as described in claim 5, characterized in that, The etching rate of the wet etching method on the first material layer is less than the etching rate of the wet etching method on the second material layer, including: the first material layer and the second material layer are oxide layers, and the density of the first material layer is higher than the density of the second material layer.

7. The through-hole manufacturing method as described in claim 1, characterized in that, The etching selectivity ratio of the sacrificial layer material relative to the first dielectric layer is greater than 1; The material of the sacrificial layer includes: polycrystalline silicon; The materials of the second dielectric layer include borosilicate glass and fluorosilicone glass.

8. The through-hole manufacturing method as described in claim 1, characterized in that, After the sacrificial layer is filled into the communication cavity, and before the second dielectric layer is deposited on the first dielectric layer, the method further includes: The top of the sacrificial layer is planarized to be flush with the top of the first dielectric layer through a preset planarization process.

9. The through-hole manufacturing method as described in claim 8, characterized in that, The preset planarization process includes: chemical mechanical polishing and etching back.

10. The through-hole manufacturing method as described in claim 4, characterized in that, After depositing a first dielectric layer on the semiconductor device substrate, and before etching the first dielectric layer using a preset first etching method to obtain the initial cavity, the method further includes: Photolithography is performed on the first dielectric layer based on a pre-selected first photomask; After depositing the second dielectric layer on the first dielectric layer and before etching the second dielectric layer to obtain the via cavity, the method further includes: The second dielectric layer is photolithographically ...

11. The through-hole manufacturing method as described in claim 10, characterized in that, The first photomask and the second photomask are the same photomask, or the first photomask and the second photomask are different photomasks.

12. The through-hole manufacturing method as described in claim 1, characterized in that, The sacrificial layer is removed using a wet process; the wet process uses low-concentration ammonia water to remove the sacrificial layer.

13. A semiconductor structure, characterized in that, include: Semiconductor device substrate; A via is located above the semiconductor device substrate. The via includes a communication via penetrating a first dielectric layer on the semiconductor device substrate and a first via penetrating a second dielectric layer on the first dielectric layer. The projection of the communication via onto the second dielectric layer covers the first via.

14. The semiconductor structure as described in claim 13, characterized in that, The semiconductor device substrate includes a substrate, or the semiconductor device substrate includes a substrate and a gate structure.

Images