MdiP semiconductor device including backfilled vias

Abstract

The present disclosure relates to mDiP semiconductor devices including backfilled vias. A mirror die pair (mDiP) semiconductor device includes deep trench vias having portions backfilled with a conductive material at an upper surface and / or a lower surface of the mDiP device. Backfilling the deep trench vias ensures, for example, solid state, low resistance bonding between stacks of mDiP semiconductor devices.

Description

Background Technology

[0001] The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, are widely used to meet the ever-increasing demand for digital information storage and exchange. The portability, versatility, and custom design of non-volatile memory products, along with their high reliability and large capacity, make them ideal for use in a wide range of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs, cellular phones, and solid-state drives (SSDs).

[0002] Artificial intelligence (AI) and machine learning (ML) applications require advanced memory and computing solutions with high performance, low power consumption, low latency, and high bandwidth to support intensive read and write operations during feature training and inference phases. To meet these requirements, 3D BiCS (Bit-Cost Scalable) technology has emerged as a viable solution, offering rapid scaling to achieve higher storage capacity per die.

[0003] Traditionally, multi-die stacking using wire-bonded dies, such as BiCS memory dies, has been employed to increase memory capacity. However, this approach has significant drawbacks, including limitations on semiconductor die thickness. In particular, given the ongoing drive to provide larger memory capacities with smaller form factors, semiconductor devices are manufactured as thin as possible, currently around 36 micrometers (μm) or smaller. However, mechanical or thermal stress factors causing die warping, chipping, and / or cracking during semiconductor packaging manufacturing demonstrate obstacles to further reducing semiconductor die thickness.

[0004] Furthermore, conventional die stacking methods face significant limitations in meeting customers' demands for in-memory computing power in artificial intelligence / machine learning (AI / ML) applications. A major drawback is the large pin-capacitance, which increases power consumption and reduces signal integrity, thereby degrading overall performance. Additionally, traditional stacking methods offer limited parallelism, restricting the number of simultaneous read and write operations, which is crucial for high-speed AI / ML workloads. Higher read latency is another issue, as data access time is extended due to increased interconnect distances between stacked dies and signal propagation delays. Reliability issues associated with microbumps further exacerbate these challenges, as stress, electromigration, and thermal cycling caused by microbumps can lead to performance degradation and potential failures over time. These limitations collectively hinder the use of conventional die stacking in AI / ML in-memory computing architectures, necessitating innovative design approaches to overcome these constraints.

[0005] To address these challenges, mirrored die-pair (mDiP) bonding methods have been developed, in which two memory wafers are bonded face-to-face. Face-to-face bonding significantly reduces warpage and allows for further wafer thinning during semiconductor packaging or assembly without chipping and / or breaking. Furthermore, die pairs effectively double memory capacity, enabling parallelism and increased bandwidth for computing applications. Electrical connections in mDiP die stacks are achieved using TSVs (Through Silicon Vias) or other high aspect ratio deep trench vias, which efficiently route high voltages, logic, I / O, and other signals from the controller die to the memory die.

[0006] This approach introduces new challenges, such as in via formation. Conventional TSV formation results in underfilled vias, where concave menisci are formed at the top and / or bottom of each TSV. Underfilled TSVs can lead to high resistance and voids. In other words, underfilled TSVs are electrically decoupled. These defects cause significant signal transmission losses, data corruption, computational inference delays, and reliability issues that can hinder product performance and field usability or use. Attached Figure Description

[0007] Figure 1 This is a flowchart illustrating an embodiment of the present invention for forming an mDiP memory device.

[0008] Figure 2 This is a top view of a first semiconductor wafer and a first semiconductor die therefrom, according to an embodiment of the present invention.

[0009] Figure 3 This is a top view of a second semiconductor wafer and a second semiconductor die therefrom, according to an embodiment of the present invention.

[0010] Figure 4 This is a side-cross view of a first semiconductor of a first wafer die according to an embodiment of the present invention.

[0011] Figure 5 This is a side-cross view of a second semiconductor die on a second wafer according to an embodiment of the present invention.

[0012] Figure 6 This is a cross-sectional side view of a first wafer and a second wafer joined together to form a CBA memory wafer according to an embodiment of the present invention.

[0013] Figure 7 This is a cross-sectional side view of a first CBA memory wafer and a second CBA memory wafer positioned together according to an embodiment of the present invention.

[0014] Figure 8This is a cross-sectional side view of a first CBA memory wafer and a second CBA memory wafer joined together to form an mDiP memory wafer according to an embodiment of the present invention.

[0015] Figure 9 This is a flowchart illustrating an embodiment of the present invention for forming an mDiP semiconductor memory device from stacked mDiP memory wafers.

[0016] Figure 10 This is a side-cross-sectional view of an mDiP memory wafer having a first surface thinned in a back-side grinding and polishing process, according to an embodiment of the present invention.

[0017] Figure 11 This is an enlarged cross-sectional view of the first surface of an mDiP memory wafer according to an embodiment of the present invention, showing a concave meniscus formed in a deep trench via after thinning of the first wafer surface.

[0018] Figure 12 This is an enlarged cross-sectional view of the first surface of an mDiP memory wafer according to an embodiment of the present invention, showing the processing of deep trench vias to enlarge the vias at the first surface.

[0019] Figure 13 This is an enlarged cross-sectional view of the first surface of an mDiP memory wafer according to an embodiment of the present invention, showing a deep trench via with an enlarged filled section at the first surface.

[0020] Figure 14 This is a side-cross-sectional view of an mDiP memory wafer having a second surface thinned in a back-side grinding and polishing process, according to an embodiment of the present invention.

[0021] Figure 15 This is a cross-sectional side view of a pair of mDiP memory wafers bonded together at an enlarged filled surface section, according to an embodiment of the present invention.

[0022] Figure 16 This is an enlarged cross-sectional side view of an enlarged filled surface segment of the deep trench via bonding of the first and second bonded mDiP memory wafers according to an embodiment of the present invention.

[0023] Figure 17 This is an enlarged cross-sectional side view of the bonding surface segment of a deep trench via from a first and second bonded mDiP memory wafer, according to an alternative embodiment of the present invention.

[0024] Figure 18This is an enlarged cross-sectional side view of the bonding surface segment of a deep trench via from a first and second bonded mDiP memory wafer, according to another alternative embodiment of the technology of the present invention.

[0025] Figure 19 This is a cross-sectional side view of a plurality of mDiP stacked on a substrate according to an embodiment of the present invention. Detailed Implementation

[0026] The invention will now be described with reference to the accompanying drawings, which, in embodiments, relate to mirror-image die-pair (mDiP) semiconductor devices including deep trench vias, the vias comprising portions backfilled with a conductive material on the upper and / or lower surfaces of the mDiP device. As described in the Background section, the processing of mDiP semiconductor wafers produces vias having concave menisci on a first and / or second surface of the mDiP wafer. Backfilling these concave menisci ensures, for example, electrical coupling, solid-state, and low-resistance bonding to another mDiP semiconductor device or wafer.

[0027] In one example, the backfill portion of a deep trench via from two bonded mDiP wafers can be enlarged first and then backfilled. This ensures a large surface area at the bonding side of the bonding pads or microbumps. In another example, where a first via and a second via are bonded together in adjacent mDiP wafers, the surface portion of the first via can be enlarged and backfilled, while the surface portion of the second via can be smaller and backfilled. This increases the likelihood that the second via will be entirely within the bonding surface or occupied area of ​​the second via, thereby minimizing the resistivity of the bonding pads or microbumps. Another example can be similar to the examples above, but the surface portion of the two vias bonded together is made smaller and backfilled.

[0028] It should be understood that the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. In fact, the invention is intended to cover alternatives, modifications, and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of the invention to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without such specific details.

[0029] The terms “top” and “bottom,” “upper” and “lower”, and “vertical” and “horizontal” as used herein, and their various forms, are by way of example and for illustrative purposes only, and are not intended to limit the description of the technique, as the referenced items may be interchanged in position and orientation. Furthermore, as used herein, the terms “substantially” and / or “about” mean that a specified dimension or parameter may vary within acceptable manufacturing tolerances for a given application. In one embodiment, acceptable manufacturing tolerances are ±0.15 mm or alternatively ±2.5% of a given dimension.

[0030] For the purposes of this disclosure, physical or electrical connections can be direct or indirect (e.g., via one or more other parts). In some cases, when the first element is referred to as a (physical or electrical) connection, attachment, mounting, or coupling to the second element, the first and second elements can be directly connected, attached, mounted, or coupled to each other or indirectly (physical or electrical) connected, attached, mounted, or coupled to each other. When the first element is referred to as a direct connection, attachment, mounting, or coupling to the second element, there is no intermediate element between the first and second elements (other than the possibility of adhesives or molten metal used to connect, attach, mount, or couple the first and second elements).

[0031] Now refer to Figure 1 and Figure 9 Flowchart and Figures 2-8 and Figures 10-19 The following view illustrates one embodiment of the invention. In step 200, the first semiconductor wafer 100 can be processed into a plurality of first semiconductor dies 102, such as memory array semiconductor dies, as shown below. Figure 2 As shown. The first semiconductor wafer 100 may begin as an ingot of wafer material, which may be single-crystal silicon grown according to a Czochralski (CZ) or floating zone (FZ) process. However, in another embodiment, the first wafer 100 may be formed from other materials and by other processes.

[0032] Semiconductor wafer 100 can be cut from an ingot and onto a first main flat surface 104 and a second main flat surface 105 opposite to surface 104. Figure 4Both surfaces are polished to provide a smooth surface. The first main surface 104 may undergo various processing steps to divide the wafer 100 into corresponding first semiconductor dies 102, and to form integrated circuits of the corresponding first semiconductor dies 102 on and / or within the first main surface 104. In the illustrated embodiment, each die 102 may have four separate (independently accessible) memory planes or channels CH0 to CH3. Each channel may also consist of more or fewer planes. The memory planes in each channel can be controlled independently. Separate, independently accessible memory planes increase the bandwidth of the die 102, but in other embodiments, separate memory planes may be omitted. Figure 2 Further details of a single semiconductor die 102 are shown, including patterns of bonding or microbump pads 106 as described below.

[0033] like Figure 4 As shown in the cross-sectional side view, the processing of wafer 100 in step 200 may include forming an integrated circuit memory cell array 122, which is formed in a semiconductor or dielectric substrate including layer 124. A reticle may be used to transfer the integrated circuit pattern of each semiconductor die 102 in a photolithography process. The patterned wafer may then undergo various processes, such as etching, ion implantation, and deposition, to produce the actual semiconductor components and interconnects required to construct the integrated circuit of semiconductor die 102. In an embodiment, the integrated circuit may be a memory cell array 122 formed as a 3D stacked memory structure having strings of memory cells formed as layers. However, it should be understood that the first semiconductor die 102 may be processed to include integrated circuits other than a 3D stacked memory structure. As described above, in an embodiment, the memory array 122 on each semiconductor die 102 may include a separate memory plane for each of the channels CH0 to CH3. A passivation layer 128 (in one example, an oxide layer or other dielectric layer) may be formed on top of the metal interconnect layer 130.

[0034] After forming the memory cell array 122, in step 204, internal electrical connections may be formed within the first semiconductor die 102. The internal electrical connections may include multilayer metal interconnects 130, vias 132, and deep trench vias 134 sequentially formed through layers of the substrate 124. As described below, the deep trench vias 134 extend through the finished mDiP semiconductor device, while the vias 132 may partially extend through one or more dies of the mDiP semiconductor device. Each via 132, 134 may include sidewalls, barrier metal, and fill metal, as described below. In embodiments, the fill metal may be copper, aluminum, alloys thereof, or other conductive compounds as described below.

[0035] As known in the art, the metal interconnects 130, vias 132, and deep trench vias 134 can be formed, for example, using a damascene process performed layer by layer using photolithography and thin-film deposition processes. Photolithography processes can include, for example, patterning, plasma, chemical, or dry etching and polishing. Thin-film deposition processes can include, for example, sputtering and / or chemical vapor deposition. The metal interconnects 130 can be formed of various conductive metals, including, for example, copper and copper alloys known in the art, and the vias 132 can be lined and / or filled with various conductive metals, including, for example, tungsten, copper, and copper alloys known in the art. For example, in… Figure 4 As seen, metal interconnects 130, vias 132, and deep trench vias 134 may be formed to and through the memory cell array 122 to carry signals to and from the memory cell array 122 of the logic devices and host devices.

[0036] In step 208, microbump pads 106 may be formed on the first (active) master planar surface 104 of the first semiconductor die 102. For example... Figure 2 and Figure 4 As shown, these bump pads may be formed on top of vias 132 and / or 134 and may be used to transmit signals to and from the semiconductor die 102. The bump pads may be etched into the passivation layer 128, and each bump pad 106 may be formed over the liner 136. As known in the art, the bump pads 106 may be formed of, for example, copper, aluminum, and alloys thereof, and the liner 136 may be formed of, for example, a titanium / titanium nitride stack (e.g., Ti / TiN / Ti), but these materials may vary in other embodiments. The bump pads 106 and the liner 136 may be applied by vapor deposition and / or electroplating techniques. The integrated circuit memory array 122 may be electrically connected to the bump pads 106 via metal interconnects 130 and vias 132, 134.

[0037] In step 210, the first (active) surface 104 of wafer 100 may be supported on a temporary carrier (not shown), and the second (passive) surface 105 may be thinned to the final thickness of wafer 100 during a back-side polishing process (e.g., ...). Figure 4 (As shown). Thinning of wafer 100 exposes deep trench vias 134 at the second surface 105. Subsequently, in step 212, microbump pads 108 can be formed on the deep trench vias 134 on the passive surface 105, such as, for example... Figure 4 As shown.

[0038] Figure 2 An exemplary pattern of a first semiconductor die 102 on wafer 100 is shown. However, Figure 2The pattern and number of first semiconductor dies 102 shown on wafer 100 are for illustrative purposes, and wafer 100 may include more or fewer first semiconductor dies 102 than shown in other embodiments, and with different patterns. Similarly, for illustrative purposes, the pattern shown is... Figure 2 and Figure 4 The diagram shows the pattern and number of pads 106 and microbumps 108 on the first semiconductor die 102. Each first die 102 may include more pads 106 and / or microbumps 108 than shown in other embodiments, and may include various other patterns and densities of pads 106 and / or microbumps 108.

[0039] Before, after, or in parallel with the formation of the first semiconductor die on wafer 100, in such a way as Figure 3 In step 220 shown, the second semiconductor wafer 110 can be processed into a plurality of second semiconductor dies 112, such as CMOS logic circuit dies. The semiconductor wafer 110 can begin as a single-crystal silicon ingot grown according to CZ, FZ, or other processes. The second semiconductor wafer 110 can have a first main surface 114 and a second main surface 115 opposite to surface 114. Figure 5 Both are cut and polished to provide a smooth surface. The first main surface 114 may undergo various processing steps to divide the second wafer 110 into corresponding second semiconductor dies 112, and to form integrated circuits of the corresponding second semiconductor dies 112 on and / or in the first main surface 114. Figure 3 Further details of the individual semiconductor die 112 are shown, including the pattern of the microbump pads 116 described below.

[0040] In one embodiment, the second semiconductor die 112 may be processed to include an integrated circuit 142 formed in a semiconductor or dielectric substrate 144, such as Figure 5 The cross-sectional side view is shown. Integrated circuit 142 can be configured as logic circuitry to control read / write operations on one or more integrated memory cell arrays 122. CMOS technology can be used to fabricate the logic circuitry, but in other embodiments, other technologies may be used. In further embodiments described below, the second semiconductor die 112 may include other and / or additional integrated circuits. A passivation layer (in one example, an oxide layer or other dielectric layer 148) may be formed on the upper surface 114.

[0041] After forming the CMOS logic circuit 142, in step 224, internal electrical connections may be formed within the second semiconductor die 112. These internal electrical connections may include multilayer metal interconnects 150, vias 152, and deep trench vias 154 formed above the logic circuit system 142. The metal interconnects 150, vias 152, and deep trench vias 154 may be formed in the same manner as the interconnects 130, vias 132, and deep trench vias 134 described above for die 102.

[0042] For example in Figure 5 As seen, the metal interconnects 150 and vias 152 can be connected to the CMOS logic circuit 142 to transmit signals to and from the logic circuit 142. In step 228, microbump pads 116 can be formed on the main flat surface 114 of the second semiconductor die 112. Figure 3 and Figure 5 As shown, these bump pads may be on top of via 152. As further explained below, bump pad 116 is provided for transmitting signals to and from the semiconductor die 112. The bump pads may be etched into the passivation layer 148 and may include a liner 156. Bump pad 116 and liner 156 may be formed in the same manner as bump pad 106 and liner 136 described above. CMOS logic circuitry 142 may be electrically connected to bump pad 116 via metal interconnects 150 and vias 152, 154.

[0043] Figure 3 The number and pattern of the second semiconductor dies 112 on wafer 110 are shown for illustrative purposes, and in other embodiments, wafer 110 may include more or fewer second semiconductor dies 112 and other patterns of the dies 112. Similarly, for illustrative purposes, the pattern of pads 116 on the second semiconductor dies 112 and the number of bump pads 116 are shown. Each second die 112 may include more bump pads 116 than shown in other embodiments, and may include various other patterns and densities of bump pads 116.

[0044] Once the fabrication of the first semiconductor die 102 and the second semiconductor die 112 is completed, the first semiconductor wafer 100 and the second semiconductor wafer 110 can be bonded to each other in step 230, such that the corresponding memory die 102 is bonded to the CMOS logic circuit die 112. The bonded wafers 100 and 110 are referred to herein as CBA memory wafers 158, and each pair of bonded dies 102 and 112 is referred to herein as a CBA memory die 160. For example, in... Figure 6 An example of the completed CBA memory die 160 is shown in the cross-sectional side view.

[0045] In order to bond dies 102 and 112, the first semiconductor wafer 100 can be flipped (relative to...) Figure 4 (see view), and the bump pads 106 and 116 of the corresponding dies 102 and 112 can be physically and electrically coupled to each other. As shown and described, the number and pattern of the bump pads 106 can be matched with the number and pattern of the bump pads 116 such that when the dies 102 and 112 are coupled together, the pads are aligned with each other. In an embodiment where the number and pattern of the bump pads 106 and 116 are asymmetrical about the central vertical axis passing through the die, the number and pattern of the bump pads 106 can be a mirror image of the number and pattern of the bump pads 116 such that the pads 106 and 116 are aligned when the die 102 is flipped.

[0046] The first semiconductor die 102 and the second semiconductor die 112 in the CBA memory die 160 can be bonded to each other by initially aligning the bump pads 106 and 116 on the respective dies 102, 112 with each other. Thereafter, the bump pads 106, 116 can be bonded together using any of a variety of bonding techniques, depending in part on the bump pad size and bump pad spacing (i.e., bump pad pitch). These bonding techniques include, for example, Cu-Cu bonding, oxide-to-oxide bonding, and hybrid bonding. The bump pad size and spacing can then be determined by the number of electrical interconnects required by the CBA memory die.

[0047] In step 226, two CBA memory wafers 158 can be bonded together face-to-face to form a mirrored die pair (mDiP) wafer. As described in the background art, face-to-face bonding of wafers solves problems such as warpage and breakage during packaging processes or assembly. The active surfaces 104 of the first and second CBA memory wafers 158 can be bonded to each other face-to-face, as... Figure 7 and Figure 8 As shown. Figure 9 and Figure 10 Further details of this bonding at the die level are shown.

[0048] like Figure 7As shown, one of the CBA memory wafers 158 can be flipped and positioned on top of the second CBA memory wafer 158, such that the bump pads 108 on each CBA wafer in the respective CBA wafer 158 are aligned with each other. A single die of the CBA memory wafer 158 is referred to herein as die 160. Once placed together, the bump pads 108 of the respective CBA memory wafers 158 can be physically bonded to each other via Cu-Cu bonding, oxide-to-oxide bonding, and hybrid bonding. Other wafer-to-wafer bonding techniques are possible. Such additional techniques include various dielectric-to-dielectric bonding techniques, including silicon-to-silicon bonding and silicon-to-silicon dioxide bonding. The two bonded CBA memory wafers 158a and 158b are referred to herein as a mirrored die pair (mDiP) wafer 170, as... Figure 8 As shown. Individual dies bonded face-to-face in an mDiP wafer are referred to herein as mDiP 172.

[0049] Now refer to Figure 9 The flowchart illustrates the further processing of mDiP wafer 170 into a finished mDiP semiconductor device. For example... Figure 8 As shown, the mDiP wafer 170 has a first master planar (passive) surface 174 and an opposing second master planar (passive) surface 176. One of the CBA memory wafers 158 (e.g., the top CBA wafer 158a) may undergo a back-side grinding process on the master planar surface 174 in step 230 to thin the wafer 110 of the first CBA memory wafer 158a, for example, from 760 μm to a final thickness that may be in the range of 10 μm to 36 μm. Then, in step 232, the surface 174 is polished. Figure 10 This structure is illustrated. It should be understood that in other embodiments, the final thickness of the thinned wafer 110 may be greater than or less than the range described.

[0050] The back-side grinding and polishing processes in steps 230 and 232 expose the deep trench via 154 to the main flat surface 174 of the top CBA memory wafer 158a. However, as described in the Background section, the back-side grinding and polishing steps can also induce a concave meniscus in the via 154 at surface 174. This feature... Figure 11 It is shown in more detail below. Figure 11 A deep trench via 154 formed in a substrate 124 is shown. Each deep trench via 154 may include a sidewall 180, a barrier metal 182, and a fill metal 184, as described above. The sidewall 180 may be formed, for example, of an oxide (such as silicon oxide). The barrier metal 182 may be, for example, titanium nitride and / or titanium (TiN / Ti). The fill metal 184 may be, for example, copper, aluminum, and alloys thereof. The barrier metal 182 and the fill metal 184 may be other low-resistivity metals, metal alloys, Si / metal alloys, or other binary or ternary compounds. Figure 11 The concave meniscus 186 formed in each deep trench through-hole 154 at the main flat surface 174 is shown.

[0051] As now regarding Figure 12 and Figure 13 As described, the concave meniscus of various deep trench through-holes 154 exposed at surface 174 is processed. In step 234, as... Figure 12 As indicated by reference numeral 188 in the figure, the end of the through-hole 154 at surface 174 is enlarged. The enlarged portion 188 removes the concave meniscus 186 at each deep trench through-hole 154. The deep trench through-hole 154 (before step 234) may have a diameter between 1 μm and 10 μm, but the diameter of the deep trench through-hole 154 may be larger or smaller than the diameter in other embodiments. In step 234, the end of the through-hole 154 at surface 174 may be enlarged by 10% to 100%. In another example, the end of the through-hole 154 at surface 174 may be enlarged by 25% to 75%. In another example, the end of the through-hole 154 at surface 174 may be enlarged by 40% to 60%. These various ranges are only examples, and in other embodiments, the end of the through-hole 154 at surface 174 may be enlarged by more or less than these ranges. The depth of the via enlargement starting from surface 174 can be from 1 μm to 5 μm, but in other embodiments, the depth of the via enlargement can be less than or greater than this range.

[0052] The deep trench vias 154 can be enlarged at surface 174 using various techniques, including, for example, chemical etching, plasma etching, laser ablation, ion and reactive ion etching, deep reactive ion etching, and wet etching. It should be understood that, in other embodiments, the via enlargement in step 234 can be enlarged using other methods. The enlargement may be circular in shape and concentric with the remainder of each deep trench via 154. In other embodiments, the enlargement at each deep trench via 154 may be of other shapes.

[0053] In step 238, the enlarged portion 188 may be backfilled with a conductive, low-resistance metal (including, for example, copper, aluminum, and their alloys) to form as shown. Figure 13 The enlarged micropad 190 is shown. In an embodiment, the backfill metal forming the enlarged micropad 190 may be the same as the fill metal 184 forming the remaining portion of the conductive portion of the deep trench via 154.

[0054] Then, the mDiP wafer 170 can be flipped, and the first main planar surface 174 can be supported on the temporary carrier 192, as follows. Figure 14As shown. The above steps can then be repeated on the second primary flat surface 176. Specifically, surface 176 can be thinned in back-side grinding and polishing steps 240, 242 to expose the deep trench vias 154 and create the concave meniscus as described above. In step 244, enlarged portions 188 can be created at each deep trench via 154 on the second primary flat surface 176, and the enlarged portions can be backfilled in step 248 to form enlarged micropads 190 on each deep trench via 154 on the second primary flat surface 176, as... Figure 14 As shown.

[0055] although Figure 10 and Figure 14 For simplicity, a single mDiP 172 is shown, but during the manufacturing stage, the mDiP 172 remains part of its corresponding mDiP wafer 170. After forming enlarged micropads 190 on the second main flat surface 176, the mDiP wafer 170 can be supported on a dicing tape, and the mDiP wafer 170 can be diced in step 250 to form individual mDiPs 172. Each of these mDiPs 172 includes a first CBA memory die 160a and a second CBA memory die 160b mounted face-to-face to each other. The mDiP memory wafer 170 can be diced into individual mDiPs 172 using, for example, stealth laser dicing. In other embodiments, saw blades and other conventional methods can be used. After dicing, the dicing tape can be unrolled to facilitate the pickup of the mDiPs 172 from the dicing tape by a pick-and-place robot (not shown).

[0056] According to various aspects of the invention, given face-to-face mounting of corresponding CBA memory wafers 158a and 158b, wherein the active surfaces of the corresponding wafers face each other, their different coefficients of thermal expansion cancel each other out, as do the strains generated by materials with different thermal coefficients. Due to this balance, the warpage of mDiP 172 is significantly or completely eliminated.

[0057] Furthermore, the backfilled enlarged microbumps 190 ensure that the corresponding mDiP 172 can be stacked on top of each other and are physically and electrically bonded to each other simply, firmly and effectively. Figure 15 A pair of mDiP 172s are shown, electrically and physically bonded to each other by enlarged microbumps 190. Figure 16 A partially enlarged view of a pair of mDiPs is shown, in which the enlarged microbumps 190 of the deep trench vias 154 are bonded to each other. Backfill material ensures that the microbumps 190 of the two mDiPs 172 are flush with their respective surfaces, thereby minimizing resistance and ensuring a strong bond. Furthermore, even with slight misalignment between the first and second sets of deep trench vias 154, the enlarged size ensures significant overlap.

[0058] In the implementation, the enlarged micropad 190 may have a diameter at least larger than that of the filler metal 184. Figure 16 Such an embodiment is illustrated. In another embodiment, the enlarged micro pad 190 may have a larger diameter than the rest of the deep trench via as a whole (including sidewall 180, barrier metal 182, and filler metal 184). Figure 13 Such an implementation scheme is shown in the figure.

[0059] In the above embodiment, the tip of the deep trench via 154 is processed by enlarging the via in step 234 and then backfilling the enlarged via in step 238. In another embodiment, the enlarging step 234 may be omitted. In this embodiment, in step 238, the via can be simply filled with a conductive metal. Figure 11 The deep groove through-hole of the concave meniscus 186 shown makes the surface of the deep groove through-hole 154 flush with the surface 174.

[0060] Figure 17 Alternative embodiments of the present invention are shown. In this embodiment, one of the main (passive) planar surfaces of the mDiP (e.g., surface 176) includes enlarged microbumps 190 as described above. However, the opposing main (passive) planar surface (174 in this example) includes deep trench vias 154 with reduced-size microbumps 194. The reduced-size microbumps 194 can be formed in the same manner as the enlarged microbumps 190. A portion of the proximal surface of each deep trench via 154 can be removed, such as by chemical etching or other techniques described above. Subsequently, a portion of the space created by the removed material can be backfilled with metal, such as the same metal used for filler metal 184. The backfill metal can be shaped, for example, into a trapezoidal shape, wherein the diameter decreases the closer the microbumps are to the mDiP surface 174.

[0061] In this embodiment, the tip of the reduced-size microbump 194, flush with the surface of mDiP, may have a smaller diameter than the filler material 184 to which the reduced-size microbump 194 engages. For example... Figure 17 As shown, even with some misalignment in the bonded mDiP172, the reduced-diameter microbumps 194 will be perfectly aligned within the enlarged microbumps 190. This complete overlap reduces contact resistance and improves signal transmission between the bonded mDiP172s.

[0062] Figure 18Another embodiment of the invention is shown, wherein the deep trench via 154 at both the first main flat surface 174 and the second main flat surface 176 is formed with reduced-size microbumps 194. Therefore, when a pair of mDiPs are joined together, the reduced-size microbumps 194 on the first mDiP 172 are electrically coupled to the reduced-size microbumps 194 on the second mDiP 172.

[0063] Figure 19 This is a cross-sectional side view of an mDiP semiconductor device 195 formed by multiple stacked and interconnected mDiP 172s. A deep trench via 154 is shown extending through the entire mDiP semiconductor device 195. The deep trench via 154 can be connected to a controller die 196 mounted at a base of the device 195. The controller die 196 can be, for example, an ASIC, or a dedicated processor, such as an AI processor or graphics processing unit. Generally, the controller die controls data transfer to and from memory cells in the stacked mDiP 172s. As described, each mDiP 172 can consist of memory dies with multiple planes, thus allowing multiple reads / writes to a single memory die of the mDiP 172 to be performed in parallel. This greatly increases the bandwidth of input / output operations to and from the mDiP semiconductor device 195. The controller die 196 can then be mounted to a host device (not shown), such as a printed circuit board.

[0064] The mDiP semiconductor device 195 can be encapsulated in a molding compound 198 of an mDiP 172 in a protective stack. The encapsulation step can be performed by placing the mDiP semiconductor device 195 or a plate of the mDiP semiconductor device 195 in a mold cavity and injecting the liquid molding compound over the mDiP 172 and the controller die 196. In another embodiment, other encapsulation processes can be used, including, for example, FFT (flow-free thin) compression molding. The molding compound 198 may include, for example, solid epoxy resin, phenolic resin, fused silica, crystalline silica, carbon black, and / or metal hydroxide. Such molding compounds are available from, for example, Sumitomo Corp. and Nitto-Denko Corp., both headquartered in Japan. Other encapsulants from other manufacturers are contemplated.

[0065] Return to reference Figures 4-6 In the above embodiment, when forming the CBA memory die 160, the passive surface 105 of the memory die 102 is thinned to expose the deep trench via 134. Thereafter, as described above, microbump pads 108 can be formed on the exposed deep trench via 134. Next, the microbump pads 108 of the corresponding CBA memory die 160 can be physically and electrically coupled, such as... Figure 8As shown, a pair of CBA memory dies 160 are joined face-to-face to form an mDiP 170.

[0066] According to another aspect of the invention, instead of forming microbump pads 108 on the exposed deep trench via 134, Figure 4 Enlarged microbumps 190 or reduced-size microbumps 194 may be formed on the exposed deep trench via 134. In this embodiment, microbumps 190 and / or reduced-size microbumps 194 may be formed on the exposed end of the deep trench via 134, as described above regarding Figures 12-13 and Figures 16-18 As stated above.

[0067] In the above embodiments, backfill vias 190 and 194 are formed on the exposed main planar surface of the mDiP. However, the backfill vias 190 and 194 of the present invention can be used on other types of finished semiconductor devices, including, for example, CBA semiconductor devices and other semiconductor memory devices. It should also be understood that backfill microbumps can be formed on any via of the present invention, whether the via is exposed after wafer thinning or otherwise.

[0068] In summary, one example of the present invention relates to a semiconductor device comprising: a group of one or more semiconductor dies, the first group of one or more semiconductor dies comprising: a memory die; a first main planar surface; a second main planar surface; a first set of vias exposed on the first main planar surface, each via comprising a conductive material and having a concave meniscus on the first main planar surface; and a conductive backfill material backfilling the concave meniscus in each via, the backfill material making each via flush with the first main planar surface.

[0069] In another example, the present invention relates to a mirrored die-pair (mDiP) semiconductor device, the mPIP semiconductor device comprising: a first group of semiconductor dies, the first group of semiconductor dies including: a first memory die; a first CMOS logic circuit die, the first CMOS logic circuit die bonded to the first memory die; a first main planar surface; a second main planar surface opposite to the first main planar surface; and a first set of vias exposed on the first main planar surface, each via comprising a conductive material and having a recess on the first main planar surface. The first group of vias includes: a concave meniscus; and a conductive backfill material that backfills the concave meniscus in each of the vias in the first group, the backfill material making each of the vias in the first group flush with the first master planar surface; and a second group of semiconductor dies bonded to the first group of semiconductor dies, the second group of semiconductor dies including: a second memory die; a second CMOS logic die bonded to the second memory die; a third master planar surface; and a fourth master planar surface opposite the third master planar surface.

[0070] In another example, the present invention relates to a semiconductor device comprising: a group of one or more semiconductor dies, the first group of one or more semiconductor dies comprising: a memory die; a first main planar surface; a second main planar surface; a first set of vias exposed on the first main planar surface, each via comprising a conductive material and having a concave meniscus on the first main planar surface; and a conductive backfilling device for backfilling the concave meniscus in each via and flushing each via with the first main planar surface.

[0071] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in accordance with the foregoing teachings. The described embodiments have been chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and with various modifications suitable for the particular intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A semiconductor device, comprising: A group of one or more semiconductor dies, wherein the first group of one or more semiconductor dies includes: Memory die; First principal flat surface; Second primary flat surface; A first set of vias, the first set of vias exposed at the first main flat surface, each via in the first set of vias comprising a conductive material and having a concave meniscus at the first main flat surface; and A conductive backfill material is used to backfill the concave meniscus in each through-hole, such that each through-hole is flush with the first main flat surface.

2. The semiconductor device of claim 1, wherein the portion of each via comprising the conductive backfill material has an enlarged diameter relative to the remainder of each via.

3. The semiconductor device of claim 1, wherein the portion of each via comprising the conductive backfill material has a trapezoidal shape that narrows toward the first main flat surface.

4. The semiconductor device of claim 1, wherein the portion of each via comprising the conductive backfill material has a diameter matching that of the remainder of each via.

5. The semiconductor device according to claim 1, wherein the backfill material is the same as the conductive material.

6. The semiconductor device of claim 1, wherein the group of one or more semiconductor dies comprises a first group of one or more semiconductor dies, the memory die comprises a first memory die, and the semiconductor device further comprises: Third principal flat surface; Fourth principal flat surface; A second set of through-holes is exposed on the fourth main flat surface, each of the second set of through-holes comprising a conductive material and having a concave meniscus on the fourth main flat surface; and A conductive backfill material is used to backfill the concave meniscus in each of the second set of through holes, such that each of the second set of through holes is flush with the fourth main flat surface.

7. The semiconductor device of claim 6, wherein the first group and the second group of the one or more semiconductor dies are physically coupled and electrically coupled to each other at the second main flat surface and the third main flat surface.

8. The semiconductor device of claim 6, wherein the second primary flat surface and the third primary flat surface include bump pads, the bump pads of the second surface and the third surface being electrically and physically coupled to each other to bond a first group and a second group of the one or more semiconductor dies.

9. The semiconductor device of claim 8, wherein the portion of the first set of vias including the conductive backfill material has an enlarged diameter relative to the remainder of the vias in the first set, and wherein the portion of the second set of vias including the conductive backfill material has an enlarged diameter relative to the remainder of the vias in the second set.

10. The semiconductor device of claim 8, wherein the portion of the first set of vias including the conductive backfill material has an enlarged diameter relative to the remainder of the vias in the first set, and wherein the portion of the second set of vias including the conductive backfill material has a trapezoidal shape that narrows toward the fourth main flat surface.

11. The semiconductor device of claim 8, wherein the portion of the first set of vias including the conductive backfill material has a trapezoidal shape that narrows toward the first main flat surface, and wherein the portion of the second set of vias including the conductive backfill material has a trapezoidal shape that narrows toward the fourth main flat surface.

12. A mirror-image die-pair (mDiP) semiconductor device, comprising: A first group of semiconductor dies, the first group of semiconductor dies comprising: First memory die; The first CMOS logic circuit die is bonded to the first memory die. First principal flat surface; A second main flat surface opposite to the first main flat surface; A first set of vias, the first set of vias exposed at the first main flat surface, each via in the first set of vias comprising a conductive material and having a concave meniscus at the first main flat surface; and A conductive backfill material is used to backfill the concave meniscus of each of the first set of through holes, wherein the backfill material makes each of the first set of through holes flush with the first main flat surface; and A second group of semiconductor dies, the second group of semiconductor dies being bonded to the first group of semiconductor dies, the second group of semiconductor dies comprising: Second memory die; The second CMOS logic circuit die is bonded to the second memory die; The third primary flat surface; and A fourth main flat surface opposite to the third main flat surface.

13. The mDiP semiconductor device of claim 12, wherein the portion of each of the vias in the first set of vias including the conductive backfill material has an enlarged diameter relative to the remainder of each of the vias in the first set of vias.

14. The mDiP semiconductor device of claim 12, wherein the portion of each of the vias in the first set of vias including the conductive backfill material has a trapezoidal shape that narrows toward the first main flat surface.

15. The mDiP semiconductor device of claim 12, wherein the diameter of the portion of each of the vias in the first group of vias including the conductive backfill material matches the diameter of the conductive material in each of the vias in the first group of vias.

16. The mDiP semiconductor device of claim 12, wherein the backfill material is the same as the conductive material.

17. The mDiP semiconductor device according to claim 12, wherein the second set of semiconductor dies further comprises: A second set of through-holes is exposed on the fourth main flat surface, each of the second set of through-holes comprising a conductive material and having a concave meniscus on the fourth main flat surface; and A conductive backfill material is used to backfill the concave meniscus in each of the second set of through holes, such that each of the second set of through holes is flush with the fourth main flat surface.

18. The mDiP semiconductor device of claim 17, wherein the first group and the second group of semiconductor dies are physically and electrically coupled to each other face-to-face at the second surface and the third surface.

19. The mDiP semiconductor device of claim 10, wherein the portions of the first set of vias and the second set of vias including the conductive backfill material have an enlarged diameter relative to the remainder of the first set of vias and the second set of vias, the enlarged diameter vias enhancing the electrical connection between the mDiP semiconductor devices in the stack of the mDiP semiconductor devices.

20. A semiconductor device, comprising: A group of one or more semiconductor dies, wherein a first group of the one or more semiconductor dies includes: Memory die; First principal flat surface; Second primary flat surface; A first set of vias, the first set of vias exposed at the first main flat surface, each via in the first set of vias comprising a conductive material and having a concave meniscus at the first main flat surface; and A conductive backfilling device is used to backfill the concave meniscus in each of the through holes and to make each of the through holes flush with the first main flat surface.

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