Chip package structure with heat dissipation column and manufacturing method thereof

Abstract

This application relates to a chip package structure with heat sinks and its fabrication method. The fabrication method of the chip package structure with heat sinks includes: providing a temporary substrate and forming multiple heat sinks on the temporary substrate; providing a chip and a support plate, and flip-chipping the chip onto the support plate; bonding the multiple heat sinks formed on the temporary substrate to the back side of the chip; and removing the temporary substrate. In the above-described fabrication method of the chip package structure with heat sinks, by forming the heat sinks using a temporary substrate and then bonding them to the back side of the chip, it is possible to form heat sinks in a specified arrangement on the back side of the chip as needed, and to prevent the heat sinks from tilting or shifting, thereby ensuring good heat dissipation. Simultaneously, since the heat sinks are formed only on the back side of the chip, the structure is relatively simple and the volume is relatively small.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure with heat sinks and its fabrication method. Background Technology

[0002] As the chip industry places increasingly stringent demands on product reliability, heat dissipation of the package (such as chip packaging structure) has become a key bottleneck restricting performance, making innovation in heat dissipation technology crucial.

[0003] However, current packages typically incorporate additional auxiliary heat dissipation structures to improve heat dissipation performance. However, packages with auxiliary heat dissipation structures generally suffer from problems such as complex structure, large size, and poor heat dissipation effect. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip packaging structure with heat dissipation pillars and its fabrication method to address the technical problems mentioned above.

[0005] In a first aspect, this application provides a method for fabricating a chip package structure with heat dissipation pillars, the method comprising:

[0006] A temporary base is provided, and multiple heat dissipation columns are formed on the temporary base;

[0007] A chip and a support board are provided, and the chip is flip-mounted onto the support board;

[0008] The multiple heat dissipation pillars formed on the temporary base are bonded to the back of the chip;

[0009] Remove the temporary base.

[0010] In the above-mentioned method for fabricating a chip package structure with heat sinks, after forming heat sinks with the help of a temporary base, the heat sinks are then bonded to the back of the chip. This allows for the formation of heat sinks in a specified arrangement on the back of the chip as needed, while also preventing the heat sinks from tilting or shifting, thus ensuring a good heat dissipation effect. At the same time, since the heat sinks are formed only on the back of the chip, the structure is relatively simple and the volume is relatively small.

[0011] In some embodiments, the provided temporary base has a plurality of insertion holes, including blind holes or through holes; forming a plurality of heat dissipation pillars on the temporary base includes:

[0012] Each of the heat dissipation columns is inserted into the corresponding socket.

[0013] In some embodiments, a temporary base is provided, and a plurality of heat dissipation columns are formed on the temporary base, including:

[0014] Provide a temporary base;

[0015] A sacrificial layer is formed on the temporary base;

[0016] Multiple heat dissipation columns are formed on the surface of the sacrificial layer away from the temporary base.

[0017] In some embodiments, the sacrificial layer includes a photolysis layer; removing the temporary substrate includes: removing the photolysis layer using a photolithography process to remove the temporary substrate; or

[0018] The sacrificial layer includes a hydrolysis layer; removing the temporary base includes: using a water washing process to remove the hydrolysis layer to remove the temporary base.

[0019] In some embodiments, multiple heat dissipation pillars are formed on the temporary base, including:

[0020] Multiple transfer bases are provided, and the area of ​​each transfer base is smaller than the area of ​​the temporary base;

[0021] Multiple heat dissipation columns are formed on each of the aforementioned transfer bases;

[0022] The heat dissipation columns on multiple transfer bases are transferred in batches to the temporary base.

[0023] In some embodiments, a plurality of heat sinks formed on the temporary base are bonded to the back side of the chip, including:

[0024] The multiple heat dissipation pillars formed on the temporary base are attached to the back of the chip via solder;

[0025] The solder is reflow soldered to bond the heat sink to the back of the chip.

[0026] In some embodiments, the heat sinks comprise copper pillars; prior to bonding the plurality of heat sinks formed on the temporary base to the back side of the chip, the method further includes:

[0027] A metal plating layer is formed on the back side of the chip;

[0028] Bonding the plurality of heat dissipation pillars formed on the temporary base to the back side of the chip includes: bonding the plurality of heat dissipation pillars formed on the temporary base to the surface of the metal plating away from the chip.

[0029] In some embodiments, after the heat sink is bonded to the back of the chip, the heat sink is perpendicular to the back of the chip.

[0030] In some embodiments, the support plate includes a substrate, a redistribution layer, or an interposer.

[0031] Secondly, this application also provides a chip packaging structure with heat sinks, which is prepared by the method for preparing a chip packaging structure with heat sinks as described in the first aspect. Attached Figure Description

[0032] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0033] Figure 1 This is a flowchart illustrating a method for fabricating a chip packaging structure with heat dissipation pillars according to an embodiment of this application.

[0034] Figure 2 This is a cross-sectional schematic diagram of the structure obtained in step S11 of the method for preparing a chip packaging structure with heat dissipation pillars provided in one embodiment of this application.

[0035] Figure 3 This is a schematic cross-sectional view of a chip with a heat sink provided in one embodiment of the present application, which has a metal plating layer, a dielectric layer, an interconnect structure, a metal block and solder balls.

[0036] Figure 4 This is a cross-sectional schematic diagram of the structure obtained in step S12 of the method for preparing a chip packaging structure with heat dissipation pillars provided in one embodiment of this application.

[0037] Figure 5 This is a cross-sectional schematic diagram of the structure obtained in step S13 of the method for preparing a chip packaging structure with heat dissipation pillars provided in one embodiment of this application.

[0038] Figure 6 This is a cross-sectional schematic diagram of the structure obtained in step S14 of the method for preparing a chip packaging structure with heat dissipation pillars provided in one embodiment of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 10. Temporary base; 11. Heat sink; 12. Support plate; 13. Chip; 14. First solder; 15. Metal plating; 16. Dielectric layer; 17. Interconnect structure; 18. Metal block; 19. Solder ball; 20. Second solder. Detailed Implementation

[0041] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.

[0047] In one embodiment, see Figure 1 This application provides a method for fabricating a chip package structure with heat dissipation pillars, which may include the following steps: S11~S14.

[0048] S11: Provides a temporary base and forms multiple heat dissipation columns on the temporary base.

[0049] S12: Provides the chip and support board, and flips the chip onto the support board.

[0050] S13: Multiple heat dissipation pillars formed on the temporary base are bonded to the back of the chip.

[0051] S14: Remove the temporary base.

[0052] In the above-mentioned method for fabricating a chip package structure with heat sinks, after forming heat sinks with the help of a temporary base, the heat sinks are then bonded to the back of the chip. This allows for the formation of heat sinks in a specified arrangement on the back of the chip as needed, while also preventing the heat sinks from tilting or shifting, thus ensuring a good heat dissipation effect. At the same time, since the heat sinks are formed only on the back of the chip, the structure is relatively simple and the volume is relatively small.

[0053] In one example, see Figure 2In step S11, the temporary base 10 provided may have multiple sockets (not shown), which may include blind holes or through holes; forming multiple heat dissipation columns 11 on the temporary base 10 may include: inserting the multiple heat dissipation columns 11 into each socket one by one.

[0054] Specifically, when the socket is a blind hole, the heat sink 11 can be inserted to the bottom of the blind hole; when the socket is a through hole, after the heat sink 11 is inserted into the socket, it should avoid penetrating the socket, i.e., ... Figure 2 For example, after the heat sink 11 is inserted into the socket, the heat sink 11 should not extend above the temporary base 10.

[0055] As an example, the number and arrangement of sockets can be set according to actual needs. For instance, sockets can be arranged in a multi-row, multi-column array.

[0056] As an example, temporary base 10 may include, but is not limited to, a high-temperature resistant base (Socket), such as a metal base, a glass base, a ceramic base, or a semiconductor base (e.g., a silicon base, a silicon carbide base, a gallium nitride base, etc.).

[0057] As an example, both the cross-sectional area of ​​the socket and the cross-sectional area of ​​the heat sink 11 can be circular; the diameter of the socket can be slightly larger than the size of the heat sink 11. The inner wall of the socket can be coated with a coating layer, which may include, but is not limited to, a hydrolyzed layer or a heat-melting layer. When the heat sink 11 is inserted into the socket, the coating layer can be located between the heat sink 11 and the inner wall of the socket. The coating layer can completely cover the inner wall of the socket.

[0058] It should be noted that when the sidewall of the socket is coated with a coating layer, the size of the inner hole of the coating layer should not be less than the size of the heat dissipation column 11, so as to ensure that the heat dissipation column 11 can be inserted into the socket with the inner wall coated with the coating layer.

[0059] In another example, please refer to [link / reference]. Figure 2 In step S11, a temporary base 10 is provided, and a plurality of heat dissipation columns 11 are formed on the temporary base 10. This may include the following steps: S111~S113.

[0060] S111: Provides temporary base 10.

[0061] S112: A sacrificial layer (not shown) is formed on the temporary base 10; specifically, a coating process or deposition process may be used to form the sacrificial layer on the surface of the temporary base 10; the thickness of the sacrificial layer can be set according to actual needs. The sacrificial layer may cover the entire surface of the temporary base 10, or it may be formed only in the area where the heat dissipation pillar 11 needs to be formed.

[0062] S113: Multiple heat dissipation columns 11 are formed on the surface of the sacrificial layer away from the temporary base 10.

[0063] As an example, in step S111, the temporary base 10 may include, but is not limited to, a high-temperature resistant base (Socket), such as a metal base, a glass base, a ceramic base, or a semiconductor base (such as a silicon base, a silicon carbide base, a gallium nitride base, etc.).

[0064] In one example, in step S112, the sacrificial layer may include, but is not limited to, a photolysis layer; specifically, the photolysis layer may include, but is not limited to, an ultraviolet photolysis layer, a laser photolysis layer, or other photolysis layers that can be applied here.

[0065] In another example, in step S112, the sacrificial layer may include, but is not limited to, a hydrolysis layer; specifically, the hydrolysis layer may be any existing material layer that can be applied here and is removable by washing with water.

[0066] Of course, in other examples, the sacrificial layer can also be an adhesive layer that can be removed by processes such as peeling. The adhesion force between the adhesive layer and the temporary substrate 10 is much less than the bonding force between the subsequent heat sink 11 and the back of the chip 13.

[0067] In one example, in step S113, multiple heat dissipation pillars 11 can be transferred one by one to the surface of the sacrificial layer away from the temporary base 10.

[0068] In another example, step S113, forming multiple heat dissipation pillars 11 on the temporary base 10, may include the following: providing multiple transfer bases (not shown), each with an area smaller than that of the temporary base 10; forming multiple heat dissipation pillars 11 on each transfer base; and batch transferring the heat dissipation pillars 11 from the multiple transfer bases to the temporary base 10. By first forming heat dissipation pillars 11 on each small transfer base, and then batch transferring the heat dissipation pillars 11 from the multiple small transfer bases to the temporary base 10 once or multiple times, modular operation can be achieved, significantly improving the transfer efficiency of the heat dissipation pillars 11. Of course, in other examples, the heat dissipation pillars 11 on a small transfer base can also be transferred to the temporary base 10 at a time. For the specific method of forming multiple heat dissipation pillars 11 on each transfer base, please refer to the specific method of forming multiple heat dissipation pillars 11 on the temporary base 10 described above, which will not be repeated here.

[0069] As an example, in step S113, the heat dissipation column 11 may, but is not limited to, have one end attached to the surface of the sacrificial layer away from the temporary base 10 via an adhesive layer (not shown).

[0070] As an example, the multiple heat dissipation columns 11 formed on the temporary base 10 can all be perpendicular to the surface of the temporary base 10, and each heat dissipation column 11 can be arranged in parallel at intervals.

[0071] For example, please refer to Figure 3 The chip 13 provided in step S12 may include, but is not limited to, a silicon chip; the chip 13 may be a chip with functional devices formed inside, such as a photonic chip, an electronic chip, or other functional chips, etc.

[0072] As an example, in step S12, please refer to... Figure 3 After providing chip 13, the following may also be included: forming a metal plating layer 15 on the back side of chip 13. The metal plating layer 15 may include a metal plating layer containing Ti; specifically, the metal plating layer 15 may be a Ti / Cu plating layer. The metal plating layer 15 ensures the adhesion between the heat sink 11 and the back side of chip 13 in subsequent steps, preventing metal ions in the heat sink 11 from diffusing into chip 13. Specifically, the metal plating layer can be formed on the back side of chip 13 using, but is not limited to, sputtering processes. The thickness of the metal plating layer 15 can be set according to actual needs and is not specifically limited here.

[0073] As an example, in step S12, please refer to... Figure 3 After providing chip 13, the following may also be included: forming a dielectric layer 16 on the front side of chip 13; forming interconnect holes (not shown) in the dielectric layer 16; forming a metal block 18 on the surface of the dielectric layer 16 away from chip 13, and forming an interconnect structure 17 in the interconnect hole, the interconnect structure being electrically connected to both chip 13 and metal block 18; forming solder balls 19 on the surface of the metal block 18 away from dielectric layer 16.

[0074] As an example, a dielectric layer 16 may be formed on the front side of the chip 13 using, but not limited to, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes; the dielectric layer 16 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, etc.

[0075] As an example, interconnect holes can be formed in the dielectric layer 16 using, but not limited to, photolithography etching processes. The interconnect holes can penetrate the dielectric layer 16 along the thickness direction. The longitudinal cross-sectional shape of the interconnect holes can include rectangular or inverted trapezoidal shapes, etc.

[0076] As an example, forming a metal block 18 on the surface of the dielectric layer 16 away from the chip 13 and forming an interconnect structure 17 within an interconnect hole can include the following: forming a metal material layer (not shown) on the surface of the dielectric layer 16 away from the chip 13 and within the interconnect hole, the metal material layer within the interconnect hole being the interconnect structure 17; and patterning the metal material layer on the surface of the dielectric layer 16 away from the chip 13 using a photolithography etching process to obtain the metal block 18. The materials of the metal block 18 and the interconnect structure 17 can include, but are not limited to, copper.

[0077] As an example, the number of metal blocks 18, interconnect structures 17 and solder balls 19 can all be multiple and the same, and the metal blocks 18, interconnect structures 17 and solder balls 19 can be set one-to-one.

[0078] As an example, the material of solder ball 19 may include, but is not limited to, tin.

[0079] For example, please refer to Figure 4 In step S12, flip-chip 13 is flip-chip bonded onto support plate 12, which may include the following: forming a second solder 20 on the surface of support plate 12; flip-chip 13 with solder balls 19 formed thereon is flip-chip bonded onto support plate 12 via the second solder 20; after bonding, the solder balls 19 are in contact with the second solder 20. Specifically, the solder balls 19 and the second solder 20 can be bonded together using, but not limited to, reflow soldering, thermo-ultrasonic bonding, thermo-ultrasonic bonding, laser welding, or ultrasonic welding processes.

[0080] As an example, there can be multiple second solders 20, which can be formed on the surface of the support plate 12 using, but not limited to, spot welding processes. The second solders 20 can include any existing solder applicable here, such as tin solder. The number of second solders 20 can be the same as the number of solder balls 19, and each second solder 20 can be arranged in a one-to-one correspondence with a solder ball 19. Of course, besides the above-mentioned second solders 20 being multiple isolated dot structures, in other examples, the second solders 20 formed on the surface of the support plate 12 can also be a single, layered structure.

[0081] As an example, please continue reading Figure 2 After forming multiple heat dissipation pillars 11 on the temporary base 10, a first solder 14 needs to be formed on the surface of the heat dissipation pillars 11 away from the temporary base 10. Specifically, the first solder 14 can be provided at the end of each heat dissipation pillar 11 away from the temporary base 10; more specifically, the first solder 14 can be formed at the end of the heat dissipation pillar 11 away from the temporary base 10 by a process that is not limited to spot welding.

[0082] As an example, the first solder 14 can be any existing solder that can be applied here, such as tin solder, etc.

[0083] For example, please refer to Figure 5 In step S13, multiple heat dissipation pillars 11 formed on the temporary base 10 are bonded to the back of the chip 13, including the following steps: S131~S132.

[0084] S131: Multiple heat dissipation pillars 11 formed on the temporary base 10 are attached to the back of the chip 13 via solder (i.e., first solder 14).

[0085] S132: Reflow soldering is performed on the solder to bond the heat sink 11 to the back side of the chip 13. Specifically, high-temperature reflow soldering can be performed on the solder to fix the heat sink 11 to one side of the back of the chip 13. The high-temperature reflow soldering process can be set according to actual needs, as long as it ensures that the first solder 14 can soften to solder and fix the heat sink 11 to the chip 13. Of course, after the high-temperature reflow soldering process, the resulting structure needs to be cooled to room temperature.

[0086] Of course, in other examples, the heat sink 11 can also be bonded to the back of the chip 13 using other bonding or fixing processes.

[0087] It should be noted that when a metal plating layer 15 is formed on the back side of the chip 13, a plurality of heat sink pillars 11 formed on the temporary base 10 are bonded to the back side of the chip 13, including: bonding a plurality of heat sink pillars 11 formed on the temporary base 10 to the surface of the metal plating layer 15 away from the chip 13.

[0088] As an example, the heat sink 11 may include a copper sink. Of course, in other examples, the heat sink 11 may also be other metal sinks with good heat dissipation performance.

[0089] As an example, each heat sink 11 can have the same width to facilitate efficient batch processing. Of course, in other examples, the widths of the multiple heat sinks 11 may not be exactly the same.

[0090] As an example, after the heat sink 11 is bonded to the back of the chip 13, the heat sink 11 is perpendicular to the back of the chip 13.

[0091] As an example, the support plate 12 may include, but is not limited to, a substrate, a redistribution layer, or an interposer, etc.

[0092] For example, please refer to Figure 6In step S14, when a hydrolytic layer or a thermally melted layer forms on the inner wall of the socket, the hydrolytic layer or thermally melted layer can be removed by heating or washing to release the heat sink 11 and the temporary base 10, allowing the temporary base 10 to separate from the heat sink 11 and be removed. Through this method, the temporary base 10 can be easily removed without using significant external force, avoiding loosening of the solder between the heat sink 11 and the chip due to excessive external force, thus ensuring that the heat sink 11 can be firmly fixed to the back of the chip.

[0093] As an example, when a sacrificial layer is formed on the surface of the temporary base 10, if the sacrificial layer is a photolytic layer, the method for removing the temporary base 10 in step S14 may include: using a photo-irradiation process to remove the photolytic layer to remove the temporary base 10. If the sacrificial layer is a hydrolytic layer, the method for removing the temporary base 10 in step S14 may include: using a water washing process to remove the hydrolytic layer to remove the temporary base 10. If the sacrificial layer is an adhesive layer, the adhesive layer and the temporary base 10 can be removed by a peeling or other process.

[0094] As an example, the fabrication method of a chip package structure with heat sinks may further include the following steps: a forced heat exchange device is disposed on the support plate 12, the forced heat exchange device being used to force heat exchange on the heat sinks 11. Specifically, the forced heat exchange device may include, but is not limited to, a fan, with the fan's outlet facing the heat sinks 11 to ensure that the air blown by the fan can pass over the heat sinks 11, thereby quickly removing the heat transferred from the heat sinks 11 to achieve rapid heat dissipation.

[0095] Unless otherwise expressly stated herein, the execution order of these steps in the fabrication method of the chip package structure with heat sink pillars in the above embodiments is not strictly limited, and these steps can be executed in other orders. Moreover, at least some steps in the method may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0096] The fabrication method of the chip package structure with heat sink pillars in the above embodiments is intended to illustrate the formation principle of the chip package structure with heat sink pillars in the embodiments of this application, and is not intended to limit the specific limitations of the chip package structure with heat sink pillars in the embodiments of this application. Other fabrication methods can also be used to fabricate the chip package structure with heat sink pillars in the embodiments of this application.

[0097] In another embodiment, please refer to Figures 1 to 5 Continue reading Figure 6This application also provides a chip packaging structure with heat sinks, which may include: a support plate 12, a chip 13 and heat sinks 11; the chip 13 is flip-chip bonded to the support plate 12; the heat sinks 11 are located on the back side of the chip 13.

[0098] The chip packaging structure with heat sinks in this application can be based on, for example... Figures 1 to 6 The chip is prepared by the preparation method described in the corresponding embodiment. In the above-mentioned chip packaging structure with heat sink pillars, after the heat sink pillars are formed with the help of a temporary base, the heat sink pillars are then bonded to the back side of the chip. This allows for the formation of heat sink pillars in a specified arrangement on the back side of the chip as needed, and also prevents the heat sink pillars from tilting or shifting, thereby ensuring a good heat dissipation effect. At the same time, since the heat sink pillars are only formed on the back side of the chip, the structure is relatively simple and the volume is relatively small.

[0099] As an example, chip 13 may include, but is not limited to, silicon chips; chip 13 may be a chip with functional devices formed inside, such as photonic chips, electronic chips, or other functional chips, etc.

[0100] As an example, a metal plating layer 15 is also formed on the back side of the chip 13, and a first solder 14 is provided between the metal plating layer 15 and the heat sink 11. The heat sink 11 is fixed to the surface of the metal plating layer 15 away from the chip 13 via the first solder 14.

[0101] Specifically, the metal plating 15 can be a Ti / Cu plating. The metal plating 15 can ensure the adhesion between the heat sink 11 and the back of the chip 13 in subsequent steps and prevent metal ions in the heat sink 11 from diffusing into the chip 13.

[0102] As an example, the first solder 14 can be any existing solder that can be applied here, such as tin solder, etc.

[0103] As an example, a dielectric layer 16 is also formed on the front side of the chip 13, an interconnect structure 17 is formed in the dielectric layer 16, and a metal block 18 is formed on the surface of the dielectric layer 16 away from the chip 13; solder balls 19 are formed on the surface of the metal block 18 away from the dielectric layer 16.

[0104] As an example, dielectric layer 16 may include, but is not limited to, silicon oxide layer, silicon nitride layer, or silicon oxynitride layer, etc.

[0105] As an example, the materials of the metal block 18 and the interconnect structure 17 may include, but are not limited to, copper.

[0106] As an example, the number of metal blocks 18, interconnect structures 17 and solder balls 19 can all be multiple and the same, and the metal blocks 18, interconnect structures 17 and solder balls 19 can be set one-to-one.

[0107] As an example, the material of solder ball 19 may include, but is not limited to, tin.

[0108] As an example, a second solder 20 is also provided between the solder ball 19 and the support plate 12, and the solder ball 19 is in contact with the second solder 20.

[0109] As an example, there can be multiple second solders 20; the second solders 20 can include any existing solder that can be applied here, such as tin solder, etc. The number of second solders 20 can be the same as the number of solder balls 19, and the second solders 20 can be set in a one-to-one correspondence with the solder balls 19.

[0110] As an example, the heat sink 11 may include a copper sink. Of course, in other examples, the heat sink 11 may also be other metal sinks with good heat dissipation performance.

[0111] As an example, each heat sink 11 can have the same width to facilitate efficient batch processing. Of course, in other examples, the widths of the multiple heat sinks 11 may not be exactly the same.

[0112] As an example, heat sink 11 is perpendicular to the back of chip 13.

[0113] As an example, the support plate 12 may include, but is not limited to, a substrate, a redistribution layer, or an interposer, etc.

[0114] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0115] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a chip packaging structure with heat dissipation pillars, characterized in that, include: A temporary base is provided, and multiple heat dissipation columns are formed on the temporary base; A chip and a support board are provided, and the chip is flip-mounted onto the support board; The multiple heat dissipation pillars formed on the temporary base are bonded to the back of the chip; Remove the temporary base.

2. The method for fabricating a chip packaging structure with heat dissipation pillars according to claim 1, characterized in that, The provided temporary base has a plurality of insertion holes formed thereon, the insertion holes including blind holes or through holes; Forming multiple heat dissipation columns on the temporary base includes: Each of the heat dissipation columns is inserted into the corresponding socket.

3. The method for fabricating a chip packaging structure with heat dissipation pillars according to claim 1, characterized in that, A temporary base is provided, and multiple heat dissipation columns are formed on the temporary base, including: Provide a temporary base; A sacrificial layer is formed on the temporary base; Multiple heat dissipation columns are formed on the surface of the sacrificial layer away from the temporary base.

4. The method for fabricating a chip packaging structure with heat dissipation pillars according to claim 3, characterized in that, The sacrificial layer includes a photolysis layer; Removing the temporary base includes: using a photolithography process to remove the photolysis layer to remove the temporary base; or The sacrificial layer includes a hydrolysis layer; removing the temporary base includes: using a water washing process to remove the hydrolysis layer to remove the temporary base.

5. The method for fabricating a chip packaging structure with heat dissipation pillars according to claim 1, characterized in that, Multiple heat dissipation columns are formed on the temporary base, including: Multiple transfer bases are provided, and the area of ​​each transfer base is smaller than the area of ​​the temporary base; Multiple heat dissipation columns are formed on each of the aforementioned transfer bases; The heat dissipation columns on multiple transfer bases are transferred in batches to the temporary base.

6. The method for fabricating a chip packaging structure with heat dissipation pillars according to claim 1, characterized in that, The plurality of heat dissipation pillars formed on the temporary base are bonded to the back side of the chip, including: The multiple heat dissipation pillars formed on the temporary base are attached to the back of the chip via solder; The solder is reflow soldered to bond the heat sink to the back of the chip.

7. The method for fabricating a chip packaging structure with heat dissipation pillars according to claim 1, characterized in that, The heat sink pillars include copper pillars; before bonding the plurality of heat sink pillars formed on the temporary base to the back side of the chip, the method further includes: A metal plating layer is formed on the back side of the chip; Bonding the plurality of heat dissipation pillars formed on the temporary base to the back side of the chip includes: bonding the plurality of heat dissipation pillars formed on the temporary base to the surface of the metal plating away from the chip.

8. The method for fabricating a chip packaging structure with heat dissipation pillars according to claim 1, characterized in that, After the heat sink is bonded to the back of the chip, the heat sink is perpendicular to the back of the chip.

9. The method for fabricating a chip packaging structure with heat dissipation pillars according to claim 1, characterized in that, The support plate includes a substrate, a redistribution layer, or an interposer.

10. A chip packaging structure with heat dissipation pillars, characterized in that, The chip package structure with heat dissipation pillars is prepared by the preparation method described in any one of claims 1 to 9.

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