A multi-chip wafer level package structure with enhanced heat dissipation and high isolation characteristics

Abstract

This invention relates to a multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics. It includes: an EMC molding compound containing multiple chips, each chip having a eutectic solder layer, a MoCu heat sink, and a back RDL metallization layer sequentially arranged on its back side; TMV copper pillars distributed in a matrix around each chip to form a TMV array; the TMV array is a double-layer, horizontally arranged matrix; and a front RDL metal interconnect layer, where the MoCu heat sink is connected to the back side of the TMV copper pillars via the back RDL metallization layer. The front ground pad and front signal pad of each chip are fanned out through the front RDL metal interconnect layer to the corresponding BGA ground and BGA signal pads. This invention solves the problem in the prior art where heat dissipation and electromagnetic compatibility bottlenecks are mutually constrained and cannot be optimized collaboratively under rigid size constraints.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency microsystem packaging technology, and specifically relates to a multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics. Specifically, it relates to a multi-chip fan-out wafer-level package (FOWLP) for radio frequency power chips, which has integrated collaborative design capabilities for chip heat dissipation, radio frequency grounding and electromagnetic isolation. Background Technology

[0002] Advanced packaged microsystems are currently developing towards miniaturization, high integration, high frequency, and high power density. Wafer-level packaging (WLP) has become one of the important choices in the field of multi-chip microsystem packaging due to its significant advantages in miniaturization, high-frequency performance, cost, and efficiency. Especially in the radio frequency and microwave bands, multi-chip fan-out wafer-level packaging (FOWLP) can achieve high-density three-dimensional interconnects and fan-out wiring by embedding multiple chips into an epoxy molding compound (EMC) substrate and supplementing it with redistribution layer (RDL) technology.

[0003] However, with increasing integration and frequency, near-field crosstalk and heat dissipation issues within the package have become increasingly prominent, and these two factors mutually constrain each other, becoming key bottlenecks restricting the performance and reliability of RF multi-chip microsystems. Regarding heat dissipation, the FOWLP structure embeds the chip in EMC material with extremely low thermal conductivity (approximately 1 W / m·K), severely hindering heat conduction and causing heat accumulation, thus leading to the risk of thermal failure. Although back-side thinning technology can reduce longitudinal thermal resistance, excessive thinning significantly increases the risk of wafer warpage. Therefore, the body thickness of wafer-level packages is typically limited to no less than 280 μm. Furthermore, since RF microsystems are primarily used in mobile terminals, portable devices, and other applications sensitive to size and weight, the miniaturization requirements impose strict upper limits on package thickness—currently, the thickness of mass-produced FOWLPs is typically limited to the range of 300 μm to 400 μm, prohibiting significant increases in package thickness. Under these dual constraints (i.e., a lower limit of 280 μm for warpage resistance and an upper limit of approximately 400 μm for miniaturization), the traditional approach of reducing thermal resistance by shortening the heat propagation distance is severely limited. In terms of electromagnetic compatibility (EMC), for wafer-level packaging in the RF and microwave bands, near-field coupling and crosstalk between multiple chips can lead to performance degradation or even functional failure. In traditional packaging, the grounding path of RF chips typically relies solely on the front-side ground pad, reaching the system reference ground after multiple interconnections via RDL, TMV, and BGA. This single path can be equivalent to a series parasitic inductance, and the introduced grounding impedance increases linearly with frequency, resulting in a decrease in effective transconductance, deterioration of power gain, and a deterioration of stability factor. Furthermore, existing packages lack effective inter-chip electromagnetic shielding structures. While traditional metal shields can suppress crosstalk to some extent, they significantly increase package thickness and weight, and the shielding body is often a floating conductor with a potential difference between it and the RF reference ground, failing to fundamentally suppress common-mode noise coupling.

[0004] In summary, existing wafer-level packaging structures have the following technical shortcomings: ① Existing FOWLP heat dissipation paths heavily rely on low thermal conductivity EMC materials (thermal conductivity of about 1 W / m·K), resulting in extremely high junction thermal resistance. Although thinning the back side can reduce longitudinal thermal resistance, excessive thinning will significantly increase the risk of wafer warpage. Therefore, the thickness of the package body is usually limited to 280μm~400μm, making it difficult to achieve efficient heat dissipation while maintaining structural reliability.

[0005] ② The existing package grounding path is singular, relying solely on the traditional path from the front RDL fan-out to the BGA. This path has a large equivalent series parasitic inductance, which leads to significant fluctuations in the RF reference ground potential at high frequencies (such as above 20GHz), thereby deteriorating the power gain, effective transconductance, and circuit stability factor (k-factor).

[0006] ③ Existing packaging lacks integrated inter-chip electromagnetic shielding structures, resulting in severe near-field coupling and crosstalk between multiple chips. Isolation deteriorates with increasing frequency, making it difficult to meet electromagnetic compatibility requirements for frequency bands above 20GHz.

[0007] ④ The existing heat dissipation structure and grounding design are independent of each other, and the functions of heat conduction channel and low impedance grounding channel are not reused, resulting in low internal space utilization and high interconnection complexity.

[0008] ⑤ Existing packaging shielding structures are mostly floating conductors, or require the introduction of additional metal shielding covers, which not only increases the packaging thickness and process cost, but also cannot eliminate common-mode noise coupling caused by the potential difference between the shield and the ground plane.

[0009] ⑥ Under the rigid constraint of existing package body thickness of 280μm~400μm, it is impossible to achieve synergistic optimization of reducing the thermal resistance of the junction by orders of magnitude and significantly improving the electromagnetic isolation between chips. Summary of the Invention

[0010] The purpose of this invention is to provide a multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics. This invention aims to solve the problems of severe near-field crosstalk between chips, insufficient isolation, and common-mode noise coupling caused by floating shields in existing technologies. Under the rigid constraint of a package body thickness of 280μm~400μm and without introducing an additional metal shield, this invention achieves a reduction in junction-to-case thermal resistance to 1.2% of that of traditional structures and a chip-to-chip isolation of ≥80dB in the 20~30GHz frequency band through integrated collaborative design. This solves the problem of mutual constraints between heat dissipation and electromagnetic compatibility bottlenecks in existing technologies, which prevent collaborative optimization under rigid size constraints.

[0011] To address the aforementioned technical problems, this invention provides a multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics, comprising: An EMC molded package contains multiple chips, and each chip has a eutectic solder layer, a MoCu heat sink, and a back RDL metallization layer arranged sequentially on its back side. TMV copper pillars are arranged in a matrix around each chip to form a TMV array; the TMV array is a double-layered horizontally arranged matrix. The front RDL metal interconnect layer connects the MoCu heat sink to the back of the TMV copper pillar through the back RDL metallization layer. The front ground pad and front signal pad of each chip are fanned out to the corresponding BGA ground ball and BGA signal ball through the front RDL metal interconnect layer. At the same time, the front of the TMV copper pillar is at the same potential as the BGA ground ball through the front RDL metal interconnect layer, forming an active ground shield at the same potential as the RF reference ground, so that the TMV array is equivalent to a Faraday-like shield when the periodic condition is met.

[0012] Preferably, the plurality of chips are GaN RF power chips, and the back side of the package structure is connected to an external heat sink via a thermal interface material (TIM).

[0013] Preferably, the eutectic solder layer is made of Au80Sn20 material with a thickness of 50μm.

[0014] Preferably, the thickness of the MoCu heat sink is 145 μm and the thermal conductivity is 180 W / m·K.

[0015] Preferably, the TMV array, when satisfying the periodic condition, is equivalent to a Faraday-like shielding wall, including: p≤λ / 10, where p represents the period, i.e., the center-to-center distance between every two adjacent TMV copper pillars, and λ represents the wavelength corresponding to the chip's operating frequency band.

[0016] Preferably, the center spacing is adjusted according to the radio frequency band to adapt to the requirements of multiple frequency bands, forming a "fully enclosed" electromagnetic isolation environment, so that the packaging structure has high isolation characteristics.

[0017] Preferably, the diameter of the TMV copper pillar is 150 μm, and the center-to-center distance between any two adjacent TMV copper pillars is 400 μm.

[0018] Preferably, the thickness of the back RDL metallization layer is 5 μm and the thermal conductivity is 380 W / m·K.

[0019] Preferably, the MoCu heat sink serves as both a high thermal conductivity heat dissipation medium and a low resistivity ground electrode to construct a low-inductive first grounding path from the back of the chip to the BGA grounding solder ball, achieving functional reuse of the heat conduction channel and the low-impedance grounding channel; at the same time, the front RDL metal interconnect layer serves as a second grounding path and is connected in parallel with the first grounding path to significantly reduce the equivalent ground inductance, thereby suppressing RF reference ground potential fluctuations.

[0020] Preferably, the back RDL metallization layer, the MoCu heat sink, the eutectic solder layer, the TMV copper pillars, and the front ground pads and BGA ground balls of the chip work together to form independent metal grounding shield cavities between each chip and achieve an order-of-magnitude reduction in junction-to-case thermal resistance. The conventional shielding gaps on the sides of the metal grounding shield cavity are TMV center-to-center spacing p. To meet the signal line requirements of the power chip, each metal grounding shield cavity has two leakage gaps of 2p at the signal input and output ports. The metal grounding shield cavity suppresses near-field coupling crosstalk in the 20GHz~30GHz frequency band, ensuring an electromagnetic isolation of ≥80dB between chips.

[0021] Compared with the prior art, the present invention has the following beneficial effects: This invention replaces the low thermal conductivity EMC material in the traditional structure with a MoCu heat sink, reducing the junction-to-case thermal resistance to 1.2% of the traditional structure. While maintaining the package thickness, it overcomes the heat dissipation limitations caused by the low thermal conductivity of EMC. Multi-chip simulations show that the surface temperature of each chip in the new structure is approximately half that of the corresponding chip in the traditional structure, and temperature uniformity is significantly improved. A dual-ground architecture with a heat dissipation-grounding path reuse is constructed. The first low-inductance back ground path is connected in parallel with the second traditional front ground path. Based on the parallel inductance formula, the equivalent ground inductance is significantly reduced, thereby suppressing RF reference ground potential fluctuations and improving power gain and circuit stability factor. An active ground shield cavity is constructed using a TMV array, achieving chip-to-chip isolation of ≥83dB in the 20~30GHz operating frequency band, an improvement of over 50dB compared to the traditional structure, effectively suppressing near-field coupling crosstalk between multiple chips. The MoCu heatsink serves the dual function of a high thermal conductivity heat dissipation medium and a low impedance ground electrode, while the TMV array serves the dual function of vertical interconnect and electromagnetic shielding. This achieves functional reuse of the heat conduction channel and the low impedance grounding channel, improving the internal space utilization of the package and reducing interconnect complexity. The back of the TMV array is shorted to the back ground network of the chip (MoCu heatsink), and the front is at the same potential as the BGA ground pad, forming a non-floating active ground shield at the same potential as the RF reference ground. This fundamentally eliminates the potential difference between the shield and the ground plane, suppresses common-mode noise coupling, and eliminates the need for an additional metal shield. Under the rigid constraints of not increasing package thickness and not introducing an additional shield, this invention achieves an order-of-magnitude reduction in junction-to-case thermal resistance (down to 1.2% of the traditional level) and a significant improvement in inter-chip electromagnetic isolation (≥80dB) through integrated co-design, providing a scalable solution for next-generation high power density, high-frequency multi-chip microsystem packaging.

[0022] Furthermore, the simulation results of both single-chip and multi-chip models of this invention show that the error between the theoretical calculation of thermal resistance and the numerical simulation is controlled within 2%, which verifies the accuracy of the established thermal conduction model and electromagnetic shielding model. Attached Figure Description

[0023] Figure 1 This is an overall cross-sectional view of a multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics provided by the present invention.

[0024] Figure 2 A top sectional view of the power chip port is provided for this invention.

[0025] Figure 3 This is a comparison diagram of the thermal resistance paths of a traditional packaging structure and the packaging structure provided by this invention.

[0026] Figure 4 The figure shows a comparison of simulation verification results between the single-chip package provided by this invention and the traditional single-chip package when the single chip is working.

[0027] Figure 5 A comparison diagram of the simulated chip temperature distribution structure between the multi-chip package provided by this invention and the traditional multi-chip package during multi-chip operation.

[0028] Figure 6 A comparison chart showing the highest surface temperature of the multi-chip package provided by this invention and the highest surface temperature of the conventional method.

[0029] Figure 7 A comparison chart of the S-parameters for inter-chip isolation of the TMV-free grounding array provided by this invention.

[0030] Figure 8 A comparison chart of the S-parameters for inter-chip isolation with a TMV grounding array provided by the present invention.

[0031] Figure 9 A schematic diagram of the metal layer of the multi-chip package provided by the present invention; wherein (a) is a chip distribution diagram; and (b) is a perspective view.

[0032] Figure 10 The images show a front view and a partial magnified view of the metal layer of the multi-chip package provided by this invention.

[0033] Figure 11 The images show a front view of the metal layer of the multi-chip package and a partial magnified view of the TMV gap provided by the present invention. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0035] like Figure 1As shown, this embodiment of the invention specifically provides a multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics, including: An EMC molded package contains multiple chips, and each chip has a eutectic solder layer, a MoCu (molybdenum copper) heat sink, and a back RDL metallization layer arranged sequentially on its back side. TMV copper pillars are arranged in a matrix around each chip to form a TMV array; the TMV array is a double-layered horizontally arranged matrix. The front RDL metal interconnect layer connects the MoCu heat sink to the back of the TMV copper pillar through the back RDL metallization layer. The front ground pad and front signal pad of each chip are fanned out to the corresponding BGA ground ball and BGA signal ball through the front RDL metal interconnect layer. At the same time, the front of the TMV copper pillar is at the same potential as the BGA ground ball through the front RDL metal interconnect layer, forming an active ground shield at the same potential as the RF reference ground, so that the TMV array is equivalent to a Faraday-like shield when the periodic condition is met.

[0036] As a further explanation, the package structure includes multiple GaN RF power chips. Each GaN RF power chip has a front ground pad and a front signal pad designed on the front side for RF signal input / output and front grounding. Each GaN RF power chip has a back gold layer on the back side, which serves as both a back ohmic contact layer and a metallization interface for subsequent eutectic bonding.

[0037] The back gold layer of the GaN RF power chip is rigidly connected to the MoCu heat sink through the eutectic solder layer, completing the back metallization and MoCu heat sink integration of the GaN RF power chip. Together with the pre-set through-hole TMV copper pillars, it is embedded in the epoxy molding compound EMC matrix to form a fan-out package. The TMV copper pillars are arranged in two horizontal rows, forming a matrix around each GaN RF power chip, thus forming a TMV array. The period p of the TMV array (i.e., the center-to-center distance pitch between two adjacent TMV copper pillars) satisfies the equivalent condition of the electromagnetic shielding wall: p≤λ / 10, where λ represents the wavelength corresponding to the operating frequency band of the RF power chip. A back RDL metallization layer is provided to connect the MoCu heat sink to the back of the TMV copper pillar. The TMV copper pillar is grounded, forming a key segment of the first grounding path. A front-side RDL metal interconnect layer is provided to fan out the front-side ground pad and RF signal pad of the GaN RF power chip to the corresponding BGA ground and BGA signal pad positions on the front side of the package through the front-side RDL metal interconnect layer; the fan-out of the front-side ground pad of the GaN RF power chip constitutes the key segment of the second ground path. The chip's front ground pad and BGA ground ball, back RDL metallization layer, MoCu heat sink, and TMV copper pillars work together to form an independent metal shielding cavity. This shielding cavity places each chip in an independent shielding chamber, greatly improving isolation. The back side is a complete back RDL metallization layer, and the spacing p of the TMV pillars around it is adjusted according to the radio frequency band to adapt to multi-band requirements, forming a "fully enclosed" electromagnetic isolation environment, giving the package high isolation characteristics.

[0038] To describe the embodiments of the present invention in more detail, the electrical and electromagnetic shielding connections of the TMV array are as follows: Back side: The back RDL metallization layer is directly shorted to the MoCu heat sink, thus connecting to the back ground network of the chip; Front side: The front RDL metal interconnect layer shares the same potential with the BGA ground solder ball. The back RDL metallization layer and the front RDL metal interconnect layer are interconnected and share a common ground via TMV copper pillars.

[0039] Furthermore, the eutectic solder layer uses Au80Sn20 eutectic solder with a thickness of 50μm.

[0040] Furthermore, the MoCu heat sink has a thickness of 145 μm and a thermal conductivity of 180 W / m·K.

[0041] Furthermore, the diameter of the TMV copper pillars is 150 μm, and the center-to-center spacing p is 400 μm.

[0042] Furthermore, the back of the packaged GaN RF power chip is connected to an external heat sink via a thermal interface material (TIM). Depending on the actual situation, thermally conductive pads or thermally conductive adhesives or other TIM materials can be selected.

[0043] Furthermore, the thermal conductivity of the back RDL metallization layer is 380 W / m·K, and the thickness is 5 μm.

[0044] As a preferred embodiment of the present invention will be described in detail, it also includes: (1) Core active device—RF power chip; This invention uses multiple GaN RF power chips as the core active devices. The chips are 100μm thick, and each chip has a front ground pad and a front signal pad on its front side for RF signal input / output and front grounding. Each chip has a back gold layer on its back side, which serves as both a back ohmic contact layer and a metallization interface for subsequent eutectic bonding.

[0045] (2) High thermal conductivity heat dissipation-grounding composite layer - MoCu heat sink and eutectic solder layer; On the back of the chip, a rigid connection is achieved with the MoCu heat sink through a eutectic solder layer.

[0046] The eutectic solder layer uses Au80Sn20 eutectic solder with a thickness of approximately 50μm. It combines high thermal conductivity (approximately 60 W / m·K) with good electrical conductivity, ensuring a low thermal resistance and low electrical resistance metallurgical bond between the chip back gold layer and the MoCu heat sink.

[0047] The MoCu heatsink is 145 μm thick, and its planar dimensions are identical to those of the corresponding chip to optimize the heat diffusion path. Heat is conducted from the chip junction region through the eutectic solder layer, the MoCu heatsink, the back RDL metallization layer, and the TIM to the external heat sink, achieving efficient heat dissipation. MoCu material has a thermal conductivity of 180 W / m·K and low resistivity; therefore, this heatsink serves as both an efficient heat dissipation medium and an electrical ground electrode on the back of the chip.

[0048] (3) Encapsulation substrate—epoxy molding compound EMC substrate; The chip, with its back metallized and MoCu heatsink integrated, along with pre-installed TMV copper pillars and through-hole molding compounds, is embedded in an epoxy molding compound EMC matrix to form a fan-out package. The EMC matrix has a thermal conductivity of approximately 1 W / m·K, and its main functions are mechanical support and environmental protection.

[0049] (4) Vertical interconnection and shielding structure – TMV copper pillars and TMV array; High-density plastic-encapsulated through-hole TMV copper pillars are pre-placed in the EMC substrate, and multiple TMV copper pillars are arranged to form a TMV array.

[0050] The TMV copper pillars have a diameter of 150μm and a center-to-center spacing p of 400μm, arranged in a matrix around the perimeter of the chip. A dual-row TMV configuration is used to enhance the mechanical reliability and electromagnetic shielding effectiveness of the shielding network.

[0051] The period p of the TMV array satisfies the equivalent condition of an electromagnetic shielding wall: p ≤ λ / 10; where λ is the wavelength corresponding to the operating frequency band (20~30GHz) of the RF power chip. When this period condition is met, the TMV array can be modeled according to the equivalent surface impedance theory, and is equivalent to a Faraday-like shielding wall with continuous conductive boundaries.

[0052] The electrical and electromagnetic shielding connections of the TMV array are as follows: Back side: The back RDL metallization layer is directly shorted to the top surface of the MoCu heat sink, thus connecting it to the ground network on the back of the chip; Front side: Shares potential with BGA ground solder balls via the front RDL metal interconnect layer.

[0053] Therefore, the TMV array is not a floating conductor, but an active grounded shield with the same potential as the RF reference ground, which fundamentally eliminates the potential difference between the shield and the ground plane and suppresses common-mode noise coupling.

[0054] (5) Double-sided wiring layer – back RDL and front RDL; After the chip and TMV array are reconstructed on the EMC substrate, a double-sided redistribution layer (RDL) is formed, including a front RDL metal interconnect layer on the upper surface of the EMC substrate and a back RDL metallization layer on the lower surface.

[0055] Backside RDL metallization layer: used to connect the MoCu heat sink to the backside of the TMV copper pillar, forming a key segment of the first grounding path; Front RDL metal interconnect layer: Used to fan out the front ground attribute PAD and RF signal attribute PAD to the corresponding BGA solder ball position on the front of the package through the front RDL metal interconnect layer.

[0056] The thermal conductivity of the back RDL metallization layer is 380 W / m·K, and the thickness is about 5 μm.

[0057] (6) Front external interface – Ball Grid Array (BGA); The front side of the package features a ball grid array (BGA), including: BGA grounding solder ball: Used to connect to the system board-level reference ground, while also providing a front potential reference for the TMV array; BGA signal solder balls: used for external input and output of radio frequency signals and DC control signals.

[0058] (7) External heat dissipation interface – thermal interface material TIM and external heat sink; To further reduce the contact thermal resistance from the package housing to the external environment, the back of the package is connected to the external heat sink via a thermal interface material (TIM).

[0059] The TIM uses thermally conductive silver paste as one of the thermal pads, with a thermal conductivity of 40 W / m·K and a thickness of 50 μm. This TIM is directly attached to the back of the package (i.e., the metallized RDL area on the back), efficiently conducting heat to the external heat sink.

[0060] (8) Summary of the connection and positional relationships of each component; Vertical stacking relationship (from front to back of the chip): like Figure 3 As shown, the sequence is: BGA solder ball → front RDL metal interconnect layer / PI polyimide layer → chip → eutectic solder layer → MoCu heat sink → back RDL metallization layer (using Cu metal material) → TIM → external heat sink.

[0061] Lateral wrapping relationship: The TMV array is arranged around the chip, connected to the MoCu heat sink through the RDL metallization layer on the back, and connected to the BGA ground ball through the RDL metal interconnect layer on the front.

[0062] Electrical connection relationship - dual grounding path: First grounding path (low inductance back grounding path): Chip back side → Eutectic solder layer → MoCu heat sink → Back RDL metallization layer → TMV copper pillar → Front RDL metal interconnect layer → BGA grounding solder ball.

[0063] Second grounding path (traditional front grounding path): chip front grounding pad → front RDL metal interconnect layer (RDL grounding trace, via) → BGA grounding solder ball.

[0064] The two grounding paths are electrically connected in parallel, and their equivalent parasitic inductances satisfy the following: ;in Indicates the equivalent parasitic inductance. Indicates the parasitic inductance of the first grounding path. This indicates the parasitic inductance of the second grounding path.

[0065] Due to the low resistivity of the MoCu heatsink, the ohmic loss of the first ground path is negligible, thereby significantly reducing the potential fluctuation of the RF reference ground.

[0066] This invention solves three major problems—thermal management, radio frequency grounding, and electromagnetic compatibility—in a single package structure through an integrated collaborative design of heat dissipation, grounding, and isolation.

[0067] Heat dissipation principle: In the packaging structure of this invention, the heat generated during operation originates from the chip junction region and is sequentially conducted through the eutectic solder layer, MoCu heat sink, back RDL metallization layer, and TIM to the external heat sink, achieving efficient heat dissipation. Because the MoCu heat sink replaces a large amount of low thermal conductivity EMC material on the back of the chip in traditional structures, a low thermal resistance heat dissipation path is established from the chip junction region to the package shell.

[0068] Grounding principle: Utilizing the low resistivity of the MoCu heatsink, a first grounding path is constructed from the back of the chip to the BGA grounding solder ball, and connected in parallel with the traditional grounding path via RDL for the GND attribute PAD on the front of the chip. According to the inductor parallel formula, the equivalent grounding inductance is significantly reduced, thereby maintaining a stable RF reference ground potential in the high-frequency operating band.

[0069] Electromagnetic isolation principle: When the periodicity condition p ≤ λ / 10 is met, the TMV array surrounding the chip exhibits a surface impedance to incident electromagnetic waves that is much lower than that of the surrounding EMC dielectric, forcing near-field coupled waves to propagate along a high-loss path, effectively acting as a Faraday-like shield. Simultaneously, the back of the TMV array is shorted to the MoCu heatsink, and the front is at the same potential as the BGA grounding solder ball, forming an active grounding shield cavity that divides the package interior into multiple independent shielding regions, achieving high-isolation electromagnetic isolation between chips.

[0070] The packaging structure of this invention operates in the following manner in a radio frequency microsystem: System assembly stage: The package is surface mounted on the system substrate using BGA, the BGA grounding solder ball is connected to the system reference ground, the BGA signal solder ball is connected to the RF front-end circuit, and the TIM is attached to the system heat dissipation structure.

[0071] During the radio frequency (RF) operation phase: RF signals are transmitted to the front signal pads of the chip via the BGA signal solder balls and the front RDL; the RF power generated by the chip is stably returned to the system reference ground via the front ground pad and the back RDL metallization layer through a dual parallel grounding path.

[0072] Thermal management phase: The heat generated by the chip during operation starts from the chip junction area and is conducted to the external heat sink in sequence through the eutectic solder layer, MoCu heat sink, back RDL metallization layer and TIM to achieve efficient heat dissipation and maintain the chip junction temperature within a safe range.

[0073] Electromagnetic compatibility stage: The TMV array forms a grounded shield cavity between each chip to suppress near-field coupling crosstalk in the 20~30GHz frequency band and ensure that the isolation between multiple chips is ≥80dB.

[0074] like Figure 2 As shown, P1, P3, P5, and P7 are the input ports of the RF power chip, and P2, P4, P6, and P8 are the output ports of the RF power chip. A schematic diagram of the two-layer arrangement of the TMV array is also given.

[0075] like Figure 3 As shown, T cold This indicates the temperature of the cold end of the top heat dissipation unit, T. chip The value represents the temperature of the chip's heating surface, and R represents the thermal resistance. The subscript indicates the thermal resistance of a specific structural component. The total thermal resistance can be decomposed into the sum of the series thermal resistances of different structural components. Where R... chip R represents the thermal resistance as heat flows from the front to the back of the chip. EMC R represents the thermal resistance when heat passes through the EMC of the molding compound. Solder R represents the thermal resistance as heat passes through the eutectic solder layer. MoCu R represents the thermal resistance as heat passes through the molybdenum-copper sheet. RDL R represents the thermal resistance as heat passes through the back RDL metallization layer.TIM R represents the thermal resistance of heat passing through the thermal interface material. jc Junction-case thermal resistance (JCR) represents the thermal resistance from the front of the bare die to the die casing, and is also known as the junction-case thermal resistance. It is an important parameter characterizing the heat dissipation performance of a chip. In a traditional structure, the junction-case thermal resistance R... jc = R chip + R EMC The thermal resistance R of the shell under the structure of this invention jc = R chip + R Solder + R MoCu +R RDL Due to R in the traditional structure EMC It has high thermal resistance, and therefore is the structural part that this invention focuses on optimizing.

[0076] In the traditional structure, the RDL+PI thickness on the front side of the GaN chip is 10μm, the GaN chip thickness is 100μm, and the EMC thickness is 200μm (referring to...). Figure 3 The thickness of the layer located above the GaN chip is 300 μm (the overall EMC molding thickness is 300 μm), and the total body thickness is 310 μm. In the structure of this invention, the thickness of the RDL+PI layer on the front side of the GaN chip is 10 μm, the thickness of the GaN chip is 100 μm, the thickness of the eutectic solder layer is 50 μm, the thickness of the MoCu heat sink is 145 μm, the thickness of the RDL metallization layer on the back side is 5 μm, and the total body thickness is 310 μm.

[0077] like Figure 4 The figure shows a comparison of theoretical calculations and numerical simulations of the traditional single-chip packaging structure and the single-chip packaging structure of the present invention under single-chip operating conditions. Where R... jp =R chip R js =R chip + R Solder R jm =R chip +R Solder + R MoCu The theoretical calculation formula mentioned above is as follows: , T j This refers to the chip junction temperature (°C). T c Chip case temperature (°C). Q Heat transferred by conduction (W). A The heat transfer area (m²) is perpendicular to the heat flow direction. λ The thermal conductivity of the material is (W / (m·K)). This formula represents the vertical distance for heat transfer. The thermal resistance of other layers (bare chip layer, eutectic solder layer, EMC layer, etc.) can be calculated using this formula.

[0078] In traditional structures, theoretical calculations show that the GaN thickness represents the vertical distance of heat transfer. =1×10 -4 m, A = 0.0028 (width) × 0.004 (length) = 1.12 × 10 -5 m 2 The thermal conductivity of GaN material is 160 W / (m·K); the thickness of the EMC covering the GaN represents the vertical distance of heat transfer. =2×10 -4 A = 0.0029 (width) × 0.0041 (length) = 1.189 × 10 -5 m 2 (EMC encapsulates the chip, therefore it is slightly larger than the chip, and edge EMC also contributes to heat transfer), the EMC thermal conductivity is 1 W / (m·K). Therefore, R jp =1×10 -4 / (1.12×10 -5 (×160)=0.0558W / ℃, R jc =0.0558+2×10 -4 / (1.189×10 -5 ×1)=16.8766W / ℃.

[0079] The relevant parameters for the above calculations under the structure of this invention are: GaN thickness, i.e., the vertical distance of heat transfer. =1×10 - 4 m, A = 0.0028 (width) × 0.004 (length) = 1.12 × 10 -5 m 2 The thermal conductivity of GaN material is 160 W / (m·K); the thickness of the eutectic solder layer (Solder) is the vertical distance for heat transfer. =0.50×10 -4 m, A = 0.0028 (width) × 0.004 (length) = 1.12 × 10 -5 m 2 The thermal conductivity of the solder material is 60 W / (m·K); the MoCu thickness represents the vertical distance of heat transfer. =1.45×10 -4 m, A = 0.0028 (width) × 0.004 (length) = 1.12 × 10 -5 m 2 The thermal conductivity of MoCu material is 180 W / (m·K); the thickness of the back RDL is the vertical distance for heat transfer. =5×10 -6 m, A = 0.0029 (width) × 0.0041 (length) = 1.189 × 10 -5m 2 The thermal conductivity of the RDL material on the back side is 380 W / (m·K). The calculation process is the same as that for traditional structures, where the corresponding formulas are used. It will not be repeated here. The specific thermal resistance calculation data is shown in Table 1.

[0080] In terms of simulation data, the GaN power consumption is 2.5W (continuous), and the heat dissipation is evenly distributed on the GaN circuit surface. The basic chip data is the same as in theoretical calculations. Under the traditional structure, the center temperature of the GaN circuit surface is 109.76℃, the back surface temperature is 109.62℃, and the center temperature of the EMC top surface (casing) is 67.12℃. Therefore, R... jp =(109.76-109.62) / 2.5=0.056, R jc =(109.76-67.12) / 2.5=17.056. Under the structure of this invention, the center temperature of the GaN circuit surface is 67.657℃, the temperature of the GaN back side is 67.52℃, the temperature of the center of the Solder back side is 67.334℃, the temperature of the center of the MoCu back side is 67.158℃, and the temperature of the center of the top surface (shell) of the back RDL is 67.155℃. The calculation process is the same as that of the traditional structure, which is calculated by substituting the corresponding formulas. It will not be repeated here. The specific thermal resistance calculation data is shown in Table 1.

[0081] Table 1. Thermal Resistance Statistics of Single-Chip Package

[0082] Data shows that the theoretically calculated thermal resistance of the traditional structure is 16.8766 (W / ℃), while the simulated thermal resistance of the junction is 17.056 (W / ℃). The error between the theoretical calculation and the simulation analysis is (17.056-16.8766) / 16.8766=1.06%. The theoretically calculated thermal resistance of the structure of this invention is 0.2033 (W / ℃), while the simulated thermal resistance of the junction is 0.2008 (W / ℃). The error between the theoretical calculation and the simulation analysis is (0.2033-0.2008) / 0.2033=1.2297%. Therefore, the errors in the theoretically calculated and simulated thermal resistance values ​​for both the traditional structure and the structure of this invention are less than 2%. Data shows that the theoretically calculated thermal resistance of the junction-shell structure under the traditional structure is 16.8766 (W / ℃), while the theoretically calculated thermal resistance of the structure of this invention is 0.2033 (W / ℃). The ratio of the thermal resistance of the structure of this invention to that of the traditional structure is 0.2033 / 16.8766 = 1.2046%. The theoretically calculated thermal resistance of the structure of this invention is 17.056, and the simulated thermal resistance is 0.2008. The ratio of the thermal resistance of the structure of this invention to that of the traditional structure is 0.2008 / 17.056 = 1.1773%. In summary, the theoretical calculation and simulation analysis errors of the thermal resistance of both the structure of this invention and the traditional structure are less than 2%, and the junction-shell thermal resistance (Rjc) is reduced to 1.2% of that of the traditional packaging structure.

[0083] like Figure 5 As shown, the comparison of the internal chip surface temperature of the conventional multi-chip packaging structure and the multi-chip packaging structure of the present invention under multi-chip operating conditions demonstrates that the chip surface temperature of the packaging structure of the present invention is lower.

[0084] like Figure 6 As shown, by analyzing Figure 5 Statistical analysis of medium temperature data shows that the highest temperature of multiple chips in the packaging structure of this invention decreased from 124.8℃ to 56.2℃, and the maximum temperature difference between chips decreased from 54.9℃ to 9.5℃, with significant improvements in heat dissipation efficiency and temperature uniformity between chips.

[0085] like Figure 7 and Figure 8 As shown, the improved isolation effect in the 20~30GHz frequency band is illustrated. S21 represents the transmission loss from port 1 to port 2, which is an important parameter characterizing isolation performance. Similarly, S31, S41, S51, S61, S71, and S81 all represent the transmission loss of the port devices. The isolation of traditional packaging structures in the operating frequency band is only ≥30dB, and it decreases with increasing frequency. Thanks to the vertical grounding and shielding effect of the TMV array, the isolation between ports can reach ≥83dB in the operating frequency range.

[0086] like Figure 9 As shown, four power chips are located in the shielded cavity of the TMV array, and there are two leakage gaps on the side at the signal line input port and output port, both of which are 2p. That is, there are 2p gaps at the double-layered TMV copper pillars, while the regular gaps at the other TMV arrays are all center-to-center spacing p.

[0087] like Figure 10 As shown, the front view layout structure of the TMV array of the packaging structure of the present invention is given, as follows: Figure 11 The 2p shown represents the maximum gap between the side of the shielded cavity and the outside electromagnetic interconnection, and there are two gaps for each cavity, namely at the signal input port and the output port. The remaining conventional gaps are the TMV center-to-center spacing p.

[0088] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics, characterized in that, include: An EMC molded package contains multiple chips, and each chip has a eutectic solder layer, a MoCu heat sink, and a back RDL metallization layer arranged sequentially on its back side. TMV copper pillars are arranged in a matrix around each chip to form a TMV array; and the TMV array is a double-layered horizontally arranged matrix. The front RDL metal interconnect layer connects the MoCu heat sink to the back of the TMV copper pillar through the back RDL metallization layer. The front ground pad and front signal pad of each chip are fanned out to the corresponding BGA ground ball and BGA signal ball through the front RDL metal interconnect layer. At the same time, the front of the TMV copper pillar is at the same potential as the BGA ground ball through the front RDL metal interconnect layer, forming an active ground shield at the same potential as the RF reference ground, so that the TMV array is equivalent to a Faraday-like shield when the periodic condition is met.

2. The multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 1, characterized in that, The multiple chips are GaN RF power chips, and the back of the package structure is connected to an external heat sink via a thermal interface material (TIM).

3. The multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 1, characterized in that, The eutectic solder layer is made of Au80Sn20 material and has a thickness of 50μm.

4. The multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 1, characterized in that, The MoCu heat sink has a thickness of 145 μm and a thermal conductivity of 180 W / m·K.

5. A multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 1, characterized in that, The TMV array, when satisfying the periodic condition, is equivalent to a Faraday-like shielding wall, including: p≤λ / 10, where p represents the period, i.e., the center-to-center distance between every two adjacent TMV copper pillars, and λ represents the wavelength corresponding to the chip's operating frequency band.

6. The multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 5, characterized in that, The center spacing is adjusted according to the radio frequency band to adapt to the requirements of multiple frequency bands, forming a "fully enclosed" electromagnetic isolation environment, so that the packaging structure has high isolation characteristics.

7. A multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 5, characterized in that, The diameter of the TMV copper pillar is 150 μm, and the center-to-center distance between any two adjacent TMV copper pillars is 400 μm.

8. The multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 1, characterized in that, The thickness of the back RDL metallization layer is 5 μm, and the thermal conductivity is 380 W / m·K.

9. A multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 1, characterized in that, The MoCu heat sink serves as both a high thermal conductivity heat dissipation medium and a low resistivity ground electrode, thereby constructing a low-inductive first grounding path from the back of the chip to the BGA grounding solder ball, achieving functional reuse of the heat conduction channel and the low-impedance grounding channel. At the same time, the front RDL metal interconnect layer serves as a second grounding path and is connected in parallel with the first grounding path to significantly reduce the equivalent ground inductance, thereby suppressing RF reference ground potential fluctuations.

10. A multi-chip wafer-level packaging structure with enhanced heat dissipation and high isolation characteristics as described in claim 5, characterized in that, The back RDL metallization layer, the MoCu heat sink, the eutectic solder layer, the TMV copper pillars, and the front ground pads and BGA ground balls of the chip work together to form independent metal grounding shield cavities between each chip and achieve an order-of-magnitude reduction in junction-to-case thermal resistance. The conventional shielding gaps on the sides of the metal grounding shield cavity are TMV center-to-center spacing p. To meet the signal line requirements of the power chip, the two leakage gaps on the sides of each metal grounding shield cavity at the signal input and output ports are both 2p. The metal grounding shield cavity suppresses near-field coupling crosstalk in the 20GHz~30GHz frequency band to ensure electromagnetic isolation ≥80dB between chips.

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