A high-power field effect transistor anti-radiation packaging structure

Abstract

The application discloses a kind of high-power field effect transistor anti-radiation packaging structure, including tube seat, cover plate, ceramic copper-clad plate, TVS chip, resistance, multiple MOSFET chips, bridging copper sheet, outer pin and silicone rubber.Multiple MOSFET chips are arranged on the ceramic copper-clad plate of tube seat bottom surface, and D pole lead-out island and S pole lead-out island are respectively arranged at both ends of each ceramic copper-clad plate, and are connected with outer pin by bridging copper sheet. The gate of each MOSFET chip is independently connected with resistance in series, and bidirectional TVS chip is connected in parallel between the gate and source of all chips. Tube seat and cover plate form metal sealed cavity and are sealed by parallel sealing welding, and the cavity is filled with silicone rubber. The application provides reliable insulation redundancy on the basis of anti-radiation by double protection of metal airtight packaging and filling glue, realizes multi-chip dynamic current sharing by symmetrization chip layout and independent gate resistance, reduces junction to shell thermal resistance to below 0.2K / W by Si3N4 ceramic substrate and bottom surface direct connection cold plate structure, and meets the demand of space high power density application.

Description

Technical Field

[0001] This invention relates to a radiation-resistant packaging structure for high-power field-effect transistors. Background Technology

[0002] As the power levels of spacecraft power systems continue to increase, increasingly stringent requirements are being placed on the packaging performance of power semiconductor devices. In the space radiation environment, power devices not only need to withstand high-energy particle bombardment and total dose radiation effects, but also need to meet multiple stringent requirements such as high current carrying capacity, efficient heat dissipation, and high reliability. Traditional radiation-hardened field-effect transistor (FET) packaging uses a metal casing and cover plate to form a sealed cavity through parallel bonding technology, with the internal chip electrically connected to the casing pins via bonding wires. However, this traditional packaging structure has revealed several technical shortcomings in practical applications.

[0003] Existing traditional radiation-hardened field-effect transistors (FETs) have small package sizes, supporting only single-chip packaging, which cannot meet the high-power application requirements of multi-chip parallel connection. In actual aerospace power supply design, users have to use multiple single transistors in external parallel connection to achieve high current output, resulting in low overall system current density, a large number of devices, and long external lead connection lengths. This introduces a large number of parasitic parameters, leading to problems such as switching oscillation and uneven current. At the same time, the external parallel connection of multiple devices makes it difficult to coordinate the overall heat dissipation scheme, and the power density and reliability of the system are significantly constrained.

[0004] Regarding heat dissipation, traditional surface mount technology (SMD-2) packages require heat dissipation through a PCB board. However, PCBs are typically made of FR4 material, which has extremely low thermal conductivity, resulting in a thermal resistance between the chip junction and the environment typically in the range of 15-25 K / W. Under high-power operating conditions, the chip junction temperature rises sharply, severely impacting the long-term reliability and lifespan of the device. Furthermore, there is a significant difference in the coefficient of thermal expansion (CTE) between the metal casing and the silicon chip. Under the frequent temperature cycling conditions experienced by spacecraft, interfacial thermal stress concentration easily leads to failures such as bonding wire breakage, solder joint cracking, and chip edge fragmentation, becoming a key reliability bottleneck restricting the application of high-power devices in space.

[0005] In hermetic packaging, parallel sealing processes have extremely stringent requirements for weld airtightness. Even minor welding defects can allow external moisture to penetrate the package cavity. Once moisture enters, under high-voltage operating conditions, electrochemical corrosion and insulation degradation can easily occur between the exposed internal electrodes, potentially leading to short-circuit failure. Traditional packaging lacks redundant design to protect against moisture intrusion; once airtightness is lost, the device's insulation reliability collapses.

[0006] For packaging multi-chip parallel modules, CN103928447B discloses a high-power, fully hermetically sealed semiconductor module packaging structure, which uses a structure of sequentially soldered thermally conductive base plate, metal sealing frame, internal ceramic substrate, and semiconductor chip to achieve hermetically sealed packaging. However, it focuses on hermetically sealed packaging and does not address the current sharing design for multi-chip parallel connections or the integration scheme of the radiation-resistant chip itself. CN118676210A discloses a radiation-resistant structure for SiC MOSFET devices, which blocks spatial radiation particles from the outside of the device body by setting a deflection electric field structure inside the source metal. However, it only focuses on the deflection electric field inside the chip and does not solve the problems of heat dissipation path optimization and parasitic parameter balancing in multi-chip modular packaging. CN114121910A discloses a symmetrically arranged full-bridge power module to solve the problems of excessively high turn-off voltage and severe switching oscillation caused by structural layout. However, it does not involve the metal hermetically sealed high-power module packaging of radiation-resistant field-effect transistors, nor does it involve the systematic comprehensive design of Kelvin signal source lead-out, gate protection structure with gate series resistor and TVS, and redundant protection of potting colloid against water vapor intrusion failure.

[0007] Due to the numerous problems existing in the above-mentioned technologies, there are currently no integrated modular packaging products in the field of traditional radiation-resistant field-effect transistors. When designing power supply systems, designers of aerospace power systems can only use discrete single-transistor packages for external parallel connection. As a result, systemic problems such as low current density, large parasitic parameters, difficult heat dissipation, and insufficient reliability have not been effectively solved for a long time. Summary of the Invention

[0008] The present invention aims to overcome the shortcomings of the prior art and provide a radiation-resistant packaging structure for high-power field-effect transistors, so as to systematically solve the technical problems of traditional radiation-resistant field-effect transistor packaging in multiple dimensions such as multi-chip parallel integration, current density improvement, efficient heat dissipation, thermal stress adaptability, gate protection and water vapor intrusion protection redundancy.

[0009] The technical solution of the present invention is as follows: a high-power field-effect transistor radiation-resistant packaging structure, comprising a socket; a cover plate disposed on the top of the socket, forming a sealed cavity with the socket; at least one TVS chip, multiple resistors, and multiple MOSFET chips, all disposed on a ceramic copper-clad plate on the bottom surface of the socket; multiple bridging copper sheets and external leads, the bridging copper sheets being connected to the ceramic copper-clad plate, the external leads being disposed on the side wall of the socket, the inner end being connected to the bridging copper sheets, and the outer end extending out of the socket; and silicone rubber filling the sealed cavity.

[0010] The packaging structure of this invention provides a complete physical barrier through a metal-sealed cavity formed by a socket and a cover plate. In the space environment, high-energy cosmic rays such as alpha particles and protons have the ability to penetrate semiconductor materials and generate non-equilibrium charge carriers inside the device, inducing single-event effects. The density and thickness of the metal shell are sufficient to effectively block conventional space radiation particles. The chip is placed in this sealed cavity, where the metal shell directly absorbs and scatters incident particles, reducing the flux of radiation particles reaching the chip surface, thereby suppressing single-event burn-out and single-event gate penetration effects. At the same time, the closed metal shell formed by the socket and the cover plate forms a Faraday cage structure. When an external electromagnetic pulse acts on the shell, free charges redistribute on the conductor surface, and the internal electric fields cancel each other out to zero. The chip and internal circuits are not affected by external high-frequency electromagnetic fields, achieving electromagnetic shielding.

[0011] Furthermore, the socket is made of Kovar alloy. The coefficient of thermal expansion of Kovar alloy (Fe-Ni-Co system) is well-matched with the alumina ceramic insulating material and glass sealing material used in the packaging structure. During temperature cycling, excessive thermal stress will not occur between the socket and the insulating component due to differences in thermal expansion, thus ensuring the long-term integrity of the sealing gasket and insulating support block, and ensuring that the insulation withstand voltage and gas sealing performance between the external pins and the socket do not degrade. The socket is square with mounting ears at each of the four corners, and the mounting ears have through holes. The square socket combined with the four corner mounting ears allows the module to be directly fixed to the cold plate or heat sink using screws. After applying pre-tightening force to the through holes on the mounting ears, the bottom surface of the socket is tightly fitted to the surface of the cold plate, significantly reducing the interface contact thermal resistance. Compared with traditional surface mount soldering, screw crimping does not require heat transfer through the PCB board, eliminating the thermal bottleneck of high thermal resistance dielectric layers such as FR4. At the same time, the interface contact pressure formed by screw crimping is large and uniform, and the micro air gaps at the contact interface are fully compressed, allowing the heat flow to be directly introduced from the socket to the cold plate without obstruction.

[0012] Furthermore, the multiple MOSFET chips are divided into at least one group, and each group of MOSFET chips is disposed on the same ceramic copper-clad laminate. Each of the ceramic copper-clad laminates has a drain (D) lead-out island and a source (S) lead-out island at both ends, and the D lead-out island and the S lead-out island are respectively connected to the corresponding external pins through bridging copper sheets.

[0013] Multi-chip grouping and islanded D / S terminal structures have a direct physical effect on reducing parasitic parameters and improving current sharing performance. In power modules with multiple chips connected in parallel, the inconsistency of parasitic inductance in each parallel branch is the root cause of dynamic current sharing loss mismatch—during switching transients, branches with smaller parasitic inductance will bear larger di / dt and disproportionate current peaks, resulting in uneven switching losses and thermal stress between chips. This invention groups multiple MOSFET chips onto the same ceramic copper-clad laminate, with each ceramic copper-clad laminate having a consistent structure and symmetrical wiring. This ensures that the electrical interconnect path length, cross-sectional shape of the metal conductor, and routing direction of each group of chips on the ceramic substrate remain consistent, suppressing the differences in parasitic inductance parameters of each branch to a very small range, thus eliminating the cause of parasitic parameter asymmetry from a geometrical perspective. Furthermore, D-terminal and S-terminal islands are respectively located at both ends of each ceramic copper-clad laminate. A bridging copper strip directly connects this island to the outer pin on the sidewall of the socket via the shortest path, shortening the total trace length of the high-current main circuit within the package and significantly reducing the total stray inductance and equivalent series resistance caused by interconnections within the package. The bridging copper strip is made of highly conductive oxygen-free copper and has a large width and thickness, providing a low-impedance connection in the electrical path. This reduces the total line resistance from D to S within the module to an extremely low level, thereby significantly improving the overall overcurrent capacity.

[0014] Furthermore, an insulating support block is provided between the outer pin and the sidewall of the socket, and a sealing gasket is provided between the outer pin and the insulating support block. In aerospace high-voltage busbar applications, multi-tube series boosting requires the device casing and internal circuitry to withstand an insulation withstand voltage of over 3000V. The insulating support block increases the creepage distance between the outer pin and the casing—that is, the minimum discharge path length along the insulator surface. Under high-voltage conditions, the path of surface leakage current along the surface of the insulating support block is significantly extended, effectively suppressing surface flashover. The sealing gasket provides a gas seal while filling the micro-gap between the outer pin and the insulating support block, blocking the channels for moisture and contaminant ions to penetrate into the cavity along the pin-insulator interface.

[0015] Furthermore, the external pins include S-pins and G-pins, which are respectively located on opposite sides of the socket; the external pins also include SS-pins and D-pins, which are located on the other side of the socket. Arranging the power circuit pins and signal circuit pins on different sidewalls of the socket increases the physical distance between the high-power current path and the low-signal current path, reducing the magnetic and capacitive coupling of the strong electromagnetic field of the power circuit to the signal circuit.

[0016] Furthermore, the signal source of the MOSFET chip is connected to the SS pin via a parallel connection of the signal source island on the ceramic copper-clad board. The structure of independently led-out Kelvin sources physically decouples the power circuit and the drive signal circuit: the S pin of the power source carries a high-current main circuit, and there is a non-negligible parasitic inductance Ls on its bonding wires and lead paths. When the power drain current changes with a high di / dt, the induced voltage VLs generated on Ls is superimposed on the source reference potential in the gate drive circuit, making the effective drive voltage Vgs_eff = Vgs_applied - VLs actually applied between the chip gate and source. For the turn-off process, this induced voltage will offset part of the turn-off drive voltage, slowing down the turn-off speed and increasing switching losses. By physically separating the signal source SS and the power source S inside the package, the SS pin only carries a microamp-level gate drive circuit current. The induced voltage generated by the parasitic inductance of its leads is extremely small. When the drive circuit provides the gate drive voltage with the SS pin as a reference ground, it will not be affected by the large current changes in the main power circuit. The accuracy and stability of the gate drive voltage are greatly improved.

[0017] Furthermore, each MOSFET chip has its gate independently connected in series with a resistor. This independent gate series resistor plays a crucial role in the dynamic current sharing of multiple parallel chips. The physical principle is that although the parasitic parameters of each parallel chip are highly consistent after symmetrical design, slight differences in intrinsic chip parameters (such as threshold voltage Vth, transconductance gm, and input capacitance Ciss) still lead to inconsistent switching speeds. By connecting an independent resistor in series in the gate circuit of each chip, the gate resistor and the chip's own input capacitance Ciss form an RC delay network. The time constant τ = Rg × Ciss of this RC network determines the rise and fall rates of the gate voltage. When each chip's gate is connected in series with an independent resistor, the charging and discharging time constant of each gate circuit is mainly determined by the resistor value and the chip's own Ciss. The application and removal of the gate drive voltage have a consistent time response across all chips, avoiding the phenomenon of a chip experiencing disproportionate current peaks due to excessively fast switching. Preferably, the resistance value is 3-20Ω. If the resistance is too small, the effect of suppressing time constant differences will be insufficient, and the current sharing effect will be poor; if the resistance is too large, the switching speed will be too slow and the switching loss will be too large. This resistance range has been experimentally verified to achieve a good balance between current sharing effect and switching loss.

[0018] Furthermore, the TVS chip is a bidirectional TVS, connected in parallel between the gate and source of all the MOSFET chips. The core physical mechanism of the TVS diode is based on the characteristic that the PN junction can instantly switch from a high-resistance state to a low-resistance state under reverse breakdown voltage. When a forward or reverse transient voltage spike exceeding the TVS clamping voltage occurs between the gate and source, the TVS completes the breakdown process from cutoff to conduction within nanoseconds. The low dynamic resistance after conduction forces the gate-source voltage to be clamped within a safe voltage threshold. The energy of the transient overvoltage is discharged through the TVS in the form of conduction current, preventing the MOSFET gate oxide layer from being subjected to electric field stress exceeding its dielectric strength. Dielectric breakdown of the gate oxide layer is an irreversible failure mode of the MOSFET, which once occurs, causes a permanent short circuit between the gate and the channel. The bidirectional TVS configuration ensures that regardless of whether the polarity of the transient voltage spike is positive or negative, there is a low-impedance discharge path corresponding to the TVS breakdown conduction direction, providing bipolar transient protection for the gate oxide layer. Preferably, the clamping voltage of the TVS chip is ≤40V. For the gate oxide withstand voltage of conventional power MOSFETs (typically ±20V to ±30V), a 40V clamping voltage can ensure that the gate voltage will not exceed the oxide's breakdown voltage before the TVS is fully turned on. This effectively protects the chip gate in scenarios such as electrostatic discharge, gate voltage fluctuations caused by the Miller effect during switching, and gate overshoot induced by spatial electromagnetic interference.

[0019] Furthermore, the bottom surface of the ceramic copper-clad laminate is connected to the bottom surface of the socket via solder; the bottom surface of the MOSFET chip is connected to the upper surface of the ceramic copper-clad laminate via solder; the bottom surfaces of the TVS chip and the resistor are both connected to the upper surface of the ceramic copper-clad laminate via solder; the MOSFET chip, resistor, TVS chip, and ceramic copper-clad laminate are all electrically interconnected via bonding wires. This multi-layer solder connection structure ensures the reliability of the heat dissipation path and its temperature cycling tolerance from both thermodynamic and stress relief perspectives. The Joule heat generated by the chip in the conducting state is conducted downwards layer by layer from the silicon material on its bottom surface: first through the solder layer bonding the chip to the ceramic copper-clad laminate, then into the upper copper layer of the ceramic copper-clad laminate, downwards through the ceramic substrate to the lower copper layer, then through the solder layer bonding the ceramic copper-clad laminate to the bottom surface of the socket, and finally into the tungsten copper or Kovar material on the bottom surface of the socket. Each interface material along this heat dissipation path is made of a material with high thermal conductivity. The total thermal resistance from the chip to the bottom of the socket mainly depends on the intrinsic thermal conductivity of each layer and the quality of the interface contact. Since the welding of each layer is completed in a vacuum or protective atmosphere, the solder fully wets both sides of the surface in the molten state, and forms a continuous and dense metallurgical bonding layer after solidification. There are no micro-gaps or voids at the interface, and the scattering effect of phonons at the interface is suppressed. The total thermal resistance is controlled at an extremely low level of less than 0.2K / W, providing sufficient thermal management guarantee for the long-term stable operation of the module under high power density.

[0020] Furthermore, the source electrode of the MOSFET chip is bonded to the S-terminal of the ceramic copper-clad laminate via the bonding wire, forming an island. Similarly, the gate electrode of the MOSFET chip is bonded to the gate island of the ceramic copper-clad laminate via the bonding wire. The principle of aluminum wire ultrasonic bonding is as follows: applying ultrasonic vibration energy and a certain pressure to the aluminum wire at room temperature causes atomic-level solid-state diffusion welding between the aluminum wire and the electrode surface metal, forming a low-resistance metallurgical interface without melting the base material. The bonding wire is made of aluminum, utilizing its high conductivity and good compatibility with ultrasonic bonding processes to achieve reliable electrical interconnection between the chip's top electrode and the substrate island.

[0021] Furthermore, the two ends of the copper strip are connected to the S-terminal and D-terminal outgoing islands on the adjacent ceramic copper-clad laminates, respectively. When the module contains multiple ceramic copper-clad laminates, the copper strip establishes a current-sharing and busbar connection between the S-terminal and D-terminal across the multiple laminates, allowing the current to be evenly collected or distributed from the outgoing islands of the multiple laminates, thus avoiding hot spot stress problems caused by excessive current concentration in a certain path.

[0022] Furthermore, the silicone rubber fills the sealed cavity, and its Shore A hardness after curing is 10-40. The protective principle of silicone rubber potting lies in the fact that liquid silicone rubber has excellent fluidity and permeability before curing, which can fully fill the space where all electrodes, chips, bonding wires, resistors, TVS chips, and substrate traces are located within the cavity. After curing, it forms a continuous, flexible, and dense insulating coating layer. This coating layer completely isolates the exposed conductor surface from the environment inside the cavity—even if the parallel seal weld between the tube socket and the cover plate loses its airtightness due to long-term thermal stress fatigue or micro-defects, external moisture and contaminants entering the cavity can only contact the outer surface of the silicone rubber. The diffusion coefficient of moisture molecules in the silicone rubber matrix is ​​extremely low, and they cannot penetrate the silicone rubber layer to reach the internal electrode surface. Therefore, the insulation resistance between the electrodes will not decrease due to moisture condensation, and there will be no moisture-assisted electrochemical migration or metal dendrite growth. The cured Shore A hardness is 10-40, which gives the silicone rubber sufficient flexibility and elasticity. When the relative displacement of the materials is caused by thermal expansion and contraction due to temperature cycling, the silicone rubber elastically expands and contracts with the deformation of the substrate. It will not crack inside the silicone rubber layer due to thermal stress, nor will it detach from the bonded surface, thus always maintaining complete coverage of the electrode.

[0023] Furthermore, the substrate of the ceramic copper-clad laminate is made of Si3N4, AlN, or Al2O3, with copper layers covering both its upper and lower surfaces. The selection of materials for the ceramic copper-clad laminate is crucial for thermal management and thermal stress control. The coefficient of thermal expansion (CTE) of Si3N4 ceramic is highly similar to that of silicon chips (CTE approximately 2.6-3.0 ppm / K), and their thermal expansion and contraction during temperature cycling are essentially synchronized, resulting in minimal differential expansion strain at the interface and a significant reduction in shear stress on the solder layer. While Al2O3 ceramic has a relatively low thermal conductivity (approximately 20-30 W / m·K), its low cost, mature manufacturing process, and high insulation strength make it suitable for low- to medium-power applications. AlN ceramic combines high thermal conductivity (approximately 170-230 W / m·K) with a CTE close to that of silicon (approximately 4.0-4.5 ppm / K), providing another effective trade-off between high-power heat dissipation requirements and thermal stress control. After copper layers are applied to both the upper and lower surfaces, the upper copper layer provides a solderable metal surface and circuit pattern for soldering chips and components, while the lower copper layer provides a solderable surface for soldering to the bottom of the socket.

[0024] The beneficial effects of this invention are as follows: This invention constructs a high-power radiation-resistant field-effect transistor module packaging scheme for space applications. Through a multi-chip grouped symmetrical layout and independent gate series resistors, dynamic and static current sharing of parallel chips is ensured from an electrical perspective. Meanwhile, the Kelvin signal source lead-out ensures the accuracy of the gate drive reference from a measurement and drive perspective, eliminating the modulation effect of parasitic inductance in the power circuit on the gate drive waveform. The matching thermal expansion coefficients of the Si3N4 ceramic substrate and the chip, combined with the stress release of the multilayer soft solder, suppress interface fatigue failure under temperature cycling from a thermodynamic perspective. The short heat dissipation path, with the socket bottom directly connected to the cold plate, efficiently dissipates the chip's heat dissipation. Together, these three elements elevate thermal management reliability to a level unattainable by traditional packaging. The metal hermetically sealed packaging provides the first physical barrier against radiated particles and electromagnetic pulses, while the silicone rubber potting provides a second redundant layer of protection for electrode insulation through flexible full-coverage. When hermetically sealed properties are lost due to weld failure, the isolation effect of the potting compound ensures that the internal electrical insulation performance remains unaffected, achieving a dual-layer reliability architecture of "hermetically sealed + potting". The combination of bidirectional TVS gate transient voltage protection and independent gate series resistor forms a complete gate protection mechanism that resists external transient voltage surges and ensures internal switching synchronization. The synergistic effect of these technical features enables the modular packaging structure of this invention to operate reliably for extended periods under extreme conditions such as spacecraft power systems, satellite power management, and high-radiation environments in the nuclear industry. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the internal structure of the present invention.

[0026] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure at point AA.

[0027] Figure 3 This is a schematic diagram of the pin structure of the present invention.

[0028] Figure 4 This is a schematic diagram of the circuit principle of the present invention.

[0029] In the diagram: 1-Socket, 2-Cover plate, 3-Ceramic copper-clad laminate, 4-Silicone rubber, 5-Copper strip, 6-TVS chip, 7-Bonding wire, 8-Resistor, 9-MOSFET chip, 10-Bridging copper sheet, 11-External pin, 12-Insulating support block, 13-Sealing gasket, 14-S pin, 15-G pin, 16-SS pin, 17-D pin, 18-Mounting ear, 19-S-terminal island, 20-D-terminal island, 21-Resistor island, 22-Signal source island. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0031] Reference Figures 1 to 4 This embodiment provides a radiation-resistant packaging structure for high-power field-effect transistors, suitable for high-current power switching applications in spacecraft power systems.

[0032] The packaging structure of this embodiment includes a socket 1, a cover plate 2, a ceramic copper-clad plate 3, silicone rubber 4, a copper strip 5, a TVS chip 6, a bonding wire 7, a resistor 8, a MOSFET chip 9, a bridging copper sheet 10, external leads 11, an insulating support block 12, a sealing gasket 13, and a mounting ear 18.

[0033] The tube socket 1 is a square Kovar shell, with its bottom surface made of tungsten-copper composite material to balance high thermal conductivity and CTE matching with the ceramic substrate. Mounting ears 18 are located at the four corners of the tube socket 1, each with through holes for M3 screws to secure the module to an aluminum alloy cold plate or heat pipe radiator. Multiple leads are located on the sidewalls of the tube socket 1, separated from the shell by alumina ceramic insulating support blocks 12. A sealing gasket 13 is installed between the leads and the insulating support blocks 12 to ensure gas tightness. The cover plate 2 is a Kovar flat plate, welded to the upper edge of the tube socket 1 using a parallel sealing welding process. The weld seam achieves a helium mass spectrometry leak detection rate ≤1×10⁻⁶. -9 Pa·m 3 / s, forming a reliable metal hermetically sealed cavity.

[0034] The encapsulation cavity contains three ceramic copper-clad laminates 3. In this embodiment, the substrate of the ceramic copper-clad laminate 3 is Si3N4 (silicon nitride) ceramic with a thickness of 0.3 mm, and the upper and lower surfaces are coated with copper layers with a thickness of 0.3 mm. The bottom surface of the ceramic copper-clad laminate 3 is soldered to the tungsten copper bottom surface of the socket 1 using SnAg solder. Three MOSFET chips 9 are soldered onto each ceramic copper-clad laminate 3, for a total of nine chips on the three ceramic copper-clad laminates 3, arranged in a centrally symmetrical three-row, three-column layout on the bottom surface of the socket 1, and the structure and copper layer pattern of each ceramic copper-clad laminate 3 are completely identical. The two ends of each ceramic copper-clad laminate 3 are etched to form a source island 19 and a drain island 20, respectively, and the middle area has a gate island and a source island 22.

[0035] MOSFET chip 9 is a silicon-based radiation-hardened MOSFET with resistance to single-particle radiation ≥75MeV·cm. 2 Performance indicators include a per-mg radiation resistance and a total radiation dose resistance of ≥100Krad (Si). The chip measures 5mm x 5mm in length and width, with a thickness of 180μm. A single chip has a withstand voltage of 200V and an overcurrent capability of 50A. All nine chips are sourced from the same wafer and screened using CP testing to ensure consistency in threshold voltage Vth and on-resistance Rds(on). The bottom surface of each MOSFET chip 9 is soldered to the upper copper layer of the ceramic copper-clad laminate 3 using PbSnAg solder. The source electrode on the top surface of the chip is bonded to the source (S) island 19 of the ceramic copper-clad laminate 3 via a 300μm diameter aluminum wire bonding wire 7, and the gate electrode on the top surface of the chip is bonded to the gate island of the ceramic copper-clad laminate 3 via a 150μm diameter aluminum wire bonding wire 7.

[0036] Each MOSFET chip 9 has an independent resistor 8 connected in series in its gate circuit. In this embodiment, the resistance value of the resistor 8 is preferably 10Ω based on testing. The package is a 0805 surface mount type, with the bottom surface soldered to the resistor island 21 of the ceramic copper-clad laminate 3 using SnAg solder, and the top surface connected to the gate island via bonding wire 7. All the gate islands of the chips are connected to the G pin 15 via the resistor 8.

[0037] A bidirectional TVS chip 6 is connected in parallel between the gate and the source. In this embodiment, the clamping voltage of the TVS chip 6 is 30V. The bottom surface of the TVS chip 6 is soldered to the upper surface of the ceramic copper-clad laminate 3, and the top surface is connected to the gate island and the source island respectively through bonding wires 7, thereby being connected in parallel between the G pin 15 and the S pin 14 to provide uniform transient voltage protection for the gate and source of all nine MOSFET chips 9.

[0038] The signal source terminals of each chip are connected in parallel to the signal source terminal islands 22 on the ceramic copper-clad laminate 3 via bonding wire 7, and then connected to the SS pin 16 to achieve independent Kelvin signal source terminals. The power source terminals of each chip are connected via the S terminal island 19 and then connected to the S pin 14 on the side wall of the socket 1 via bridging copper sheet 10. The drain terminals of each chip are connected via the D terminal island 20 and then connected to the D pin 17 on the side wall of the socket 1 via bridging copper sheet 10. The bridging copper sheet 10 is made of high-conductivity oxygen-free copper, with a width of 8 mm and a thickness of 0.5 mm. The two ends of the copper strip 5 are soldered to the S terminal island 19 and the D terminal island 20 on the adjacent ceramic copper-clad laminate 3, respectively, forming a bus path between multiple boards.

[0039] External pin 11 is divided into four groups: S pin 14 and G pin 15 are respectively set on opposite sides of the tube socket 1 to realize the physical separation of the power circuit and the drive circuit; SS pin 16 and D pin 17 are set on the other side of the tube socket 1.

[0040] After all the above electrical connections are completed and pass the tests, two-component liquid silicone rubber is injected into the cavity of tube socket 1. Degassing is then performed in a vacuum environment to remove air bubbles from the potting compound, followed by heat curing. The cured silicone rubber 4 has a Shore A hardness of 25, completely covering and insulating all exposed electrodes, chips, bonding wires, and substrate traces inside.

[0041] The working process of the packaging structure described in this embodiment is as follows: In the spacecraft power system, the module is fixed to the surface of the cold plate heat sink by screws through the through holes on the mounting ear 18. The external DC bus voltage is applied between the drain and source of the module through the D pin 17 and the S pin 14. The external PWM drive controller outputs the gate drive signal, with the G pin 15 as the drive voltage output terminal and the SS pin 16 as the drive signal reference ground, forming a complete gate drive circuit. When the gate drive voltage Vgs exceeds the chip threshold voltage Vth, the channels of the nine MOSFET chips 9 simultaneously form an inversion layer, and the drain to source is in a low-resistance conduction state. The current enters the D terminal from the D pin 17 through the bridging copper plate 10 and exits the island 20. It then splits into three paths and enters the drain copper layer of the three ceramic copper-clad laminates 3. Each path then flows into the S terminal through the drain-source channel of the three parallel chips and exits the island 19. It then flows out from the S pin 14 through the bridging copper plate 10, realizing high-current switching control. When current flows through the chip, Joule heating is generated inside the chip. The heat is conducted through the PbSnAg solder layer on the bottom surface of the chip to the upper copper layer of the ceramic copper-clad laminate 3, through the Si3N4 ceramic substrate to the lower copper layer, then through the SnAg solder layer to the tungsten copper material on the bottom surface of the socket 1, and finally to the cold plate heat sink where it is carried away by the cooling medium. When external electromagnetic interference or the Miller effect during the switching process causes the gate voltage spike to exceed 30V, the TVS chip 6 switches from a high-resistance cutoff state to a low-resistance on state within nanoseconds, clamping the gate-source voltage at 30V. The transient overvoltage energy is discharged in the form of TVS conduction current, protecting the gate oxide layer from damage.

[0042] Through actual testing, the module packaged in this embodiment achieved significant results in the following aspects: the total thermal resistance of the module (from the chip junction to the bottom surface of the casing) is less than 0.2K / W, which is less than 1 / 5 of the total thermal resistance of the traditional SMD-2 surface mount package structure; the total current carrying capacity of the nine chips connected in parallel is about nine times that of a single transistor; the gate series resistance and symmetrical layout control the difference in transient current distribution during the switching process of each chip to a very small range; the Kelvin signal source lead-out ensures that the driving waveform is not affected by the parasitic inductance of the power circuit, and the switching waveform is clean and oscillating; the insulation withstand voltage between the casing and the internal circuit exceeds 3000V; after silicone rubber potting, even if there is air leakage at the cover plate weld, the internal electrodes still maintain good insulation performance in a moisture environment; the metal hermetically sealed packaging combined with potting enabled the module to pass the space irradiation environment simulation test.

[0043] Example 2: This embodiment, based on Embodiment 1, modifies and expands the material selection and parameters to illustrate the adaptability and flexibility of the technical solution of the present invention in multiple application scenarios.

[0044] Regarding the selection of ceramic substrate materials, when cost control and compatibility with mature processes are paramount in applications, Al2O3 (alumina) can be used as the substrate for the ceramic copper-clad laminate 3. Al2O3 ceramics have high insulation strength, excellent chemical stability, widely available raw materials, and extremely mature manufacturing processes. In current applications with low to medium power levels and relatively mild heat dissipation requirements, Al2O3 substrates are a reasonable choice due to their excellent overall cost-effectiveness and long-proven space application reliability. When higher heat dissipation performance is required but cost is acceptable, AlN (aluminum nitride) ceramic substrates can be used. AlN has a thermal conductivity of 170-230 W / m·K, approximately 7-10 times that of Al2O3, providing superior thermal conductivity for further increasing power density or reducing junction temperature. Regardless of the ceramic substrate chosen, the solder connection method and multi-layer thermal path structure of this package structure remain consistent, allowing the same packaging platform to cover different power levels and application requirements through flexible selection of ceramic substrate materials.

[0045] Regarding the configuration of MOSFET chip 9, the single-chip voltage range can be extended to 60V-1200V. For example, for low-voltage, high-current spacecraft battery discharge management applications, 60V-rated chips can be selected and connected in parallel with more chips to achieve a greater total current carrying capacity; in high-voltage bus power distribution applications, 1200V-rated chips can be selected and connected in parallel to meet high-voltage, high-power requirements. The single-chip overcurrent capacity can be reasonably selected within the range of 1A-100A according to the total current specifications. The number of chips is not limited to 9; the number of chips on each ceramic copper-clad laminate and the total number of ceramic copper-clad laminates can be adjusted according to the actual current requirements, as long as the symmetrical layout principle is maintained.

[0046] Regarding the selection of resistor 8, the resistance range is 3-20Ω. For applications requiring high switching speed, choosing a smaller resistance value of 3-5Ω is beneficial for shortening the gate RC charging and discharging time constant and reducing switching losses, but the matching consistency requirements of chip parameters are correspondingly increased. For applications with a large number of parallel chips and significant parameter differences, choosing a larger resistance value of 10-20Ω can provide more sufficient current sharing suppression margin, at the cost of a slight decrease in switching speed. Generally, a value around 10Ω is recommended as a compromise.

[0047] Regarding the hardness parameters of silicone rubber 4, the Shore A hardness ranges from 10 to 40. Silicone rubber with lower hardness (10-20) exhibits better flexibility and a lower elastic modulus, resulting in better relative displacement response to thermal expansion and contraction during temperature cycling. However, its mechanical strength is relatively lower, making it suitable for low-Earth orbit spacecraft applications with large temperature fluctuations. Silicone rubber with higher hardness (30-40) has greater mechanical strength and better resistance to mechanical impact, making it suitable for harsh vibration and impact environments during launch.

Claims

1. A radiation-resistant package structure for a high-power field-effect transistor, comprising: Tube seat (1), the bottom surface of tube seat (1) is provided with a ceramic copper-clad plate (3); A cover plate (2) is disposed on the top of the tube seat (1) and forms a sealed cavity with the tube seat (1); At least one TVS chip (6), multiple resistors (8), and multiple MOSFET chips (9) are all disposed on a ceramic copper-clad plate (3) disposed on the bottom surface of the tube socket (1); Multiple bridging copper plates (10) and external pins (11) are provided. The bridging copper plates (10) are connected to the ceramic copper-clad plate (3). The external pins (11) are provided on the side wall of the tube seat (1). The inner end is connected to the bridging copper plates (10), and the outer end extends out of the tube seat (1). Silicone rubber (4) is filled into the sealed cavity.

2. The high-power field-effect transistor radiation-resistant packaging structure according to claim 1, characterized in that, The tube seat (1) is made of Kovar material. The tube seat (1) is square and has mounting ears (18) on each of the four corners. The mounting ears (18) have through holes.

3. The high-power field-effect transistor radiation-resistant packaging structure according to claim 1, characterized in that, Multiple MOSFET chips (9) are divided into at least one group. Each group of MOSFET chips is set on the same ceramic copper-clad plate (3). Each ceramic copper-clad plate (3) has a D-terminal lead-out island (20) and a S-terminal lead-out island (19) at both ends. The D-terminal lead-out island and the S-terminal lead-out island are respectively connected to the corresponding external pins (11) through bridging copper sheets (10).

4. The high-power field-effect transistor radiation-resistant packaging structure according to claim 3, characterized in that, An insulating support block (12) is provided between the outer pin (11) and the side wall of the tube seat (1), and a sealing gasket (13) is provided between the outer pin (11) and the insulating support block (12).

5. The high-power field-effect transistor radiation-resistant packaging structure according to claim 4, characterized in that, The external pin (11) includes an S pin (14) and a G pin (15), which are respectively located on opposite sides of the socket (1); the external pin (11) also includes an SS pin (16) and a D pin (17), which are located on the other side of the socket (1); the signal source of the MOSFET chip (9) is connected to the SS pin (168) after being connected in parallel through the signal source island (22) on the ceramic copper-clad plate (3); the resistor (8) is connected to the D pin (17) after being connected in parallel through the resistor island (22).

6. The high-power field-effect transistor radiation-resistant packaging structure according to claim 1, characterized in that, The gate of each MOSFET chip (9) is independently connected in series with a resistor (8); the TVS chip (6) is a bidirectional TVS connected in parallel between the gate and source of all the MOSFET chips (9).

7. The high-power field-effect transistor radiation-resistant packaging structure according to claim 1, characterized in that: The bottom surface of the ceramic copper-clad plate (3) is connected to the bottom surface of the tube seat (1) by solder; The bottom surface of the MOSFET chip (9) is connected to the upper surface of the ceramic copper-clad plate (3) by solder; The bottom surfaces of the TVS chip (6) and the resistor (8) are both connected to the upper surface of the ceramic copper-clad laminate (3) by solder. The MOSFET chip (9), resistor (8), TVS chip (6) and ceramic copper-clad laminate (3) are all electrically interconnected through bonding wires (7).

8. The high-power field-effect transistor radiation-resistant packaging structure according to claim 7, characterized in that, The source of the MOSFET chip (9) is bonded to the S-terminal of the ceramic copper-clad laminate (3) via the bonding line (7) to form an island. The gate of the MOSFET chip (9) is bonded to the gate island of the ceramic copper-clad laminate (3) via the bonding line (7). The two ends of the copper strip (5) are respectively connected to the source island and drain island on the adjacent ceramic copper-clad laminate (3).

9. The high-power field-effect transistor radiation-resistant packaging structure according to claim 1, characterized in that, The cured silicone rubber (4) has a Shore A hardness of 10-40.

10. The high-power field-effect transistor radiation-resistant packaging structure according to claim 1, characterized in that, The substrate of the ceramic copper-clad laminate (3) is made of Si3N4, AlN or Al2O3, and its upper and lower surfaces are covered with copper layers.

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