Thick gate oxide and rf-specific interposer with aluminum vias and edge seal

Abstract

An interposer structure and method of manufacture are disclosed: providing a wafer substrate in which FEOL transistors having gate oxides having a minimum specified thickness are formed; forming a BEOL ILD stack having interconnect structures on the wafer substrate; selectively etching openings extending at least partially downward through the BEOL ILD stack; filling the etched openings with at least a deposition of aluminum to form a plurality of aluminum via structures and aluminum crack stop structures extending at least partially downward through the BEOL ILD stack from a top surface of the BEOL ILD stack; and partially recessing a bottom surface of the wafer substrate layer to at least expose the aluminum crack stop structures.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor devices. In one aspect, this disclosure relates to integrated circuit interposers for electrically connecting integrated circuit dies or modules to electrical devices. Background Technology

[0002] Modern integrated circuits (ICs) typically have conductor structures formed in multiple interlayer dielectric (ILD) layers to provide conductive interconnects that provide electrical connections to and from circuitry formed on the IC substrate. These conductors can be used to transmit information in the form of signals sent to and from the IC formed on the underlying substrate. Additionally, conductor structures can be formed in the ILD layers to provide other circuit elements, such as capacitor plates electrically connected to the circuitry formed on the IC substrate. After forming the circuitry on the substrate during front-end process (FEOL) processing, existing copper metallization techniques for semiconductor wafer fabrication form interlayer conductor structures in a series of ILD layers by patterning and etching each ILD layer to form etched openings, depositing and / or filling each etched opening with one or more conductive layers, and then applying chemical mechanical planarization (CMP) or polishing steps to remove the conductive layers from outside the etched openings.

[0003] As technology shrinks and power consumption increases, the decrease in interconnect resistance (IR) across conductive interconnect layers becomes a critical issue for designs using wire-bonded packages. When power demands become excessive, the amount and thickness of the final metallization of patterned aluminum (ALUCAP) in the die interconnect may increase, and / or flip-chip packaging should be used, but such solutions increase die and package costs. Other solutions to meet increased power requirements include forming copper pillar conductors in an internal region of the die, which make direct electrical contact with circuit elements on the die via interconnects (rather than "lateral" connections from die pads on the outer periphery). While these power delivery solutions may be feasible for older technology nodes, the required rules for metal, via lines, and space for designing other circuit connections for more advanced nodes can cause significant congestion problems. For example, more advanced nodes are fabricated using critical and very expensive silicon technologies to meet optical constraints caused by double and triple patterning and the uniformity requirements of such advanced node devices. On the other hand, as technology nodes advance, the number of power and ground transmission connections increases non-linearly, and the resistance of the wires and vias also increases non-linearly. While some solutions have been proposed to address the power delivery challenges at more advanced nodes by forming copper through-silicon via (TSV) structures that pass through the completed back-end process (BEOL) stack, stress from the copper via structures can cause silicon to disconnect from the model, which can lead to significant shifts in the threshold voltage Vt and mobility of core devices, especially RF / analog devices.

[0004] As can be seen from the foregoing, existing IC device designs and manufacturing processes do not offer a power delivery solution that connects top-side aluminum metal to front-end process (FEOL) devices while avoiding the resistance and space constraints required for front-end IC devices. Furthermore, existing advanced node technologies suffer from potential product delays due to product redesign and tapeout delays if any density and layout constraints are not met, or if the foundry makes later changes to the rules. Other limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art after reviewing the remainder of this application with reference to the accompanying drawings and detailed description. Summary of the Invention

[0005] As described above, this disclosure provides a mechanism for integrating conductive via structures and sealing ring / crack arrest structures into an interposer structure that includes only non-core device components (e.g., thick gate oxide transistors and / or radio frequency (RF) components), allowing core device components (e.g., advanced node core transistors or memory transistors) to be formed in advanced node high-cost, high-speed silicon dies. By utilizing a single aluminum deposition step to form the disclosed conductive via structures and sealing ring / crack arrest structures in a low-cost interposer structure, the wafer cost and cycle time for fabricating the interposer structure are significantly reduced because there are no threshold voltages or critical patterning constraints for the interposer structure. Furthermore, the number of BEOLILD layers used in the interposer structure is minimized to accommodate non-core device components formed within the interposer structure, such as I / O transistors, capacitors, inductors, transmission lines, and baluns. Shorter BEOLILD stacks also further reduce costs and improve mechanical stability by fabricating conductive vias, sealing ring structures, and TSV copper pillar pads within the BEOLILD stack of the interposer structure. Additionally, the manufacturing cost of the core device IC can be reduced by using fewer metal layers. Furthermore, using a silicon-based interposer structure helps prevent some CTE mismatch stresses.

[0006] It should now be understood that this document provides a packaged component and an associated manufacturing method. In the disclosed method, a semiconductor interposer structure is formed, the semiconductor interposer structure including a back-end process (BEOL) interlayer dielectric (ILD) stack formed over a silicon substrate, in which a plurality of front-end process (FEOL) integrated circuit (IC) transistor devices are formed, the plurality of FEOL IC transistor devices having one or more gate dielectric layers having a specified minimum thickness, wherein the BEOL ILD stack includes a plurality of conductive interconnect structures extending through the BEOL ILD stack and a plurality of aluminum via structures and aluminum crack arresters extending at least partially downward through the BEOL ILD stack from the top surface of the BEOL ILD stack. In a selected embodiment, the semiconductor interposer structure is formed by: forming at least partially the plurality of FEOL IC transistor devices in the silicon substrate; forming the BEOL ILD stack above the plurality of FEOL IC transistor devices and the silicon substrate; selectively etching a plurality of etched openings that extend at least partially downward from the top surface of the BEOL ILD stack through the BEOL ILD stack; and filling the plurality of etched openings with at least deposited aluminum to form the plurality of aluminum via structures and aluminum crack arrest structures. In a selected embodiment, the BEOL ILD stack is formed to have capacitor structures and / or inductor structures within the BEOL ILD stack. In other selected embodiments, selectively etching the plurality of etched openings includes: selectively etching one or more deep trench through-substrate via openings extending through the BEOL ILD stack and the silicon substrate; selectively etching one or more partial trench through-hole openings extending from the top surface of the BEOL ILD stack and extending only partially downward through the BEOL ILD stack; and selectively etching deep trench anti-crack openings extending through the BEOL ILD stack and the silicon substrate. In other selected embodiments, filling the plurality of etched openings includes: depositing a barrier liner layer to conformally cover the sidewalls and bottom surface of the plurality of etched openings; depositing aluminum to fill the plurality of etched openings; and applying a top-side polishing step to substantially planarize the deposited aluminum and barrier liner layer with respect to the top surface of the BEOL ILD stack. The disclosed method also includes attaching one or more core device integrated circuit devices to a first surface of the semiconductor interposer structure, each core device integrated circuit device having a plurality of core transistors having one or more gate dielectric layers having a specified maximum thickness less than or less than the specified minimum thickness. In selected embodiments, the disclosed method further includes attaching a printed circuit board to a second opposing surface of the semiconductor interposer structure.In selected embodiments, the specified maximum thickness of the one or more gate dielectric layers in the plurality of core transistors is about 40 angstroms, and the specified minimum thickness of the one or more gate dielectric layers in the plurality of FEOL IC transistor devices is at least about 50 angstroms. In selected embodiments, the disclosed method may further include forming a passivation layer over the BEOLILD stack before or after selectively etching one or more deep trench through-substrate via openings.

[0007] In another embodiment, an interposer structure and an associated manufacturing method are provided. In the disclosed method, a semiconductor interposer wafer substrate is provided having a plurality of front-end process (FEOL) integrated circuit (IC) transistor devices, the plurality of FEOL IC transistor devices having a gate oxide with a minimum thickness of approximately 50 angstroms. The disclosed method further includes forming a back-end process (BEOL) interlayer dielectric (ILD) stack over the semiconductor interposer wafer substrate, the BEOLILD stack having a plurality of conductive interconnect structures extending through a plurality of interconnect levels in the BEOLILD stack. In selected embodiments, forming the BEOLILD stack further includes forming capacitor structures and / or inductor structures in the BEOLILD stack. The disclosed method further includes selectively etching a plurality of etch openings that extend at least partially downward from the top surface of the BEOLILD stack through at least the top interconnect level of the BEOLILD stack. In selected embodiments, selectively etching the plurality of etched openings includes: selectively etching one or more deep trench through-substrate via openings extending through the BEOLILD stack and the semiconductor interposer wafer substrate; selectively etching one or more partial trench through-hole openings extending from the top surface of the BEOL ILD stack and extending only partially downward through the BEOL ILD stack; and selectively etching deep trench crack arrest openings extending through the BEOL ILD stack and the semiconductor interposer wafer substrate. In selected embodiments, a single etch mask with patterned openings of different sizes can be used to selectively etch the deep trench through-substrate via openings, partial trench through-hole openings, and deep trench crack arrest openings in a single deep RIE etch step. In other selected embodiments, multiple separate etch masks and RIE etch steps can be used sequentially to selectively etch the deep trench through-substrate via openings, partial trench through-hole openings, and deep trench crack arrest openings using separate deep RIE etch steps. In selected embodiments, a passivation layer is formed on the top surface of the BEOL ILD stack before selectively etching the plurality of etched openings. Additionally, the disclosed method includes filling the plurality of etched openings with at least deposited aluminum to form a plurality of aluminum via structures and aluminum crack arrest structures extending at least partially downward through the top surface of the BEOL ILD stack. In a selected embodiment, the plurality of etched openings may be filled by: depositing a barrier liner layer to conformally cover the sidewalls and bottom surface of the plurality of etched openings; depositing aluminum to fill the plurality of etched openings; and applying a top-side polishing step to substantially planarize the deposited aluminum and barrier liner layer with the top surface of the BEOL ILD stack.In selected embodiments, a passivation layer is formed on the top surface of the BEOL ILD stack and on the sidewalls and bottom surfaces of the plurality of etched openings before filling the plurality of etched openings. The disclosed method also includes partially recessing the bottom surface of the semiconductor interposer wafer substrate to at least expose the aluminum crack arrestor structure. In selected embodiments, the disclosed method may further include cutting through the aluminum crack arrestor structure in the BEOL ILD stack and the semiconductor interposer wafer substrate to isolate a plurality of FEOL IC transistor devices in the interposer structure. In selected embodiments, the bottom surface of the semiconductor interposer wafer substrate is partially etched by performing a back-side etching or polishing step to thin the semiconductor interposer wafer substrate and at least expose the aluminum crack arrestor structure. In selected embodiments, the disclosed method may further include attaching a core device integrated circuit device to the bottom surface of the semiconductor interposer wafer substrate, forming a plurality of core transistor devices having gate oxides having a maximum thickness of about 10-40 angstroms in the core device integrated circuit device. In selected embodiments, chip-to-chip bonding can be used to attach the core device integrated circuit device to the bottom surface of the semiconductor interposer wafer substrate.

[0008] In another embodiment, an electronic device and an associated method of manufacturing are provided. As disclosed, the electronic device includes a semiconductor interposer structure having a back-end process (BEOL) interlayer dielectric (ILD) stack above a silicon substrate, in which a plurality of front-end process (FEOL) integrated circuit (IC) transistor devices having gate oxides having a specified minimum thickness are formed. The BEOL ILD stack includes a plurality of conductive interconnect structures extending through a plurality of interconnect levels in the BEOL ILD stack, and a plurality of aluminum via structures and aluminum crack arresters extending at least partially downward from the top surface of the BEOL ILD stack through at least a first interconnect level of the BEOL ILD stack. Additionally, the disclosed electronic device includes a plurality of first interconnect conductors located on a first surface of the semiconductor interposer structure and electrically contacting the plurality of aluminum via structures. The disclosed electronic device also includes a plurality of second interconnect conductors located on a second surface of the semiconductor interposer structure and electrically contacting the plurality of aluminum via structures. Additionally, the disclosed electronic device includes one or more core device integrated circuit devices attached to a first or second plurality of interconnect conductors, wherein each core device integrated circuit device includes a plurality of core transistors having a gate oxide having a specified maximum oxide thickness less than a specified minimum thickness. In a selected embodiment, each of the plurality of core transistors has a gate oxide thickness less than about 40 angstroms, and each of the plurality of FEOL IC transistor devices has a gate oxide thickness greater than about 50 angstroms. Attached Figure Description

[0009] Many objectives, features, and advantages of the invention and its implementation will be understood when the following detailed description of preferred embodiments is considered in conjunction with the following figures.

[0010] Figure 1 A cross-sectional view of an interposer structure connected to a core device chip according to a selected embodiment of the present disclosure is shown.

[0011] Figure 2-8 A cross-sectional view is shown of a series of steps according to a first selected embodiment of the present disclosure for manufacturing an intermediary structure having fully and partially stacked aluminum through-hole structures and sealing ring / crack arrest structures formed in a BEOL ILD / interconnect layer.

[0012] Figure 9-14 A cross-sectional view is shown of a series of steps for manufacturing an interlayer structure having fully and partially stacked aluminum sealing rings / crack arrest structures and through holes formed in an alternative selected embodiment of the present disclosure. Detailed Implementation

[0013] A process for manufacturing integrated circuit (IC) devices is described, wherein an interposer structure includes selected non-core device components (e.g., thick gate oxide transistors and / or radio frequency (RF) elements) and a full back-to-the-line (BEOL) interconnect stack formed in an interposer substrate. The BEOL interconnect stack has via structures and sealing ring / crack arrestor structures formed in the full BEOL interconnect stack by selectively etching deep trench openings to one or more predetermined depths and then filling the deep trench openings with a barrier liner layer and deposited aluminum to form aluminum via structures and sealing ring / crack arrestor structures. By forming a low-cost interposer structure to include non-core device components, selected core device components (e.g., advanced node core transistors or memory transistors) can be formed in advanced node high-cost silicon high-speed dies connected to the low-cost interposer structure via suitable conductors. In selected embodiments, the interposer structure is formed to include only non-core device components, such as thick gate oxide devices with a minimum specified gate oxide thickness (e.g., 50-200 angstroms), capacitors, inductors, and / or radio frequency (RF) passive devices, but not any core device components, such as advanced node core transistors or memory transistors. In such embodiments, the advanced node high-cost silicon high-speed die is formed to include only core device components, such as advanced node core transistors or memory transistors with a smaller maximum specified gate oxide thickness (e.g., 20-40 angstroms). In this way, the functional circuitry is partitioned between the low-cost interposer structure and the advanced node high-cost silicon high-speed die, resulting in a significant reduction in wafer cost and cycle time of the interposer structure by providing aluminum via structures and sealing ring / crack arrestor structures in the interposer structure that do not require design protection against threshold voltage and critical patterning. Additionally, by forming aluminum via structures and sealing ring / crack-stop structures in the interposer structure, non-core device components (e.g., thick gate oxide transistors, input / output transistors, capacitors, large-area inductors, and / or other RF passive devices) with a minimum number of BEOL interconnect stacks can be formed on the interposer structure. According to this disclosure, the interposer structure may include transistors with varying gate oxide thicknesses exceeding a minimum oxide thickness, or it may include all transistors with the same thick gate oxide thickness.

[0014] This disclosure describes an improved IC structure and manufacturing method for forming conductive via structures and sealing ring / crack-stop structures in a full BEOL interconnect stack of an interposer structure to facilitate a low IR drop interposer structure that hosts IC device components that would otherwise interfere with the fabrication of high-performance IC device components formed on a shared semiconductor substrate, thereby solving various problems in the art. Various limitations and disadvantages of conventional solutions and techniques will become apparent to those skilled in the art after reading the remainder of this application with reference to the accompanying drawings and the detailed description provided herein. Various illustrative embodiments of the invention will now be described in detail with reference to the accompanying drawings. While various details are set forth in the following description, it should be understood that the invention can be practiced without these specific details, and many implementation-specific decisions can be made regarding the invention described herein to achieve specific device designer objectives, such as compliance with process technology requirements or design-related constraints that may vary from implementation to implementation. While such research and development may be complex and time-consuming, it is merely a routine task for those skilled in the art who will benefit from this disclosure. For example, selected aspects are depicted with reference to simplified cross-sectional views of a semiconductor device, but not every device feature or geometry is included to avoid limiting or obscuring the invention. Such descriptions and representations are commonly used by those skilled in the art to describe and convey the gist of their work to others skilled in the art. It should also be noted that throughout this specific embodiment, certain elements are shown in the figures for simplicity and clarity and are not necessarily drawn to scale. Additionally, the dimensions of some elements in the figures may be enlarged relative to other elements to aid in understanding embodiments of this disclosure. Furthermore, reference numerals have been repeated in the figures to denote corresponding or similar elements. Additionally, the depicted device layers shown as being deposited and / or etched are represented by simplified line drawings; however, it should be understood that in practice, the actual profile or dimensions of the device layers will be non-linear, for example, when the described etching process is applied at different rates to different materials, or when the described deposition or growth process generates layers based on the underlying material.

[0015] To better understand selected embodiments of this disclosure, reference is now made to Figure 1The figure depicts a simplified cross-sectional view of an integrated circuit package assembly 1, which includes one or more core device integrated circuits 30 attached or mounted to an interposer structure 32 using first-level interconnects 31, details of which are described more fully below. When implemented as a flip-chip package, the first-level interconnects 31 connecting the discrete core device IC chips 30 to the interposer structure 32 can be implemented as copper pillars, solder balls, conductive rails, or any other standard attachment method. Additionally, the interposer structure 32 is attached to one or more second-level interconnects 33 for connecting the interposer structure 32 to external circuitry, such as a printed circuit board (not shown). As depicted, the core device IC chips 30 are positioned and arranged with upward-facing patterned conductors for alignment with the first-level interconnects 31, which are in turn positioned and arranged for alignment with downward-facing patterned conductors attached to the interposer 32. For example, the first-level interconnect 31 can be implemented using an array of conductive die rails aligned and positioned to provide direct electrical connection between the core device IC chip 30 and the interposer 32. However, it should be understood that the core device IC chip 30 can be positioned and arranged with downward-facing patterned conductors for alignment and attachment above the interconnects to the top of the interposer 32, which in turn is positioned and arranged for alignment and attachment above the interconnects on the bottom of the interposer 32. Although not shown, it should be understood that redistribution (RDL) stack layers can be formed on the upper surface of the core device IC 30 and / or the bottom surface of the interposer 32 to provide a fine-pitch wiring layer.

[0016] Reference Figure 1-14 Various illustrative embodiments of the invention are described in detail. Furthermore, although specific example materials, thicknesses, and processes are described herein, those skilled in the art will recognize that other materials, thicknesses, and processes having similar properties or characteristics can be substituted without loss of functionality. It should be noted that throughout this detailed description, certain material layers will be deposited and removed to form an intermediate layer structure. Where specific procedures for processing such layers or the thickness of such layers are not detailed below, it is contemplated that techniques conventional to those skilled in the art will be used to deposit, remove, form, or otherwise process such layers at appropriate thicknesses. Such details are well known and are not to be considered necessary to teach those skilled in the art how to make or use the invention.

[0017] To better understand selected embodiments of this disclosure, reference is now made to Figure 2-14 These figures illustrate a series of cross-sectional views at different stages of fabricating an intermediate layer structure with fully and partially stacked aluminum through-hole structures and sealing ring / crack arrest structures formed in the BEOL ILD / interconnect layer. Specifically, Figure 2A cross-sectional view is shown of a portion of an interposer structure 2 that can be formed as part of a semiconductor wafer, wherein one or more BEOL interlayer dielectric (ILD) layers 14 are formed over an interposer semiconductor substrate 10, in which one or more thick gate oxide IC devices or elements 13 are fabricated using FEOL wafer processing steps. It should be understood that the FEOL thick gate oxide IC device or element 13 may include one or more transistors, resistors, capacitors, diodes, or other semiconductor components formed on or within the semiconductor substrate 10 using any suitable semiconductor material or combination of materials (e.g., gallium arsenide, gallium nitride, silicon germanium, semiconductor-on-insulator (SOI), strained semiconductor-on-insulator (SSOI), silicon, single-crystal silicon, etc.). As depicted, a transistor may include gates G1, G2 and one or more relatively thick gate dielectric or oxide layers having a first minimum thickness (e.g., 50-200 angstroms) formed over the interposer semiconductor substrate 10, wherein source / drain (S / D) regions and channel regions are formed in an n-well 11 or a p-well 12. Additionally, transistors can be isolated from each other via isolation regions (ISOs). Typically, such thick gate oxide devices are used for high-voltage transistors, such as I / O transistors, but the interposer structure 2 can include any slower-operating circuit components, such as static random access memory (SRAM), read-only memory (ROM), electrically programmable ROM (EPROM) devices, electrically programmable fuses, etc. In other words, the interposer structure 2 can include any circuit components that do not require high-speed operation and / or require thin gate oxide devices.

[0018] Above the IC element, one or more BEOL ILD layers 14 can be formed using any suitable insulating material to separate and define the patterned conductive metal lines or layers M1-Mn and vias V1-Vn formed therein. As depicted, multiple patterned conductive metal lines or layers M1-Mn and vias V1-Vn can be vertically stacked or otherwise electrically connected together to create conductive paths for transmitting signals or power through the BEOL ILD layers 14 to the FEOL thick gate oxide IC device or element 13, wherein the patterned conductive metal lines and via structures in each level are formed in the interlayer dielectric layer of said level. Although the stacked BEOL ILD layers 14 are depicted as a vertical stack including patterned conductive metal lines and via structures in levels 1-n, it should be understood that this is a simplified illustration and other conductive paths can be established in the stacked BEOL ILD layers 14. It should also be understood that additional elements can be included at each layer of the stacked BEOL ILD layers 14. For example, the etch stop layer (ESL) 26 can be formed and positioned in the first ILD layer with a suitable etch stop material (e.g., metal or other suitable etch stop material) such that subsequent dielectric etch processes applied to the stacked BEOL ILD layer 14 will terminate at the ESL 26.

[0019] As should be understood, one or more IC elements can be formed in BEOL ILD layer 14 by patterned conductive metal lines. For example, IC capacitor elements, such as decoupling capacitors, can be formed in the final metal layer Mn by depicted capacitor elements C1-C3. Alternatively, IC inductor elements, such as large-area inductors, can be formed by patterned conductive metal lines or conductive inductor elements (not shown) in layers. Generally, any RF passive device can be formed in the stack of BEOL ILD layers 14 by patterned conductive metal lines or layers.

[0020] After the stacking of the BEOL ILD layers 14 is completed, a passivation layer 15 is formed above the top surface of the BEOL ILD layers 14. While any suitable fabrication process can be used, one or more suitable dielectric passivation layers (e.g., polyimide, SiN, SiC, SiCN, SiON, SiO) can be deposited. x Si x N y SiCON, aC, or combinations and variations thereof, some of which may also be fluorinated, are used to form a passivation layer 15 to a predetermined thickness. At this point in the manufacturing process, conductive pillar conductors, such as the final terminating aluminum layer, have not yet been formed above the interlayer structure 2 for connection to the buried conductor formed in the BEOL ILD layer 14.

[0021] Figure 3 Selected embodiments according to this disclosure are shown. Figure 2 The intermediate layer structure 3 is then processed after the passivation layer 15 is patterned using a patterned etch mask or photoresist (PR) layer 16A-C, wherein the patterned etch mask openings 17A-D expose the top surface of the passivation layer 15. While any suitable photoresist patterning process can be used, the patterned photoresist mask 16A-C can be formed on the passivation layer 15 by depositing, patterning, etching, or developing a photoresist layer made of any material suitable for photolithography. For example, the patterned photoresist mask 16A-C can be formed by: coating the passivation layer 15 with a photosensitive organic material; applying a light source, wherein a light-blocking patterned mask is present above the surface of the wafer substrate, such that only the unmasked areas of the material are exposed to light; and applying a solvent to develop the material, such that the photosensitive material, degraded by light and developer, dissolves the light-exposed areas, leaving the PR coating 16A-C with the mask placed and the etch mask openings 17A-D with the coating removed. In this manner, the patterned photoresist mask 16A-C includes defined openings 17A-D that expose the underlying passivation layer 15 at intended etch locations for fully and partially stacked via structures, and sealing ring / crack arrest structures are formed at designated locations in the BEOL ILD 14. In selected embodiments, the patterned etch mask openings 17A-D may extend substantially above the top surface of the interposer structure 3. In other embodiments, the patterned etch mask openings 17A-D may define openings of any desired size or shape (e.g., vias of 2×2 μm or 3×3 μm size) for the ultimately formed fully and partially stacked via structures and sealing ring / crack arrest structures.

[0022] Figure 4 Selected embodiments according to this disclosure are shown. Figure 3The intermediate layer structure 4 is then processed by selectively etching openings 19A-D through the stack of passivation layer 15 and underlying BEOL ILD layer 14 exposed by etch mask openings 17A-D in patterned photoresist masks 16A-C. As those skilled in the art will understand, the selective etching process can use any suitable anisotropic etching process 18 to form the etch openings 19A-D, which extend through the stack of passivation layer 15 and underlying BEOL ILD layer 14 to a predetermined depth. For example, when the patterned photoresist masks 16A-C are defined as including etch mask openings 17A-D with wider width dimensions for etch openings 19A, 19C, 19D and narrower width dimensions for etch opening 19B, a single deep reactive ion etching (RIE) step 18 with suitable etching chemistry can be applied to remove exposed portions of the underlying BEOL ILD layer 14 stack to form etch openings 19A-D with different depths, as shown, wherein the depth of each etch opening 19A-D is based on the relative size of the width dimensions of the etch mask openings 17A-D. Since the aim is to form conductive TSVs / pillars at selected locations (e.g., 19C) in the deep trench etch openings 19A-D, the diameter of such deep trench etch openings 19C can be limited to the extent that they can be completely filled by one or more subsequent metal (e.g., aluminum) deposition steps.

[0023] In an exemplary embodiment, a controlled etching process 18, such as timed anisotropic dry etching, can be applied to form high aspect ratio openings 19A-D. Alternatively, as shown by the dashed lines of patterned photoresist masks 16A-C, separate patterned etch masks and deep RIE etching steps can be applied to define relatively shallow etched openings 19B and relatively deep etched openings 19A, 19C-D. In yet another embodiment, an etch stop layer (ESL) 26 formed in the stacked BEOL ILD layer 14 can be used to terminate the progress of the etching process 18, such that the depth of the etched opening 19B is controlled. As disclosed herein, ESL 26 can be formed with any suitable etch stop material (e.g., metal or other suitable etch stop material) such that the etching process 18 terminates at ESL 26. Although the sidewalls of the etched openings 19A-D are shown as substantially vertical, it should be understood that slight deviations in the sidewall profiles may occur due to variations in the etching process. It should also be understood that the location of via openings 19B-C is not necessarily constrained to be adjacent to the continuous patterned metal layers shown, nor is the absence of metal interaction required. The patterned metal layers in BEOL ILD layer 14 can be used to obstruct, constrain, or connect to the fully stacked vias as required by optimal circuit design. Finally, etched openings 19A-D are depicted as being formed at different levels of the six-metal layer stack in BEOL ILD layer 14, but it should be understood that additional or fewer metal layers can be used in the interposer structure 4.

[0024] Figure 5 Selected embodiments according to this disclosure are shown. Figure 4The subsequent processing of the interposer structure 5 involves stripping the patterned photoresist mask 16A-C and filling the etched openings 19A-D with one or more deposited metal layers 20A-D. While any suitable fabrication process can be used, the etched openings 19A-D can be filled with any suitable sequence of steps 20, including depositing a barrier film layer and an aluminum filler layer followed by a top-side polishing step to planarize the deposited metal layers 20A-D with the passivation layer 15. For example, the etched openings 19A-D can be filled by first depositing a conductive barrier film or liner layer of any suitable diffusion barrier material (e.g., Ti, TiN, Ta, TaN, TiN, TiC, TaC, CuWP, etc.) above the top surface of the interposer structure 5 and along the inner sidewalls of the etched openings 19A-D, which also allows for electrodeposition. On the conductive barrier film / liner layer, the remaining portions of the etched openings 19A-D can then be filled with a metallic material, for example, by using electroplating, electroless plating, or depositing aluminum to fill the etched openings 19A-D (but in other embodiments, other suitable conductive materials (e.g., Cu, Co, Ni, Mn, Mg, Zn, etc.)) to form a deposited metal layer 20A-D. The electroplating process can be controlled to provide bottom-up plating, such that the metallic material is formed only on the horizontal surface to cover the bottom of the etched openings and to make direct electrical contact with any exposed underlying conductive metal layer in the BEOL ILD layer 14. The deposited metal layer 20A-D can then be planarized using a top-side polishing step, for example, by using a chemical mechanical polishing (CMP) planarization process. In other embodiments, the deposited metal layer 20A-D can be patterned and selectively etched to form aluminum pillars or struts extending over the passivation layer 15.

[0025] Figure 6 Selected embodiments according to this disclosure are shown. Figure 5 The subsequent processing of the interposer structure 6 after performing back-side etching or polishing step 21. While any suitable manufacturing process can be used, back-side etching process 21 can be applied, for example by applying one or more thinning etching processes to planarize the interposer substrate 10 with the metal layers 20A, 20C-D, to expose the deeper metal layers 20A, 20C-D on the back surface of the etched interposer substrate 10. In other embodiments, back-side etching process 21 can use a chemical mechanical polishing (CMP) planarization process to thin the interposer substrate 10 and expose the metal layers 20A, 20C-D. In any case, back-side etching or polishing step 21 can be applied to thin the interposer substrate 10 until it reaches the bottom of the metal layers 20A, 20C-D, or back-side etching or polishing step 21 can be applied to etch the interposer substrate 10 and the bottom of the metal layers 20A, 20C-D into a thinner planarized substrate structure.

[0026] Figure 7Selected embodiments according to this disclosure are shown. Figure 6 The subsequent processing of the interposer structure 7 after the formation of the second-level interconnects. At this point in the manufacturing process, the outer metal layers 20A and 20D formed on the outer periphery of the interposer substrate 10 are part of a continuous or segmented crack-stop or edge-sealing ring 22. The crack-stop or edge-sealing ring 22 surrounds the internal circuit structure of the interposer structure 6 to increase crack resistance during the slitting of the semiconductor wafer in which the interposer structure 5 is formed. Additionally, the inner metal layer 20B is an example of a conductive spike via 23 that partially extends into the BEOL ILD layer 14 to contact one or more patterned metal layers. Additionally, the inner metal layer 20C is an example of a conductive through-substrate via (TSV) 24 extending through the entire BEOL ILD layer 14. A second-level interconnect structure, such as a C4 bump, copper pillar pads and solder caps, under-bump metallization, etc., can be formed at the top of the interposer 7 in contact with the conductive TSV 24. For example, a second-level interconnect can be fabricated by forming a patterned under-bump metallization (UBM) layer 27 having one or more conductive layers to contact and cover the conductive TSV 24, for example by depositing, patterning, and etching one or more conductive layers over the interposer structure 7. On the UBM layer 27, metal pillars or posts 28 can be fabricated, for example by forming a patterned polymer layer (not shown) over the interposer structure 7 using an opening above the UBM layer 27, and then depositing, etching, or polishing one or more conductive layers (e.g., copper) over the interposer structure 7 to form the metal pillars 28. On the metal pillars 28, solder ball connectors 29 can be formed using any suitable bump flow. Of course, it should be understood that alternative structures and manufacturing sequences exist for forming the second-level interconnect structure.

[0027] To better understand selected embodiments of this disclosure, reference is now made to Figure 8The figure depicts a simplified cross-sectional view of an integrated circuit package assembly 8 after one or more core device integrated circuits 34 are attached or mounted to an interposer structure 36 via first-level interconnects 35. When implemented as a flip-chip package, the core device IC 34 is connected to a printed circuit board 37 using conductive element paths defined in the interposer structure 36. Specifically, the core device IC 34 is attached to a first or bottom surface of the interposer structure 36 using a set of first-level interconnects 35 (e.g., solder bumps or microbump conductors). Similarly, a second or top surface of the interposer structure 36 is attached to the printed circuit board 37 using a set of second-level interconnects 27-29 (e.g., copper pillar solder balls or bumps). During formation, the interposer structure 35 is configured to include only non-core device components, such as thick gate oxide devices with a minimum specified gate oxide thickness (e.g., 50-200 angstroms), capacitors, inductors, and / or radio frequency (RF) passive devices, but not any core device components, such as advanced node core transistors or memory transistors. Additionally, the core device IC 34 is configured to include only core transistor components, such as advanced node core transistors or memory transistors with a relatively small maximum specified gate oxide thickness (e.g., about 20-40 angstroms). For example, a core transistor component with a gate dielectric layer thickness of about 40 angstroms may have one or more high-k gate dielectric layers formed. Alternatively, or in an alternative, a core transistor component with a gate dielectric layer thickness of about 20 angstroms may have one or more non-high-k gate dielectric layers formed. In selected embodiments, the gate dielectric layer of the core transistor may be formed as a dielectric layer stack, such as a bottom gate dielectric interface layer formed with a non-high-k dielectric material and an upper gate dielectric layer formed with a high-k dielectric material (e.g., hafnium oxide (HfO2)).

[0028] As disclosed herein, the use of a silicon-based interposer substrate 10 to form the interposer structure 36 allows the thick gate oxide transistor device 13 to be formed on the interposer structure 36 instead of on the core device IC 34. This has the advantage of reducing wafer costs and design cycle time for fabricating the interposer structure 36, because when only the thick gate oxide transistor device 13 is formed in the interposer structure 36, there are no design constraints on threshold voltage and critical patterning. Furthermore, this allocation of the thick gate oxide transistor device 13 in the interposer structure 36 and the thin gate oxide device in the core device IC 34 means that the interposer structure 36 can be formed with a minimal number of BEOL layers to accommodate any I / O device, decoupling capacitor, or RF device, such as a large-area inductor. This may be more important when the core device IC 34 is formed using advanced techniques, such as full gate-around transistors, which do not include thick gate oxide FETs formed with thick gate oxide, nor do they include voltage levels higher than the core. In the context of this disclosure, it should be understood that the core voltage level refers to the permissible voltage of a transistor having a thin gate oxide with a thickness not exceeding the maximum thickness of the core device IC. Furthermore, using a single aluminum deposition step to form the sealing ring structures 22, 25, spike via 23, and through-substrate via copper pillar pads 24 provides cost savings and mechanical stability for the interposer structure 36, regardless of the number of ILD layers in the BEOL stack 14. Another advantage of moving the thick gate oxide device 13, capacitors, and other RF passive devices to the interposer structure is that advanced node chip designs for the core device IC 34 can use fewer BEOL metal layers, thereby reducing the manufacturing cost of the core device IC 34. Additionally, using a silicon-based interposer substrate 10 helps prevent some CTE mismatch stresses.

[0029] like Figure 8 As shown, by controlling the depth of the etched openings 19B in which the conductive barrier film and aluminum filler layers are deposited, the aluminum via structure 23 formed in the stack of BEOL ILD layers 14 can terminate at the BEOL, MEOL, and FEOL layers. Alternatively, the aluminum via structure 24 formed in the stack of BEOL ILD layers 14 can terminate in or extend through the silicon-based interposer substrate 10. Similarly, the aluminum crack-stopping / edge-sealing structures 22 and 25 can extend through the stack of BEOL ILD layers 14 and the silicon-based interposer substrate 10.

[0030] To better understand selected embodiments of this disclosure, reference is now made to Figure 9-14 These figures illustrate a series of cross-sectional and planar views of intermediate layer structures using a passivation layer as the polishing endpoint layer at different manufacturing stages. Specifically, Figure 9A cross-sectional view is shown of a portion of an interposer structure 9 that can be formed as part of a semiconductor wafer, wherein one or more BEOL interlayer dielectric (ILD) layers 14 are formed over an interposer semiconductor substrate 10, in which one or more thick gate oxide IC devices or elements 13 are fabricated using FEOL wafer processing steps. In the depicted fabrication stage, the interposer structure 9 is similar to... Figure 2 The details of the interposer structure 2 shown herein will not be repeated for the interposer substrate 10, the thick gate oxide IC devices or elements 11-13, and the BEOL ILD layer 14. However, the interposer structure 9 does not include the passivation layer 15 on the stack of the BEOL ILD layer 14. Alternatively, according to a selected embodiment of this disclosure, a patterned etch mask or photoresist (PR) layer 40A-C is formed on the stack of the BEOL ILD layer 14, wherein the patterned PR layer 40A-C includes patterned etch mask openings 41A-D to expose the top surface of the BEOL ILD layer 14. As disclosed herein, the patterned photoresist mask 40A-C can be formed using any suitable photoresist patterning process, such as depositing, patterning, etching, or developing a photoresist layer formed from any material suitable for photolithography. During formation, patterned photoresist masks 40A-C expose the stack of BEOL ILD layers 14 at the intended etch locations for full and partial stacked via structures and sealing ring / crack arrest structures.

[0031] Figure 10 Selected embodiments according to this disclosure are shown. Figure 9The intermediate layer structure 10 is then processed by applying etching process 42 to selectively etch openings 43A-D through the stack of underlying BEOL ILD layers 14 exposed by etch mask openings 41A-D in patterned photoresist masks 40A-C, after which the openings 43A-D are etched. As disclosed herein, etching process 42 can be used with any suitable anisotropic etching process to form the etch openings 43A-D extending through the stack of underlying BEOL ILD layers 14 to a predetermined depth. For example, a single deep reactive ion etching (RIE) step 42 can be applied to patterned photoresist masks 40A-C having defined etch mask openings 41A-D having a wider width dimension for etch openings 43A, 43C, 43D and a narrower width dimension for etch opening 43B, wherein the depth of each etch opening 43A-D is based on the relative size of the width dimensions of the etch mask openings 41A-D. Alternatively, as shown by the dashed lines of the patterned photoresist masks 40A-C, separate patterned etch masks and deep RIE etch steps can be applied to define relatively shallow etch openings 43B and relatively deep etch openings 43A, 43C-D. In yet another embodiment, an etch stop layer (ESL) 26 formed in the stacked BEOLILD layer 14 can be used to stop the progress of the etch process 42, thereby controlling the depth of the etch opening 43B.

[0032] Figure 11 It shows Figure 10 The subsequent process involves the removal of the patterned photoresist mask 40A-C and the formation of a passivation layer 44 above the top surface of the BEOL ILD layer 14, followed by the treatment of the intermediate layer structure 11. As disclosed herein, this can be achieved through any suitable fabrication process, such as by depositing one or more suitable dielectric passivation layers (e.g., polyimide, SiN, SiC, SiCN, SiON, SiO). x Si x N y SiCON, aC, or combinations and variations thereof, some of which may also be fluorinated, are used to form a passivation layer 44 to a predetermined thickness. During deposition, the passivation layer 44 covers the top of the interposer structure 11 and coats the inner sidewalls and bottom of the etched openings 43A-D.

[0033] Figure 12 Selected embodiments according to this disclosure are shown. Figure 11The intermediate layer structure 12 is then processed by applying a series of steps 45 to fill the etched openings 43A-D with one or more deposited metal layers 45A-D. As disclosed herein, the metal layers 45A-D can be formed using any suitable fabrication process step 45, such as by depositing a barrier film layer and an aluminum filler layer, followed by a top-side polishing step to planarize the deposited metal layers 45A-D with the passivation layer 44 formed on top of the BEOL ILD layer 14. For example, the metal layers 45A-D can be formed by depositing TiN as a conformal barrier diffusion liner layer along the inner sidewall of the etched openings 43A-D, then depositing aluminum on the conductive barrier diffusion liner layer to fill the etched openings 43A-D, followed by a top-side polishing step, for example by using a chemical mechanical polishing (CMP) planarization process to planarize the deposited metal layers 45A-D.

[0034] although Figure 12 It is shown that all etched openings 43A-D are lined with a passivation layer 44 before the formation of the conductive barrier film and aluminum filler layers 454A-D, but in selected embodiments, the interposer structure may form passivated lining etched openings (e.g. Figure 12 (as shown) and etched openings excluding the passivation liner layer (e.g.) Figure 6 (as shown in the diagram). In such embodiments, passivation layer 44 can be deposited as a sidewall / bottom passivation liner layer in all etched openings 43A-D, and then completely stripped from some selected etched openings before forming a conductive barrier film liner and an aluminum filler layer. For example, after forming passivation layer 44 as a sidewall / bottom passivation liner layer in all etched openings 43A-D, a patterned mask can be formed on the interposer structure, and a suitable stripping or etching process can be applied to remove the sidewall / bottom passivation liner layer from the etched openings exposed by the patterned mask. After stripping the patterned mask, a conductive barrier film liner and an aluminum filler layer can be formed in all etched openings.

[0035] Figure 13 Selected embodiments according to this disclosure are shown. Figure 12 The subsequent processing of the interposer structure 13 after performing back-side etching or polishing step 46. As disclosed herein, the back-side polishing step 46 can use any suitable manufacturing process to expose the deeper metal layers 45A, 45C-D on the back surface of the etched interposer substrate 10, for example, by applying a chemical mechanical polishing (CMP) planarization process to thin the interposer substrate 10 and expose the metal layers 45A, 45C-D. In such embodiments, the passivation layer 44 previously formed at the bottom of the etched openings 43A, 43C-D can be used as a CMP polishing endpoint determinant to control the extent and duration of the back-side etching or polishing step 46.

[0036] To better understand selected embodiments of this disclosure, reference is now made to Figure 14 The figure depicts a simplified cross-sectional view of an integrated circuit package assembly 14 after one or more core device integrated circuits 50 are attached or mounted to an interposer structure 52 via first-level interconnects 51. When implemented as a flip-chip package, the core device IC 50 is connected to a printed circuit board 56 using conductive element paths defined in the interposer structure 52. Specifically, the core device IC 50 is attached to a first or bottom surface of the interposer substrate 52 using a set of first-level interconnects 51 (e.g., solder bumps or microbump conductors). Similarly, a second or top surface of the interposer substrate 52 is attached to the printed circuit board 56 using a set of second-level interconnects formed with a UMB layer 53, copper or metal pillars 54, and solder balls or bumps 55. In the depicted integrated circuit package assembly 14, the interposer structure 52 includes only non-core device components (e.g., thick gate oxide transistors and / or radio frequency (RF) elements) formed in a stack of BEOL interconnect stack 14, which includes partially stacked aluminum via structures 53, fully stacked aluminum via structures 54, and / or sealing ring / crack arrest structures 52, 54, formed by selectively etching deep trench openings to one or more predetermined depths in the fully stacked BEOL interconnect stack 14, followed by filling the deep trench openings with a barrier liner layer and deposited aluminum to form aluminum via structures and sealing ring / crack arrest structures 52-55. By forming a low-cost interposer structure 52 to include non-core device components, a core device IC 50 with core device components (e.g., advanced node core transistors or memory transistors) can be formed using an advanced node high-cost silicon high-speed die connected to the low-cost interposer structure 52 via suitable interconnect conductors 51. In this way, the functional circuit system is partitioned between the low-cost interposer structure 52 and the advanced node high-cost silicon high-speed die 50, resulting in a significant reduction in wafer cost and cycle time.

[0037] While the exemplary embodiments described herein relate to various semiconductor and IC device structures and methods of manufacturing thereof, the invention is not necessarily limited to the example embodiments shown that are applicable to a wide variety of semiconductor processes and / or devices. Therefore, the specific embodiments disclosed above are illustrative only and should not be considered as limiting the invention, as the invention can be modified and implemented in different but equivalent ways, which will be apparent to those skilled in the art who benefit from the teachings herein. Accordingly, the foregoing description is not intended to limit the invention to the specific forms set forth, but rather is intended to cover such alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art will understand that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the invention as presented in its broadest form.

[0038] The benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these benefits, advantages, solutions to problems, and any elements that may make any benefit, advantage, or solution occur or become more significant should not be construed as essential, necessary, or fundamental features or elements of any or all claims. As used herein, the terms "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not simply include those elements, but may include other elements not expressly listed or not inherent to such process, method, article, or apparatus.

Claims

1. A method for manufacturing a packaged assembly, characterized by, include: A semiconductor interposer structure is formed, the semiconductor interposer structure including a back-end process (BEOL) interlayer dielectric (ILD) stack formed above a silicon substrate, wherein a plurality of front-end process (FEOL) integrated circuit (IC) transistor devices are formed in the silicon substrate, the plurality of FEOL IC transistor devices having one or more gate dielectric layers having a specified minimum thickness, wherein the BEOL ILD stack includes a plurality of conductive interconnect structures extending through the BEOL ILD stack and a plurality of aluminum via structures and aluminum crack arrest structures extending at least partially downward through the BEOL ILD stack from the top surface of the BEOL ILD stack; as well as One or more core device integrated circuit devices are attached to a first surface of the semiconductor interposer structure, each core device integrated circuit device having a plurality of core transistors, the plurality of core transistors having one or more gate dielectric layers, the one or more gate dielectric layers having a specified maximum thickness less than the specified minimum thickness.

2. The method according to claim 1, characterized in that, Additionally, it includes attaching a printed circuit board to the second opposing surface of the semiconductor interposer structure.

3. The method according to claim 1, characterized in that, The specified maximum thickness of the one or more gate dielectric layers in the plurality of core transistors is about 40 angstroms, and the specified minimum thickness of the one or more gate dielectric layers in the plurality of FEOL IC transistor devices is at least about 50 angstroms.

4. The method according to claim 1, characterized in that, Forming the semiconductor interposer structure includes: The plurality of FEOL IC transistor devices are formed at least partially in the silicon substrate layer; The BEOL ILD stack is formed over the plurality of FEOL IC transistor devices and the silicon substrate layer; Selectively etch a plurality of etch openings, the plurality of etch openings extending at least partially downward from the top surface of the BEOL ILD stack through the BEOL ILD stack; and The plurality of etched openings are filled with at least deposited aluminum to form the plurality of aluminum through-hole structures and aluminum crack arrest structures.

5. The method according to claim 4, characterized in that, Forming the BEOL ILD stack includes forming capacitor structures and / or inductor structures within the BEOL ILD stack.

6. The method according to claim 4, characterized in that, Selectively etching the plurality of etched openings includes: Selectively etch one or more deep trench through-substrate via openings extending through the BEOL ILD stack and the silicon substrate layer; Selectively etch one or more partial trench via openings, said one or more partial trench via openings extending from the top surface of the BEOL ILD stack and extending only partially downward through the BEOL ILD stack; and Selectively etch deep trench anti-crack openings extending through the BEOL ILD stack and the silicon substrate.

7. The method according to claim 4, characterized in that, Filling the plurality of etched openings includes: A deposited barrier liner layer is used to conformally cover the sidewalls and bottom surface of the plurality of etched openings; Depositing aluminum to fill the plurality of etched openings; and A top-side polishing step is applied to substantially planarize the top surface of the deposited aluminum and barrier liner layer stacked with the BEOL ILD.

8. The method according to claim 4, characterized in that, In addition, including: A passivation layer is formed over the BEOL ILD stack before or after selectively etching one or more deep trench through-substrate via openings.

9. A method for forming an intermediate layer structure, characterized in that, include: A semiconductor interposer wafer substrate is provided in which a plurality of front-end process (FEOL) integrated circuit (IC) transistor devices having gate oxides are formed, the gate oxides having a minimum thickness of about 50 angstroms; A back-to-back process (BEOL) interlayer dielectric (ILD) stack is formed above the semiconductor interposer wafer substrate, the BEOL ILD stack including multiple conductive interconnect structures extending through multiple interconnect layers in the BEOL ILD stack; Selectively etch a plurality of etch openings, the plurality of etch openings extending at least partially downward from the top surface of the BEOL ILD stack through at least the top interconnect level of the BEOL ILD stack; The plurality of etched openings are filled with at least deposited aluminum to form a plurality of aluminum through-hole structures and aluminum crack arrest structures that extend at least partially downward from the top surface of the BEOL ILD stack through the BEOL ILD stack. as well as The bottom surface of the semiconductor interposer wafer substrate is partially recessed to at least expose the aluminum crack-resistant structure.

10. An electronic device, characterized in that, include: A semiconductor interposer structure comprising a back-end process (BEOL) interlayer dielectric (ILD) stack above a silicon substrate, wherein a plurality of front-end process (FEOL) integrated circuit (IC) transistor devices having gate oxides having a specified minimum thickness are formed in the silicon substrate, wherein the BEOL ILD stack comprises a plurality of conductive interconnect structures extending through a plurality of interconnect layers in the BEOL ILD stack, and a plurality of aluminum via structures and aluminum crack arresters extending at least partially downward from the top surface of the BEOL ILD stack through at least a first interconnect layer of the BEOL ILD stack; The first plurality of interconnecting conductors are located on a first surface of the semiconductor interposer structure and are in electrical contact with the plurality of aluminum via structures; The second plurality of interconnecting conductors are located on the second surface of the semiconductor interposer structure and are in electrical contact with the plurality of aluminum via structures; as well as One or more core device integrated circuit devices are attached to a first plurality of interconnect conductors or a second plurality of interconnect conductors, wherein each core device integrated circuit device includes a plurality of core transistors having a gate oxide having a specified maximum oxide thickness less than the specified minimum thickness.

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