Transmission structure, data center system architecture and method for preparing transmission structure

Abstract

The application discloses a transmission structure, a data center system architecture and a preparation method of the transmission structure. The transmission structure is used for connecting an optical chip and an electrical chip. The transmission structure comprises an outer conductor, a support structure and two inner conductors. The outer conductor is formed with a cavity. The outer conductor comprises two side walls which are oppositely arranged along a first direction. The support structure is located in the cavity and connected with the two side walls of the outer conductor. The two inner conductors are located in the cavity and arranged on opposite sides of the support structure along a second direction. The inner conductors are connected with the support structure. The inner conductors are spaced apart from the outer conductor. The second direction forms an angle with the first direction. According to the application, the two inner conductors are arranged on opposite sides of the support structure, so that a differential pair can be formed inside the transmission structure. By connecting the optical chip and the electrical chip by using the transmission structure, the electrical interconnection distance between the optical chip and the electrical chip can be effectively shortened, so that the signal integrity can be improved, and the transmission loss and power consumption can be reduced.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a transmission structure, a data center system architecture, and a method for preparing the transmission structure. Background Technology

[0002] With the rapid development of high-performance computing scenarios such as artificial intelligence, big data centers, and 5G / 6G communications, the requirements for data transmission bandwidth, power consumption, latency, and signal integrity are becoming increasingly stringent. In traditional pluggable optical module solutions, electrical signals need to be transmitted over long distances of copper wires between the motherboard, electrical chips, and optical chips, resulting in poor signal integrity and high power consumption. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a transmission structure, a data center system architecture, and a method for fabricating the transmission structure, which can improve signal integrity and reduce transmission loss and power consumption.

[0004] The technical solution adopted to achieve the purpose of this application is as follows: This application provides a transmission structure for connecting an optical chip and an electrical chip, the transmission structure comprising: An outer conductor having a cavity, the outer conductor including two sidewalls disposed opposite each other along a first direction; A supporting structure is located within the cavity, and the supporting structure is connected to the two side walls of the outer conductor. Two inner conductors are located within the cavity, and the two inner conductors are respectively disposed on opposite sides of the support structure along a second direction; the inner conductors are connected to the support structure, and the inner conductors are spaced apart from the outer conductor; the second direction forms an angle with the first direction.

[0005] In some embodiments, the two inner conductors are symmetrically disposed on opposite sides of the support structure along the second direction.

[0006] In some embodiments, the transmission structure includes two substrates disposed opposite each other along the second direction, with grooves provided on opposite sides of the two substrates, and the outer conductor disposed on the inner surface of the two grooves.

[0007] In some embodiments, the transmission structure further includes a spacer portion located between the two substrates, the spacer portion being located outside the outer conductor, and an isolation groove being formed between the spacer portion and the outer conductor, the isolation groove being filled with an isolation material.

[0008] This application also provides a data center system architecture, including: The transmission structure described in any of the above items; The optical chip is electrically connected to one end of the two inner conductors in the transmission structure. The electrical chip is electrically connected to the other end of the two inner conductors in the transmission structure.

[0009] This application also provides a method for preparing a transmission structure, including: Provide a base; A conductor portion is formed on one side of the substrate, the conductor portion having a cavity, and an opening communicating with the cavity is formed on the side of the conductor portion opposite to the substrate; A support and an inner conductor are formed on one side of the substrate, such that the support is connected to the two side walls of the conductor portion and the opening is sealed, and the inner conductor is connected to the support and located in the cavity to form a wafer to be bonded; The two sheets to be bonded are bonded on the side where the support body is located, so that the conductor portions of the two sheets to be bonded are bonded together to form an outer conductor, the support bodies of the two sheets to be bonded are connected to form a support structure, and the two inner conductors are respectively located on opposite sides of the support structure.

[0010] In some embodiments, forming a conductor portion on one side of the substrate includes: A groove is formed on one side of the substrate; A first metal layer is formed on the substrate such that the first metal layer at least covers the inner surface of the groove to form a first sub-bonded wafer; the first metal layer located on the inner surface of the groove forms a conductor portion.

[0011] In some embodiments, forming a support and an inner conductor on one side of the substrate, connecting the support to two sidewalls of the conductor portion and sealing the opening, and connecting the inner conductor to the support and placing it within the cavity to form the bonding wafer includes: A substrate is provided, and a support material is formed on the substrate; A second metal layer is formed on the support material, and the second metal layer is patterned to form an inner conductor and a second sub-bonded sheet. The inner conductor side of the second sub-bonded wafer is bonded to the first metal layer side of the first sub-bonded wafer; The substrate is removed, and the support material is patterned to form a support body connected to the two sidewalls of the conductor portion; the support body exposes a first metal layer on the surface of the substrate and a portion of the first metal layer on the side surface of the groove.

[0012] In some embodiments, before bonding the two sheets to be bonded on the support side, the method further includes: A third metal layer is formed on the first metal layer and the third metal layer is patterned so that the third metal layer is located on opposite sides of the support and covers the first metal layer located on the surface of the substrate and a portion of the first metal layer located on the side surface of the groove; the surface of the third metal layer is flush with the surface of the support.

[0013] In some embodiments, before bonding the two sheets to be bonded on the support side, the method further includes: The third metal layer and the first metal layer are patterned to form an isolation groove on the outside of the conductor portion; the isolation groove isolates the conductor portion and the first metal layer and the third metal layer located on the surface of the substrate; The isolation groove is filled with isolation material.

[0014] As can be seen from the above technical solution, this application integrates the outer conductor, the support structure and the inner conductor, and sets the two inner conductors on opposite sides of the support structure, which can form a differential pair inside the transmission structure. By using the transmission structure to connect the optical chip and the electrical chip, the electrical interconnection distance between the optical chip and the electrical chip can be effectively shortened, thereby helping to improve signal integrity and reduce transmission loss and power consumption. Attached Figure Description

[0015] Figure 1 This is a three-dimensional structural diagram of a transmission structure provided in an embodiment of this application; Figure 2 Provided for the embodiments of this application Figure 1 Cross-sectional view of the transmission structure in the middle; Figure 3 A flowchart illustrating a method for fabricating a transmission structure according to an embodiment of this application; Figure 4 Provided for the embodiments of this application Figure 3 A schematic diagram of the structure corresponding to step S200; Figure 5 Provided for the embodiments of this application Figure 3 The flowchart corresponding to step S300; Figure 6 Provided for the embodiments of this application Figure 5 A schematic diagram of the structure corresponding to steps S301 to S304; Figure 7 Provided for the embodiments of this application Figure 5 A schematic diagram of the structure corresponding to step S305 in the middle section; Figure 8 Provided for the embodiments of this application Figure 5 A schematic diagram of the structure corresponding to steps S306 to S307; Figure 9Provided for the embodiments of this application Figure 8 A magnified view of a portion of the substrate to be bonded.

[0016] Explanation of reference numerals in the attached figures: 1-Transmission structure; 11-Outer conductor; 111-Cavity; 112-Opening; 113-Conductor portion; 12-Support structure; 121-Support body; 13-Inner conductor; 14-Substrate; 141-Groove; 15-September portion; 16-Isolation groove; 17-Isolation material; 18-Layer to be bonded; 181-First sub-layer to be bonded; 182-Second sub-layer to be bonded; 19-First metal layer; 20-Substrate; 21-Support material; 22-Second metal layer; 23-Third metal layer; X-First direction; Y-Second direction. Detailed Implementation

[0017] To enable those skilled in the art to better understand this application, the technical solution of this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] With the rapid development of high-performance computing scenarios such as artificial intelligence, big data centers, and 5G / 6G communications, the requirements for data transmission bandwidth, power consumption, latency, and signal integrity are becoming increasingly stringent. In traditional pluggable optical module solutions, electrical signals need to be transmitted over long distances of copper wires between the motherboard, electrical chips, and optical chips, resulting in poor signal integrity and high power consumption. To address this challenge, co-packaged optoelectronics (CPO) technology encapsulates optical chips and electrical chips on the same substrate or within a package, significantly shortening the electrical interconnection distance between them. However, CPO technology requires high-density heterogeneous integration of optical chips and electrical chips using different process nodes and material systems. This complex and expensive heterogeneous integration leads to high manufacturing costs.

[0019] Furthermore, the tight integration of optical and electrical chips results in extremely high power density, which traditional air cooling cannot meet. High-efficiency liquid cooling systems must be introduced for thermal management, increasing system complexity and introducing leakage risks and maintenance challenges. Simultaneously, CPO permanently encapsulates optical and electrical chips together. If any component fails, it cannot be repaired or replaced locally; the entire system must be replaced. This one-time, permanent encapsulation method leads to extremely high maintenance costs. Moreover, the widespread adoption of CPO requires redesigning core equipment such as servers and switches, altering the mainstream AI / data center architecture based on pluggable optical engine modules, resulting in a long technology iteration cycle.

[0020] To address this issue, this application proposes a transmission structure for connecting optical chips and electrical chips to achieve high-speed, low-loss signal transmission, meeting the interconnect performance requirements of modern data centers and high-performance computing systems. Please refer to... Figure 1 and Figure 2 The transmission structure 1 includes an outer conductor 11, which is a conductive structure forming an external shielding layer for the transmission path. The material of the outer conductor 11 can be copper, aluminum, or gold. The outer conductor 11 has a cavity 111 and includes two sidewalls arranged opposite each other along a first direction X. The cavity 111 is an open space formed inside the outer conductor 11, used to accommodate the support structure 12 and the inner conductor 13, and to provide the necessary medium environment for signal transmission, such as air.

[0021] The transmission structure 1 includes a support structure 12 located within the cavity 111 and connected to the two sidewalls of the outer conductor 11. The support structure 12 provides mechanical support and electrical insulation for the internal conductive elements. The support structure 12 can be made of a dielectric material, such as a polymer, ceramic, or glass fiber reinforced resin. By connecting the support structure 12 to the two sidewalls of the outer conductor 11, its stable position within the cavity 111 is ensured.

[0022] The transmission structure 1 includes two inner conductors 13 located within the cavity 111. The two inner conductors 13 are positioned on opposite sides of the support structure 12 along the second direction Y. For example, if the support structure 12 is a flat plate, the two inner conductors 13 can be located above and below the plate, respectively. The two inner conductors 13 can form a differential pair with good differential impedance matching. The inner conductors 13 can be linear, strip-shaped, or columnar, and their material can be copper, gold, or aluminum, etc. The second direction Y forms an angle with the first direction X. For example, the first direction X can be the width direction of the outer conductor 11, and the second direction Y can be the thickness direction of the outer conductor 11.

[0023] The inner conductor 13 is connected to the support structure 12. This connection can be a physical attachment or by forming the inner conductor 13 on the surface of the support structure 12. This connection ensures the fixed position of the inner conductor 13 in the transmission structure 1 and maintains its relative relationship with the support structure 12. The inner conductor 13 and the outer conductor 11 are spaced apart, meaning there is a certain distance between them, and this distance is filled with dielectric material or air. This spacing is a fundamental requirement for forming a transmission line, used to control the characteristic impedance of the transmission line and reduce signal loss.

[0024] This embodiment integrates the outer conductor 11, the support structure 12, and the inner conductor 13, and places the two inner conductors 13 on opposite sides of the support structure 12. This enables the formation of a differential pair within the transmission structure 1. By using the transmission structure 1 to connect the optical chip and the electrical chip, the electrical interconnection distance between the optical chip and the electrical chip can be effectively shortened, thereby helping to improve signal integrity and reduce transmission loss and power consumption.

[0025] In some embodiments, two inner conductors 13 are symmetrically arranged on opposite sides of the support structure 12 along a second direction Y. Symmetrical arrangement means that the two inner conductors 13 are mirror- or centrally symmetrical in geometry, size, and spatial position relative to the support structure 12 and the outer conductor 11. For example, the two inner conductors 13 may have the same cross-sectional shape and size, and they may be equidistant from the centerline or center plane of the support structure 12. Simultaneously, the spacing between each inner conductor 13 and the sidewall of its adjacent outer conductor 11 may also be the same. This symmetry ensures a high degree of electrical consistency in the differential signal transmission paths formed by the two inner conductors 13; for example, the characteristic impedance, propagation delay, and loss characteristics of the two paths are consistent.

[0026] By symmetrically arranging the two inner conductors 13 along the second direction Y on opposite sides of the support structure 12, the geometric and electrical symmetry of the differential signal transmission path is ensured. This symmetrical arrangement gives the two signal paths almost identical transmission characteristics, such as propagation speed, impedance, and loss, thereby helping to improve the common-mode noise suppression capability of the differential signal, effectively reducing mode conversion loss, and facilitating precise differential impedance matching. This enhances the signal integrity of the transmission structure 1 in high-frequency, high-speed signal transmission, reduces the bit error rate, and simplifies subsequent circuit design and system integration.

[0027] In some embodiments, the transmission structure 1 includes two substrates 14 disposed opposite to each other along the second direction Y. The substrates 14 can serve as basic support components of the transmission structure 1 and can be made of materials with good insulation properties and mechanical strength, such as silicon, glass, ceramics or polymer materials.

[0028] Two substrates 14 each have a groove 141 on one side facing each other. The groove 141 can be a recessed structure of a specific shape pre-formed on the surface of the substrate 14. When the two substrates 14 are precisely aligned and closed, the two grooves 141 together form a closed or semi-closed cavity. The groove 141 can be formed by various micromachining techniques, such as anisotropic wet etching, deep reactive ion etching, laser ablation, or precision machining. The geometry and size of the groove 141 can be adjusted according to the design requirements of the outer conductor 11 to ensure that it can accurately support and define the structure of the outer conductor 11 in subsequent steps.

[0029] The outer conductor 11 is disposed on the inner surface of the two grooves 141. That is, after the grooves 141 of the substrate 14 are formed, a conductive layer can be formed on the inner wall of the grooves 141 by deposition or growth of conductive materials (such as copper, gold, aluminum, etc.). Deposition techniques can include physical vapor deposition (PVD, such as sputtering), chemical vapor deposition (CVD), electroplating, or electroless plating. When the two substrates 14 with the outer conductor 11 are joined together, the outer conductors 11 on the inner surface of the grooves 141 will contact and connect with each other, thereby forming a complete and continuous outer conductor 11 structure with a specific geometry. This split-manufacturing and rebonding strategy makes the formation process of the outer conductor 11 more controllable and precise.

[0030] By disassembling the outer conductor 11 onto two independent substrates 14 for processing, and utilizing the grooves 141 on the substrates 14 to precisely define the shape and position of the outer conductor 11, the precision and complexity issues that may be encountered in traditional integrated manufacturing of the outer conductor 11 are effectively solved. This structured design makes the manufacturing process of the outer conductor 11 more refined and controllable, helping to achieve high-precision geometric dimensions, thereby optimizing the electromagnetic performance of the transmission structure 1. In addition, using two substrates 14 for separate processing and bonding simplifies the overall manufacturing process, reduces the requirements for complex three-dimensional processing capabilities, and improves production efficiency and yield. This modular design also facilitates subsequent integration and packaging, helping to improve the overall stability and reliability of the transmission structure 1.

[0031] In some embodiments, the transmission structure 1 further includes a spacer portion 15 located between the two substrates 14. The spacer portion 15 is located outside the outer conductor 11 and serves to provide structural support and connect the two substrates 14 to ensure the overall structural stability of the transmission structure 1. The spacer portion 15 can be made of various materials, such as a dielectric material compatible with the substrate 14 material, such as silicon, glass, ceramic, or polymer, formed by processes such as bonding, deposition, or growth; or it can be made of the same material as the outer conductor 11 and formed simultaneously with the outer conductor 11 to serve as a bonding interface between the two substrates.

[0032] An isolation groove 16 is formed between the spacer portion 15 and the outer conductor 11, and the isolation groove 16 is filled with an insulating material 17. The isolation groove 16 is a physical gap that effectively separates the outer conductor 11 from the spacer portion 15 electromagnetically and provides space for the insulating material 17. The isolation groove 16 can be formed using microfabrication techniques. For example, after the spacer portion 15 is formed, a portion of the spacer portion 15 material can be precisely removed around the outer conductor 11 using processes such as photolithography and etching to form the desired groove structure. The insulating material 17 can be a dielectric with a low dielectric constant, such as polyimide, benzocyclobutene, silicon dioxide, or silicon nitride. By filling with a low dielectric constant material, the parasitic capacitance between the outer conductor 11 and the spacer portion 15 can be effectively reduced, thereby reducing electromagnetic coupling and further suppressing signal leakage and external interference.

[0033] Through the synergistic effect of the spacer portion 15 located between the two substrates 14, the isolation groove 16 formed between the spacer portion 15 and the outer conductor 11, and the isolation material 17 filled in the isolation groove 16, an effective electromagnetic isolation region is constructed outside the outer conductor 11. This isolation region significantly reduces the electromagnetic coupling between the outer conductor 11 and the external environment, thereby suppressing signal leakage and external electromagnetic interference, ensuring the signal integrity and stability of the transmission structure 1 during high-frequency signal transmission, and thus improving the reliability of the entire transmission structure 1.

[0034] With the rapid development of high-performance computing scenarios such as artificial intelligence, big data centers, and 5G / 6G communications, the requirements for data transmission bandwidth, power consumption, latency, and signal integrity are becoming increasingly stringent. In response, this application also proposes a data center system architecture, which includes a transmission structure 1. The specific structure of the transmission structure 1 can be referred to the relevant descriptions in the above embodiments, and will not be repeated here.

[0035] The data center system architecture also includes optical chips and electrical chips. The optical chip is electrically connected to one end of the two inner conductors 13 in the transmission structure 1, and the electrical chip is electrically connected to the other end of the two inner conductors 13 in the transmission structure 1. The optical chip receives or transmits optical signals through one end of the transmission structure 1, which are converted into electrical signals through photoelectric conversion. This electrical signal is differentially transmitted through the two inner conductors 13 inside the transmission structure 1. Since the inner conductors 13 and the outer conductor 11 are precisely spaced through the support structure 12, electromagnetic interference is effectively suppressed and signal attenuation is reduced. The electrical chip receives or processes this electrical signal through the other end of the transmission structure 1 to complete the data exchange function. By directly electrically connecting the transmission structure 1 to the optical chip and the electrical chip, complex heterogeneous integration processes can be avoided, thereby helping to reduce packaging costs and simplify the system architecture.

[0036] Through the aforementioned technical solution, this data center system architecture significantly simplifies the interconnection process between optical and electrical chips while ensuring high-speed signal transmission performance. Since there is no need for high-density heterogeneous integration of optical and electrical chips, they can be coupled to the aforementioned transmission structure 1 via standardized electrical connections, thus avoiding material compatibility issues and complex packaging processes. Furthermore, the shielding characteristics of transmission structure 1 effectively control signal integrity, avoiding the losses associated with traditional long-distance copper wire transmission. Simultaneously, its structural design eliminates the need for additional thermal management measures, significantly reducing system power consumption and manufacturing costs. Overall, this architecture provides a highly reliable and low-cost interconnection solution for next-generation data centers, AI clusters, and high-performance computing systems, meeting the stringent future demands for bandwidth density and energy efficiency.

[0037] It should be noted that since the optical chip and electrical chip can be directly connected to both ends of the transmission structure 1, this system architecture supports partial repair and module replacement, thereby avoiding the overall replacement cost of a one-time permanent fixed package and helping to reduce maintenance costs. Furthermore, this application does not require significant changes to mainstream AI / data center architectures based on pluggable optical engine modules, and performance upgrades can be achieved on the basis of existing systems, lowering the threshold for technological iteration.

[0038] This application also proposes a method for preparing a transport structure; please refer to [link to relevant documentation]. Figure 3 The method mainly includes the following steps: S100, provides a substrate 14.

[0039] S200, A conductor portion 113 is formed on one side of the substrate 14. The conductor portion 113 has a cavity 111, and an opening 112 communicating with the cavity 111 is formed on the side of the conductor portion 113 away from the substrate 14.

[0040] S300, a support 121 and an inner conductor 13 are formed on one side of the substrate 14, the support 121 is connected to the two side walls of the conductor portion 113 and the opening 112 is sealed, and the inner conductor 13 is connected to the support 121 and located in the cavity 111 to form the bonding sheet 18.

[0041] S400, the two sheets to be bonded are bonded on the side where the support body 121 is located, so that the conductor portions 113 of the two sheets to be bonded are bonded together to form an outer conductor 11, the support bodies 121 of the two sheets to be bonded are connected to form a support structure 12, and the two inner conductors 13 are respectively located on opposite sides of the support structure 12.

[0042] This application employs a step-by-step process to form the conductor portion 113, the support body 121, and the inner conductor 13. First, the wafer to be bonded 18 is prepared independently, and then the structure is assembled through bonding. Since the conductor portion 113 forms a complete outer conductor 11 after bonding, the support body 121 connects to form a support structure 12, and the inner conductor 13 is symmetrically distributed on both sides of the support structure 12, thus forming a differential pair of two symmetrical single inner conductor 13 micro-coaxial structures. This structural design effectively shortens the electrical interconnection distance between the optical chip and the electrical chip, while ensuring the stability of signal transmission. Furthermore, this method eliminates the complex multi-layer stacking and release process in traditional sacrificial layer processes, helping to simplify the fabrication process, reduce production costs, and avoid structural reliability and yield problems caused by sacrificial layer stress.

[0043] In some embodiments, please refer to Figure 4 Step S200 mainly includes the following steps: First, a groove 141 is formed on one side of the substrate 14. The formation of the groove 141 is intended to provide a predefined structure for the subsequent precise construction of the conductor portion 113. By pre-etching, machining, or using other micromachining techniques to form the groove 141 with specific dimensions and shapes on the surface of the substrate 14, the geometric contour of the internal cavity 111 of the conductor portion 113 can be effectively controlled. For example, techniques such as wet etching (e.g., anisotropic etching of the silicon substrate 14 using potassium hydroxide or tetramethylammonium hydroxide solution) or dry etching (e.g., reactive ion etching) can be used to achieve a high-precision and high aspect ratio groove 141 structure.

[0044] Subsequently, a first metal layer 19 is formed on the substrate 14. Methods for forming the first metal layer 19 include sputtering, evaporation, electroplating, or chemical vapor deposition. To ensure that the conductor portion 113 can completely form the desired cavity 111 structure, the first metal layer 19 is designed to at least cover the inner surface of the groove 141; that is, the metal layer needs to have good conformal deposition capability, capable of uniformly covering the bottom and sidewalls of the groove 141. By selecting appropriate deposition process parameters, it can be ensured that the first metal layer 19 forms a continuous and uniform coverage inside the groove 141. After the above steps, the first sub-bonded wafer 181 is formed, wherein the first metal layer 19 located on the inner surface of the groove 141 constitutes the conductor portion 113. This conductor portion 113 has a cavity 111 determined by the shape of the groove 141, and its side facing away from the substrate 14 (i.e., the opening of the groove 141) forms an opening 112 communicating with the cavity 111, providing a precise interface for the subsequent fabrication of the support structure 12 and the inner conductor 13.

[0045] Through the above technical solution, this application achieves precise control over the geometry of the conductor portion 113, particularly its internal cavity 111 and opening 112 structure, by pre-forming a precise groove 141 on the substrate 14 and using conformal deposition technology to form a first metal layer 19 on the inner surface of the groove 141. This step-by-step construction method decomposes the complex three-dimensional conductor structure into more easily controlled two-dimensional planar processing and subsequent conformal deposition, significantly improving the accuracy and repeatability of the conductor portion 113 forming. The formed conductor portion 113 can also more accurately meet the stringent requirements of high-frequency transmission lines for size and shape, thereby effectively reducing impedance mismatch and signal loss during signal transmission, ensuring excellent signal integrity of the transmission structure 1 when connecting optical chips and electrical chips, and providing a reliable foundation for high-performance interconnection.

[0046] In some embodiments, please refer to Figure 5 and Figure 6 Step S300 mainly includes the following steps: S301. A substrate 20 is provided, and a support material 21 is formed on the substrate 20.

[0047] S302. A second metal layer 22 is formed on the support material 21, and the second metal layer 22 is patterned to form an inner conductor 13 and a second sub-bonded sheet 182.

[0048] S303, Bond the side of the inner conductor 13 of the second sub-bonded sheet 182 to the side of the first metal layer 19 of the first sub-bonded sheet 181.

[0049] S304. Remove the substrate 20 and pattern the support material 21 to form a support 121 connected to the two sidewalls of the conductor portion 113; the support 121 exposes the first metal layer 19 on the surface of the substrate 14 and a portion of the first metal layer 19 on the side surface of the groove 141.

[0050] First, a substrate 20 is provided as a temporary carrier. The substrate 20 can be made of materials such as silicon, glass, or sapphire, and is characterized by good mechanical strength and thermal stability, and is easily selectively removed in subsequent processes. A support material 21 is formed on the substrate 20. The support material 21 can be made of polymers (such as polyimide or benzocyclobutene), dielectric materials (such as silicon dioxide or silicon nitride), etc., and is uniformly coated or deposited by methods such as spin coating, sputtering, or chemical vapor deposition (CVD).

[0051] Next, a second metal layer 22 is formed on the support material 21. The second metal layer 22 can be made of a highly conductive metal material, such as copper, gold, or aluminum, and is achieved through processes such as sputtering, evaporation, or electroplating. Subsequently, the second metal layer 22 is patterned, for example using photolithography and etching techniques, to precisely define the geometry and dimensions of the inner conductor 13. In this way, a second sub-bonded wafer 182 comprising the substrate 20, the support material 21, and the inner conductor 13 is formed. This step-by-step manufacturing method allows the formation of the inner conductor 13 to be performed on a relatively flat and easily controlled surface, thereby improving the precision and consistency of the inner conductor 13.

[0052] Subsequently, the side containing the inner conductor 13 of the second sub-bonded piece 182 is bonded to the side containing the first metal layer 19 of the first sub-bonded piece 181. The first sub-bonded piece 181 includes a substrate 14, a groove 141, and a first metal layer 19 (i.e., conductor portion 113) covering the inner surface of the groove 141. The purpose of bonding is to precisely position the pre-formed inner conductor 13 within the cavity 111 formed by the conductor portion 113 (first metal layer 19) and maintain a precise distance between it and the conductor portion 113. Bonding techniques such as thermoforming bonding, eutectic bonding, and direct bonding can be used to ensure that the bonding interface has good mechanical strength and electrical properties.

[0053] After bonding is completed, the substrate 20 is removed. The method for removing the substrate 20 depends on its material properties; for example, silicon substrate 20 can be removed by wet etching or dry etching, while glass substrate 20 can be removed by laser lift-off or chemical etching. The purpose of removing the substrate 20 is to expose the support material 21 for further processing. Subsequently, the support material 21 is patterned, for example by photolithography and etching processes, to form a support 121 connected to the two sidewalls of the conductor portion 113. This support 121 not only provides mechanical support for the inner conductor 13 but also seals the opening 112 of the conductor portion 113, thereby forming a closed cavity 111 structure. During the patterning process, the support 121 exposes the first metal layer 19 on the surface of the substrate 14 and a portion of the first metal layer 19 on the side surface of the groove 141, providing an interface for subsequent electrical connections or further structural integration.

[0054] By employing the above technical solution, the formation of the inner conductor 13 and the support 121 is decoupled from the formation of the conductor portion 113. A modular, step-by-step bonding strategy is adopted, greatly simplifying the manufacturing difficulty of complex three-dimensional microstructures. This method allows each component to be fabricated separately under its respective process conditions, thereby improving the geometric accuracy and material quality of the inner conductor 13 and the support 121. Precise bonding and subsequent removal of the substrate 20 and patterning of the support material 21 ensure the accurate positioning of the inner conductor 13 within the cavity 111 and the effective sealing of the cavity 111, thus achieving high-precision integration and structural integrity at a microscale.

[0055] In some embodiments, please refer to Figure 5 and Figure 7 Before bonding the two sheets 18 to be bonded on the side where the support 121 is located, the following steps are also included: S305. A third metal layer 23 is formed on the first metal layer 19 and the third metal layer 23 is patterned so that the third metal layer 23 is located on opposite sides of the support 121 and covers the first metal layer 19 located on the surface of the substrate 14 and a portion of the first metal layer 19 located on the side surface of the groove 141; the surface of the third metal layer 23 is flush with the surface of the support 121.

[0056] The third metal layer 23 is an additional metal thin film, whose main function is to optimize the surface properties of the sheet to be bonded 18 and provide a more ideal interface for subsequent bonding steps. The third metal layer 23 can be made of a material that has good compatibility with the first metal layer 19 and is easy to bond, such as gold, copper, nickel, or their alloys.

[0057] First, a third metal layer 23 is deposited on the first metal layer 19. Then, photoresist is coated and exposed and developed to form a photoresist mask with the desired pattern. Next, the portion of the third metal layer 23 not covered by the photoresist is removed by wet etching or dry etching. Finally, the photoresist is removed, thus precisely positioning the third metal layer 23 on opposite sides of the support 121. These areas are critical locations where the first metal layer 19 is exposed and needs to be bonded to another wafer 18. This selective coverage helps optimize the bonding performance of localized areas while avoiding unnecessary material waste and process complexity.

[0058] The third metal layer 23 covers the first metal layer 19 on the surface of the substrate 14 and a portion of the first metal layer 19 on the side surface of the groove 141. Specifically, the third metal layer 23 covers the portion of the first metal layer 19 exposed on the surface of the substrate 14 and the portion exposed on the sidewall of the groove 141. These regions are critical interfaces for forming the outer conductor 11 and ensuring electrical connections. By covering these regions, the third metal layer 23 provides a uniform and optimized surface for these critical interfaces. Furthermore, the surface of the third metal layer 23 is flush with the surface of the support 121, which can be achieved through precise control of the deposition thickness of the third metal layer 23, the patterning etching depth, and subsequent processes such as chemical mechanical polishing (CMP). By placing the surface of the third metal layer 23 at the same height as the surface of the support 121, a highly flat bonding interface can be formed.

[0059] In some embodiments, please refer to Figure 5 , Figure 8 and Figure 9 Before bonding the two sheets 18 to be bonded on the side where the support 121 is located, the following steps are also included: S306. The third metal layer 23 and the first metal layer 19 are patterned to form an isolation groove 16 on the outside of the conductor portion 113; the isolation groove 16 isolates the conductor portion 113 and the first metal layer 19 and the third metal layer 23 located on the surface of the substrate 14.

[0060] S307. Fill the isolation groove 16 with isolation material 17.

[0061] First, a photoresist layer is coated onto the third metal layer 23 and the first metal layer 19, and then exposed through a mask to cause a photochemical reaction in specific areas of the photoresist. Next, the exposed or unexposed photoresist is removed by development to form the desired pattern. Then, using chemical etching or physical etching (such as reactive ion etching), the metal layers not protected by the photoresist are selectively removed, thereby forming an isolation trench 16 with a precise geometry. The formation of the isolation trench 16 aims to physically separate the conductor portion 113 from the surrounding metal structures (including the first metal layer 19 and the third metal layer 23 located on the surface of the substrate 14). This physical isolation effectively prevents undesirable current flow between these metal structures, thereby reducing electromagnetic coupling and signal leakage. Here, "isolation" refers to creating a non-conductive region between the conductor portion 113 and the first metal layer 19 and the third metal layer 23 on the surface of the substrate 14 by removing a portion of the metal material. This isolation mechanism is the basis for achieving electrical isolation; it breaks potential conductive paths, thereby preventing direct conduction or inductive coupling of signals between different metal structures.

[0062] Subsequently, the isolation groove 16 is filled with an insulating material 17. The insulating material 17 can be a dielectric material with a low dielectric constant and good insulating properties, such as silicon dioxide, silicon nitride, or polyimide. The purpose of filling the insulating material 17 is to further enhance the electrical isolation between the conductor portion 113 and the surrounding environment and to provide mechanical support. The low dielectric constant material can reduce parasitic capacitance, thereby reducing signal transmission loss and crosstalk. The filling process can employ techniques such as chemical vapor deposition, spin coating, or atomic layer deposition to ensure that the insulating material 17 is uniformly and densely filled within the isolation groove 16, avoiding the formation of voids or defects.

[0063] By forming an isolation trench 16 and filling it with an isolation material 17 on the outside of the conductor portion 113, the conductor portion 113 can be effectively electrically isolated from the first metal layer 19 and the third metal layer 23 located on the surface of the substrate 14. The formation of the isolation trench 16 cuts off the direct conductive path between the conductor portion 113 and the surrounding metal structure, while the filling low-dielectric-constant isolation material 17 further reduces the parasitic capacitance between them, thereby optimizing the impedance matching characteristics of the transmission structure 1. This enables the transmission structure 1 to maintain higher signal integrity when connecting optical chips and electrical chips, ensuring the accuracy and reliability of data transmission. Especially in application scenarios with extremely high signal quality requirements, such as data centers, AI clusters, and high-performance computing systems, it can provide a more stable and efficient interconnection solution.

[0064] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0065] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A transmission structure, characterized in that, The transmission structure is used to connect the optical chip and the electrical chip, and the transmission structure includes: An outer conductor having a cavity, the outer conductor including two sidewalls disposed opposite each other along a first direction; A supporting structure is located within the cavity, and the supporting structure is connected to the two side walls of the outer conductor. Two inner conductors are located within the cavity, and the two inner conductors are respectively disposed on opposite sides of the support structure along a second direction; the inner conductors are connected to the support structure, and the inner conductors are spaced apart from the outer conductor; the second direction forms an angle with the first direction.

2. The transmission structure according to claim 1, characterized in that, The two inner conductors are symmetrically arranged on opposite sides of the support structure along the second direction.

3. The transmission structure according to claim 1, characterized in that, The transmission structure includes two substrates arranged opposite each other along the second direction, with grooves provided on opposite sides of the two substrates, and the outer conductor disposed on the inner surface of the two grooves.

4. The transmission structure according to claim 3, characterized in that, The transmission structure further includes a spacer portion located between the two substrates, the spacer portion being located outside the outer conductor, an isolation groove being formed between the spacer portion and the outer conductor, and the isolation groove being filled with an isolation material.

5. A data center system architecture, characterized in that, include: The transmission structure according to any one of claims 1 to 4; The optical chip is electrically connected to one end of the two inner conductors in the transmission structure. The electrical chip is electrically connected to the other end of the two inner conductors in the transmission structure.

6. A method for preparing a transmission structure, characterized in that, include: Provide a base; A conductor portion is formed on one side of the substrate, the conductor portion having a cavity, and an opening communicating with the cavity is formed on the side of the conductor portion opposite to the substrate; A support and an inner conductor are formed on one side of the substrate, such that the support is connected to the two side walls of the conductor portion and the opening is sealed, and the inner conductor is connected to the support and located in the cavity to form a wafer to be bonded; The two sheets to be bonded are bonded on the side where the support body is located, so that the conductor portions of the two sheets to be bonded are bonded together to form an outer conductor, the support bodies of the two sheets to be bonded are connected to form a support structure, and the two inner conductors are respectively located on opposite sides of the support structure.

7. The method for preparing the transmission structure according to claim 6, characterized in that, The formation of a conductor portion on one side of the substrate includes: A groove is formed on one side of the substrate; A first metal layer is formed on the substrate such that the first metal layer at least covers the inner surface of the groove to form a first sub-bonded wafer; the first metal layer located on the inner surface of the groove forms a conductor portion.

8. The method for preparing the transmission structure according to claim 7, characterized in that, The process involves forming a support and an inner conductor on one side of the substrate, connecting the support to two sidewalls of the conductor portion and sealing the opening, and connecting the inner conductor to the support and placing it within the cavity to form the bonding wafer. A substrate is provided, and a support material is formed on the substrate; A second metal layer is formed on the support material, and the second metal layer is patterned to form an inner conductor and a second sub-bonded sheet. The inner conductor side of the second sub-bonded wafer is bonded to the first metal layer side of the first sub-bonded wafer; The substrate is removed, and the support material is patterned to form a support body connected to the two sidewalls of the conductor portion; the support body exposes a first metal layer on the surface of the substrate and a portion of the first metal layer on the side surface of the groove.

9. The method for preparing the transmission structure according to claim 8, characterized in that, Before bonding the two sheets to be bonded on the support side, the method further includes: A third metal layer is formed on the first metal layer and the third metal layer is patterned so that the third metal layer is located on opposite sides of the support and covers the first metal layer located on the surface of the substrate and a portion of the first metal layer located on the side surface of the groove; the surface of the third metal layer is flush with the surface of the support.

10. The method for preparing the transmission structure according to claim 9, characterized in that, Before bonding the two sheets to be bonded on the support side, the method further includes: The third metal layer and the first metal layer are patterned to form an isolation groove on the outside of the conductor portion; the isolation groove isolates the conductor portion and the first metal layer and the third metal layer located on the surface of the substrate; The isolation groove is filled with isolation material.

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